1 /* SPU target-dependent code for GDB, the GNU debugger.
2 Copyright (C) 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
5 Based on a port by Sid Manning <sid@us.ibm.com>.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
25 #include "arch-utils.h"
29 #include "gdb_string.h"
30 #include "gdb_assert.h"
32 #include "frame-unwind.h"
33 #include "frame-base.h"
34 #include "trad-frame.h"
43 #include "reggroups.h"
44 #include "floatformat.h"
50 /* The tdep structure. */
53 /* SPU-specific vector type. */
54 struct type
*spu_builtin_type_vec128
;
58 /* SPU-specific vector type. */
60 spu_builtin_type_vec128 (struct gdbarch
*gdbarch
)
62 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
64 if (!tdep
->spu_builtin_type_vec128
)
68 t
= init_composite_type ("__spu_builtin_type_vec128", TYPE_CODE_UNION
);
69 append_composite_type_field (t
, "uint128", builtin_type_int128
);
70 append_composite_type_field (t
, "v2_int64",
71 init_vector_type (builtin_type_int64
, 2));
72 append_composite_type_field (t
, "v4_int32",
73 init_vector_type (builtin_type_int32
, 4));
74 append_composite_type_field (t
, "v8_int16",
75 init_vector_type (builtin_type_int16
, 8));
76 append_composite_type_field (t
, "v16_int8",
77 init_vector_type (builtin_type_int8
, 16));
78 append_composite_type_field (t
, "v2_double",
79 init_vector_type (builtin_type_double
, 2));
80 append_composite_type_field (t
, "v4_float",
81 init_vector_type (builtin_type_float
, 4));
83 TYPE_FLAGS (t
) |= TYPE_FLAG_VECTOR
;
84 TYPE_NAME (t
) = "spu_builtin_type_vec128";
86 tdep
->spu_builtin_type_vec128
= t
;
89 return tdep
->spu_builtin_type_vec128
;
93 /* The list of available "info spu " commands. */
94 static struct cmd_list_element
*infospucmdlist
= NULL
;
99 spu_register_name (int reg_nr
)
101 static char *register_names
[] =
103 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
104 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
105 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
106 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
107 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
108 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
109 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
110 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
111 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
112 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
113 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
114 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
115 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
116 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
117 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
118 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
119 "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status"
124 if (reg_nr
>= sizeof register_names
/ sizeof *register_names
)
127 return register_names
[reg_nr
];
131 spu_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
133 if (reg_nr
< SPU_NUM_GPRS
)
134 return spu_builtin_type_vec128 (gdbarch
);
139 return builtin_type_uint32
;
142 return builtin_type_void_func_ptr
;
145 return builtin_type_void_data_ptr
;
147 case SPU_FPSCR_REGNUM
:
148 return builtin_type_uint128
;
150 case SPU_SRR0_REGNUM
:
151 return builtin_type_uint32
;
153 case SPU_LSLR_REGNUM
:
154 return builtin_type_uint32
;
156 case SPU_DECR_REGNUM
:
157 return builtin_type_uint32
;
159 case SPU_DECR_STATUS_REGNUM
:
160 return builtin_type_uint32
;
163 internal_error (__FILE__
, __LINE__
, "invalid regnum");
167 /* Pseudo registers for preferred slots - stack pointer. */
170 spu_pseudo_register_read_spu (struct regcache
*regcache
, const char *regname
,
177 regcache_raw_read_unsigned (regcache
, SPU_ID_REGNUM
, &id
);
178 xsnprintf (annex
, sizeof annex
, "%d/%s", (int) id
, regname
);
179 memset (reg
, 0, sizeof reg
);
180 target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
183 store_unsigned_integer (buf
, 4, strtoulst (reg
, NULL
, 16));
187 spu_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
188 int regnum
, gdb_byte
*buf
)
197 regcache_raw_read (regcache
, SPU_RAW_SP_REGNUM
, reg
);
198 memcpy (buf
, reg
, 4);
201 case SPU_FPSCR_REGNUM
:
202 regcache_raw_read_unsigned (regcache
, SPU_ID_REGNUM
, &id
);
203 xsnprintf (annex
, sizeof annex
, "%d/fpcr", (int) id
);
204 target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
, buf
, 0, 16);
207 case SPU_SRR0_REGNUM
:
208 spu_pseudo_register_read_spu (regcache
, "srr0", buf
);
211 case SPU_LSLR_REGNUM
:
212 spu_pseudo_register_read_spu (regcache
, "lslr", buf
);
215 case SPU_DECR_REGNUM
:
216 spu_pseudo_register_read_spu (regcache
, "decr", buf
);
219 case SPU_DECR_STATUS_REGNUM
:
220 spu_pseudo_register_read_spu (regcache
, "decr_status", buf
);
224 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
229 spu_pseudo_register_write_spu (struct regcache
*regcache
, const char *regname
,
236 regcache_raw_read_unsigned (regcache
, SPU_ID_REGNUM
, &id
);
237 xsnprintf (annex
, sizeof annex
, "%d/%s", (int) id
, regname
);
238 xsnprintf (reg
, sizeof reg
, "0x%s",
239 phex_nz (extract_unsigned_integer (buf
, 4), 4));
240 target_write (¤t_target
, TARGET_OBJECT_SPU
, annex
,
241 reg
, 0, strlen (reg
));
245 spu_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
246 int regnum
, const gdb_byte
*buf
)
255 regcache_raw_read (regcache
, SPU_RAW_SP_REGNUM
, reg
);
256 memcpy (reg
, buf
, 4);
257 regcache_raw_write (regcache
, SPU_RAW_SP_REGNUM
, reg
);
260 case SPU_FPSCR_REGNUM
:
261 regcache_raw_read_unsigned (regcache
, SPU_ID_REGNUM
, &id
);
262 xsnprintf (annex
, sizeof annex
, "%d/fpcr", (int) id
);
263 target_write (¤t_target
, TARGET_OBJECT_SPU
, annex
, buf
, 0, 16);
266 case SPU_SRR0_REGNUM
:
267 spu_pseudo_register_write_spu (regcache
, "srr0", buf
);
270 case SPU_LSLR_REGNUM
:
271 spu_pseudo_register_write_spu (regcache
, "lslr", buf
);
274 case SPU_DECR_REGNUM
:
275 spu_pseudo_register_write_spu (regcache
, "decr", buf
);
278 case SPU_DECR_STATUS_REGNUM
:
279 spu_pseudo_register_write_spu (regcache
, "decr_status", buf
);
283 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
287 /* Value conversion -- access scalar values at the preferred slot. */
289 static struct value
*
290 spu_value_from_register (struct type
*type
, int regnum
,
291 struct frame_info
*frame
)
293 struct value
*value
= default_value_from_register (type
, regnum
, frame
);
294 int len
= TYPE_LENGTH (type
);
296 if (regnum
< SPU_NUM_GPRS
&& len
< 16)
298 int preferred_slot
= len
< 4 ? 4 - len
: 0;
299 set_value_offset (value
, preferred_slot
);
305 /* Register groups. */
308 spu_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
309 struct reggroup
*group
)
311 /* Registers displayed via 'info regs'. */
312 if (group
== general_reggroup
)
315 /* Registers displayed via 'info float'. */
316 if (group
== float_reggroup
)
319 /* Registers that need to be saved/restored in order to
320 push or pop frames. */
321 if (group
== save_reggroup
|| group
== restore_reggroup
)
324 return default_register_reggroup_p (gdbarch
, regnum
, group
);
328 /* Decoding SPU instructions. */
365 is_rr (unsigned int insn
, int op
, int *rt
, int *ra
, int *rb
)
367 if ((insn
>> 21) == op
)
370 *ra
= (insn
>> 7) & 127;
371 *rb
= (insn
>> 14) & 127;
379 is_rrr (unsigned int insn
, int op
, int *rt
, int *ra
, int *rb
, int *rc
)
381 if ((insn
>> 28) == op
)
383 *rt
= (insn
>> 21) & 127;
384 *ra
= (insn
>> 7) & 127;
385 *rb
= (insn
>> 14) & 127;
394 is_ri7 (unsigned int insn
, int op
, int *rt
, int *ra
, int *i7
)
396 if ((insn
>> 21) == op
)
399 *ra
= (insn
>> 7) & 127;
400 *i7
= (((insn
>> 14) & 127) ^ 0x40) - 0x40;
408 is_ri10 (unsigned int insn
, int op
, int *rt
, int *ra
, int *i10
)
410 if ((insn
>> 24) == op
)
413 *ra
= (insn
>> 7) & 127;
414 *i10
= (((insn
>> 14) & 0x3ff) ^ 0x200) - 0x200;
422 is_ri16 (unsigned int insn
, int op
, int *rt
, int *i16
)
424 if ((insn
>> 23) == op
)
427 *i16
= (((insn
>> 7) & 0xffff) ^ 0x8000) - 0x8000;
435 is_ri18 (unsigned int insn
, int op
, int *rt
, int *i18
)
437 if ((insn
>> 25) == op
)
440 *i18
= (((insn
>> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
448 is_branch (unsigned int insn
, int *offset
, int *reg
)
452 if (is_ri16 (insn
, op_br
, &rt
, &i16
)
453 || is_ri16 (insn
, op_brsl
, &rt
, &i16
)
454 || is_ri16 (insn
, op_brnz
, &rt
, &i16
)
455 || is_ri16 (insn
, op_brz
, &rt
, &i16
)
456 || is_ri16 (insn
, op_brhnz
, &rt
, &i16
)
457 || is_ri16 (insn
, op_brhz
, &rt
, &i16
))
459 *reg
= SPU_PC_REGNUM
;
464 if (is_ri16 (insn
, op_bra
, &rt
, &i16
)
465 || is_ri16 (insn
, op_brasl
, &rt
, &i16
))
472 if (is_ri7 (insn
, op_bi
, &rt
, reg
, &i7
)
473 || is_ri7 (insn
, op_bisl
, &rt
, reg
, &i7
)
474 || is_ri7 (insn
, op_biz
, &rt
, reg
, &i7
)
475 || is_ri7 (insn
, op_binz
, &rt
, reg
, &i7
)
476 || is_ri7 (insn
, op_bihz
, &rt
, reg
, &i7
)
477 || is_ri7 (insn
, op_bihnz
, &rt
, reg
, &i7
))
487 /* Prolog parsing. */
489 struct spu_prologue_data
491 /* Stack frame size. -1 if analysis was unsuccessful. */
494 /* How to find the CFA. The CFA is equal to SP at function entry. */
498 /* Offset relative to CFA where a register is saved. -1 if invalid. */
499 int reg_offset
[SPU_NUM_GPRS
];
503 spu_analyze_prologue (CORE_ADDR start_pc
, CORE_ADDR end_pc
,
504 struct spu_prologue_data
*data
)
509 int reg_immed
[SPU_NUM_GPRS
];
511 CORE_ADDR prolog_pc
= start_pc
;
516 /* Initialize DATA to default values. */
519 data
->cfa_reg
= SPU_RAW_SP_REGNUM
;
520 data
->cfa_offset
= 0;
522 for (i
= 0; i
< SPU_NUM_GPRS
; i
++)
523 data
->reg_offset
[i
] = -1;
525 /* Set up REG_IMMED array. This is non-zero for a register if we know its
526 preferred slot currently holds this immediate value. */
527 for (i
= 0; i
< SPU_NUM_GPRS
; i
++)
530 /* Scan instructions until the first branch.
532 The following instructions are important prolog components:
534 - The first instruction to set up the stack pointer.
535 - The first instruction to set up the frame pointer.
536 - The first instruction to save the link register.
538 We return the instruction after the latest of these three,
539 or the incoming PC if none is found. The first instruction
540 to set up the stack pointer also defines the frame size.
542 Note that instructions saving incoming arguments to their stack
543 slots are not counted as important, because they are hard to
544 identify with certainty. This should not matter much, because
545 arguments are relevant only in code compiled with debug data,
546 and in such code the GDB core will advance until the first source
547 line anyway, using SAL data.
549 For purposes of stack unwinding, we analyze the following types
550 of instructions in addition:
552 - Any instruction adding to the current frame pointer.
553 - Any instruction loading an immediate constant into a register.
554 - Any instruction storing a register onto the stack.
556 These are used to compute the CFA and REG_OFFSET output. */
558 for (pc
= start_pc
; pc
< end_pc
; pc
+= 4)
561 int rt
, ra
, rb
, rc
, immed
;
563 if (target_read_memory (pc
, buf
, 4))
565 insn
= extract_unsigned_integer (buf
, 4);
567 /* AI is the typical instruction to set up a stack frame.
568 It is also used to initialize the frame pointer. */
569 if (is_ri10 (insn
, op_ai
, &rt
, &ra
, &immed
))
571 if (rt
== data
->cfa_reg
&& ra
== data
->cfa_reg
)
572 data
->cfa_offset
-= immed
;
574 if (rt
== SPU_RAW_SP_REGNUM
&& ra
== SPU_RAW_SP_REGNUM
582 else if (rt
== SPU_FP_REGNUM
&& ra
== SPU_RAW_SP_REGNUM
588 data
->cfa_reg
= SPU_FP_REGNUM
;
589 data
->cfa_offset
-= immed
;
593 /* A is used to set up stack frames of size >= 512 bytes.
594 If we have tracked the contents of the addend register,
595 we can handle this as well. */
596 else if (is_rr (insn
, op_a
, &rt
, &ra
, &rb
))
598 if (rt
== data
->cfa_reg
&& ra
== data
->cfa_reg
)
600 if (reg_immed
[rb
] != 0)
601 data
->cfa_offset
-= reg_immed
[rb
];
603 data
->cfa_reg
= -1; /* We don't know the CFA any more. */
606 if (rt
== SPU_RAW_SP_REGNUM
&& ra
== SPU_RAW_SP_REGNUM
612 if (reg_immed
[rb
] != 0)
613 data
->size
= -reg_immed
[rb
];
617 /* We need to track IL and ILA used to load immediate constants
618 in case they are later used as input to an A instruction. */
619 else if (is_ri16 (insn
, op_il
, &rt
, &immed
))
621 reg_immed
[rt
] = immed
;
623 if (rt
== SPU_RAW_SP_REGNUM
&& !found_sp
)
627 else if (is_ri18 (insn
, op_ila
, &rt
, &immed
))
629 reg_immed
[rt
] = immed
& 0x3ffff;
631 if (rt
== SPU_RAW_SP_REGNUM
&& !found_sp
)
635 /* STQD is used to save registers to the stack. */
636 else if (is_ri10 (insn
, op_stqd
, &rt
, &ra
, &immed
))
638 if (ra
== data
->cfa_reg
)
639 data
->reg_offset
[rt
] = data
->cfa_offset
- (immed
<< 4);
641 if (ra
== data
->cfa_reg
&& rt
== SPU_LR_REGNUM
649 /* _start uses SELB to set up the stack pointer. */
650 else if (is_rrr (insn
, op_selb
, &rt
, &ra
, &rb
, &rc
))
652 if (rt
== SPU_RAW_SP_REGNUM
&& !found_sp
)
656 /* We terminate if we find a branch. */
657 else if (is_branch (insn
, &immed
, &ra
))
662 /* If we successfully parsed until here, and didn't find any instruction
663 modifying SP, we assume we have a frameless function. */
667 /* Return cooked instead of raw SP. */
668 if (data
->cfa_reg
== SPU_RAW_SP_REGNUM
)
669 data
->cfa_reg
= SPU_SP_REGNUM
;
674 /* Return the first instruction after the prologue starting at PC. */
676 spu_skip_prologue (CORE_ADDR pc
)
678 struct spu_prologue_data data
;
679 return spu_analyze_prologue (pc
, (CORE_ADDR
)-1, &data
);
682 /* Return the frame pointer in use at address PC. */
684 spu_virtual_frame_pointer (CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
686 struct spu_prologue_data data
;
687 spu_analyze_prologue (pc
, (CORE_ADDR
)-1, &data
);
689 if (data
.size
!= -1 && data
.cfa_reg
!= -1)
691 /* The 'frame pointer' address is CFA minus frame size. */
693 *offset
= data
.cfa_offset
- data
.size
;
697 /* ??? We don't really know ... */
698 *reg
= SPU_SP_REGNUM
;
703 /* Return true if we are in the function's epilogue, i.e. after the
704 instruction that destroyed the function's stack frame.
706 1) scan forward from the point of execution:
707 a) If you find an instruction that modifies the stack pointer
708 or transfers control (except a return), execution is not in
710 b) Stop scanning if you find a return instruction or reach the
711 end of the function or reach the hard limit for the size of
713 2) scan backward from the point of execution:
714 a) If you find an instruction that modifies the stack pointer,
715 execution *is* in an epilogue, return.
716 b) Stop scanning if you reach an instruction that transfers
717 control or the beginning of the function or reach the hard
718 limit for the size of an epilogue. */
721 spu_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
723 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
726 int rt
, ra
, rb
, rc
, immed
;
728 /* Find the search limits based on function boundaries and hard limit.
729 We assume the epilogue can be up to 64 instructions long. */
731 const int spu_max_epilogue_size
= 64 * 4;
733 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
736 if (pc
- func_start
< spu_max_epilogue_size
)
737 epilogue_start
= func_start
;
739 epilogue_start
= pc
- spu_max_epilogue_size
;
741 if (func_end
- pc
< spu_max_epilogue_size
)
742 epilogue_end
= func_end
;
744 epilogue_end
= pc
+ spu_max_epilogue_size
;
746 /* Scan forward until next 'bi $0'. */
748 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= 4)
750 if (target_read_memory (scan_pc
, buf
, 4))
752 insn
= extract_unsigned_integer (buf
, 4);
754 if (is_branch (insn
, &immed
, &ra
))
756 if (immed
== 0 && ra
== SPU_LR_REGNUM
)
762 if (is_ri10 (insn
, op_ai
, &rt
, &ra
, &immed
)
763 || is_rr (insn
, op_a
, &rt
, &ra
, &rb
)
764 || is_ri10 (insn
, op_lqd
, &rt
, &ra
, &immed
))
766 if (rt
== SPU_RAW_SP_REGNUM
)
771 if (scan_pc
>= epilogue_end
)
774 /* Scan backward until adjustment to stack pointer (R1). */
776 for (scan_pc
= pc
- 4; scan_pc
>= epilogue_start
; scan_pc
-= 4)
778 if (target_read_memory (scan_pc
, buf
, 4))
780 insn
= extract_unsigned_integer (buf
, 4);
782 if (is_branch (insn
, &immed
, &ra
))
785 if (is_ri10 (insn
, op_ai
, &rt
, &ra
, &immed
)
786 || is_rr (insn
, op_a
, &rt
, &ra
, &rb
)
787 || is_ri10 (insn
, op_lqd
, &rt
, &ra
, &immed
))
789 if (rt
== SPU_RAW_SP_REGNUM
)
798 /* Normal stack frames. */
800 struct spu_unwind_cache
803 CORE_ADDR frame_base
;
804 CORE_ADDR local_base
;
806 struct trad_frame_saved_reg
*saved_regs
;
809 static struct spu_unwind_cache
*
810 spu_frame_unwind_cache (struct frame_info
*next_frame
,
811 void **this_prologue_cache
)
813 struct spu_unwind_cache
*info
;
814 struct spu_prologue_data data
;
817 if (*this_prologue_cache
)
818 return *this_prologue_cache
;
820 info
= FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache
);
821 *this_prologue_cache
= info
;
822 info
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
823 info
->frame_base
= 0;
824 info
->local_base
= 0;
826 /* Find the start of the current function, and analyze its prologue. */
827 info
->func
= frame_func_unwind (next_frame
, NORMAL_FRAME
);
830 /* Fall back to using the current PC as frame ID. */
831 info
->func
= frame_pc_unwind (next_frame
);
835 spu_analyze_prologue (info
->func
, frame_pc_unwind (next_frame
), &data
);
838 /* If successful, use prologue analysis data. */
839 if (data
.size
!= -1 && data
.cfa_reg
!= -1)
844 /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */
845 frame_unwind_register (next_frame
, data
.cfa_reg
, buf
);
846 cfa
= extract_unsigned_integer (buf
, 4) + data
.cfa_offset
;
848 /* Call-saved register slots. */
849 for (i
= 0; i
< SPU_NUM_GPRS
; i
++)
850 if (i
== SPU_LR_REGNUM
851 || (i
>= SPU_SAVED1_REGNUM
&& i
<= SPU_SAVEDN_REGNUM
))
852 if (data
.reg_offset
[i
] != -1)
853 info
->saved_regs
[i
].addr
= cfa
- data
.reg_offset
[i
];
856 info
->frame_base
= cfa
;
857 info
->local_base
= cfa
- data
.size
;
860 /* Otherwise, fall back to reading the backchain link. */
863 CORE_ADDR reg
, backchain
;
865 /* Get the backchain. */
866 reg
= frame_unwind_register_unsigned (next_frame
, SPU_SP_REGNUM
);
867 backchain
= read_memory_unsigned_integer (reg
, 4);
869 /* A zero backchain terminates the frame chain. Also, sanity
870 check against the local store size limit. */
871 if (backchain
!= 0 && backchain
< SPU_LS_SIZE
)
873 /* Assume the link register is saved into its slot. */
874 if (backchain
+ 16 < SPU_LS_SIZE
)
875 info
->saved_regs
[SPU_LR_REGNUM
].addr
= backchain
+ 16;
878 info
->frame_base
= backchain
;
879 info
->local_base
= reg
;
883 /* The previous SP is equal to the CFA. */
884 trad_frame_set_value (info
->saved_regs
, SPU_SP_REGNUM
, info
->frame_base
);
886 /* Read full contents of the unwound link register in order to
887 be able to determine the return address. */
888 if (trad_frame_addr_p (info
->saved_regs
, SPU_LR_REGNUM
))
889 target_read_memory (info
->saved_regs
[SPU_LR_REGNUM
].addr
, buf
, 16);
891 frame_unwind_register (next_frame
, SPU_LR_REGNUM
, buf
);
893 /* Normally, the return address is contained in the slot 0 of the
894 link register, and slots 1-3 are zero. For an overlay return,
895 slot 0 contains the address of the overlay manager return stub,
896 slot 1 contains the partition number of the overlay section to
897 be returned to, and slot 2 contains the return address within
898 that section. Return the latter address in that case. */
899 if (extract_unsigned_integer (buf
+ 8, 4) != 0)
900 trad_frame_set_value (info
->saved_regs
, SPU_PC_REGNUM
,
901 extract_unsigned_integer (buf
+ 8, 4));
903 trad_frame_set_value (info
->saved_regs
, SPU_PC_REGNUM
,
904 extract_unsigned_integer (buf
, 4));
910 spu_frame_this_id (struct frame_info
*next_frame
,
911 void **this_prologue_cache
, struct frame_id
*this_id
)
913 struct spu_unwind_cache
*info
=
914 spu_frame_unwind_cache (next_frame
, this_prologue_cache
);
916 if (info
->frame_base
== 0)
919 *this_id
= frame_id_build (info
->frame_base
, info
->func
);
923 spu_frame_prev_register (struct frame_info
*next_frame
,
924 void **this_prologue_cache
,
925 int regnum
, int *optimizedp
,
926 enum lval_type
*lvalp
, CORE_ADDR
* addrp
,
927 int *realnump
, gdb_byte
*bufferp
)
929 struct spu_unwind_cache
*info
930 = spu_frame_unwind_cache (next_frame
, this_prologue_cache
);
932 /* Special-case the stack pointer. */
933 if (regnum
== SPU_RAW_SP_REGNUM
)
934 regnum
= SPU_SP_REGNUM
;
936 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
937 optimizedp
, lvalp
, addrp
, realnump
, bufferp
);
940 static const struct frame_unwind spu_frame_unwind
= {
943 spu_frame_prev_register
946 const struct frame_unwind
*
947 spu_frame_sniffer (struct frame_info
*next_frame
)
949 return &spu_frame_unwind
;
953 spu_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
955 struct spu_unwind_cache
*info
956 = spu_frame_unwind_cache (next_frame
, this_cache
);
957 return info
->local_base
;
960 static const struct frame_base spu_frame_base
= {
962 spu_frame_base_address
,
963 spu_frame_base_address
,
964 spu_frame_base_address
968 spu_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
970 CORE_ADDR pc
= frame_unwind_register_unsigned (next_frame
, SPU_PC_REGNUM
);
971 /* Mask off interrupt enable bit. */
976 spu_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
978 return frame_unwind_register_unsigned (next_frame
, SPU_SP_REGNUM
);
982 spu_read_pc (struct regcache
*regcache
)
985 regcache_cooked_read_unsigned (regcache
, SPU_PC_REGNUM
, &pc
);
986 /* Mask off interrupt enable bit. */
991 spu_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
993 /* Keep interrupt enabled state unchanged. */
995 regcache_cooked_read_unsigned (regcache
, SPU_PC_REGNUM
, &old_pc
);
996 regcache_cooked_write_unsigned (regcache
, SPU_PC_REGNUM
,
997 (pc
& -4) | (old_pc
& 3));
1001 /* Function calling convention. */
1004 spu_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1010 spu_scalar_value_p (struct type
*type
)
1012 switch (TYPE_CODE (type
))
1015 case TYPE_CODE_ENUM
:
1016 case TYPE_CODE_RANGE
:
1017 case TYPE_CODE_CHAR
:
1018 case TYPE_CODE_BOOL
:
1021 return TYPE_LENGTH (type
) <= 16;
1029 spu_value_to_regcache (struct regcache
*regcache
, int regnum
,
1030 struct type
*type
, const gdb_byte
*in
)
1032 int len
= TYPE_LENGTH (type
);
1034 if (spu_scalar_value_p (type
))
1036 int preferred_slot
= len
< 4 ? 4 - len
: 0;
1037 regcache_cooked_write_part (regcache
, regnum
, preferred_slot
, len
, in
);
1043 regcache_cooked_write (regcache
, regnum
++, in
);
1049 regcache_cooked_write_part (regcache
, regnum
, 0, len
, in
);
1054 spu_regcache_to_value (struct regcache
*regcache
, int regnum
,
1055 struct type
*type
, gdb_byte
*out
)
1057 int len
= TYPE_LENGTH (type
);
1059 if (spu_scalar_value_p (type
))
1061 int preferred_slot
= len
< 4 ? 4 - len
: 0;
1062 regcache_cooked_read_part (regcache
, regnum
, preferred_slot
, len
, out
);
1068 regcache_cooked_read (regcache
, regnum
++, out
);
1074 regcache_cooked_read_part (regcache
, regnum
, 0, len
, out
);
1079 spu_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1080 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1081 int nargs
, struct value
**args
, CORE_ADDR sp
,
1082 int struct_return
, CORE_ADDR struct_addr
)
1085 int regnum
= SPU_ARG1_REGNUM
;
1089 /* Set the return address. */
1090 memset (buf
, 0, sizeof buf
);
1091 store_unsigned_integer (buf
, 4, bp_addr
);
1092 regcache_cooked_write (regcache
, SPU_LR_REGNUM
, buf
);
1094 /* If STRUCT_RETURN is true, then the struct return address (in
1095 STRUCT_ADDR) will consume the first argument-passing register.
1096 Both adjust the register count and store that value. */
1099 memset (buf
, 0, sizeof buf
);
1100 store_unsigned_integer (buf
, 4, struct_addr
);
1101 regcache_cooked_write (regcache
, regnum
++, buf
);
1104 /* Fill in argument registers. */
1105 for (i
= 0; i
< nargs
; i
++)
1107 struct value
*arg
= args
[i
];
1108 struct type
*type
= check_typedef (value_type (arg
));
1109 const gdb_byte
*contents
= value_contents (arg
);
1110 int len
= TYPE_LENGTH (type
);
1111 int n_regs
= align_up (len
, 16) / 16;
1113 /* If the argument doesn't wholly fit into registers, it and
1114 all subsequent arguments go to the stack. */
1115 if (regnum
+ n_regs
- 1 > SPU_ARGN_REGNUM
)
1121 spu_value_to_regcache (regcache
, regnum
, type
, contents
);
1125 /* Overflow arguments go to the stack. */
1126 if (stack_arg
!= -1)
1130 /* Allocate all required stack size. */
1131 for (i
= stack_arg
; i
< nargs
; i
++)
1133 struct type
*type
= check_typedef (value_type (args
[i
]));
1134 sp
-= align_up (TYPE_LENGTH (type
), 16);
1137 /* Fill in stack arguments. */
1139 for (i
= stack_arg
; i
< nargs
; i
++)
1141 struct value
*arg
= args
[i
];
1142 struct type
*type
= check_typedef (value_type (arg
));
1143 int len
= TYPE_LENGTH (type
);
1146 if (spu_scalar_value_p (type
))
1147 preferred_slot
= len
< 4 ? 4 - len
: 0;
1151 target_write_memory (ap
+ preferred_slot
, value_contents (arg
), len
);
1152 ap
+= align_up (TYPE_LENGTH (type
), 16);
1156 /* Allocate stack frame header. */
1159 /* Store stack back chain. */
1160 regcache_cooked_read (regcache
, SPU_RAW_SP_REGNUM
, buf
);
1161 target_write_memory (sp
, buf
, 16);
1163 /* Finally, update the SP register. */
1164 regcache_cooked_write_unsigned (regcache
, SPU_SP_REGNUM
, sp
);
1169 static struct frame_id
1170 spu_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1172 return frame_id_build (spu_unwind_sp (gdbarch
, next_frame
),
1173 spu_unwind_pc (gdbarch
, next_frame
));
1176 /* Function return value access. */
1178 static enum return_value_convention
1179 spu_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1180 struct regcache
*regcache
, gdb_byte
*out
, const gdb_byte
*in
)
1182 enum return_value_convention rvc
;
1184 if (TYPE_LENGTH (type
) <= (SPU_ARGN_REGNUM
- SPU_ARG1_REGNUM
+ 1) * 16)
1185 rvc
= RETURN_VALUE_REGISTER_CONVENTION
;
1187 rvc
= RETURN_VALUE_STRUCT_CONVENTION
;
1193 case RETURN_VALUE_REGISTER_CONVENTION
:
1194 spu_value_to_regcache (regcache
, SPU_ARG1_REGNUM
, type
, in
);
1197 case RETURN_VALUE_STRUCT_CONVENTION
:
1198 error ("Cannot set function return value.");
1206 case RETURN_VALUE_REGISTER_CONVENTION
:
1207 spu_regcache_to_value (regcache
, SPU_ARG1_REGNUM
, type
, out
);
1210 case RETURN_VALUE_STRUCT_CONVENTION
:
1211 error ("Function return value unknown.");
1222 static const gdb_byte
*
1223 spu_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
1225 static const gdb_byte breakpoint
[] = { 0x00, 0x00, 0x3f, 0xff };
1227 *lenptr
= sizeof breakpoint
;
1232 /* Software single-stepping support. */
1235 spu_software_single_step (struct frame_info
*frame
)
1237 CORE_ADDR pc
, next_pc
;
1242 pc
= get_frame_pc (frame
);
1244 if (target_read_memory (pc
, buf
, 4))
1246 insn
= extract_unsigned_integer (buf
, 4);
1248 /* Next sequential instruction is at PC + 4, except if the current
1249 instruction is a PPE-assisted call, in which case it is at PC + 8.
1250 Wrap around LS limit to be on the safe side. */
1251 if ((insn
& 0xffffff00) == 0x00002100)
1252 next_pc
= (pc
+ 8) & (SPU_LS_SIZE
- 1);
1254 next_pc
= (pc
+ 4) & (SPU_LS_SIZE
- 1);
1256 insert_single_step_breakpoint (next_pc
);
1258 if (is_branch (insn
, &offset
, ®
))
1260 CORE_ADDR target
= offset
;
1262 if (reg
== SPU_PC_REGNUM
)
1266 get_frame_register_bytes (frame
, reg
, 0, 4, buf
);
1267 target
+= extract_unsigned_integer (buf
, 4) & -4;
1270 target
= target
& (SPU_LS_SIZE
- 1);
1271 if (target
!= next_pc
)
1272 insert_single_step_breakpoint (target
);
1278 /* Target overlays for the SPU overlay manager.
1280 See the documentation of simple_overlay_update for how the
1281 interface is supposed to work.
1283 Data structures used by the overlay manager:
1291 } _ovly_table[]; -- one entry per overlay section
1293 struct ovly_buf_table
1296 } _ovly_buf_table[]; -- one entry per overlay buffer
1298 _ovly_table should never change.
1300 Both tables are aligned to a 16-byte boundary, the symbols _ovly_table
1301 and _ovly_buf_table are of type STT_OBJECT and their size set to the size
1302 of the respective array. buf in _ovly_table is an index into _ovly_buf_table.
1304 mapped is an index into _ovly_table. Both the mapped and buf indices start
1305 from one to reference the first entry in their respective tables. */
1307 /* Using the per-objfile private data mechanism, we store for each
1308 objfile an array of "struct spu_overlay_table" structures, one
1309 for each obj_section of the objfile. This structure holds two
1310 fields, MAPPED_PTR and MAPPED_VAL. If MAPPED_PTR is zero, this
1311 is *not* an overlay section. If it is non-zero, it represents
1312 a target address. The overlay section is mapped iff the target
1313 integer at this location equals MAPPED_VAL. */
1315 static const struct objfile_data
*spu_overlay_data
;
1317 struct spu_overlay_table
1319 CORE_ADDR mapped_ptr
;
1320 CORE_ADDR mapped_val
;
1323 /* Retrieve the overlay table for OBJFILE. If not already cached, read
1324 the _ovly_table data structure from the target and initialize the
1325 spu_overlay_table data structure from it. */
1326 static struct spu_overlay_table
*
1327 spu_get_overlay_table (struct objfile
*objfile
)
1329 struct minimal_symbol
*ovly_table_msym
, *ovly_buf_table_msym
;
1330 CORE_ADDR ovly_table_base
, ovly_buf_table_base
;
1331 unsigned ovly_table_size
, ovly_buf_table_size
;
1332 struct spu_overlay_table
*tbl
;
1333 struct obj_section
*osect
;
1337 tbl
= objfile_data (objfile
, spu_overlay_data
);
1341 ovly_table_msym
= lookup_minimal_symbol ("_ovly_table", NULL
, objfile
);
1342 if (!ovly_table_msym
)
1345 ovly_buf_table_msym
= lookup_minimal_symbol ("_ovly_buf_table", NULL
, objfile
);
1346 if (!ovly_buf_table_msym
)
1349 ovly_table_base
= SYMBOL_VALUE_ADDRESS (ovly_table_msym
);
1350 ovly_table_size
= MSYMBOL_SIZE (ovly_table_msym
);
1352 ovly_buf_table_base
= SYMBOL_VALUE_ADDRESS (ovly_buf_table_msym
);
1353 ovly_buf_table_size
= MSYMBOL_SIZE (ovly_buf_table_msym
);
1355 ovly_table
= xmalloc (ovly_table_size
);
1356 read_memory (ovly_table_base
, ovly_table
, ovly_table_size
);
1358 tbl
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
1359 objfile
->sections_end
- objfile
->sections
,
1360 struct spu_overlay_table
);
1362 for (i
= 0; i
< ovly_table_size
/ 16; i
++)
1364 CORE_ADDR vma
= extract_unsigned_integer (ovly_table
+ 16*i
+ 0, 4);
1365 CORE_ADDR size
= extract_unsigned_integer (ovly_table
+ 16*i
+ 4, 4);
1366 CORE_ADDR pos
= extract_unsigned_integer (ovly_table
+ 16*i
+ 8, 4);
1367 CORE_ADDR buf
= extract_unsigned_integer (ovly_table
+ 16*i
+ 12, 4);
1369 if (buf
== 0 || (buf
- 1) * 4 >= ovly_buf_table_size
)
1372 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
1373 if (vma
== bfd_section_vma (objfile
->obfd
, osect
->the_bfd_section
)
1374 && pos
== osect
->the_bfd_section
->filepos
)
1376 int ndx
= osect
- objfile
->sections
;
1377 tbl
[ndx
].mapped_ptr
= ovly_buf_table_base
+ (buf
- 1) * 4;
1378 tbl
[ndx
].mapped_val
= i
+ 1;
1384 set_objfile_data (objfile
, spu_overlay_data
, tbl
);
1388 /* Read _ovly_buf_table entry from the target to dermine whether
1389 OSECT is currently mapped, and update the mapped state. */
1391 spu_overlay_update_osect (struct obj_section
*osect
)
1393 struct spu_overlay_table
*ovly_table
;
1396 ovly_table
= spu_get_overlay_table (osect
->objfile
);
1400 ovly_table
+= osect
- osect
->objfile
->sections
;
1401 if (ovly_table
->mapped_ptr
== 0)
1404 val
= read_memory_unsigned_integer (ovly_table
->mapped_ptr
, 4);
1405 osect
->ovly_mapped
= (val
== ovly_table
->mapped_val
);
1408 /* If OSECT is NULL, then update all sections' mapped state.
1409 If OSECT is non-NULL, then update only OSECT's mapped state. */
1411 spu_overlay_update (struct obj_section
*osect
)
1413 /* Just one section. */
1415 spu_overlay_update_osect (osect
);
1420 struct objfile
*objfile
;
1422 ALL_OBJSECTIONS (objfile
, osect
)
1423 if (section_is_overlay (osect
->the_bfd_section
))
1424 spu_overlay_update_osect (osect
);
1428 /* Whenever a new objfile is loaded, read the target's _ovly_table.
1429 If there is one, go through all sections and make sure for non-
1430 overlay sections LMA equals VMA, while for overlay sections LMA
1431 is larger than local store size. */
1433 spu_overlay_new_objfile (struct objfile
*objfile
)
1435 struct spu_overlay_table
*ovly_table
;
1436 struct obj_section
*osect
;
1438 /* If we've already touched this file, do nothing. */
1439 if (!objfile
|| objfile_data (objfile
, spu_overlay_data
) != NULL
)
1442 /* Check if this objfile has overlays. */
1443 ovly_table
= spu_get_overlay_table (objfile
);
1447 /* Now go and fiddle with all the LMAs. */
1448 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
1450 bfd
*obfd
= objfile
->obfd
;
1451 asection
*bsect
= osect
->the_bfd_section
;
1452 int ndx
= osect
- objfile
->sections
;
1454 if (ovly_table
[ndx
].mapped_ptr
== 0)
1455 bfd_section_lma (obfd
, bsect
) = bfd_section_vma (obfd
, bsect
);
1457 bfd_section_lma (obfd
, bsect
) = bsect
->filepos
+ SPU_LS_SIZE
;
1462 /* "info spu" commands. */
1465 info_spu_event_command (char *args
, int from_tty
)
1467 struct frame_info
*frame
= get_selected_frame (NULL
);
1468 ULONGEST event_status
= 0;
1469 ULONGEST event_mask
= 0;
1470 struct cleanup
*chain
;
1476 id
= get_frame_register_unsigned (frame
, SPU_ID_REGNUM
);
1478 xsnprintf (annex
, sizeof annex
, "%d/event_status", id
);
1479 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1480 buf
, 0, sizeof buf
);
1482 error (_("Could not read event_status."));
1483 event_status
= strtoulst (buf
, NULL
, 16);
1485 xsnprintf (annex
, sizeof annex
, "%d/event_mask", id
);
1486 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1487 buf
, 0, sizeof buf
);
1489 error (_("Could not read event_mask."));
1490 event_mask
= strtoulst (buf
, NULL
, 16);
1492 chain
= make_cleanup_ui_out_tuple_begin_end (uiout
, "SPUInfoEvent");
1494 if (ui_out_is_mi_like_p (uiout
))
1496 ui_out_field_fmt (uiout
, "event_status",
1497 "0x%s", phex_nz (event_status
, 4));
1498 ui_out_field_fmt (uiout
, "event_mask",
1499 "0x%s", phex_nz (event_mask
, 4));
1503 printf_filtered (_("Event Status 0x%s\n"), phex (event_status
, 4));
1504 printf_filtered (_("Event Mask 0x%s\n"), phex (event_mask
, 4));
1507 do_cleanups (chain
);
1511 info_spu_signal_command (char *args
, int from_tty
)
1513 struct frame_info
*frame
= get_selected_frame (NULL
);
1514 ULONGEST signal1
= 0;
1515 ULONGEST signal1_type
= 0;
1516 int signal1_pending
= 0;
1517 ULONGEST signal2
= 0;
1518 ULONGEST signal2_type
= 0;
1519 int signal2_pending
= 0;
1520 struct cleanup
*chain
;
1526 id
= get_frame_register_unsigned (frame
, SPU_ID_REGNUM
);
1528 xsnprintf (annex
, sizeof annex
, "%d/signal1", id
);
1529 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
, buf
, 0, 4);
1531 error (_("Could not read signal1."));
1534 signal1
= extract_unsigned_integer (buf
, 4);
1535 signal1_pending
= 1;
1538 xsnprintf (annex
, sizeof annex
, "%d/signal1_type", id
);
1539 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1540 buf
, 0, sizeof buf
);
1542 error (_("Could not read signal1_type."));
1543 signal1_type
= strtoulst (buf
, NULL
, 16);
1545 xsnprintf (annex
, sizeof annex
, "%d/signal2", id
);
1546 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
, buf
, 0, 4);
1548 error (_("Could not read signal2."));
1551 signal2
= extract_unsigned_integer (buf
, 4);
1552 signal2_pending
= 1;
1555 xsnprintf (annex
, sizeof annex
, "%d/signal2_type", id
);
1556 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1557 buf
, 0, sizeof buf
);
1559 error (_("Could not read signal2_type."));
1560 signal2_type
= strtoulst (buf
, NULL
, 16);
1562 chain
= make_cleanup_ui_out_tuple_begin_end (uiout
, "SPUInfoSignal");
1564 if (ui_out_is_mi_like_p (uiout
))
1566 ui_out_field_int (uiout
, "signal1_pending", signal1_pending
);
1567 ui_out_field_fmt (uiout
, "signal1", "0x%s", phex_nz (signal1
, 4));
1568 ui_out_field_int (uiout
, "signal1_type", signal1_type
);
1569 ui_out_field_int (uiout
, "signal2_pending", signal2_pending
);
1570 ui_out_field_fmt (uiout
, "signal2", "0x%s", phex_nz (signal2
, 4));
1571 ui_out_field_int (uiout
, "signal2_type", signal2_type
);
1575 if (signal1_pending
)
1576 printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1
, 4));
1578 printf_filtered (_("Signal 1 not pending "));
1581 printf_filtered (_("(Type Overwrite)\n"));
1583 printf_filtered (_("(Type Or)\n"));
1585 if (signal2_pending
)
1586 printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2
, 4));
1588 printf_filtered (_("Signal 2 not pending "));
1591 printf_filtered (_("(Type Overwrite)\n"));
1593 printf_filtered (_("(Type Or)\n"));
1596 do_cleanups (chain
);
1600 info_spu_mailbox_list (gdb_byte
*buf
, int nr
,
1601 const char *field
, const char *msg
)
1603 struct cleanup
*chain
;
1609 chain
= make_cleanup_ui_out_table_begin_end (uiout
, 1, nr
, "mbox");
1611 ui_out_table_header (uiout
, 32, ui_left
, field
, msg
);
1612 ui_out_table_body (uiout
);
1614 for (i
= 0; i
< nr
; i
++)
1616 struct cleanup
*val_chain
;
1618 val_chain
= make_cleanup_ui_out_tuple_begin_end (uiout
, "mbox");
1619 val
= extract_unsigned_integer (buf
+ 4*i
, 4);
1620 ui_out_field_fmt (uiout
, field
, "0x%s", phex (val
, 4));
1621 do_cleanups (val_chain
);
1623 if (!ui_out_is_mi_like_p (uiout
))
1624 printf_filtered ("\n");
1627 do_cleanups (chain
);
1631 info_spu_mailbox_command (char *args
, int from_tty
)
1633 struct frame_info
*frame
= get_selected_frame (NULL
);
1634 struct cleanup
*chain
;
1640 id
= get_frame_register_unsigned (frame
, SPU_ID_REGNUM
);
1642 chain
= make_cleanup_ui_out_tuple_begin_end (uiout
, "SPUInfoMailbox");
1644 xsnprintf (annex
, sizeof annex
, "%d/mbox_info", id
);
1645 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1646 buf
, 0, sizeof buf
);
1648 error (_("Could not read mbox_info."));
1650 info_spu_mailbox_list (buf
, len
/ 4, "mbox", "SPU Outbound Mailbox");
1652 xsnprintf (annex
, sizeof annex
, "%d/ibox_info", id
);
1653 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1654 buf
, 0, sizeof buf
);
1656 error (_("Could not read ibox_info."));
1658 info_spu_mailbox_list (buf
, len
/ 4, "ibox", "SPU Outbound Interrupt Mailbox");
1660 xsnprintf (annex
, sizeof annex
, "%d/wbox_info", id
);
1661 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1662 buf
, 0, sizeof buf
);
1664 error (_("Could not read wbox_info."));
1666 info_spu_mailbox_list (buf
, len
/ 4, "wbox", "SPU Inbound Mailbox");
1668 do_cleanups (chain
);
1672 spu_mfc_get_bitfield (ULONGEST word
, int first
, int last
)
1674 ULONGEST mask
= ~(~(ULONGEST
)0 << (last
- first
+ 1));
1675 return (word
>> (63 - last
)) & mask
;
1679 info_spu_dma_cmdlist (gdb_byte
*buf
, int nr
)
1681 static char *spu_mfc_opcode
[256] =
1683 /* 00 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1684 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1685 /* 10 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1686 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1687 /* 20 */ "put", "putb", "putf", NULL
, "putl", "putlb", "putlf", NULL
,
1688 "puts", "putbs", "putfs", NULL
, NULL
, NULL
, NULL
, NULL
,
1689 /* 30 */ "putr", "putrb", "putrf", NULL
, "putrl", "putrlb", "putrlf", NULL
,
1690 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1691 /* 40 */ "get", "getb", "getf", NULL
, "getl", "getlb", "getlf", NULL
,
1692 "gets", "getbs", "getfs", NULL
, NULL
, NULL
, NULL
, NULL
,
1693 /* 50 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1694 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1695 /* 60 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1696 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1697 /* 70 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1698 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1699 /* 80 */ "sdcrt", "sdcrtst", NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1700 NULL
, "sdcrz", NULL
, NULL
, NULL
, "sdcrst", NULL
, "sdcrf",
1701 /* 90 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1702 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1703 /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL
, NULL
, NULL
, NULL
, NULL
,
1704 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1705 /* b0 */ "putlluc", NULL
, NULL
, NULL
, "putllc", NULL
, NULL
, NULL
,
1706 "putqlluc", NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1707 /* c0 */ "barrier", NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1708 "mfceieio", NULL
, NULL
, NULL
, "mfcsync", NULL
, NULL
, NULL
,
1709 /* d0 */ "getllar", NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1710 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1711 /* e0 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1712 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1713 /* f0 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1714 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1717 struct cleanup
*chain
;
1720 chain
= make_cleanup_ui_out_table_begin_end (uiout
, 10, nr
, "dma_cmd");
1722 ui_out_table_header (uiout
, 7, ui_left
, "opcode", "Opcode");
1723 ui_out_table_header (uiout
, 3, ui_left
, "tag", "Tag");
1724 ui_out_table_header (uiout
, 3, ui_left
, "tid", "TId");
1725 ui_out_table_header (uiout
, 3, ui_left
, "rid", "RId");
1726 ui_out_table_header (uiout
, 18, ui_left
, "ea", "EA");
1727 ui_out_table_header (uiout
, 7, ui_left
, "lsa", "LSA");
1728 ui_out_table_header (uiout
, 7, ui_left
, "size", "Size");
1729 ui_out_table_header (uiout
, 7, ui_left
, "lstaddr", "LstAddr");
1730 ui_out_table_header (uiout
, 7, ui_left
, "lstsize", "LstSize");
1731 ui_out_table_header (uiout
, 1, ui_left
, "error_p", "E");
1733 ui_out_table_body (uiout
);
1735 for (i
= 0; i
< nr
; i
++)
1737 struct cleanup
*cmd_chain
;
1738 ULONGEST mfc_cq_dw0
;
1739 ULONGEST mfc_cq_dw1
;
1740 ULONGEST mfc_cq_dw2
;
1741 ULONGEST mfc_cq_dw3
;
1742 int mfc_cmd_opcode
, mfc_cmd_tag
, rclass_id
, tclass_id
;
1743 int lsa
, size
, list_lsa
, list_size
, mfc_lsa
, mfc_size
;
1745 int list_valid_p
, noop_valid_p
, qw_valid_p
, ea_valid_p
, cmd_error_p
;
1747 /* Decode contents of MFC Command Queue Context Save/Restore Registers.
1748 See "Cell Broadband Engine Registers V1.3", section 3.3.2.1. */
1750 mfc_cq_dw0
= extract_unsigned_integer (buf
+ 32*i
, 8);
1751 mfc_cq_dw1
= extract_unsigned_integer (buf
+ 32*i
+ 8, 8);
1752 mfc_cq_dw2
= extract_unsigned_integer (buf
+ 32*i
+ 16, 8);
1753 mfc_cq_dw3
= extract_unsigned_integer (buf
+ 32*i
+ 24, 8);
1755 list_lsa
= spu_mfc_get_bitfield (mfc_cq_dw0
, 0, 14);
1756 list_size
= spu_mfc_get_bitfield (mfc_cq_dw0
, 15, 26);
1757 mfc_cmd_opcode
= spu_mfc_get_bitfield (mfc_cq_dw0
, 27, 34);
1758 mfc_cmd_tag
= spu_mfc_get_bitfield (mfc_cq_dw0
, 35, 39);
1759 list_valid_p
= spu_mfc_get_bitfield (mfc_cq_dw0
, 40, 40);
1760 rclass_id
= spu_mfc_get_bitfield (mfc_cq_dw0
, 41, 43);
1761 tclass_id
= spu_mfc_get_bitfield (mfc_cq_dw0
, 44, 46);
1763 mfc_ea
= spu_mfc_get_bitfield (mfc_cq_dw1
, 0, 51) << 12
1764 | spu_mfc_get_bitfield (mfc_cq_dw2
, 25, 36);
1766 mfc_lsa
= spu_mfc_get_bitfield (mfc_cq_dw2
, 0, 13);
1767 mfc_size
= spu_mfc_get_bitfield (mfc_cq_dw2
, 14, 24);
1768 noop_valid_p
= spu_mfc_get_bitfield (mfc_cq_dw2
, 37, 37);
1769 qw_valid_p
= spu_mfc_get_bitfield (mfc_cq_dw2
, 38, 38);
1770 ea_valid_p
= spu_mfc_get_bitfield (mfc_cq_dw2
, 39, 39);
1771 cmd_error_p
= spu_mfc_get_bitfield (mfc_cq_dw2
, 40, 40);
1773 cmd_chain
= make_cleanup_ui_out_tuple_begin_end (uiout
, "cmd");
1775 if (spu_mfc_opcode
[mfc_cmd_opcode
])
1776 ui_out_field_string (uiout
, "opcode", spu_mfc_opcode
[mfc_cmd_opcode
]);
1778 ui_out_field_int (uiout
, "opcode", mfc_cmd_opcode
);
1780 ui_out_field_int (uiout
, "tag", mfc_cmd_tag
);
1781 ui_out_field_int (uiout
, "tid", tclass_id
);
1782 ui_out_field_int (uiout
, "rid", rclass_id
);
1785 ui_out_field_fmt (uiout
, "ea", "0x%s", phex (mfc_ea
, 8));
1787 ui_out_field_skip (uiout
, "ea");
1789 ui_out_field_fmt (uiout
, "lsa", "0x%05x", mfc_lsa
<< 4);
1791 ui_out_field_fmt (uiout
, "size", "0x%05x", mfc_size
<< 4);
1793 ui_out_field_fmt (uiout
, "size", "0x%05x", mfc_size
);
1797 ui_out_field_fmt (uiout
, "lstaddr", "0x%05x", list_lsa
<< 3);
1798 ui_out_field_fmt (uiout
, "lstsize", "0x%05x", list_size
<< 3);
1802 ui_out_field_skip (uiout
, "lstaddr");
1803 ui_out_field_skip (uiout
, "lstsize");
1807 ui_out_field_string (uiout
, "error_p", "*");
1809 ui_out_field_skip (uiout
, "error_p");
1811 do_cleanups (cmd_chain
);
1813 if (!ui_out_is_mi_like_p (uiout
))
1814 printf_filtered ("\n");
1817 do_cleanups (chain
);
1821 info_spu_dma_command (char *args
, int from_tty
)
1823 struct frame_info
*frame
= get_selected_frame (NULL
);
1824 ULONGEST dma_info_type
;
1825 ULONGEST dma_info_mask
;
1826 ULONGEST dma_info_status
;
1827 ULONGEST dma_info_stall_and_notify
;
1828 ULONGEST dma_info_atomic_command_status
;
1829 struct cleanup
*chain
;
1835 id
= get_frame_register_unsigned (frame
, SPU_ID_REGNUM
);
1837 xsnprintf (annex
, sizeof annex
, "%d/dma_info", id
);
1838 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1839 buf
, 0, 40 + 16 * 32);
1841 error (_("Could not read dma_info."));
1843 dma_info_type
= extract_unsigned_integer (buf
, 8);
1844 dma_info_mask
= extract_unsigned_integer (buf
+ 8, 8);
1845 dma_info_status
= extract_unsigned_integer (buf
+ 16, 8);
1846 dma_info_stall_and_notify
= extract_unsigned_integer (buf
+ 24, 8);
1847 dma_info_atomic_command_status
= extract_unsigned_integer (buf
+ 32, 8);
1849 chain
= make_cleanup_ui_out_tuple_begin_end (uiout
, "SPUInfoDMA");
1851 if (ui_out_is_mi_like_p (uiout
))
1853 ui_out_field_fmt (uiout
, "dma_info_type", "0x%s",
1854 phex_nz (dma_info_type
, 4));
1855 ui_out_field_fmt (uiout
, "dma_info_mask", "0x%s",
1856 phex_nz (dma_info_mask
, 4));
1857 ui_out_field_fmt (uiout
, "dma_info_status", "0x%s",
1858 phex_nz (dma_info_status
, 4));
1859 ui_out_field_fmt (uiout
, "dma_info_stall_and_notify", "0x%s",
1860 phex_nz (dma_info_stall_and_notify
, 4));
1861 ui_out_field_fmt (uiout
, "dma_info_atomic_command_status", "0x%s",
1862 phex_nz (dma_info_atomic_command_status
, 4));
1866 const char *query_msg
;
1868 switch (dma_info_type
)
1870 case 0: query_msg
= _("no query pending"); break;
1871 case 1: query_msg
= _("'any' query pending"); break;
1872 case 2: query_msg
= _("'all' query pending"); break;
1873 default: query_msg
= _("undefined query type"); break;
1876 printf_filtered (_("Tag-Group Status 0x%s\n"),
1877 phex (dma_info_status
, 4));
1878 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
1879 phex (dma_info_mask
, 4), query_msg
);
1880 printf_filtered (_("Stall-and-Notify 0x%s\n"),
1881 phex (dma_info_stall_and_notify
, 4));
1882 printf_filtered (_("Atomic Cmd Status 0x%s\n"),
1883 phex (dma_info_atomic_command_status
, 4));
1884 printf_filtered ("\n");
1887 info_spu_dma_cmdlist (buf
+ 40, 16);
1888 do_cleanups (chain
);
1892 info_spu_proxydma_command (char *args
, int from_tty
)
1894 struct frame_info
*frame
= get_selected_frame (NULL
);
1895 ULONGEST dma_info_type
;
1896 ULONGEST dma_info_mask
;
1897 ULONGEST dma_info_status
;
1898 struct cleanup
*chain
;
1904 id
= get_frame_register_unsigned (frame
, SPU_ID_REGNUM
);
1906 xsnprintf (annex
, sizeof annex
, "%d/proxydma_info", id
);
1907 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1908 buf
, 0, 24 + 8 * 32);
1910 error (_("Could not read proxydma_info."));
1912 dma_info_type
= extract_unsigned_integer (buf
, 8);
1913 dma_info_mask
= extract_unsigned_integer (buf
+ 8, 8);
1914 dma_info_status
= extract_unsigned_integer (buf
+ 16, 8);
1916 chain
= make_cleanup_ui_out_tuple_begin_end (uiout
, "SPUInfoProxyDMA");
1918 if (ui_out_is_mi_like_p (uiout
))
1920 ui_out_field_fmt (uiout
, "proxydma_info_type", "0x%s",
1921 phex_nz (dma_info_type
, 4));
1922 ui_out_field_fmt (uiout
, "proxydma_info_mask", "0x%s",
1923 phex_nz (dma_info_mask
, 4));
1924 ui_out_field_fmt (uiout
, "proxydma_info_status", "0x%s",
1925 phex_nz (dma_info_status
, 4));
1929 const char *query_msg
;
1931 switch (dma_info_type
)
1933 case 0: query_msg
= _("no query pending"); break;
1934 case 1: query_msg
= _("'any' query pending"); break;
1935 case 2: query_msg
= _("'all' query pending"); break;
1936 default: query_msg
= _("undefined query type"); break;
1939 printf_filtered (_("Tag-Group Status 0x%s\n"),
1940 phex (dma_info_status
, 4));
1941 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
1942 phex (dma_info_mask
, 4), query_msg
);
1943 printf_filtered ("\n");
1946 info_spu_dma_cmdlist (buf
+ 24, 8);
1947 do_cleanups (chain
);
1951 info_spu_command (char *args
, int from_tty
)
1953 printf_unfiltered (_("\"info spu\" must be followed by the name of an SPU facility.\n"));
1954 help_list (infospucmdlist
, "info spu ", -1, gdb_stdout
);
1958 /* Set up gdbarch struct. */
1960 static struct gdbarch
*
1961 spu_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1963 struct gdbarch
*gdbarch
;
1964 struct gdbarch_tdep
*tdep
;
1966 /* Find a candidate among the list of pre-declared architectures. */
1967 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1969 return arches
->gdbarch
;
1972 if (info
.bfd_arch_info
->mach
!= bfd_mach_spu
)
1975 /* Yes, create a new architecture. */
1976 tdep
= XCALLOC (1, struct gdbarch_tdep
);
1977 gdbarch
= gdbarch_alloc (&info
, tdep
);
1980 set_gdbarch_print_insn (gdbarch
, print_insn_spu
);
1983 set_gdbarch_num_regs (gdbarch
, SPU_NUM_REGS
);
1984 set_gdbarch_num_pseudo_regs (gdbarch
, SPU_NUM_PSEUDO_REGS
);
1985 set_gdbarch_sp_regnum (gdbarch
, SPU_SP_REGNUM
);
1986 set_gdbarch_pc_regnum (gdbarch
, SPU_PC_REGNUM
);
1987 set_gdbarch_read_pc (gdbarch
, spu_read_pc
);
1988 set_gdbarch_write_pc (gdbarch
, spu_write_pc
);
1989 set_gdbarch_register_name (gdbarch
, spu_register_name
);
1990 set_gdbarch_register_type (gdbarch
, spu_register_type
);
1991 set_gdbarch_pseudo_register_read (gdbarch
, spu_pseudo_register_read
);
1992 set_gdbarch_pseudo_register_write (gdbarch
, spu_pseudo_register_write
);
1993 set_gdbarch_value_from_register (gdbarch
, spu_value_from_register
);
1994 set_gdbarch_register_reggroup_p (gdbarch
, spu_register_reggroup_p
);
1997 set_gdbarch_char_signed (gdbarch
, 0);
1998 set_gdbarch_ptr_bit (gdbarch
, 32);
1999 set_gdbarch_addr_bit (gdbarch
, 32);
2000 set_gdbarch_short_bit (gdbarch
, 16);
2001 set_gdbarch_int_bit (gdbarch
, 32);
2002 set_gdbarch_long_bit (gdbarch
, 32);
2003 set_gdbarch_long_long_bit (gdbarch
, 64);
2004 set_gdbarch_float_bit (gdbarch
, 32);
2005 set_gdbarch_double_bit (gdbarch
, 64);
2006 set_gdbarch_long_double_bit (gdbarch
, 64);
2007 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
2008 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
2009 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
2011 /* Inferior function calls. */
2012 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
2013 set_gdbarch_frame_align (gdbarch
, spu_frame_align
);
2014 set_gdbarch_push_dummy_call (gdbarch
, spu_push_dummy_call
);
2015 set_gdbarch_unwind_dummy_id (gdbarch
, spu_unwind_dummy_id
);
2016 set_gdbarch_return_value (gdbarch
, spu_return_value
);
2018 /* Frame handling. */
2019 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2020 frame_unwind_append_sniffer (gdbarch
, spu_frame_sniffer
);
2021 frame_base_set_default (gdbarch
, &spu_frame_base
);
2022 set_gdbarch_unwind_pc (gdbarch
, spu_unwind_pc
);
2023 set_gdbarch_unwind_sp (gdbarch
, spu_unwind_sp
);
2024 set_gdbarch_virtual_frame_pointer (gdbarch
, spu_virtual_frame_pointer
);
2025 set_gdbarch_frame_args_skip (gdbarch
, 0);
2026 set_gdbarch_skip_prologue (gdbarch
, spu_skip_prologue
);
2027 set_gdbarch_in_function_epilogue_p (gdbarch
, spu_in_function_epilogue_p
);
2030 set_gdbarch_decr_pc_after_break (gdbarch
, 4);
2031 set_gdbarch_breakpoint_from_pc (gdbarch
, spu_breakpoint_from_pc
);
2032 set_gdbarch_cannot_step_breakpoint (gdbarch
, 1);
2033 set_gdbarch_software_single_step (gdbarch
, spu_software_single_step
);
2036 set_gdbarch_overlay_update (gdbarch
, spu_overlay_update
);
2042 _initialize_spu_tdep (void)
2044 register_gdbarch_init (bfd_arch_spu
, spu_gdbarch_init
);
2046 /* Add ourselves to objfile event chain. */
2047 observer_attach_new_objfile (spu_overlay_new_objfile
);
2048 spu_overlay_data
= register_objfile_data ();
2050 /* Add root prefix command for all "info spu" commands. */
2051 add_prefix_cmd ("spu", class_info
, info_spu_command
,
2052 _("Various SPU specific commands."),
2053 &infospucmdlist
, "info spu ", 0, &infolist
);
2055 /* Add various "info spu" commands. */
2056 add_cmd ("event", class_info
, info_spu_event_command
,
2057 _("Display SPU event facility status.\n"),
2059 add_cmd ("signal", class_info
, info_spu_signal_command
,
2060 _("Display SPU signal notification facility status.\n"),
2062 add_cmd ("mailbox", class_info
, info_spu_mailbox_command
,
2063 _("Display SPU mailbox facility status.\n"),
2065 add_cmd ("dma", class_info
, info_spu_dma_command
,
2066 _("Display MFC DMA status.\n"),
2068 add_cmd ("proxydma", class_info
, info_spu_proxydma_command
,
2069 _("Display MFC Proxy-DMA status.\n"),