gdb/testsuite/gdb.arch/s390-vregs.exp

   1 # Copyright 2015 Free Software Foundation, Inc.
   2
   3 # This program is free software; you can redistribute it and/or modify
   4 # it under the terms of the GNU General Public License as published by
   5 # the Free Software Foundation; either version 3 of the License, or
   6 # (at your option) any later version.
   7 #
   8 # This program is distributed in the hope that it will be useful,
   9 # but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 # GNU General Public License for more details.
  12 #
  13 # You should have received a copy of the GNU General Public License
  14 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15
  16 # Test vector register access for s390 platforms.
  17
  18 if { ![istarget s390-*-*] && ![istarget s390x-*-* ] } {
  19     verbose "Skipping s390 vector register tests."
  20     return
  21 }
  22
  23 standard_testfile .S
  24
  25 if [isnative] {
  26     # Create a temporary directory, to take a core dump there later.
  27     set coredir [standard_output_file ${testfile}.d]
  28     remote_exec build "rm -rf $coredir"
  29     remote_exec build "mkdir $coredir"
  30 }
  31
  32 if { [prepare_for_testing ${testfile}.exp $testfile $srcfile] } {
  33     return -1
  34 }
  35
  36 if ![runto_main] {
  37     untested "could not run to main"
  38     return -1
  39 }
  40
  41 # Run to the first vector instruction and step it.  If the inferior
  42 # doesn't crash, we have vector support.
  43
  44 gdb_breakpoint "check_vx"
  45 gdb_continue_to_breakpoint "first vector insn"
  46 set before_pc 0
  47 gdb_test_multiple "x/i \$pc" "get PC at vector insn" {
  48     -re "(0x\\S+)\\s+\\S+\\s+vlr\\s+.*$gdb_prompt $" {
  49         set before_pc $expect_out(1,string)
  50     }
  51 }
  52
  53 gdb_test_multiple "stepi" "check for vector support" {
  54     -re "Program received signal SIGILL,.*\r\n$gdb_prompt $" {
  55         unsupported "no vector support."
  56         return
  57     }
  58     -re "\[0-9\]+.*\r\n$gdb_prompt $" {
  59         pass "vector support available"
  60     }
  61     -re "$gdb_prompt $" {
  62         fail "no vector support (unknown error)"
  63         return
  64     }
  65 }
  66
  67 # Has the PC advanced by the expected amount?  The kernel may do
  68 # something special for the first vector insn in the process.
  69
  70 set after_pc 0
  71 gdb_test_multiple "x/i \$pc" "get PC after vector insn" {
  72     -re "(0x\\S+)\\s+.*$gdb_prompt $" {
  73         set after_pc $expect_out(1,string)
  74     }
  75 }
  76
  77 if [expr $before_pc + 6 != $after_pc] {
  78     fail "stepping first vector insn"
  79 }
  80
  81 # Lift the core file limit, if possible, and change into the temporary
  82 # directory.
  83
  84 if { $coredir != "" } {
  85     gdb_test {print setrlimit (4, &(unsigned long [2]){~0UL, ~0UL})} \
  86         " = .*" "setrlimit"
  87     gdb_test "print chdir (\"${coredir}\")" " = 0" "chdir"
  88 }
  89
  90 # Initialize all vector registers with GDB "set" commands, using
  91 # distinct values.  Handle left and right halves separately, in
  92 # pseudo-random order.
  93
  94 set a_high 1
  95 set a_low 2
  96 set b_high 3
  97 set b_low 5
  98
  99 set a [expr ($a_high << 32) | $a_low]
 100 set b [expr ($b_high << 32) | $b_low]
 101
 102 for {set j 0} {$j < 32} {incr j 1} {
 103     set i [expr 17 * $j % 32]
 104     gdb_test_no_output \
 105         "set \$v$i.v2_int64\[0\] = [expr $a * ($i + 1)]" \
 106         "set v$i left"
 107     set i [expr 19 * (31 - $j) % 32]
 108     gdb_test_no_output \
 109         "set \$v$i.v2_int64\[1\] = [expr $b * (32 - $i)]" \
 110         "set v$i right"
 111 }
 112
 113 # Verify a vector register's union members.
 114
 115 gdb_test "info register v0 v31" \
 116     "v4_float .* v2_double .* v16_int8 .* v8_int16 .* v4_int32 .* v2_int64 .* uint128\
 117      .*v4_float .* v2_double .* v16_int8 .* v8_int16 .* v4_int32 .* v2_int64 .* uint128 .*"
 118
 119 # Let the inferior store all vector registers in a buffer, then dump
 120 # the buffer and check it.
 121
 122 gdb_continue_to_breakpoint "store vrs"
 123 set vregs [capture_command_output "x/64xg &save_area" ""]
 124
 125 set i 0
 126 foreach {- left right} [regexp -all -inline -line {^.*:\s+(\w+)\s+(\w+)} $vregs] {
 127     if [expr $left != $a * ($i + 1) || $right != $b * (32 - $i)] {
 128         fail "verify \$v$i after set"
 129     }
 130     if { $i < 16 } {
 131         # Check that the FP register was updated accordingly.
 132         gdb_test "info register f$i" "raw ${left}.*"
 133     }
 134     incr i 1
 135 }
 136
 137 if { $i != 32 } {
 138     fail "dump save area (bad output)"
 139 }
 140
 141 # Let the inferior change all VRs according to a simple algorithm,
 142 # then print all VRs and compare their values with our result of the
 143 # same algorithm.
 144
 145 gdb_continue_to_breakpoint "change vrs"
 146 set vregs [capture_command_output "info registers vector" ""]
 147
 148 set j 1
 149 foreach {- r i val} [regexp -all -inline -line \
 150                          {^(\D*)(\d+)\s+.*?uint128 = 0x([0-9a-f]+?)} $vregs] {
 151     if { $r ne "v" } {
 152         fail "info registers vector: bad line $j"
 153     } elseif { $val ne [format %08x%08x%08x%08x \
 154                             [expr $a_high * ($i + 1) * $a_high ] \
 155                             [expr $a_low * ($i + 1) * $a_low ] \
 156                             [expr $b_high * (32 - $i) * $b_high * 32] \
 157                             [expr $b_low * (32 - $i) * $b_low * 32] ] } {
 158         fail "compare \$v$i"
 159     }
 160     incr j 1
 161 }
 162
 163 if { $j != 33 } {
 164     fail "info registers vector"
 165 }
 166
 167 if { $coredir == "" } {
 168     return
 169 }
 170
 171 # Take a core dump.
 172
 173 gdb_test "signal SIGABRT" "Program terminated with signal SIGABRT, .*"
 174 gdb_exit
 175
 176 # Find the core file and rename it (avoid accumulating core files).
 177
 178 set cores [glob -nocomplain -directory $coredir *core*]
 179 if {[llength $cores] != 1} {
 180     untested "core file not found"
 181     remote_exec build "rm -rf $coredir"
 182     return -1
 183 }
 184 set destcore [standard_output_file ${testfile}.core]
 185 remote_exec build "mv [file join $coredir [lindex $cores 0]] $destcore"
 186 remote_exec build "rm -rf $coredir"
 187
 188 # Restart gdb and load the core file.  Compare the VRs.
 189
 190 clean_restart ${testfile}
 191
 192 with_test_prefix "core" {
 193     set core_loaded [gdb_core_cmd $destcore "load"]
 194     if { $core_loaded != -1 } {
 195         set vregs_from_core [capture_command_output "info registers vector" ""]
 196         if { $vregs_from_core eq $vregs } {
 197             pass "compare vector registers"
 198         } else {
 199             fail "vector registers mismatch"
 200         }
 201     }
 202 }