1 /* Target dependent code for GDB on TI C6x systems.
3 Copyright (C) 2010-2012 Free Software Foundation, Inc.
4 Contributed by Andrew Jenner <andrew@codesourcery.com>
5 Contributed by Yao Qi <yao@codesourcery.com>
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "frame-unwind.h"
25 #include "frame-base.h"
26 #include "trad-frame.h"
27 #include "dwarf2-frame.h"
38 #include "arch-utils.h"
39 #include "floatformat.h"
40 #include "glibc-tdep.h"
43 #include "tramp-frame.h"
44 #include "linux-tdep.h"
47 #include "gdb_assert.h"
49 #include "tic6x-tdep.h"
51 #include "target-descriptions.h"
53 #include "features/tic6x-c64xp.c"
54 #include "features/tic6x-c64x.c"
55 #include "features/tic6x-c62x.c"
57 #define TIC6X_OPCODE_SIZE 4
58 #define TIC6X_FETCH_PACKET_SIZE 32
60 #define INST_S_BIT(INST) ((INST >> 1) & 1)
61 #define INST_X_BIT(INST) ((INST >> 12) & 1)
63 const gdb_byte tic6x_bkpt_illegal_opcode_be
[] = { 0x56, 0x45, 0x43, 0x14 };
64 const gdb_byte tic6x_bkpt_illegal_opcode_le
[] = { 0x14, 0x43, 0x45, 0x56 };
66 struct tic6x_unwind_cache
68 /* The frame's base, optionally used by the high-level debug info. */
71 /* The previous frame's inner most stack address. Used as this
72 frame ID's stack_addr. */
75 /* The address of the first instruction in this function */
78 /* Which register holds the return address for the frame. */
81 /* The offset of register saved on stack. If register is not saved, the
82 corresponding element is -1. */
83 CORE_ADDR reg_saved
[TIC6X_NUM_CORE_REGS
];
87 /* Name of TI C6x core registers. */
88 static const char *const tic6x_register_names
[] =
90 "A0", "A1", "A2", "A3", /* 0 1 2 3 */
91 "A4", "A5", "A6", "A7", /* 4 5 6 7 */
92 "A8", "A9", "A10", "A11", /* 8 9 10 11 */
93 "A12", "A13", "A14", "A15", /* 12 13 14 15 */
94 "B0", "B1", "B2", "B3", /* 16 17 18 19 */
95 "B4", "B5", "B6", "B7", /* 20 21 22 23 */
96 "B8", "B9", "B10", "B11", /* 24 25 26 27 */
97 "B12", "B13", "B14", "B15", /* 28 29 30 31 */
98 "CSR", "PC", /* 32 33 */
101 /* This array maps the arguments to the register number which passes argument
102 in function call according to C6000 ELF ABI. */
103 static const int arg_regs
[] = { 4, 20, 6, 22, 8, 24, 10, 26, 12, 28 };
105 /* This is the implementation of gdbarch method register_name. */
108 tic6x_register_name (struct gdbarch
*gdbarch
, int regno
)
113 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
114 return tdesc_register_name (gdbarch
, regno
);
115 else if (regno
>= ARRAY_SIZE (tic6x_register_names
))
118 return tic6x_register_names
[regno
];
121 /* This is the implementation of gdbarch method register_type. */
124 tic6x_register_type (struct gdbarch
*gdbarch
, int regno
)
127 if (regno
== TIC6X_PC_REGNUM
)
128 return builtin_type (gdbarch
)->builtin_func_ptr
;
130 return builtin_type (gdbarch
)->builtin_uint32
;
134 tic6x_setup_default (struct tic6x_unwind_cache
*cache
)
138 for (i
= 0; i
< TIC6X_NUM_CORE_REGS
; i
++)
139 cache
->reg_saved
[i
] = -1;
142 static unsigned long tic6x_fetch_instruction (struct gdbarch
*, CORE_ADDR
);
143 static int tic6x_register_number (int reg
, int side
, int crosspath
);
145 /* Do a full analysis of the prologue at START_PC and update CACHE accordingly.
146 Bail out early if CURRENT_PC is reached. Returns the address of the first
147 instruction after the prologue. */
150 tic6x_analyze_prologue (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
,
151 const CORE_ADDR current_pc
,
152 struct tic6x_unwind_cache
*cache
,
153 struct frame_info
*this_frame
)
155 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
157 unsigned int src_reg
, base_reg
, dst_reg
;
159 CORE_ADDR pc
= start_pc
;
160 CORE_ADDR return_pc
= start_pc
;
161 int frame_base_offset_to_sp
= 0;
162 /* Counter of non-stw instructions after first insn ` sub sp, xxx, sp'. */
163 int non_stw_insn_counter
= 0;
165 if (start_pc
>= current_pc
)
166 return_pc
= current_pc
;
170 /* The landmarks in prologue is one or two SUB instructions to SP.
171 Instructions on setting up dsbt are in the last part of prologue, if
172 needed. In maxim, prologue can be divided to three parts by two
173 `sub sp, xx, sp' insns. */
175 /* Step 1: Look for the 1st and 2nd insn `sub sp, xx, sp', in which, the
176 2nd one is optional. */
177 while (pc
< current_pc
)
181 unsigned long inst
= tic6x_fetch_instruction (gdbarch
, pc
);
183 if ((inst
& 0x1ffc) == 0x1dc0 || (inst
& 0x1ffc) == 0x1bc0
184 || (inst
& 0x0ffc) == 0x9c0)
186 /* SUBAW/SUBAH/SUB, and src1 is ucst 5. */
187 unsigned int src2
= tic6x_register_number ((inst
>> 18) & 0x1f,
188 INST_S_BIT (inst
), 0);
189 unsigned int dst
= tic6x_register_number ((inst
>> 23) & 0x1f,
190 INST_S_BIT (inst
), 0);
192 if (src2
== TIC6X_SP_REGNUM
&& dst
== TIC6X_SP_REGNUM
)
194 /* Extract const from insn SUBAW/SUBAH/SUB, and translate it to
195 offset. The constant offset is decoded in bit 13-17 in all
196 these three kinds of instructions. */
197 unsigned int ucst5
= (inst
>> 13) & 0x1f;
199 if ((inst
& 0x1ffc) == 0x1dc0) /* SUBAW */
200 frame_base_offset_to_sp
+= ucst5
<< 2;
201 else if ((inst
& 0x1ffc) == 0x1bc0) /* SUBAH */
202 frame_base_offset_to_sp
+= ucst5
<< 1;
203 else if ((inst
& 0x0ffc) == 0x9c0) /* SUB */
204 frame_base_offset_to_sp
+= ucst5
;
206 gdb_assert_not_reached ("unexpected instruction");
211 else if ((inst
& 0x174) == 0x74) /* stw SRC, *+b15(uconst) */
213 /* The y bit determines which file base is read from. */
214 base_reg
= tic6x_register_number ((inst
>> 18) & 0x1f,
217 if (base_reg
== TIC6X_SP_REGNUM
)
219 src_reg
= tic6x_register_number ((inst
>> 23) & 0x1f,
220 INST_S_BIT (inst
), 0);
222 cache
->reg_saved
[src_reg
] = ((inst
>> 13) & 0x1f) << 2;
226 non_stw_insn_counter
= 0;
230 non_stw_insn_counter
++;
231 /* Following instruction sequence may be emitted in prologue:
233 <+0>: subah .D2 b15,28,b15
234 <+4>: or .L2X 0,a4,b0
235 <+8>: || stw .D2T2 b14,*+b15(56)
236 <+12>:[!b0] b .S1 0xe50e4c1c <sleep+220>
237 <+16>:|| stw .D2T1 a10,*+b15(48)
238 <+20>:stw .D2T2 b3,*+b15(52)
239 <+24>:stw .D2T1 a4,*+b15(40)
241 we should look forward for next instruction instead of breaking loop
242 here. So far, we allow almost two sequential non-stw instructions
244 if (non_stw_insn_counter
>= 2)
251 /* Step 2: Skip insn on setting up dsbt if it is. Usually, it looks like,
252 ldw .D2T2 *+b14(0),b14 */
253 inst
= tic6x_fetch_instruction (gdbarch
, pc
);
254 /* The s bit determines which file dst will be loaded into, same effect as
256 dst_reg
= tic6x_register_number ((inst
>> 23) & 0x1f, (inst
>> 1) & 1, 0);
257 /* The y bit (bit 7), instead of s bit, determines which file base be
259 base_reg
= tic6x_register_number ((inst
>> 18) & 0x1f, (inst
>> 7) & 1, 0);
261 if ((inst
& 0x164) == 0x64 /* ldw */
262 && dst_reg
== TIC6X_DP_REGNUM
/* dst is B14 */
263 && base_reg
== TIC6X_DP_REGNUM
) /* baseR is B14 */
270 cache
->base
= get_frame_register_unsigned (this_frame
, TIC6X_SP_REGNUM
);
272 if (cache
->reg_saved
[TIC6X_FP_REGNUM
] != -1)
274 /* If the FP now holds an offset from the CFA then this is a frame
275 which uses the frame pointer. */
277 cache
->cfa
= get_frame_register_unsigned (this_frame
,
282 /* FP doesn't hold an offset from the CFA. If SP still holds an
283 offset from the CFA then we might be in a function which omits
284 the frame pointer. */
286 cache
->cfa
= cache
->base
+ frame_base_offset_to_sp
;
290 /* Adjust all the saved registers such that they contain addresses
291 instead of offsets. */
292 for (i
= 0; i
< TIC6X_NUM_CORE_REGS
; i
++)
293 if (cache
->reg_saved
[i
] != -1)
294 cache
->reg_saved
[i
] = cache
->base
+ cache
->reg_saved
[i
];
299 /* This is the implementation of gdbarch method skip_prologue. */
302 tic6x_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
306 struct tic6x_unwind_cache cache
;
308 /* See if we can determine the end of the prologue via the symbol table.
309 If so, then return either PC, or the PC after the prologue, whichever is
311 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
313 CORE_ADDR post_prologue_pc
314 = skip_prologue_using_sal (gdbarch
, func_addr
);
315 if (post_prologue_pc
!= 0)
316 return max (start_pc
, post_prologue_pc
);
319 /* Can't determine prologue from the symbol table, need to examine
321 return tic6x_analyze_prologue (gdbarch
, start_pc
, (CORE_ADDR
) -1, &cache
,
325 /* This is the implementation of gdbarch method breakpiont_from_pc. */
328 tic6x_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*bp_addr
,
331 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
335 if (tdep
== NULL
|| tdep
->breakpoint
== NULL
)
337 if (BFD_ENDIAN_BIG
== gdbarch_byte_order_for_code (gdbarch
))
338 return tic6x_bkpt_illegal_opcode_be
;
340 return tic6x_bkpt_illegal_opcode_le
;
343 return tdep
->breakpoint
;
346 /* This is the implementation of gdbarch method print_insn. */
349 tic6x_print_insn (bfd_vma memaddr
, disassemble_info
*info
)
351 return print_insn_tic6x (memaddr
, info
);
355 tic6x_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
356 struct dwarf2_frame_state_reg
*reg
,
357 struct frame_info
*this_frame
)
359 /* Mark the PC as the destination for the return address. */
360 if (regnum
== gdbarch_pc_regnum (gdbarch
))
361 reg
->how
= DWARF2_FRAME_REG_RA
;
363 /* Mark the stack pointer as the call frame address. */
364 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
365 reg
->how
= DWARF2_FRAME_REG_CFA
;
367 /* The above was taken from the default init_reg in dwarf2-frame.c
368 while the below is c6x specific. */
370 /* Callee save registers. The ABI designates A10-A15 and B10-B15 as
372 else if ((regnum
>= 10 && regnum
<= 15) || (regnum
>= 26 && regnum
<= 31))
373 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
375 /* All other registers are caller-save. */
376 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
379 /* This is the implementation of gdbarch method unwind_pc. */
382 tic6x_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
386 frame_unwind_register (next_frame
, TIC6X_PC_REGNUM
, buf
);
387 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
390 /* This is the implementation of gdbarch method unwind_sp. */
393 tic6x_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
395 return frame_unwind_register_unsigned (this_frame
, TIC6X_SP_REGNUM
);
399 /* Frame base handling. */
401 struct tic6x_unwind_cache
*
402 tic6x_frame_unwind_cache (struct frame_info
*this_frame
,
403 void **this_prologue_cache
)
405 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
406 CORE_ADDR current_pc
;
407 struct tic6x_unwind_cache
*cache
;
410 if (*this_prologue_cache
)
411 return *this_prologue_cache
;
413 cache
= FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache
);
414 (*this_prologue_cache
) = cache
;
416 cache
->return_regnum
= TIC6X_RA_REGNUM
;
418 tic6x_setup_default (cache
);
420 cache
->pc
= get_frame_func (this_frame
);
421 current_pc
= get_frame_pc (this_frame
);
423 /* Prologue analysis does the rest... */
425 tic6x_analyze_prologue (gdbarch
, cache
->pc
, current_pc
, cache
, this_frame
);
431 tic6x_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
432 struct frame_id
*this_id
)
434 struct tic6x_unwind_cache
*cache
=
435 tic6x_frame_unwind_cache (this_frame
, this_cache
);
437 /* This marks the outermost frame. */
438 if (cache
->base
== 0)
441 (*this_id
) = frame_id_build (cache
->cfa
, cache
->pc
);
444 static struct value
*
445 tic6x_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
448 struct tic6x_unwind_cache
*cache
=
449 tic6x_frame_unwind_cache (this_frame
, this_cache
);
451 gdb_assert (regnum
>= 0);
453 /* The PC of the previous frame is stored in the RA register of
454 the current frame. Frob regnum so that we pull the value from
455 the correct place. */
456 if (regnum
== TIC6X_PC_REGNUM
)
457 regnum
= cache
->return_regnum
;
459 if (regnum
== TIC6X_SP_REGNUM
&& cache
->cfa
)
460 return frame_unwind_got_constant (this_frame
, regnum
, cache
->cfa
);
462 /* If we've worked out where a register is stored then load it from
464 if (regnum
< TIC6X_NUM_CORE_REGS
&& cache
->reg_saved
[regnum
] != -1)
465 return frame_unwind_got_memory (this_frame
, regnum
,
466 cache
->reg_saved
[regnum
]);
468 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
472 tic6x_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
474 struct tic6x_unwind_cache
*info
475 = tic6x_frame_unwind_cache (this_frame
, this_cache
);
479 static const struct frame_unwind tic6x_frame_unwind
=
482 default_frame_unwind_stop_reason
,
484 tic6x_frame_prev_register
,
486 default_frame_sniffer
489 static const struct frame_base tic6x_frame_base
=
492 tic6x_frame_base_address
,
493 tic6x_frame_base_address
,
494 tic6x_frame_base_address
498 static struct tic6x_unwind_cache
*
499 tic6x_make_stub_cache (struct frame_info
*this_frame
)
501 struct tic6x_unwind_cache
*cache
;
503 cache
= FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache
);
505 cache
->return_regnum
= TIC6X_RA_REGNUM
;
507 tic6x_setup_default (cache
);
509 cache
->cfa
= get_frame_register_unsigned (this_frame
, TIC6X_SP_REGNUM
);
515 tic6x_stub_this_id (struct frame_info
*this_frame
, void **this_cache
,
516 struct frame_id
*this_id
)
518 struct tic6x_unwind_cache
*cache
;
520 if (*this_cache
== NULL
)
521 *this_cache
= tic6x_make_stub_cache (this_frame
);
524 *this_id
= frame_id_build (cache
->cfa
, get_frame_pc (this_frame
));
528 tic6x_stub_unwind_sniffer (const struct frame_unwind
*self
,
529 struct frame_info
*this_frame
,
530 void **this_prologue_cache
)
532 CORE_ADDR addr_in_block
;
534 addr_in_block
= get_frame_address_in_block (this_frame
);
535 if (in_plt_section (addr_in_block
, NULL
))
541 static const struct frame_unwind tic6x_stub_unwind
=
544 default_frame_unwind_stop_reason
,
546 tic6x_frame_prev_register
,
548 tic6x_stub_unwind_sniffer
551 /* Return the instruction on address PC. */
554 tic6x_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
556 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
557 return read_memory_unsigned_integer (pc
, TIC6X_OPCODE_SIZE
, byte_order
);
560 /* Compute the condition of INST if it is a conditional instruction. Always
561 return 1 if INST is not a conditional instruction. */
564 tic6x_condition_true (struct frame_info
*frame
, unsigned long inst
)
568 static const int register_numbers
[8] = { -1, 16, 17, 18, 1, 2, 0, -1 };
570 register_number
= register_numbers
[(inst
>> 29) & 7];
571 if (register_number
== -1)
574 register_value
= get_frame_register_signed (frame
, register_number
);
575 if ((inst
& 0x10000000) != 0)
576 return register_value
== 0;
577 return register_value
!= 0;
580 /* Get the register number by decoding raw bits REG, SIDE, and CROSSPATH in
584 tic6x_register_number (int reg
, int side
, int crosspath
)
586 int r
= (reg
& 15) | ((crosspath
^ side
) << 4);
587 if ((reg
& 16) != 0) /* A16 - A31, B16 - B31 */
593 tic6x_extract_signed_field (int value
, int low_bit
, int bits
)
595 int mask
= (1 << bits
) - 1;
596 int r
= (value
>> low_bit
) & mask
;
597 if ((r
& (1 << (bits
- 1))) != 0)
602 /* Determine where to set a single step breakpoint. */
605 tic6x_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
607 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
615 inst
= tic6x_fetch_instruction (gdbarch
, pc
);
619 if (inst
== TIC6X_INST_SWE
)
621 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
623 if (tdep
->syscall_next_pc
!= NULL
)
624 return tdep
->syscall_next_pc (frame
);
627 if (tic6x_condition_true (frame
, inst
))
629 if ((inst
& 0x0000007c) == 0x00000010)
631 /* B with displacement */
632 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
633 pc
+= tic6x_extract_signed_field (inst
, 7, 21) << 2;
636 if ((inst
& 0x0f83effc) == 0x00000360)
638 /* B with register */
640 register_number
= tic6x_register_number ((inst
>> 18) & 0x1f,
643 pc
= get_frame_register_unsigned (frame
, register_number
);
646 if ((inst
& 0x00001ffc) == 0x00001020)
649 register_number
= tic6x_register_number ((inst
>> 23) & 0x1f,
650 INST_S_BIT (inst
), 0);
651 if (get_frame_register_signed (frame
, register_number
) >= 0)
653 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
654 pc
+= tic6x_extract_signed_field (inst
, 7, 10) << 2;
658 if ((inst
& 0x00001ffc) == 0x00000120)
660 /* BNOP with displacement */
661 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
662 pc
+= tic6x_extract_signed_field (inst
, 16, 12) << 2;
665 if ((inst
& 0x0f830ffe) == 0x00800362)
667 /* BNOP with register */
668 register_number
= tic6x_register_number ((inst
>> 18) & 0x1f,
669 1, INST_X_BIT (inst
));
670 pc
= get_frame_register_unsigned (frame
, register_number
);
673 if ((inst
& 0x00001ffc) == 0x00000020)
676 register_number
= tic6x_register_number ((inst
>> 23) & 0x1f,
677 INST_S_BIT (inst
), 0);
678 if (get_frame_register_signed (frame
, register_number
) >= 0)
680 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
681 pc
+= tic6x_extract_signed_field (inst
, 13, 10) << 2;
685 if ((inst
& 0xf000007c) == 0x10000010)
688 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
689 pc
+= tic6x_extract_signed_field (inst
, 7, 21) << 2;
693 pc
+= TIC6X_OPCODE_SIZE
;
699 /* This is the implementation of gdbarch method software_single_step. */
702 tic6x_software_single_step (struct frame_info
*frame
)
704 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
705 struct address_space
*aspace
= get_frame_address_space (frame
);
706 CORE_ADDR next_pc
= tic6x_get_next_pc (frame
, get_frame_pc (frame
));
708 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
713 /* This is the implementation of gdbarch method frame_align. */
716 tic6x_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
718 return align_down (addr
, 8);
721 /* This is the implementation of gdbarch method register_to_value. */
724 tic6x_register_to_value (struct frame_info
*frame
, int regnum
,
725 struct type
*type
, gdb_byte
* to
,
726 int *optimizedp
, int *unavailablep
)
728 get_frame_register (frame
, regnum
, (char *) to
);
729 *optimizedp
= *unavailablep
= 0;
733 /* This is the implementation of gdbarch method value_to_register. */
736 tic6x_value_to_register (struct frame_info
*frame
, int regnum
,
737 struct type
*type
, const gdb_byte
*from
)
739 put_frame_register (frame
, regnum
, from
);
742 /* Given a return value in REGCACHE with a type VALTYPE, extract and copy its
743 value into VALBUF. */
746 tic6x_extract_return_value (struct type
*valtype
, struct regcache
*regcache
,
747 enum bfd_endian byte_order
, gdb_byte
*valbuf
)
749 int len
= TYPE_LENGTH (valtype
);
751 /* pointer types are returned in register A4,
752 up to 32-bit types in A4
753 up to 64-bit types in A5:A4 */
757 - one-byte structure or union occupies the LSB of single even register.
758 - for two-byte structure or union, the first byte occupies byte 1 of
759 register and the second byte occupies byte 0.
760 so, we read the contents in VAL from the LSBs of register. */
761 if (len
< 3 && byte_order
== BFD_ENDIAN_BIG
)
762 regcache_cooked_read_part (regcache
, TIC6X_A4_REGNUM
, 4 - len
, len
,
765 regcache_cooked_read (regcache
, TIC6X_A4_REGNUM
, valbuf
);
769 /* For a 5-8 byte structure or union in big-endian, the first byte
770 occupies byte 3 (the MSB) of the upper (odd) register and the
771 remaining bytes fill the decreasingly significant bytes. 5-7
772 byte structures or unions have padding in the LSBs of the
773 lower (even) register. */
774 if (byte_order
== BFD_ENDIAN_BIG
)
776 regcache_cooked_read (regcache
, TIC6X_A4_REGNUM
, valbuf
+ 4);
777 regcache_cooked_read (regcache
, TIC6X_A5_REGNUM
, valbuf
);
781 regcache_cooked_read (regcache
, TIC6X_A4_REGNUM
, valbuf
);
782 regcache_cooked_read (regcache
, TIC6X_A5_REGNUM
, valbuf
+ 4);
787 /* Write into appropriate registers a function return value
788 of type TYPE, given in virtual format. */
791 tic6x_store_return_value (struct type
*valtype
, struct regcache
*regcache
,
792 enum bfd_endian byte_order
, const gdb_byte
*valbuf
)
794 int len
= TYPE_LENGTH (valtype
);
796 /* return values of up to 8 bytes are returned in A5:A4 */
800 if (len
< 3 && byte_order
== BFD_ENDIAN_BIG
)
801 regcache_cooked_write_part (regcache
, TIC6X_A4_REGNUM
, 4 - len
, len
,
804 regcache_cooked_write (regcache
, TIC6X_A4_REGNUM
, valbuf
);
808 if (byte_order
== BFD_ENDIAN_BIG
)
810 regcache_cooked_write (regcache
, TIC6X_A4_REGNUM
, valbuf
+ 4);
811 regcache_cooked_write (regcache
, TIC6X_A5_REGNUM
, valbuf
);
815 regcache_cooked_write (regcache
, TIC6X_A4_REGNUM
, valbuf
);
816 regcache_cooked_write (regcache
, TIC6X_A5_REGNUM
, valbuf
+ 4);
821 /* This is the implementation of gdbarch method return_value. */
823 static enum return_value_convention
824 tic6x_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
825 struct type
*type
, struct regcache
*regcache
,
826 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
828 if (TYPE_LENGTH (type
) > 8)
829 return RETURN_VALUE_STRUCT_CONVENTION
;
832 tic6x_extract_return_value (type
, regcache
,
833 gdbarch_byte_order (gdbarch
), readbuf
);
835 tic6x_store_return_value (type
, regcache
,
836 gdbarch_byte_order (gdbarch
), writebuf
);
838 return RETURN_VALUE_REGISTER_CONVENTION
;
841 /* This is the implementation of gdbarch method dummy_id. */
843 static struct frame_id
844 tic6x_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
846 return frame_id_build
847 (get_frame_register_unsigned (this_frame
, TIC6X_SP_REGNUM
),
848 get_frame_pc (this_frame
));
851 /* Get the alignment requirement of TYPE. */
854 tic6x_arg_type_alignment (struct type
*type
)
856 int len
= TYPE_LENGTH (check_typedef (type
));
857 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
859 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
861 /* The stack alignment of a structure (and union) passed by value is the
862 smallest power of two greater than or equal to its size.
863 This cannot exceed 8 bytes, which is the largest allowable size for
864 a structure passed by value. */
873 gdb_assert_not_reached ("unexpected length of data");
881 if (typecode
== TYPE_CODE_COMPLEX
)
888 if (typecode
== TYPE_CODE_COMPLEX
)
894 internal_error (__FILE__
, __LINE__
, _("unexpected length %d of type"),
899 /* This is the implementation of gdbarch method push_dummy_call. */
902 tic6x_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
903 struct regcache
*regcache
, CORE_ADDR bp_addr
,
904 int nargs
, struct value
**args
, CORE_ADDR sp
,
905 int struct_return
, CORE_ADDR struct_addr
)
910 int stack_offset
= 4;
911 int references_offset
= 4;
912 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
913 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
914 struct type
*func_type
= value_type (function
);
915 /* The first arg passed on stack. Mostly the first 10 args are passed by
917 int first_arg_on_stack
= 10;
918 /* If this inf-call is a cpp method call, and return value is passed by
919 reference, this flag is set to 1, otherwise set to 0. We need this flag
920 because computation of the return location in
921 infcall.c:call_function_by_hand is wrong for C6000 ELF ABI. In
922 call_function_by_hand, the language is considered first, and then
923 target ABI is considered. If language_pass_by_reference returns true,
924 the return location is passed as the first parameter to the function,
925 which is conflict with C6000 ELF ABI. If this flag is true, we should
926 adjust args and return locations accordingly to comply with C6000 ELF
928 int cplus_return_struct_by_reference
= 0;
930 if (current_language
->la_language
== language_cplus
)
932 struct type
*values_type
;
934 find_function_addr (function
, &values_type
);
938 CHECK_TYPEDEF (values_type
);
939 if (language_pass_by_reference (values_type
))
940 cplus_return_struct_by_reference
= 1;
944 /* Set the return address register to point to the entry point of
945 the program, where a breakpoint lies in wait. */
946 regcache_cooked_write_unsigned (regcache
, TIC6X_RA_REGNUM
, bp_addr
);
948 /* The caller must pass an argument in A3 containing a destination address
949 for the returned value. The callee returns the object by copying it to
950 the address in A3. */
952 regcache_cooked_write_unsigned (regcache
, 3, struct_addr
);
953 else if (cplus_return_struct_by_reference
)
954 /* When cplus_return_struct_by_reference is 1, means local variable
955 lang_struct_return in call_function_by_hand is 1, so struct is
956 returned by reference, even STRUCT_RETURN is 0. Note that STRUCT_ADDR
957 is still valid in this case. */
958 regcache_cooked_write_unsigned (regcache
, 3, struct_addr
);
960 /* Determine the type of this function. */
961 func_type
= check_typedef (func_type
);
962 if (TYPE_CODE (func_type
) == TYPE_CODE_PTR
)
963 func_type
= check_typedef (TYPE_TARGET_TYPE (func_type
));
965 gdb_assert (TYPE_CODE (func_type
) == TYPE_CODE_FUNC
966 || TYPE_CODE (func_type
) == TYPE_CODE_METHOD
);
968 /* For a variadic C function, the last explicitly declared argument and all
969 remaining arguments are passed on the stack. */
970 if (TYPE_VARARGS (func_type
))
971 first_arg_on_stack
= TYPE_NFIELDS (func_type
) - 1;
973 /* Now make space on the stack for the args. If
974 cplus_return_struct_by_reference is 1, means GDB pass an extra parameter
975 in ARGS, which is useless here, skip it. */
976 for (argnum
= cplus_return_struct_by_reference
; argnum
< nargs
; argnum
++)
978 int len
= align_up (TYPE_LENGTH (value_type (args
[argnum
])), 4);
979 if (argnum
>= 10 - argreg
)
980 references_offset
+= len
;
984 /* SP should be 8-byte aligned, see C6000 ABI section 4.4.1
986 sp
= align_down (sp
, 8);
989 /* Now load as many as possible of the first arguments into
990 registers, and push the rest onto the stack. Loop through args
991 from first to last. */
992 for (argnum
= cplus_return_struct_by_reference
; argnum
< nargs
; argnum
++)
995 struct value
*arg
= args
[argnum
];
996 struct type
*arg_type
= check_typedef (value_type (arg
));
997 int len
= TYPE_LENGTH (arg_type
);
998 enum type_code typecode
= TYPE_CODE (arg_type
);
1000 val
= value_contents (arg
);
1002 /* Copy the argument to general registers or the stack in
1003 register-sized pieces. */
1004 if (argreg
< first_arg_on_stack
)
1008 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
1011 - one-byte structure or union occupies the LSB of single
1013 - for two-byte structure or union, the first byte
1014 occupies byte 1 of register and the second byte occupies
1016 so, we write the contents in VAL to the lsp of
1018 if (len
< 3 && byte_order
== BFD_ENDIAN_BIG
)
1019 regcache_cooked_write_part (regcache
, arg_regs
[argreg
],
1022 regcache_cooked_write (regcache
, arg_regs
[argreg
], val
);
1026 /* The argument is being passed by value in a single
1028 CORE_ADDR regval
= extract_unsigned_integer (val
, len
,
1031 regcache_cooked_write_unsigned (regcache
, arg_regs
[argreg
],
1039 if (typecode
== TYPE_CODE_STRUCT
1040 || typecode
== TYPE_CODE_UNION
)
1042 /* For a 5-8 byte structure or union in big-endian, the
1043 first byte occupies byte 3 (the MSB) of the upper (odd)
1044 register and the remaining bytes fill the decreasingly
1045 significant bytes. 5-7 byte structures or unions have
1046 padding in the LSBs of the lower (even) register. */
1047 if (byte_order
== BFD_ENDIAN_BIG
)
1049 regcache_cooked_write (regcache
,
1050 arg_regs
[argreg
] + 1, val
);
1051 regcache_cooked_write_part (regcache
,
1052 arg_regs
[argreg
], 0,
1057 regcache_cooked_write (regcache
, arg_regs
[argreg
],
1059 regcache_cooked_write_part (regcache
,
1060 arg_regs
[argreg
] + 1, 0,
1066 /* The argument is being passed by value in a pair of
1068 ULONGEST regval
= extract_unsigned_integer (val
, len
,
1071 regcache_cooked_write_unsigned (regcache
,
1074 regcache_cooked_write_unsigned (regcache
,
1075 arg_regs
[argreg
] + 1,
1081 /* The argument is being passed by reference in a single
1085 /* It is not necessary to adjust REFERENCES_OFFSET to
1086 8-byte aligned in some cases, in which 4-byte alignment
1087 is sufficient. For simplicity, we adjust
1088 REFERENCES_OFFSET to 8-byte aligned. */
1089 references_offset
= align_up (references_offset
, 8);
1091 addr
= sp
+ references_offset
;
1092 write_memory (addr
, val
, len
);
1093 references_offset
+= align_up (len
, 4);
1094 regcache_cooked_write_unsigned (regcache
, arg_regs
[argreg
],
1102 /* The argument is being passed on the stack. */
1105 /* There are six different cases of alignment, and these rules can
1106 be found in tic6x_arg_type_alignment:
1108 1) 4-byte aligned if size is less than or equal to 4 byte, such
1109 as short, int, struct, union etc.
1110 2) 8-byte aligned if size is less than or equal to 8-byte, such
1111 as double, long long,
1112 3) 4-byte aligned if it is of type _Complex float, even its size
1114 4) 8-byte aligned if it is of type _Complex double or _Complex
1115 long double, even its size is 16-byte. Because, the address of
1116 variable is passed as reference.
1117 5) struct and union larger than 8-byte are passed by reference, so
1118 it is 4-byte aligned.
1119 6) struct and union of size between 4 byte and 8 byte varies.
1120 alignment of struct variable is the alignment of its first field,
1121 while alignment of union variable is the max of all its fields'
1125 ; /* Default is 4-byte aligned. Nothing to be done. */
1127 stack_offset
= align_up (stack_offset
,
1128 tic6x_arg_type_alignment (arg_type
));
1131 /* _Complex double or _Complex long double */
1132 if (typecode
== TYPE_CODE_COMPLEX
)
1134 /* The argument is being passed by reference on stack. */
1136 references_offset
= align_up (references_offset
, 8);
1138 addr
= sp
+ references_offset
;
1139 /* Store variable on stack. */
1140 write_memory (addr
, val
, len
);
1142 references_offset
+= align_up (len
, 4);
1144 /* Pass the address of variable on stack as reference. */
1145 store_unsigned_integer ((gdb_byte
*) val
, 4, byte_order
,
1151 internal_error (__FILE__
, __LINE__
,
1152 _("unexpected type %d of arg %d"),
1156 internal_error (__FILE__
, __LINE__
,
1157 _("unexpected length %d of arg %d"), len
, argnum
);
1159 addr
= sp
+ stack_offset
;
1160 write_memory (addr
, val
, len
);
1161 stack_offset
+= align_up (len
, 4);
1165 regcache_cooked_write_signed (regcache
, TIC6X_SP_REGNUM
, sp
);
1167 /* Return adjusted stack pointer. */
1171 /* This is the implementation of gdbarch method in_function_epilogue_p. */
1174 tic6x_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1176 unsigned long inst
= tic6x_fetch_instruction (gdbarch
, pc
);
1177 /* Normally, the epilogue is composed by instruction `b .S2 b3'. */
1178 if ((inst
& 0x0f83effc) == 0x360)
1180 unsigned int src2
= tic6x_register_number ((inst
>> 18) & 0x1f,
1183 if (src2
== TIC6X_RA_REGNUM
)
1190 /* This is the implementation of gdbarch method get_longjmp_target. */
1193 tic6x_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
1195 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1196 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1200 /* JMP_BUF is passed by reference in A4. */
1201 jb_addr
= get_frame_register_unsigned (frame
, 4);
1203 /* JMP_BUF contains 13 elements of type int, and return address is stored
1204 in the last slot. */
1205 if (target_read_memory (jb_addr
+ 12 * 4, buf
, 4))
1208 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
1213 static struct gdbarch
*
1214 tic6x_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1216 struct gdbarch
*gdbarch
;
1217 struct gdbarch_tdep
*tdep
;
1218 struct tdesc_arch_data
*tdesc_data
= NULL
;
1219 const struct target_desc
*tdesc
= info
.target_desc
;
1222 /* Check any target description for validity. */
1223 if (tdesc_has_registers (tdesc
))
1225 const struct tdesc_feature
*feature
;
1228 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.tic6x.core");
1230 if (feature
== NULL
)
1233 tdesc_data
= tdesc_data_alloc ();
1236 for (i
= 0; i
< 32; i
++) /* A0 - A15, B0 - B15 */
1237 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
1238 tic6x_register_names
[i
]);
1241 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++,
1242 tic6x_register_names
[TIC6X_CSR_REGNUM
]);
1243 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++,
1244 tic6x_register_names
[TIC6X_PC_REGNUM
]);
1248 tdesc_data_cleanup (tdesc_data
);
1252 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.tic6x.gp");
1256 static const char *const gp
[] =
1258 "A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23",
1259 "A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31",
1260 "B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23",
1261 "B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31",
1266 for (j
= 0; j
< 32; j
++) /* A16 - A31, B16 - B31 */
1267 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++,
1272 tdesc_data_cleanup (tdesc_data
);
1277 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.tic6x.c6xp");
1280 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++, "TSR");
1281 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++, "ILC");
1282 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++, "RILC");
1286 tdesc_data_cleanup (tdesc_data
);
1293 /* Find a candidate among extant architectures. */
1294 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1296 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
1298 tdep
= gdbarch_tdep (arches
->gdbarch
);
1300 if (has_gp
!= tdep
->has_gp
)
1303 if (tdep
&& tdep
->breakpoint
)
1304 return arches
->gdbarch
;
1307 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
1309 tdep
->has_gp
= has_gp
;
1310 gdbarch
= gdbarch_alloc (&info
, tdep
);
1312 /* Data type sizes. */
1313 set_gdbarch_ptr_bit (gdbarch
, 32);
1314 set_gdbarch_addr_bit (gdbarch
, 32);
1315 set_gdbarch_short_bit (gdbarch
, 16);
1316 set_gdbarch_int_bit (gdbarch
, 32);
1317 set_gdbarch_long_bit (gdbarch
, 32);
1318 set_gdbarch_long_long_bit (gdbarch
, 64);
1319 set_gdbarch_float_bit (gdbarch
, 32);
1320 set_gdbarch_double_bit (gdbarch
, 64);
1322 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
1323 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
1325 /* The register set. */
1326 set_gdbarch_num_regs (gdbarch
, TIC6X_NUM_REGS
);
1327 set_gdbarch_sp_regnum (gdbarch
, TIC6X_SP_REGNUM
);
1328 set_gdbarch_pc_regnum (gdbarch
, TIC6X_PC_REGNUM
);
1330 set_gdbarch_register_name (gdbarch
, tic6x_register_name
);
1331 set_gdbarch_register_type (gdbarch
, tic6x_register_type
);
1333 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1335 set_gdbarch_skip_prologue (gdbarch
, tic6x_skip_prologue
);
1336 set_gdbarch_breakpoint_from_pc (gdbarch
, tic6x_breakpoint_from_pc
);
1338 set_gdbarch_unwind_pc (gdbarch
, tic6x_unwind_pc
);
1339 set_gdbarch_unwind_sp (gdbarch
, tic6x_unwind_sp
);
1342 dwarf2_append_unwinders (gdbarch
);
1344 frame_unwind_append_unwinder (gdbarch
, &tic6x_stub_unwind
);
1345 frame_unwind_append_unwinder (gdbarch
, &tic6x_frame_unwind
);
1347 dwarf2_frame_set_init_reg (gdbarch
, tic6x_dwarf2_frame_init_reg
);
1349 /* Single stepping. */
1350 set_gdbarch_software_single_step (gdbarch
, tic6x_software_single_step
);
1352 set_gdbarch_print_insn (gdbarch
, tic6x_print_insn
);
1354 /* Call dummy code. */
1355 set_gdbarch_frame_align (gdbarch
, tic6x_frame_align
);
1357 set_gdbarch_register_to_value (gdbarch
, tic6x_register_to_value
);
1358 set_gdbarch_value_to_register (gdbarch
, tic6x_value_to_register
);
1360 set_gdbarch_return_value (gdbarch
, tic6x_return_value
);
1362 set_gdbarch_dummy_id (gdbarch
, tic6x_dummy_id
);
1364 /* Enable inferior call support. */
1365 set_gdbarch_push_dummy_call (gdbarch
, tic6x_push_dummy_call
);
1367 set_gdbarch_get_longjmp_target (gdbarch
, tic6x_get_longjmp_target
);
1369 set_gdbarch_in_function_epilogue_p (gdbarch
, tic6x_in_function_epilogue_p
);
1371 /* Hook in ABI-specific overrides, if they have been registered. */
1372 gdbarch_init_osabi (info
, gdbarch
);
1375 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
1381 _initialize_tic6x_tdep (void)
1383 register_gdbarch_init (bfd_arch_tic6x
, tic6x_gdbarch_init
);
1385 initialize_tdesc_tic6x_c64xp ();
1386 initialize_tdesc_tic6x_c64x ();
1387 initialize_tdesc_tic6x_c62x ();