1 /* Target dependent code for GDB on TI C6x systems.
3 Copyright (C) 2010-2017 Free Software Foundation, Inc.
4 Contributed by Andrew Jenner <andrew@codesourcery.com>
5 Contributed by Yao Qi <yao@codesourcery.com>
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "frame-unwind.h"
25 #include "frame-base.h"
26 #include "trad-frame.h"
27 #include "dwarf2-frame.h"
38 #include "arch-utils.h"
39 #include "glibc-tdep.h"
42 #include "tramp-frame.h"
43 #include "linux-tdep.h"
47 #include "tic6x-tdep.h"
49 #include "target-descriptions.h"
52 #include "features/tic6x-c64xp.c"
53 #include "features/tic6x-c64x.c"
54 #include "features/tic6x-c62x.c"
56 #define TIC6X_OPCODE_SIZE 4
57 #define TIC6X_FETCH_PACKET_SIZE 32
59 #define INST_S_BIT(INST) ((INST >> 1) & 1)
60 #define INST_X_BIT(INST) ((INST >> 12) & 1)
62 const gdb_byte tic6x_bkpt_illegal_opcode_be
[] = { 0x56, 0x45, 0x43, 0x14 };
63 const gdb_byte tic6x_bkpt_illegal_opcode_le
[] = { 0x14, 0x43, 0x45, 0x56 };
65 struct tic6x_unwind_cache
67 /* The frame's base, optionally used by the high-level debug info. */
70 /* The previous frame's inner most stack address. Used as this
71 frame ID's stack_addr. */
74 /* The address of the first instruction in this function */
77 /* Which register holds the return address for the frame. */
80 /* The offset of register saved on stack. If register is not saved, the
81 corresponding element is -1. */
82 CORE_ADDR reg_saved
[TIC6X_NUM_CORE_REGS
];
86 /* Name of TI C6x core registers. */
87 static const char *const tic6x_register_names
[] =
89 "A0", "A1", "A2", "A3", /* 0 1 2 3 */
90 "A4", "A5", "A6", "A7", /* 4 5 6 7 */
91 "A8", "A9", "A10", "A11", /* 8 9 10 11 */
92 "A12", "A13", "A14", "A15", /* 12 13 14 15 */
93 "B0", "B1", "B2", "B3", /* 16 17 18 19 */
94 "B4", "B5", "B6", "B7", /* 20 21 22 23 */
95 "B8", "B9", "B10", "B11", /* 24 25 26 27 */
96 "B12", "B13", "B14", "B15", /* 28 29 30 31 */
97 "CSR", "PC", /* 32 33 */
100 /* This array maps the arguments to the register number which passes argument
101 in function call according to C6000 ELF ABI. */
102 static const int arg_regs
[] = { 4, 20, 6, 22, 8, 24, 10, 26, 12, 28 };
104 /* This is the implementation of gdbarch method register_name. */
107 tic6x_register_name (struct gdbarch
*gdbarch
, int regno
)
112 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
113 return tdesc_register_name (gdbarch
, regno
);
114 else if (regno
>= ARRAY_SIZE (tic6x_register_names
))
117 return tic6x_register_names
[regno
];
120 /* This is the implementation of gdbarch method register_type. */
123 tic6x_register_type (struct gdbarch
*gdbarch
, int regno
)
126 if (regno
== TIC6X_PC_REGNUM
)
127 return builtin_type (gdbarch
)->builtin_func_ptr
;
129 return builtin_type (gdbarch
)->builtin_uint32
;
133 tic6x_setup_default (struct tic6x_unwind_cache
*cache
)
137 for (i
= 0; i
< TIC6X_NUM_CORE_REGS
; i
++)
138 cache
->reg_saved
[i
] = -1;
141 static unsigned long tic6x_fetch_instruction (struct gdbarch
*, CORE_ADDR
);
142 static int tic6x_register_number (int reg
, int side
, int crosspath
);
144 /* Do a full analysis of the prologue at START_PC and update CACHE accordingly.
145 Bail out early if CURRENT_PC is reached. Returns the address of the first
146 instruction after the prologue. */
149 tic6x_analyze_prologue (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
,
150 const CORE_ADDR current_pc
,
151 struct tic6x_unwind_cache
*cache
,
152 struct frame_info
*this_frame
)
155 unsigned int src_reg
, base_reg
, dst_reg
;
157 CORE_ADDR pc
= start_pc
;
158 CORE_ADDR return_pc
= start_pc
;
159 int frame_base_offset_to_sp
= 0;
160 /* Counter of non-stw instructions after first insn ` sub sp, xxx, sp'. */
161 int non_stw_insn_counter
= 0;
163 if (start_pc
>= current_pc
)
164 return_pc
= current_pc
;
168 /* The landmarks in prologue is one or two SUB instructions to SP.
169 Instructions on setting up dsbt are in the last part of prologue, if
170 needed. In maxim, prologue can be divided to three parts by two
171 `sub sp, xx, sp' insns. */
173 /* Step 1: Look for the 1st and 2nd insn `sub sp, xx, sp', in which, the
174 2nd one is optional. */
175 while (pc
< current_pc
)
177 unsigned long inst
= tic6x_fetch_instruction (gdbarch
, pc
);
179 if ((inst
& 0x1ffc) == 0x1dc0 || (inst
& 0x1ffc) == 0x1bc0
180 || (inst
& 0x0ffc) == 0x9c0)
182 /* SUBAW/SUBAH/SUB, and src1 is ucst 5. */
183 unsigned int src2
= tic6x_register_number ((inst
>> 18) & 0x1f,
184 INST_S_BIT (inst
), 0);
185 unsigned int dst
= tic6x_register_number ((inst
>> 23) & 0x1f,
186 INST_S_BIT (inst
), 0);
188 if (src2
== TIC6X_SP_REGNUM
&& dst
== TIC6X_SP_REGNUM
)
190 /* Extract const from insn SUBAW/SUBAH/SUB, and translate it to
191 offset. The constant offset is decoded in bit 13-17 in all
192 these three kinds of instructions. */
193 unsigned int ucst5
= (inst
>> 13) & 0x1f;
195 if ((inst
& 0x1ffc) == 0x1dc0) /* SUBAW */
196 frame_base_offset_to_sp
+= ucst5
<< 2;
197 else if ((inst
& 0x1ffc) == 0x1bc0) /* SUBAH */
198 frame_base_offset_to_sp
+= ucst5
<< 1;
199 else if ((inst
& 0x0ffc) == 0x9c0) /* SUB */
200 frame_base_offset_to_sp
+= ucst5
;
202 gdb_assert_not_reached ("unexpected instruction");
207 else if ((inst
& 0x174) == 0x74) /* stw SRC, *+b15(uconst) */
209 /* The y bit determines which file base is read from. */
210 base_reg
= tic6x_register_number ((inst
>> 18) & 0x1f,
213 if (base_reg
== TIC6X_SP_REGNUM
)
215 src_reg
= tic6x_register_number ((inst
>> 23) & 0x1f,
216 INST_S_BIT (inst
), 0);
218 cache
->reg_saved
[src_reg
] = ((inst
>> 13) & 0x1f) << 2;
222 non_stw_insn_counter
= 0;
226 non_stw_insn_counter
++;
227 /* Following instruction sequence may be emitted in prologue:
229 <+0>: subah .D2 b15,28,b15
230 <+4>: or .L2X 0,a4,b0
231 <+8>: || stw .D2T2 b14,*+b15(56)
232 <+12>:[!b0] b .S1 0xe50e4c1c <sleep+220>
233 <+16>:|| stw .D2T1 a10,*+b15(48)
234 <+20>:stw .D2T2 b3,*+b15(52)
235 <+24>:stw .D2T1 a4,*+b15(40)
237 we should look forward for next instruction instead of breaking loop
238 here. So far, we allow almost two sequential non-stw instructions
240 if (non_stw_insn_counter
>= 2)
247 /* Step 2: Skip insn on setting up dsbt if it is. Usually, it looks like,
248 ldw .D2T2 *+b14(0),b14 */
249 inst
= tic6x_fetch_instruction (gdbarch
, pc
);
250 /* The s bit determines which file dst will be loaded into, same effect as
252 dst_reg
= tic6x_register_number ((inst
>> 23) & 0x1f, (inst
>> 1) & 1, 0);
253 /* The y bit (bit 7), instead of s bit, determines which file base be
255 base_reg
= tic6x_register_number ((inst
>> 18) & 0x1f, (inst
>> 7) & 1, 0);
257 if ((inst
& 0x164) == 0x64 /* ldw */
258 && dst_reg
== TIC6X_DP_REGNUM
/* dst is B14 */
259 && base_reg
== TIC6X_DP_REGNUM
) /* baseR is B14 */
266 cache
->base
= get_frame_register_unsigned (this_frame
, TIC6X_SP_REGNUM
);
268 if (cache
->reg_saved
[TIC6X_FP_REGNUM
] != -1)
270 /* If the FP now holds an offset from the CFA then this is a frame
271 which uses the frame pointer. */
273 cache
->cfa
= get_frame_register_unsigned (this_frame
,
278 /* FP doesn't hold an offset from the CFA. If SP still holds an
279 offset from the CFA then we might be in a function which omits
280 the frame pointer. */
282 cache
->cfa
= cache
->base
+ frame_base_offset_to_sp
;
286 /* Adjust all the saved registers such that they contain addresses
287 instead of offsets. */
288 for (i
= 0; i
< TIC6X_NUM_CORE_REGS
; i
++)
289 if (cache
->reg_saved
[i
] != -1)
290 cache
->reg_saved
[i
] = cache
->base
+ cache
->reg_saved
[i
];
295 /* This is the implementation of gdbarch method skip_prologue. */
298 tic6x_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
301 struct tic6x_unwind_cache cache
;
303 /* See if we can determine the end of the prologue via the symbol table.
304 If so, then return either PC, or the PC after the prologue, whichever is
306 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
308 CORE_ADDR post_prologue_pc
309 = skip_prologue_using_sal (gdbarch
, func_addr
);
310 if (post_prologue_pc
!= 0)
311 return std::max (start_pc
, post_prologue_pc
);
314 /* Can't determine prologue from the symbol table, need to examine
316 return tic6x_analyze_prologue (gdbarch
, start_pc
, (CORE_ADDR
) -1, &cache
,
320 /* Implement the breakpoint_kind_from_pc gdbarch method. */
323 tic6x_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
328 /* Implement the sw_breakpoint_from_kind gdbarch method. */
330 static const gdb_byte
*
331 tic6x_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
333 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
337 if (tdep
== NULL
|| tdep
->breakpoint
== NULL
)
339 if (BFD_ENDIAN_BIG
== gdbarch_byte_order_for_code (gdbarch
))
340 return tic6x_bkpt_illegal_opcode_be
;
342 return tic6x_bkpt_illegal_opcode_le
;
345 return tdep
->breakpoint
;
349 tic6x_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
350 struct dwarf2_frame_state_reg
*reg
,
351 struct frame_info
*this_frame
)
353 /* Mark the PC as the destination for the return address. */
354 if (regnum
== gdbarch_pc_regnum (gdbarch
))
355 reg
->how
= DWARF2_FRAME_REG_RA
;
357 /* Mark the stack pointer as the call frame address. */
358 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
359 reg
->how
= DWARF2_FRAME_REG_CFA
;
361 /* The above was taken from the default init_reg in dwarf2-frame.c
362 while the below is c6x specific. */
364 /* Callee save registers. The ABI designates A10-A15 and B10-B15 as
366 else if ((regnum
>= 10 && regnum
<= 15) || (regnum
>= 26 && regnum
<= 31))
367 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
369 /* All other registers are caller-save. */
370 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
373 /* This is the implementation of gdbarch method unwind_pc. */
376 tic6x_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
380 frame_unwind_register (next_frame
, TIC6X_PC_REGNUM
, buf
);
381 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
384 /* This is the implementation of gdbarch method unwind_sp. */
387 tic6x_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
389 return frame_unwind_register_unsigned (this_frame
, TIC6X_SP_REGNUM
);
393 /* Frame base handling. */
395 static struct tic6x_unwind_cache
*
396 tic6x_frame_unwind_cache (struct frame_info
*this_frame
,
397 void **this_prologue_cache
)
399 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
400 CORE_ADDR current_pc
;
401 struct tic6x_unwind_cache
*cache
;
403 if (*this_prologue_cache
)
404 return (struct tic6x_unwind_cache
*) *this_prologue_cache
;
406 cache
= FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache
);
407 (*this_prologue_cache
) = cache
;
409 cache
->return_regnum
= TIC6X_RA_REGNUM
;
411 tic6x_setup_default (cache
);
413 cache
->pc
= get_frame_func (this_frame
);
414 current_pc
= get_frame_pc (this_frame
);
416 /* Prologue analysis does the rest... */
418 tic6x_analyze_prologue (gdbarch
, cache
->pc
, current_pc
, cache
, this_frame
);
424 tic6x_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
425 struct frame_id
*this_id
)
427 struct tic6x_unwind_cache
*cache
=
428 tic6x_frame_unwind_cache (this_frame
, this_cache
);
430 /* This marks the outermost frame. */
431 if (cache
->base
== 0)
434 (*this_id
) = frame_id_build (cache
->cfa
, cache
->pc
);
437 static struct value
*
438 tic6x_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
441 struct tic6x_unwind_cache
*cache
=
442 tic6x_frame_unwind_cache (this_frame
, this_cache
);
444 gdb_assert (regnum
>= 0);
446 /* The PC of the previous frame is stored in the RA register of
447 the current frame. Frob regnum so that we pull the value from
448 the correct place. */
449 if (regnum
== TIC6X_PC_REGNUM
)
450 regnum
= cache
->return_regnum
;
452 if (regnum
== TIC6X_SP_REGNUM
&& cache
->cfa
)
453 return frame_unwind_got_constant (this_frame
, regnum
, cache
->cfa
);
455 /* If we've worked out where a register is stored then load it from
457 if (regnum
< TIC6X_NUM_CORE_REGS
&& cache
->reg_saved
[regnum
] != -1)
458 return frame_unwind_got_memory (this_frame
, regnum
,
459 cache
->reg_saved
[regnum
]);
461 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
465 tic6x_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
467 struct tic6x_unwind_cache
*info
468 = tic6x_frame_unwind_cache (this_frame
, this_cache
);
472 static const struct frame_unwind tic6x_frame_unwind
=
475 default_frame_unwind_stop_reason
,
477 tic6x_frame_prev_register
,
479 default_frame_sniffer
482 static const struct frame_base tic6x_frame_base
=
485 tic6x_frame_base_address
,
486 tic6x_frame_base_address
,
487 tic6x_frame_base_address
491 static struct tic6x_unwind_cache
*
492 tic6x_make_stub_cache (struct frame_info
*this_frame
)
494 struct tic6x_unwind_cache
*cache
;
496 cache
= FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache
);
498 cache
->return_regnum
= TIC6X_RA_REGNUM
;
500 tic6x_setup_default (cache
);
502 cache
->cfa
= get_frame_register_unsigned (this_frame
, TIC6X_SP_REGNUM
);
508 tic6x_stub_this_id (struct frame_info
*this_frame
, void **this_cache
,
509 struct frame_id
*this_id
)
511 struct tic6x_unwind_cache
*cache
;
513 if (*this_cache
== NULL
)
514 *this_cache
= tic6x_make_stub_cache (this_frame
);
515 cache
= (struct tic6x_unwind_cache
*) *this_cache
;
517 *this_id
= frame_id_build (cache
->cfa
, get_frame_pc (this_frame
));
521 tic6x_stub_unwind_sniffer (const struct frame_unwind
*self
,
522 struct frame_info
*this_frame
,
523 void **this_prologue_cache
)
525 CORE_ADDR addr_in_block
;
527 addr_in_block
= get_frame_address_in_block (this_frame
);
528 if (in_plt_section (addr_in_block
))
534 static const struct frame_unwind tic6x_stub_unwind
=
537 default_frame_unwind_stop_reason
,
539 tic6x_frame_prev_register
,
541 tic6x_stub_unwind_sniffer
544 /* Return the instruction on address PC. */
547 tic6x_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
549 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
550 return read_memory_unsigned_integer (pc
, TIC6X_OPCODE_SIZE
, byte_order
);
553 /* Compute the condition of INST if it is a conditional instruction. Always
554 return 1 if INST is not a conditional instruction. */
557 tic6x_condition_true (struct regcache
*regcache
, unsigned long inst
)
561 static const int register_numbers
[8] = { -1, 16, 17, 18, 1, 2, 0, -1 };
563 register_number
= register_numbers
[(inst
>> 29) & 7];
564 if (register_number
== -1)
567 register_value
= regcache_raw_get_signed (regcache
, register_number
);
568 if ((inst
& 0x10000000) != 0)
569 return register_value
== 0;
570 return register_value
!= 0;
573 /* Get the register number by decoding raw bits REG, SIDE, and CROSSPATH in
577 tic6x_register_number (int reg
, int side
, int crosspath
)
579 int r
= (reg
& 15) | ((crosspath
^ side
) << 4);
580 if ((reg
& 16) != 0) /* A16 - A31, B16 - B31 */
586 tic6x_extract_signed_field (int value
, int low_bit
, int bits
)
588 int mask
= (1 << bits
) - 1;
589 int r
= (value
>> low_bit
) & mask
;
590 if ((r
& (1 << (bits
- 1))) != 0)
595 /* Determine where to set a single step breakpoint. */
598 tic6x_get_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
600 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
607 inst
= tic6x_fetch_instruction (gdbarch
, pc
);
611 if (inst
== TIC6X_INST_SWE
)
613 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
615 if (tdep
->syscall_next_pc
!= NULL
)
616 return tdep
->syscall_next_pc (get_current_frame ());
619 if (tic6x_condition_true (regcache
, inst
))
621 if ((inst
& 0x0000007c) == 0x00000010)
623 /* B with displacement */
624 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
625 pc
+= tic6x_extract_signed_field (inst
, 7, 21) << 2;
628 if ((inst
& 0x0f83effc) == 0x00000360)
630 /* B with register */
632 register_number
= tic6x_register_number ((inst
>> 18) & 0x1f,
635 pc
= regcache_raw_get_unsigned (regcache
, register_number
);
638 if ((inst
& 0x00001ffc) == 0x00001020)
641 register_number
= tic6x_register_number ((inst
>> 23) & 0x1f,
642 INST_S_BIT (inst
), 0);
643 if (regcache_raw_get_signed (regcache
, register_number
) >= 0)
645 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
646 pc
+= tic6x_extract_signed_field (inst
, 7, 10) << 2;
650 if ((inst
& 0x00001ffc) == 0x00000120)
652 /* BNOP with displacement */
653 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
654 pc
+= tic6x_extract_signed_field (inst
, 16, 12) << 2;
657 if ((inst
& 0x0f830ffe) == 0x00800362)
659 /* BNOP with register */
660 register_number
= tic6x_register_number ((inst
>> 18) & 0x1f,
661 1, INST_X_BIT (inst
));
662 pc
= regcache_raw_get_unsigned (regcache
, register_number
);
665 if ((inst
& 0x00001ffc) == 0x00000020)
668 register_number
= tic6x_register_number ((inst
>> 23) & 0x1f,
669 INST_S_BIT (inst
), 0);
670 if (regcache_raw_get_signed (regcache
, register_number
) >= 0)
672 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
673 pc
+= tic6x_extract_signed_field (inst
, 13, 10) << 2;
677 if ((inst
& 0xf000007c) == 0x10000010)
680 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
681 pc
+= tic6x_extract_signed_field (inst
, 7, 21) << 2;
685 pc
+= TIC6X_OPCODE_SIZE
;
691 /* This is the implementation of gdbarch method software_single_step. */
693 static std::vector
<CORE_ADDR
>
694 tic6x_software_single_step (struct regcache
*regcache
)
696 CORE_ADDR next_pc
= tic6x_get_next_pc (regcache
, regcache_read_pc (regcache
));
701 /* This is the implementation of gdbarch method frame_align. */
704 tic6x_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
706 return align_down (addr
, 8);
709 /* Given a return value in REGCACHE with a type VALTYPE, extract and copy its
710 value into VALBUF. */
713 tic6x_extract_return_value (struct type
*valtype
, struct regcache
*regcache
,
714 enum bfd_endian byte_order
, gdb_byte
*valbuf
)
716 int len
= TYPE_LENGTH (valtype
);
718 /* pointer types are returned in register A4,
719 up to 32-bit types in A4
720 up to 64-bit types in A5:A4 */
724 - one-byte structure or union occupies the LSB of single even register.
725 - for two-byte structure or union, the first byte occupies byte 1 of
726 register and the second byte occupies byte 0.
727 so, we read the contents in VAL from the LSBs of register. */
728 if (len
< 3 && byte_order
== BFD_ENDIAN_BIG
)
729 regcache_cooked_read_part (regcache
, TIC6X_A4_REGNUM
, 4 - len
, len
,
732 regcache_cooked_read (regcache
, TIC6X_A4_REGNUM
, valbuf
);
736 /* For a 5-8 byte structure or union in big-endian, the first byte
737 occupies byte 3 (the MSB) of the upper (odd) register and the
738 remaining bytes fill the decreasingly significant bytes. 5-7
739 byte structures or unions have padding in the LSBs of the
740 lower (even) register. */
741 if (byte_order
== BFD_ENDIAN_BIG
)
743 regcache_cooked_read (regcache
, TIC6X_A4_REGNUM
, valbuf
+ 4);
744 regcache_cooked_read (regcache
, TIC6X_A5_REGNUM
, valbuf
);
748 regcache_cooked_read (regcache
, TIC6X_A4_REGNUM
, valbuf
);
749 regcache_cooked_read (regcache
, TIC6X_A5_REGNUM
, valbuf
+ 4);
754 /* Write into appropriate registers a function return value
755 of type TYPE, given in virtual format. */
758 tic6x_store_return_value (struct type
*valtype
, struct regcache
*regcache
,
759 enum bfd_endian byte_order
, const gdb_byte
*valbuf
)
761 int len
= TYPE_LENGTH (valtype
);
763 /* return values of up to 8 bytes are returned in A5:A4 */
767 if (len
< 3 && byte_order
== BFD_ENDIAN_BIG
)
768 regcache_cooked_write_part (regcache
, TIC6X_A4_REGNUM
, 4 - len
, len
,
771 regcache_cooked_write (regcache
, TIC6X_A4_REGNUM
, valbuf
);
775 if (byte_order
== BFD_ENDIAN_BIG
)
777 regcache_cooked_write (regcache
, TIC6X_A4_REGNUM
, valbuf
+ 4);
778 regcache_cooked_write (regcache
, TIC6X_A5_REGNUM
, valbuf
);
782 regcache_cooked_write (regcache
, TIC6X_A4_REGNUM
, valbuf
);
783 regcache_cooked_write (regcache
, TIC6X_A5_REGNUM
, valbuf
+ 4);
788 /* This is the implementation of gdbarch method return_value. */
790 static enum return_value_convention
791 tic6x_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
792 struct type
*type
, struct regcache
*regcache
,
793 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
795 /* In C++, when function returns an object, even its size is small
796 enough, it stii has to be passed via reference, pointed by register
798 if (current_language
->la_language
== language_cplus
)
802 type
= check_typedef (type
);
803 if (language_pass_by_reference (type
))
804 return RETURN_VALUE_STRUCT_CONVENTION
;
808 if (TYPE_LENGTH (type
) > 8)
809 return RETURN_VALUE_STRUCT_CONVENTION
;
812 tic6x_extract_return_value (type
, regcache
,
813 gdbarch_byte_order (gdbarch
), readbuf
);
815 tic6x_store_return_value (type
, regcache
,
816 gdbarch_byte_order (gdbarch
), writebuf
);
818 return RETURN_VALUE_REGISTER_CONVENTION
;
821 /* This is the implementation of gdbarch method dummy_id. */
823 static struct frame_id
824 tic6x_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
826 return frame_id_build
827 (get_frame_register_unsigned (this_frame
, TIC6X_SP_REGNUM
),
828 get_frame_pc (this_frame
));
831 /* Get the alignment requirement of TYPE. */
834 tic6x_arg_type_alignment (struct type
*type
)
836 int len
= TYPE_LENGTH (check_typedef (type
));
837 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
839 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
841 /* The stack alignment of a structure (and union) passed by value is the
842 smallest power of two greater than or equal to its size.
843 This cannot exceed 8 bytes, which is the largest allowable size for
844 a structure passed by value. */
853 gdb_assert_not_reached ("unexpected length of data");
861 if (typecode
== TYPE_CODE_COMPLEX
)
868 if (typecode
== TYPE_CODE_COMPLEX
)
874 internal_error (__FILE__
, __LINE__
, _("unexpected length %d of type"),
879 /* This is the implementation of gdbarch method push_dummy_call. */
882 tic6x_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
883 struct regcache
*regcache
, CORE_ADDR bp_addr
,
884 int nargs
, struct value
**args
, CORE_ADDR sp
,
885 int struct_return
, CORE_ADDR struct_addr
)
889 int stack_offset
= 4;
890 int references_offset
= 4;
891 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
892 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
893 struct type
*func_type
= value_type (function
);
894 /* The first arg passed on stack. Mostly the first 10 args are passed by
896 int first_arg_on_stack
= 10;
898 /* Set the return address register to point to the entry point of
899 the program, where a breakpoint lies in wait. */
900 regcache_cooked_write_unsigned (regcache
, TIC6X_RA_REGNUM
, bp_addr
);
902 /* The caller must pass an argument in A3 containing a destination address
903 for the returned value. The callee returns the object by copying it to
904 the address in A3. */
906 regcache_cooked_write_unsigned (regcache
, 3, struct_addr
);
908 /* Determine the type of this function. */
909 func_type
= check_typedef (func_type
);
910 if (TYPE_CODE (func_type
) == TYPE_CODE_PTR
)
911 func_type
= check_typedef (TYPE_TARGET_TYPE (func_type
));
913 gdb_assert (TYPE_CODE (func_type
) == TYPE_CODE_FUNC
914 || TYPE_CODE (func_type
) == TYPE_CODE_METHOD
);
916 /* For a variadic C function, the last explicitly declared argument and all
917 remaining arguments are passed on the stack. */
918 if (TYPE_VARARGS (func_type
))
919 first_arg_on_stack
= TYPE_NFIELDS (func_type
) - 1;
921 /* Now make space on the stack for the args. */
922 for (argnum
= 0; argnum
< nargs
; argnum
++)
924 int len
= align_up (TYPE_LENGTH (value_type (args
[argnum
])), 4);
925 if (argnum
>= 10 - argreg
)
926 references_offset
+= len
;
930 /* SP should be 8-byte aligned, see C6000 ABI section 4.4.1
932 sp
= align_down (sp
, 8);
935 /* Now load as many as possible of the first arguments into
936 registers, and push the rest onto the stack. Loop through args
937 from first to last. */
938 for (argnum
= 0; argnum
< nargs
; argnum
++)
941 struct value
*arg
= args
[argnum
];
942 struct type
*arg_type
= check_typedef (value_type (arg
));
943 int len
= TYPE_LENGTH (arg_type
);
944 enum type_code typecode
= TYPE_CODE (arg_type
);
946 val
= value_contents (arg
);
948 /* Copy the argument to general registers or the stack in
949 register-sized pieces. */
950 if (argreg
< first_arg_on_stack
)
954 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
957 - one-byte structure or union occupies the LSB of single
959 - for two-byte structure or union, the first byte
960 occupies byte 1 of register and the second byte occupies
962 so, we write the contents in VAL to the lsp of
964 if (len
< 3 && byte_order
== BFD_ENDIAN_BIG
)
965 regcache_cooked_write_part (regcache
, arg_regs
[argreg
],
968 regcache_cooked_write (regcache
, arg_regs
[argreg
], val
);
972 /* The argument is being passed by value in a single
974 CORE_ADDR regval
= extract_unsigned_integer (val
, len
,
977 regcache_cooked_write_unsigned (regcache
, arg_regs
[argreg
],
985 if (typecode
== TYPE_CODE_STRUCT
986 || typecode
== TYPE_CODE_UNION
)
988 /* For a 5-8 byte structure or union in big-endian, the
989 first byte occupies byte 3 (the MSB) of the upper (odd)
990 register and the remaining bytes fill the decreasingly
991 significant bytes. 5-7 byte structures or unions have
992 padding in the LSBs of the lower (even) register. */
993 if (byte_order
== BFD_ENDIAN_BIG
)
995 regcache_cooked_write (regcache
,
996 arg_regs
[argreg
] + 1, val
);
997 regcache_cooked_write_part (regcache
,
1003 regcache_cooked_write (regcache
, arg_regs
[argreg
],
1005 regcache_cooked_write_part (regcache
,
1006 arg_regs
[argreg
] + 1, 0,
1012 /* The argument is being passed by value in a pair of
1014 ULONGEST regval
= extract_unsigned_integer (val
, len
,
1017 regcache_cooked_write_unsigned (regcache
,
1020 regcache_cooked_write_unsigned (regcache
,
1021 arg_regs
[argreg
] + 1,
1027 /* The argument is being passed by reference in a single
1031 /* It is not necessary to adjust REFERENCES_OFFSET to
1032 8-byte aligned in some cases, in which 4-byte alignment
1033 is sufficient. For simplicity, we adjust
1034 REFERENCES_OFFSET to 8-byte aligned. */
1035 references_offset
= align_up (references_offset
, 8);
1037 addr
= sp
+ references_offset
;
1038 write_memory (addr
, val
, len
);
1039 references_offset
+= align_up (len
, 4);
1040 regcache_cooked_write_unsigned (regcache
, arg_regs
[argreg
],
1048 /* The argument is being passed on the stack. */
1051 /* There are six different cases of alignment, and these rules can
1052 be found in tic6x_arg_type_alignment:
1054 1) 4-byte aligned if size is less than or equal to 4 byte, such
1055 as short, int, struct, union etc.
1056 2) 8-byte aligned if size is less than or equal to 8-byte, such
1057 as double, long long,
1058 3) 4-byte aligned if it is of type _Complex float, even its size
1060 4) 8-byte aligned if it is of type _Complex double or _Complex
1061 long double, even its size is 16-byte. Because, the address of
1062 variable is passed as reference.
1063 5) struct and union larger than 8-byte are passed by reference, so
1064 it is 4-byte aligned.
1065 6) struct and union of size between 4 byte and 8 byte varies.
1066 alignment of struct variable is the alignment of its first field,
1067 while alignment of union variable is the max of all its fields'
1071 ; /* Default is 4-byte aligned. Nothing to be done. */
1073 stack_offset
= align_up (stack_offset
,
1074 tic6x_arg_type_alignment (arg_type
));
1077 /* _Complex double or _Complex long double */
1078 if (typecode
== TYPE_CODE_COMPLEX
)
1080 /* The argument is being passed by reference on stack. */
1082 references_offset
= align_up (references_offset
, 8);
1084 addr
= sp
+ references_offset
;
1085 /* Store variable on stack. */
1086 write_memory (addr
, val
, len
);
1088 references_offset
+= align_up (len
, 4);
1090 /* Pass the address of variable on stack as reference. */
1091 store_unsigned_integer ((gdb_byte
*) val
, 4, byte_order
,
1097 internal_error (__FILE__
, __LINE__
,
1098 _("unexpected type %d of arg %d"),
1102 internal_error (__FILE__
, __LINE__
,
1103 _("unexpected length %d of arg %d"), len
, argnum
);
1105 addr
= sp
+ stack_offset
;
1106 write_memory (addr
, val
, len
);
1107 stack_offset
+= align_up (len
, 4);
1111 regcache_cooked_write_signed (regcache
, TIC6X_SP_REGNUM
, sp
);
1113 /* Return adjusted stack pointer. */
1117 /* This is the implementation of gdbarch method stack_frame_destroyed_p. */
1120 tic6x_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1122 unsigned long inst
= tic6x_fetch_instruction (gdbarch
, pc
);
1123 /* Normally, the epilogue is composed by instruction `b .S2 b3'. */
1124 if ((inst
& 0x0f83effc) == 0x360)
1126 unsigned int src2
= tic6x_register_number ((inst
>> 18) & 0x1f,
1129 if (src2
== TIC6X_RA_REGNUM
)
1136 /* This is the implementation of gdbarch method get_longjmp_target. */
1139 tic6x_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
1141 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1142 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1146 /* JMP_BUF is passed by reference in A4. */
1147 jb_addr
= get_frame_register_unsigned (frame
, 4);
1149 /* JMP_BUF contains 13 elements of type int, and return address is stored
1150 in the last slot. */
1151 if (target_read_memory (jb_addr
+ 12 * 4, buf
, 4))
1154 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
1159 /* This is the implementation of gdbarch method
1160 return_in_first_hidden_param_p. */
1163 tic6x_return_in_first_hidden_param_p (struct gdbarch
*gdbarch
,
1169 static struct gdbarch
*
1170 tic6x_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1172 struct gdbarch
*gdbarch
;
1173 struct gdbarch_tdep
*tdep
;
1174 struct tdesc_arch_data
*tdesc_data
= NULL
;
1175 const struct target_desc
*tdesc
= info
.target_desc
;
1178 /* Check any target description for validity. */
1179 if (tdesc_has_registers (tdesc
))
1181 const struct tdesc_feature
*feature
;
1184 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.tic6x.core");
1186 if (feature
== NULL
)
1189 tdesc_data
= tdesc_data_alloc ();
1192 for (i
= 0; i
< 32; i
++) /* A0 - A15, B0 - B15 */
1193 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
1194 tic6x_register_names
[i
]);
1197 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++,
1198 tic6x_register_names
[TIC6X_CSR_REGNUM
]);
1199 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++,
1200 tic6x_register_names
[TIC6X_PC_REGNUM
]);
1204 tdesc_data_cleanup (tdesc_data
);
1208 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.tic6x.gp");
1212 static const char *const gp
[] =
1214 "A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23",
1215 "A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31",
1216 "B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23",
1217 "B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31",
1222 for (j
= 0; j
< 32; j
++) /* A16 - A31, B16 - B31 */
1223 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++,
1228 tdesc_data_cleanup (tdesc_data
);
1233 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.tic6x.c6xp");
1236 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++, "TSR");
1237 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++, "ILC");
1238 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++, "RILC");
1242 tdesc_data_cleanup (tdesc_data
);
1249 /* Find a candidate among extant architectures. */
1250 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1252 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
1254 tdep
= gdbarch_tdep (arches
->gdbarch
);
1256 if (has_gp
!= tdep
->has_gp
)
1259 if (tdep
&& tdep
->breakpoint
)
1260 return arches
->gdbarch
;
1263 tdep
= XCNEW (struct gdbarch_tdep
);
1265 tdep
->has_gp
= has_gp
;
1266 gdbarch
= gdbarch_alloc (&info
, tdep
);
1268 /* Data type sizes. */
1269 set_gdbarch_ptr_bit (gdbarch
, 32);
1270 set_gdbarch_addr_bit (gdbarch
, 32);
1271 set_gdbarch_short_bit (gdbarch
, 16);
1272 set_gdbarch_int_bit (gdbarch
, 32);
1273 set_gdbarch_long_bit (gdbarch
, 32);
1274 set_gdbarch_long_long_bit (gdbarch
, 64);
1275 set_gdbarch_float_bit (gdbarch
, 32);
1276 set_gdbarch_double_bit (gdbarch
, 64);
1278 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
1279 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
1281 /* The register set. */
1282 set_gdbarch_num_regs (gdbarch
, TIC6X_NUM_REGS
);
1283 set_gdbarch_sp_regnum (gdbarch
, TIC6X_SP_REGNUM
);
1284 set_gdbarch_pc_regnum (gdbarch
, TIC6X_PC_REGNUM
);
1286 set_gdbarch_register_name (gdbarch
, tic6x_register_name
);
1287 set_gdbarch_register_type (gdbarch
, tic6x_register_type
);
1289 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1291 set_gdbarch_skip_prologue (gdbarch
, tic6x_skip_prologue
);
1292 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
1293 tic6x_breakpoint_kind_from_pc
);
1294 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
1295 tic6x_sw_breakpoint_from_kind
);
1297 set_gdbarch_unwind_pc (gdbarch
, tic6x_unwind_pc
);
1298 set_gdbarch_unwind_sp (gdbarch
, tic6x_unwind_sp
);
1301 dwarf2_append_unwinders (gdbarch
);
1303 frame_unwind_append_unwinder (gdbarch
, &tic6x_stub_unwind
);
1304 frame_unwind_append_unwinder (gdbarch
, &tic6x_frame_unwind
);
1305 frame_base_set_default (gdbarch
, &tic6x_frame_base
);
1307 dwarf2_frame_set_init_reg (gdbarch
, tic6x_dwarf2_frame_init_reg
);
1309 /* Single stepping. */
1310 set_gdbarch_software_single_step (gdbarch
, tic6x_software_single_step
);
1312 /* Call dummy code. */
1313 set_gdbarch_frame_align (gdbarch
, tic6x_frame_align
);
1315 set_gdbarch_return_value (gdbarch
, tic6x_return_value
);
1317 set_gdbarch_dummy_id (gdbarch
, tic6x_dummy_id
);
1319 /* Enable inferior call support. */
1320 set_gdbarch_push_dummy_call (gdbarch
, tic6x_push_dummy_call
);
1322 set_gdbarch_get_longjmp_target (gdbarch
, tic6x_get_longjmp_target
);
1324 set_gdbarch_stack_frame_destroyed_p (gdbarch
, tic6x_stack_frame_destroyed_p
);
1326 set_gdbarch_return_in_first_hidden_param_p (gdbarch
,
1327 tic6x_return_in_first_hidden_param_p
);
1329 /* Hook in ABI-specific overrides, if they have been registered. */
1330 gdbarch_init_osabi (info
, gdbarch
);
1333 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
1339 _initialize_tic6x_tdep (void)
1341 register_gdbarch_init (bfd_arch_tic6x
, tic6x_gdbarch_init
);
1343 initialize_tdesc_tic6x_c64xp ();
1344 initialize_tdesc_tic6x_c64x ();
1345 initialize_tdesc_tic6x_c62x ();