gdb/ultra3-nat.c

   1 /* Native-dependent code for GDB, for NYU Ultra3 running Sym1 OS.
   2    Copyright 1988, 1989, 1991, 1992, 1995, 1996, 1999, 2000, 2001
   3    Free Software Foundation, Inc.
   4    Contributed by David Wood (wood@nyu.edu) at New York University.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 2 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 59 Temple Place - Suite 330,
  21    Boston, MA 02111-1307, USA.  */
  22
  23 #define DEBUG
  24 #include "defs.h"
  25 #include "frame.h"
  26 #include "inferior.h"
  27 #include "symtab.h"
  28 #include "value.h"
  29 #include "regcache.h"
  30
  31 #include <sys/types.h>
  32 #include <sys/param.h>
  33 #include <signal.h>
  34 #include <sys/ioctl.h>
  35 #include <fcntl.h>
  36
  37 #include "gdbcore.h"
  38
  39 #include <sys/file.h>
  40 #include "gdb_stat.h"
  41
  42 static void fetch_core_registers (char *, unsigned, int, CORE_ADDR);
  43
  44 /* Assumes support for AMD's Binary Compatibility Standard
  45    for ptrace().  If you define ULTRA3, the ultra3 extensions to
  46    ptrace() are used allowing the reading of more than one register
  47    at a time.
  48
  49    This file assumes KERNEL_DEBUGGING is turned off.  This means
  50    that if the user/gdb tries to read gr64-gr95 or any of the
  51    protected special registers we silently return -1 (see the
  52    CANNOT_STORE/FETCH_REGISTER macros).  */
  53 #define ULTRA3
  54
  55 #if !defined (offsetof)
  56 #define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER)
  57 #endif
  58
  59 extern int errno;
  60 struct ptrace_user pt_struct;
  61
  62 /* Get all available registers from the inferior.  Registers that are
  63  * defined in REGISTER_NAMES, but not available to the user/gdb are
  64  * supplied as -1.  This may include gr64-gr95 and the protected special
  65  * purpose registers.
  66  */
  67
  68 void
  69 fetch_inferior_registers (int regno)
  70 {
  71   register int i, j, ret_val = 0;
  72   char buf[128];
  73
  74   if (regno != -1)
  75     {
  76       fetch_register (regno);
  77       return;
  78     }
  79
  80 /* Global Registers */
  81 #ifdef ULTRA3
  82   errno = 0;
  83   ptrace (PT_READ_STRUCT, inferior_pid,
  84           (PTRACE_ARG3_TYPE) register_addr (GR96_REGNUM, 0),
  85           (int) &pt_struct.pt_gr[0], 32 * 4);
  86   if (errno != 0)
  87     {
  88       perror_with_name ("reading global registers");
  89       ret_val = -1;
  90     }
  91   else
  92     for (regno = GR96_REGNUM, j = 0; j < 32; regno++, j++)
  93       {
  94         supply_register (regno, &pt_struct.pt_gr[j]);
  95       }
  96 #else
  97   for (regno = GR96_REGNUM; !ret_val && regno < GR96_REGNUM + 32; regno++)
  98     fetch_register (regno);
  99 #endif
 100
 101 /* Local Registers */
 102 #ifdef ULTRA3
 103   errno = 0;
 104   ptrace (PT_READ_STRUCT, inferior_pid,
 105           (PTRACE_ARG3_TYPE) register_addr (LR0_REGNUM, 0),
 106           (int) &pt_struct.pt_lr[0], 128 * 4);
 107   if (errno != 0)
 108     {
 109       perror_with_name ("reading local registers");
 110       ret_val = -1;
 111     }
 112   else
 113     for (regno = LR0_REGNUM, j = 0; j < 128; regno++, j++)
 114       {
 115         supply_register (regno, &pt_struct.pt_lr[j]);
 116       }
 117 #else
 118   for (regno = LR0_REGNUM; !ret_val && regno < LR0_REGNUM + 128; regno++)
 119     fetch_register (regno);
 120 #endif
 121
 122 /* Special Registers */
 123   fetch_register (GR1_REGNUM);
 124   fetch_register (CPS_REGNUM);
 125   fetch_register (PC_REGNUM);
 126   fetch_register (NPC_REGNUM);
 127   fetch_register (PC2_REGNUM);
 128   fetch_register (IPC_REGNUM);
 129   fetch_register (IPA_REGNUM);
 130   fetch_register (IPB_REGNUM);
 131   fetch_register (Q_REGNUM);
 132   fetch_register (BP_REGNUM);
 133   fetch_register (FC_REGNUM);
 134
 135 /* Fake any registers that are in REGISTER_NAMES, but not available to gdb */
 136   registers_fetched ();
 137 }
 138
 139 /* Store our register values back into the inferior.
 140  * If REGNO is -1, do this for all registers.
 141  * Otherwise, REGNO specifies which register (so we can save time).
 142  * NOTE: Assumes AMD's binary compatibility standard.
 143  */
 144
 145 void
 146 store_inferior_registers (int regno)
 147 {
 148   register unsigned int regaddr;
 149   char buf[80];
 150
 151   if (regno >= 0)
 152     {
 153       if (CANNOT_STORE_REGISTER (regno))
 154         return;
 155       regaddr = register_addr (regno, 0);
 156       errno = 0;
 157       ptrace (PT_WRITE_U, inferior_pid,
 158               (PTRACE_ARG3_TYPE) regaddr, read_register (regno));
 159       if (errno != 0)
 160         {
 161           sprintf (buf, "writing register %s (#%d)", REGISTER_NAME (regno), regno);
 162           perror_with_name (buf);
 163         }
 164     }
 165   else
 166     {
 167 #ifdef ULTRA3
 168       pt_struct.pt_gr1 = read_register (GR1_REGNUM);
 169       for (regno = GR96_REGNUM; regno < GR96_REGNUM + 32; regno++)
 170         pt_struct.pt_gr[regno] = read_register (regno);
 171       for (regno = LR0_REGNUM; regno < LR0_REGNUM + 128; regno++)
 172         pt_struct.pt_gr[regno] = read_register (regno);
 173       errno = 0;
 174       ptrace (PT_WRITE_STRUCT, inferior_pid,
 175               (PTRACE_ARG3_TYPE) register_addr (GR1_REGNUM, 0),
 176               (int) &pt_struct.pt_gr1, (1 * 32 * 128) * 4);
 177       if (errno != 0)
 178         {
 179           sprintf (buf, "writing all local/global registers");
 180           perror_with_name (buf);
 181         }
 182       pt_struct.pt_psr = read_register (CPS_REGNUM);
 183       pt_struct.pt_pc0 = read_register (NPC_REGNUM);
 184       pt_struct.pt_pc1 = read_register (PC_REGNUM);
 185       pt_struct.pt_pc2 = read_register (PC2_REGNUM);
 186       pt_struct.pt_ipc = read_register (IPC_REGNUM);
 187       pt_struct.pt_ipa = read_register (IPA_REGNUM);
 188       pt_struct.pt_ipb = read_register (IPB_REGNUM);
 189       pt_struct.pt_q = read_register (Q_REGNUM);
 190       pt_struct.pt_bp = read_register (BP_REGNUM);
 191       pt_struct.pt_fc = read_register (FC_REGNUM);
 192       errno = 0;
 193       ptrace (PT_WRITE_STRUCT, inferior_pid,
 194               (PTRACE_ARG3_TYPE) register_addr (CPS_REGNUM, 0),
 195               (int) &pt_struct.pt_psr, (10) * 4);
 196       if (errno != 0)
 197         {
 198           sprintf (buf, "writing all special registers");
 199           perror_with_name (buf);
 200           return;
 201         }
 202 #else
 203       store_inferior_registers (GR1_REGNUM);
 204       for (regno = GR96_REGNUM; regno < GR96_REGNUM + 32; regno++)
 205         store_inferior_registers (regno);
 206       for (regno = LR0_REGNUM; regno < LR0_REGNUM + 128; regno++)
 207         store_inferior_registers (regno);
 208       store_inferior_registers (CPS_REGNUM);
 209       store_inferior_registers (PC_REGNUM);
 210       store_inferior_registers (NPC_REGNUM);
 211       store_inferior_registers (PC2_REGNUM);
 212       store_inferior_registers (IPC_REGNUM);
 213       store_inferior_registers (IPA_REGNUM);
 214       store_inferior_registers (IPB_REGNUM);
 215       store_inferior_registers (Q_REGNUM);
 216       store_inferior_registers (BP_REGNUM);
 217       store_inferior_registers (FC_REGNUM);
 218 #endif /* ULTRA3 */
 219     }
 220 }
 221
 222 /*
 223  * Fetch an individual register (and supply it).
 224  * return 0 on success, -1 on failure.
 225  * NOTE: Assumes AMD's Binary Compatibility Standard for ptrace().
 226  */
 227 static void
 228 fetch_register (int regno)
 229 {
 230   char buf[128];
 231   int val;
 232
 233   if (CANNOT_FETCH_REGISTER (regno))
 234     {
 235       val = -1;
 236       supply_register (regno, &val);
 237     }
 238   else
 239     {
 240       errno = 0;
 241       val = ptrace (PT_READ_U, inferior_pid,
 242                     (PTRACE_ARG3_TYPE) register_addr (regno, 0), 0);
 243       if (errno != 0)
 244         {
 245           sprintf (buf, "reading register %s (#%d)", REGISTER_NAME (regno), regno);
 246           perror_with_name (buf);
 247         }
 248       else
 249         {
 250           supply_register (regno, &val);
 251         }
 252     }
 253 }
 254
 255
 256 /*
 257  * Read AMD's Binary Compatibilty Standard conforming core file.
 258  * struct ptrace_user is the first thing in the core file
 259  *
 260  * CORE_REG_SECT, CORE_REG_SIZE, WHICH, and REG_ADDR are all ignored.
 261  */
 262
 263 static void
 264 fetch_core_registers (char *core_reg_sect, unsigned core_reg_size,
 265                       int which, CORE_ADDR reg_addr)
 266 {
 267   register int regno;
 268   int val;
 269   char buf[4];
 270
 271   for (regno = 0; regno < NUM_REGS; regno++)
 272     {
 273       if (!CANNOT_FETCH_REGISTER (regno))
 274         {
 275           val = bfd_seek (core_bfd, (file_ptr) register_addr (regno, 0), SEEK_SET);
 276           if (val < 0 || (val = bfd_read (buf, sizeof buf, 1, core_bfd)) < 0)
 277             {
 278               char *buffer = (char *) alloca (strlen (REGISTER_NAME (regno)) + 35);
 279               strcpy (buffer, "Reading core register ");
 280               strcat (buffer, REGISTER_NAME (regno));
 281               perror_with_name (buffer);
 282             }
 283           supply_register (regno, buf);
 284         }
 285     }
 286
 287   /* Fake any registers that are in REGISTER_NAMES, but not available to gdb */
 288   registers_fetched ();
 289 }
 290
 291
 292 /*
 293  * Takes a register number as defined in tm.h via REGISTER_NAMES, and maps
 294  * it to an offset in a struct ptrace_user defined by AMD's BCS.
 295  * That is, it defines the mapping between gdb register numbers and items in
 296  * a struct ptrace_user.
 297  * A register protection scheme is set up here.  If a register not
 298  * available to the user is specified in 'regno', then an address that
 299  * will cause ptrace() to fail is returned.
 300  */
 301 CORE_ADDR
 302 register_addr (int regno, CORE_ADDR blockend)
 303 {
 304   if ((regno >= LR0_REGNUM) && (regno < LR0_REGNUM + 128))
 305     {
 306       return (offsetof (struct ptrace_user, pt_lr[regno - LR0_REGNUM]));
 307     }
 308   else if ((regno >= GR96_REGNUM) && (regno < GR96_REGNUM + 32))
 309     {
 310       return (offsetof (struct ptrace_user, pt_gr[regno - GR96_REGNUM]));
 311     }
 312   else
 313     {
 314       switch (regno)
 315         {
 316         case GR1_REGNUM:
 317           return (offsetof (struct ptrace_user, pt_gr1));
 318         case CPS_REGNUM:
 319           return (offsetof (struct ptrace_user, pt_psr));
 320         case NPC_REGNUM:
 321           return (offsetof (struct ptrace_user, pt_pc0));
 322         case PC_REGNUM:
 323           return (offsetof (struct ptrace_user, pt_pc1));
 324         case PC2_REGNUM:
 325           return (offsetof (struct ptrace_user, pt_pc2));
 326         case IPC_REGNUM:
 327           return (offsetof (struct ptrace_user, pt_ipc));
 328         case IPA_REGNUM:
 329           return (offsetof (struct ptrace_user, pt_ipa));
 330         case IPB_REGNUM:
 331           return (offsetof (struct ptrace_user, pt_ipb));
 332         case Q_REGNUM:
 333           return (offsetof (struct ptrace_user, pt_q));
 334         case BP_REGNUM:
 335           return (offsetof (struct ptrace_user, pt_bp));
 336         case FC_REGNUM:
 337           return (offsetof (struct ptrace_user, pt_fc));
 338         default:
 339           fprintf_filtered (gdb_stderr, "register_addr():Bad register %s (%d)\n",
 340                             REGISTER_NAME (regno), regno);
 341           return (0xffffffff);  /* Should make ptrace() fail */
 342         }
 343     }
 344 }
 345 \f
 346
 347 /* Register that we are able to handle ultra3 core file formats.
 348    FIXME: is this really bfd_target_unknown_flavour? */
 349
 350 static struct core_fns ultra3_core_fns =
 351 {
 352   bfd_target_unknown_flavour,           /* core_flavour */
 353   default_check_format,                 /* check_format */
 354   default_core_sniffer,                 /* core_sniffer */
 355   fetch_core_registers,                 /* core_read_registers */
 356   NULL                                  /* next */
 357 };
 358
 359 void
 360 _initialize_core_ultra3 (void)
 361 {
 362   add_core_fns (&ultra3_core_fns);
 363 }