1 /* Target-dependent code for the x86-64 for GDB, the GNU debugger.
3 Copyright 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Jiri Smid, SuSE Labs.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "gdb_assert.h"
40 #include "x86-64-tdep.h"
41 #include "i387-tdep.h"
43 /* Register information. */
45 struct x86_64_register_info
51 static struct x86_64_register_info x86_64_register_info
[] =
53 { "rax", &builtin_type_int64
},
54 { "rbx", &builtin_type_int64
},
55 { "rcx", &builtin_type_int64
},
56 { "rdx", &builtin_type_int64
},
57 { "rsi", &builtin_type_int64
},
58 { "rdi", &builtin_type_int64
},
59 { "rbp", &builtin_type_void_data_ptr
},
60 { "rsp", &builtin_type_void_data_ptr
},
62 /* %r8 is indeed register number 8. */
63 { "r8", &builtin_type_int64
},
64 { "r9", &builtin_type_int64
},
65 { "r10", &builtin_type_int64
},
66 { "r11", &builtin_type_int64
},
67 { "r12", &builtin_type_int64
},
68 { "r13", &builtin_type_int64
},
69 { "r14", &builtin_type_int64
},
70 { "r15", &builtin_type_int64
},
71 { "rip", &builtin_type_void_func_ptr
},
72 { "eflags", &builtin_type_int32
},
73 { "ds", &builtin_type_int32
},
74 { "es", &builtin_type_int32
},
75 { "fs", &builtin_type_int32
},
76 { "gs", &builtin_type_int32
},
78 /* %st0 is register number 22. */
79 { "st0", &builtin_type_i387_ext
},
80 { "st1", &builtin_type_i387_ext
},
81 { "st2", &builtin_type_i387_ext
},
82 { "st3", &builtin_type_i387_ext
},
83 { "st4", &builtin_type_i387_ext
},
84 { "st5", &builtin_type_i387_ext
},
85 { "st6", &builtin_type_i387_ext
},
86 { "st7", &builtin_type_i387_ext
},
87 { "fctrl", &builtin_type_int32
},
88 { "fstat", &builtin_type_int32
},
89 { "ftag", &builtin_type_int32
},
90 { "fiseg", &builtin_type_int32
},
91 { "fioff", &builtin_type_int32
},
92 { "foseg", &builtin_type_int32
},
93 { "fooff", &builtin_type_int32
},
94 { "fop", &builtin_type_int32
},
96 /* %xmm0 is register number 38. */
97 { "xmm0", &builtin_type_v4sf
},
98 { "xmm1", &builtin_type_v4sf
},
99 { "xmm2", &builtin_type_v4sf
},
100 { "xmm3", &builtin_type_v4sf
},
101 { "xmm4", &builtin_type_v4sf
},
102 { "xmm5", &builtin_type_v4sf
},
103 { "xmm6", &builtin_type_v4sf
},
104 { "xmm7", &builtin_type_v4sf
},
105 { "xmm8", &builtin_type_v4sf
},
106 { "xmm9", &builtin_type_v4sf
},
107 { "xmm10", &builtin_type_v4sf
},
108 { "xmm11", &builtin_type_v4sf
},
109 { "xmm12", &builtin_type_v4sf
},
110 { "xmm13", &builtin_type_v4sf
},
111 { "xmm14", &builtin_type_v4sf
},
112 { "xmm15", &builtin_type_v4sf
},
113 { "mxcsr", &builtin_type_int32
}
116 /* Total number of registers. */
117 #define X86_64_NUM_REGS \
118 (sizeof (x86_64_register_info) / sizeof (x86_64_register_info[0]))
120 /* Return the name of register REGNUM. */
123 x86_64_register_name (int regnum
)
125 if (regnum
>= 0 && regnum
< X86_64_NUM_REGS
)
126 return x86_64_register_info
[regnum
].name
;
131 /* Return the GDB type object for the "standard" data type of data in
135 x86_64_register_type (struct gdbarch
*gdbarch
, int regnum
)
137 gdb_assert (regnum
>= 0 && regnum
< X86_64_NUM_REGS
);
139 return *x86_64_register_info
[regnum
].type
;
142 /* DWARF Register Number Mapping as defined in the System V psABI,
145 static int x86_64_dwarf_regmap
[] =
147 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
148 X86_64_RAX_REGNUM
, X86_64_RDX_REGNUM
, 2, 1,
149 4, X86_64_RDI_REGNUM
,
151 /* Frame Pointer Register RBP. */
154 /* Stack Pointer Register RSP. */
157 /* Extended Integer Registers 8 - 15. */
158 8, 9, 10, 11, 12, 13, 14, 15,
160 /* Return Address RA. Mapped to RIP. */
163 /* SSE Registers 0 - 7. */
164 X86_64_XMM0_REGNUM
+ 0, X86_64_XMM1_REGNUM
,
165 X86_64_XMM0_REGNUM
+ 2, X86_64_XMM0_REGNUM
+ 3,
166 X86_64_XMM0_REGNUM
+ 4, X86_64_XMM0_REGNUM
+ 5,
167 X86_64_XMM0_REGNUM
+ 6, X86_64_XMM0_REGNUM
+ 7,
169 /* Extended SSE Registers 8 - 15. */
170 X86_64_XMM0_REGNUM
+ 8, X86_64_XMM0_REGNUM
+ 9,
171 X86_64_XMM0_REGNUM
+ 10, X86_64_XMM0_REGNUM
+ 11,
172 X86_64_XMM0_REGNUM
+ 12, X86_64_XMM0_REGNUM
+ 13,
173 X86_64_XMM0_REGNUM
+ 14, X86_64_XMM0_REGNUM
+ 15,
175 /* Floating Point Registers 0-7. */
176 X86_64_ST0_REGNUM
+ 0, X86_64_ST0_REGNUM
+ 1,
177 X86_64_ST0_REGNUM
+ 2, X86_64_ST0_REGNUM
+ 3,
178 X86_64_ST0_REGNUM
+ 4, X86_64_ST0_REGNUM
+ 5,
179 X86_64_ST0_REGNUM
+ 6, X86_64_ST0_REGNUM
+ 7
182 static const int x86_64_dwarf_regmap_len
=
183 (sizeof (x86_64_dwarf_regmap
) / sizeof (x86_64_dwarf_regmap
[0]));
185 /* Convert DWARF register number REG to the appropriate register
186 number used by GDB. */
189 x86_64_dwarf_reg_to_regnum (int reg
)
193 if (reg
>= 0 || reg
< x86_64_dwarf_regmap_len
)
194 regnum
= x86_64_dwarf_regmap
[reg
];
197 warning ("Unmapped DWARF Register #%d encountered\n", reg
);
202 /* Return nonzero if a value of type TYPE stored in register REGNUM
203 needs any special handling. */
206 x86_64_convert_register_p (int regnum
, struct type
*type
)
208 return i386_fp_regnum_p (regnum
);
212 /* Register classes as defined in the psABI. */
226 /* Return the union class of CLASS1 and CLASS2. See the psABI for
229 static enum amd64_reg_class
230 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
232 /* Rule (a): If both classes are equal, this is the resulting class. */
233 if (class1
== class2
)
236 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
237 is the other class. */
238 if (class1
== AMD64_NO_CLASS
)
240 if (class2
== AMD64_NO_CLASS
)
243 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
244 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
247 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
248 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
249 return AMD64_INTEGER
;
251 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
252 MEMORY is used as class. */
253 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
254 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
255 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
258 /* Rule (f): Otherwise class SSE is used. */
262 static void amd64_classify (struct type
*type
, enum amd64_reg_class
class[2]);
264 /* Classify TYPE according to the rules for aggregate (structures and
265 arrays) and union types, and store the result in CLASS. */
268 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class
class[2])
270 int len
= TYPE_LENGTH (type
);
272 /* 1. If the size of an object is larger than two eightbytes, or in
273 C++, is a non-POD structure or union type, or contains
274 unaligned fields, it has class memory. */
277 class[0] = class[1] = AMD64_MEMORY
;
281 /* 2. Both eightbytes get initialized to class NO_CLASS. */
282 class[0] = class[1] = AMD64_NO_CLASS
;
284 /* 3. Each field of an object is classified recursively so that
285 always two fields are considered. The resulting class is
286 calculated according to the classes of the fields in the
289 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
291 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
293 /* All fields in an array have the same type. */
294 amd64_classify (subtype
, class);
295 if (len
> 8 && class[1] == AMD64_NO_CLASS
)
302 /* Structure or union. */
303 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_STRUCT
304 || TYPE_CODE (type
) == TYPE_CODE_UNION
);
306 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
308 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
309 int pos
= TYPE_FIELD_BITPOS (type
, i
) / 64;
310 enum amd64_reg_class subclass
[2];
312 gdb_assert (pos
== 0 || pos
== 1);
314 amd64_classify (subtype
, subclass
);
315 class[pos
] = amd64_merge_classes (class[pos
], subclass
[0]);
317 class[1] = amd64_merge_classes (class[1], subclass
[1]);
321 /* 4. Then a post merger cleanup is done: */
323 /* Rule (a): If one of the classes is MEMORY, the whole argument is
325 if (class[0] == AMD64_MEMORY
|| class[1] == AMD64_MEMORY
)
326 class[0] = class[1] = AMD64_MEMORY
;
328 /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to
330 if (class[0] == AMD64_SSEUP
)
331 class[0] = AMD64_SSE
;
332 if (class[1] == AMD64_SSEUP
&& class[0] != AMD64_SSE
)
333 class[1] = AMD64_SSE
;
336 /* Classify TYPE, and store the result in CLASS. */
339 amd64_classify (struct type
*type
, enum amd64_reg_class
class[2])
341 enum type_code code
= TYPE_CODE (type
);
342 int len
= TYPE_LENGTH (type
);
344 class[0] = class[1] = AMD64_NO_CLASS
;
346 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
347 long, long long, and pointers are in the INTEGER class. */
348 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
349 || code
== TYPE_CODE_PTR
|| code
== TYPE_CODE_REF
)
350 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
351 class[0] = AMD64_INTEGER
;
353 /* Arguments of types float, double and __m64 are in class SSE. */
354 else if (code
== TYPE_CODE_FLT
&& (len
== 4 || len
== 8))
356 class[0] = AMD64_SSE
;
358 /* Arguments of types __float128 and __m128 are split into two
359 halves. The least significant ones belong to class SSE, the most
360 significant one to class SSEUP. */
361 /* FIXME: __float128, __m128. */
363 /* The 64-bit mantissa of arguments of type long double belongs to
364 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
366 else if (code
== TYPE_CODE_FLT
&& len
== 16)
367 /* Class X87 and X87UP. */
368 class[0] = AMD64_X87
, class[1] = AMD64_X87UP
;
371 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
372 || code
== TYPE_CODE_UNION
)
373 amd64_classify_aggregate (type
, class);
376 static enum return_value_convention
377 amd64_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
378 struct regcache
*regcache
,
379 void *readbuf
, const void *writebuf
)
381 enum amd64_reg_class
class[2];
382 int len
= TYPE_LENGTH (type
);
383 static int integer_regnum
[] = { X86_64_RAX_REGNUM
, X86_64_RDX_REGNUM
};
384 static int sse_regnum
[] = { X86_64_XMM0_REGNUM
, X86_64_XMM1_REGNUM
};
389 gdb_assert (!(readbuf
&& writebuf
));
391 /* 1. Classify the return type with the classification algorithm. */
392 amd64_classify (type
, class);
394 /* 2. If the type has class MEMORY, then the caller provides space
395 for the return value and passes the address of this storage in
396 %rdi as if it were the first argument to the function. In
397 effect, this address becomes a hidden first argument. */
398 if (class[0] == AMD64_MEMORY
)
399 return RETURN_VALUE_STRUCT_CONVENTION
;
401 gdb_assert (class[1] != AMD64_MEMORY
);
402 gdb_assert (len
<= 16);
404 for (i
= 0; len
> 0; i
++, len
-= 8)
412 /* 3. If the class is INTEGER, the next available register
413 of the sequence %rax, %rdx is used. */
414 regnum
= integer_regnum
[integer_reg
++];
418 /* 4. If the class is SSE, the next available SSE register
419 of the sequence %xmm0, %xmm1 is used. */
420 regnum
= sse_regnum
[sse_reg
++];
424 /* 5. If the class is SSEUP, the eightbyte is passed in the
425 upper half of the last used SSE register. */
426 gdb_assert (sse_reg
> 0);
427 regnum
= sse_regnum
[sse_reg
- 1];
432 /* 6. If the class is X87, the value is returned on the X87
433 stack in %st0 as 80-bit x87 number. */
434 regnum
= X86_64_ST0_REGNUM
;
436 i387_return_value (gdbarch
, regcache
);
440 /* 7. If the class is X87UP, the value is returned together
441 with the previous X87 value in %st0. */
442 gdb_assert (i
> 0 && class[0] == AMD64_X87
);
443 regnum
= X86_64_ST0_REGNUM
;
452 gdb_assert (!"Unexpected register class.");
455 gdb_assert (regnum
!= -1);
458 regcache_raw_read_part (regcache
, regnum
, offset
, min (len
, 8),
459 (char *) readbuf
+ i
* 8);
461 regcache_raw_write_part (regcache
, regnum
, offset
, min (len
, 8),
462 (const char *) writebuf
+ i
* 8);
465 return RETURN_VALUE_REGISTER_CONVENTION
;
470 amd64_push_arguments (struct regcache
*regcache
, int nargs
,
471 struct value
**args
, CORE_ADDR sp
)
473 static int integer_regnum
[] =
475 X86_64_RDI_REGNUM
, 4, /* %rdi, %rsi */
476 X86_64_RDX_REGNUM
, 2, /* %rdx, %rcx */
479 static int sse_regnum
[] =
481 /* %xmm0 ... %xmm7 */
482 X86_64_XMM0_REGNUM
+ 0, X86_64_XMM1_REGNUM
,
483 X86_64_XMM0_REGNUM
+ 2, X86_64_XMM0_REGNUM
+ 3,
484 X86_64_XMM0_REGNUM
+ 4, X86_64_XMM0_REGNUM
+ 5,
485 X86_64_XMM0_REGNUM
+ 6, X86_64_XMM0_REGNUM
+ 7,
487 struct value
**stack_args
= alloca (nargs
* sizeof (struct value
*));
488 int num_stack_args
= 0;
489 int num_elements
= 0;
495 for (i
= 0; i
< nargs
; i
++)
497 struct type
*type
= VALUE_TYPE (args
[i
]);
498 int len
= TYPE_LENGTH (type
);
499 enum amd64_reg_class
class[2];
500 int needed_integer_regs
= 0;
501 int needed_sse_regs
= 0;
504 /* Classify argument. */
505 amd64_classify (type
, class);
507 /* Calculate the number of integer and SSE registers needed for
509 for (j
= 0; j
< 2; j
++)
511 if (class[j
] == AMD64_INTEGER
)
512 needed_integer_regs
++;
513 else if (class[j
] == AMD64_SSE
)
517 /* Check whether enough registers are available, and if the
518 argument should be passed in registers at all. */
519 if (integer_reg
+ needed_integer_regs
> ARRAY_SIZE (integer_regnum
)
520 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
521 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
523 /* The argument will be passed on the stack. */
524 num_elements
+= ((len
+ 7) / 8);
525 stack_args
[num_stack_args
++] = args
[i
];
529 /* The argument will be passed in registers. */
530 char *valbuf
= VALUE_CONTENTS (args
[i
]);
533 gdb_assert (len
<= 16);
535 for (j
= 0; len
> 0; j
++, len
-= 8)
543 regnum
= integer_regnum
[integer_reg
++];
547 regnum
= sse_regnum
[sse_reg
++];
551 gdb_assert (sse_reg
> 0);
552 regnum
= sse_regnum
[sse_reg
- 1];
557 gdb_assert (!"Unexpected register class.");
560 gdb_assert (regnum
!= -1);
561 memset (buf
, 0, sizeof buf
);
562 memcpy (buf
, valbuf
+ j
* 8, min (len
, 8));
563 regcache_raw_write_part (regcache
, regnum
, offset
, 8, buf
);
568 /* Allocate space for the arguments on the stack. */
569 sp
-= num_elements
* 8;
571 /* The psABI says that "The end of the input argument area shall be
572 aligned on a 16 byte boundary." */
575 /* Write out the arguments to the stack. */
576 for (i
= 0; i
< num_stack_args
; i
++)
578 struct type
*type
= VALUE_TYPE (stack_args
[i
]);
579 char *valbuf
= VALUE_CONTENTS (stack_args
[i
]);
580 int len
= TYPE_LENGTH (type
);
582 write_memory (sp
+ element
* 8, valbuf
, len
);
583 element
+= ((len
+ 7) / 8);
586 /* The psABI says that "For calls that may call functions that use
587 varargs or stdargs (prototype-less calls or calls to functions
588 containing ellipsis (...) in the declaration) %al is used as
589 hidden argument to specify the number of SSE registers used. */
590 regcache_raw_write_unsigned (regcache
, X86_64_RAX_REGNUM
, sse_reg
);
595 x86_64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
596 struct regcache
*regcache
, CORE_ADDR bp_addr
,
597 int nargs
, struct value
**args
, CORE_ADDR sp
,
598 int struct_return
, CORE_ADDR struct_addr
)
602 /* Pass arguments. */
603 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
);
605 /* Pass "hidden" argument". */
608 store_unsigned_integer (buf
, 8, struct_addr
);
609 regcache_cooked_write (regcache
, X86_64_RDI_REGNUM
, buf
);
612 /* Store return address. */
614 store_unsigned_integer (buf
, 8, bp_addr
);
615 write_memory (sp
, buf
, 8);
617 /* Finally, update the stack pointer... */
618 store_unsigned_integer (buf
, 8, sp
);
619 regcache_cooked_write (regcache
, X86_64_RSP_REGNUM
, buf
);
621 /* ...and fake a frame pointer. */
622 regcache_cooked_write (regcache
, X86_64_RBP_REGNUM
, buf
);
628 /* The maximum number of saved registers. This should include %rip. */
629 #define X86_64_NUM_SAVED_REGS X86_64_NUM_GREGS
631 struct x86_64_frame_cache
638 /* Saved registers. */
639 CORE_ADDR saved_regs
[X86_64_NUM_SAVED_REGS
];
642 /* Do we have a frame? */
646 /* Allocate and initialize a frame cache. */
648 static struct x86_64_frame_cache
*
649 x86_64_alloc_frame_cache (void)
651 struct x86_64_frame_cache
*cache
;
654 cache
= FRAME_OBSTACK_ZALLOC (struct x86_64_frame_cache
);
658 cache
->sp_offset
= -8;
661 /* Saved registers. We initialize these to -1 since zero is a valid
662 offset (that's where %rbp is supposed to be stored). */
663 for (i
= 0; i
< X86_64_NUM_SAVED_REGS
; i
++)
664 cache
->saved_regs
[i
] = -1;
667 /* Frameless until proven otherwise. */
668 cache
->frameless_p
= 1;
673 /* Do a limited analysis of the prologue at PC and update CACHE
674 accordingly. Bail out early if CURRENT_PC is reached. Return the
675 address where the analysis stopped.
677 We will handle only functions beginning with:
680 movq %rsp, %rbp 0x48 0x89 0xe5
682 Any function that doesn't start with this sequence will be assumed
683 to have no prologue and thus no valid frame pointer in %rbp. */
686 x86_64_analyze_prologue (CORE_ADDR pc
, CORE_ADDR current_pc
,
687 struct x86_64_frame_cache
*cache
)
689 static unsigned char proto
[3] = { 0x48, 0x89, 0xe5 };
690 unsigned char buf
[3];
693 if (current_pc
<= pc
)
696 op
= read_memory_unsigned_integer (pc
, 1);
698 if (op
== 0x55) /* pushq %rbp */
700 /* Take into account that we've executed the `pushq %rbp' that
701 starts this instruction sequence. */
702 cache
->saved_regs
[X86_64_RBP_REGNUM
] = 0;
703 cache
->sp_offset
+= 8;
705 /* If that's all, return now. */
706 if (current_pc
<= pc
+ 1)
709 /* Check for `movq %rsp, %rbp'. */
710 read_memory (pc
+ 1, buf
, 3);
711 if (memcmp (buf
, proto
, 3) != 0)
714 /* OK, we actually have a frame. */
715 cache
->frameless_p
= 0;
722 /* Return PC of first real instruction. */
725 x86_64_skip_prologue (CORE_ADDR start_pc
)
727 struct x86_64_frame_cache cache
;
730 pc
= x86_64_analyze_prologue (start_pc
, 0xffffffffffffffff, &cache
);
731 if (cache
.frameless_p
)
740 static struct x86_64_frame_cache
*
741 x86_64_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
743 struct x86_64_frame_cache
*cache
;
750 cache
= x86_64_alloc_frame_cache ();
753 cache
->pc
= frame_func_unwind (next_frame
);
755 x86_64_analyze_prologue (cache
->pc
, frame_pc_unwind (next_frame
), cache
);
757 if (cache
->frameless_p
)
759 /* We didn't find a valid frame, which means that CACHE->base
760 currently holds the frame pointer for our calling frame. If
761 we're at the start of a function, or somewhere half-way its
762 prologue, the function's frame probably hasn't been fully
763 setup yet. Try to reconstruct the base address for the stack
764 frame by looking at the stack pointer. For truly "frameless"
765 functions this might work too. */
767 frame_unwind_register (next_frame
, X86_64_RSP_REGNUM
, buf
);
768 cache
->base
= extract_unsigned_integer (buf
, 8) + cache
->sp_offset
;
772 frame_unwind_register (next_frame
, X86_64_RBP_REGNUM
, buf
);
773 cache
->base
= extract_unsigned_integer (buf
, 8);
776 /* Now that we have the base address for the stack frame we can
777 calculate the value of %rsp in the calling frame. */
778 cache
->saved_sp
= cache
->base
+ 16;
780 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
781 frame we find it at the same offset from the reconstructed base
783 cache
->saved_regs
[X86_64_RIP_REGNUM
] = 8;
785 /* Adjust all the saved registers such that they contain addresses
786 instead of offsets. */
787 for (i
= 0; i
< X86_64_NUM_SAVED_REGS
; i
++)
788 if (cache
->saved_regs
[i
] != -1)
789 cache
->saved_regs
[i
] += cache
->base
;
795 x86_64_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
796 struct frame_id
*this_id
)
798 struct x86_64_frame_cache
*cache
=
799 x86_64_frame_cache (next_frame
, this_cache
);
801 /* This marks the outermost frame. */
802 if (cache
->base
== 0)
805 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
809 x86_64_frame_prev_register (struct frame_info
*next_frame
, void **this_cache
,
810 int regnum
, int *optimizedp
,
811 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
812 int *realnump
, void *valuep
)
814 struct x86_64_frame_cache
*cache
=
815 x86_64_frame_cache (next_frame
, this_cache
);
817 gdb_assert (regnum
>= 0);
819 if (regnum
== SP_REGNUM
&& cache
->saved_sp
)
827 /* Store the value. */
828 store_unsigned_integer (valuep
, 8, cache
->saved_sp
);
833 if (regnum
< X86_64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
836 *lvalp
= lval_memory
;
837 *addrp
= cache
->saved_regs
[regnum
];
841 /* Read the value in from memory. */
842 read_memory (*addrp
, valuep
,
843 register_size (current_gdbarch
, regnum
));
848 frame_register_unwind (next_frame
, regnum
,
849 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
852 static const struct frame_unwind x86_64_frame_unwind
=
855 x86_64_frame_this_id
,
856 x86_64_frame_prev_register
859 static const struct frame_unwind
*
860 x86_64_frame_sniffer (struct frame_info
*next_frame
)
862 return &x86_64_frame_unwind
;
866 /* Signal trampolines. */
868 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
869 64-bit variants. This would require using identical frame caches
870 on both platforms. */
872 static struct x86_64_frame_cache
*
873 x86_64_sigtramp_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
875 struct x86_64_frame_cache
*cache
;
876 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
884 cache
= x86_64_alloc_frame_cache ();
886 frame_unwind_register (next_frame
, X86_64_RSP_REGNUM
, buf
);
887 cache
->base
= extract_unsigned_integer (buf
, 8) - 8;
889 addr
= tdep
->sigcontext_addr (next_frame
);
890 gdb_assert (tdep
->sc_reg_offset
);
891 gdb_assert (tdep
->sc_num_regs
<= X86_64_NUM_SAVED_REGS
);
892 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
893 if (tdep
->sc_reg_offset
[i
] != -1)
894 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
901 x86_64_sigtramp_frame_this_id (struct frame_info
*next_frame
,
902 void **this_cache
, struct frame_id
*this_id
)
904 struct x86_64_frame_cache
*cache
=
905 x86_64_sigtramp_frame_cache (next_frame
, this_cache
);
907 (*this_id
) = frame_id_build (cache
->base
+ 16, frame_pc_unwind (next_frame
));
911 x86_64_sigtramp_frame_prev_register (struct frame_info
*next_frame
,
913 int regnum
, int *optimizedp
,
914 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
915 int *realnump
, void *valuep
)
917 /* Make sure we've initialized the cache. */
918 x86_64_sigtramp_frame_cache (next_frame
, this_cache
);
920 x86_64_frame_prev_register (next_frame
, this_cache
, regnum
,
921 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
924 static const struct frame_unwind x86_64_sigtramp_frame_unwind
=
927 x86_64_sigtramp_frame_this_id
,
928 x86_64_sigtramp_frame_prev_register
931 static const struct frame_unwind
*
932 x86_64_sigtramp_frame_sniffer (struct frame_info
*next_frame
)
934 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
937 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
938 if (PC_IN_SIGTRAMP (pc
, name
))
940 gdb_assert (gdbarch_tdep (current_gdbarch
)->sigcontext_addr
);
942 return &x86_64_sigtramp_frame_unwind
;
950 x86_64_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
952 struct x86_64_frame_cache
*cache
=
953 x86_64_frame_cache (next_frame
, this_cache
);
958 static const struct frame_base x86_64_frame_base
=
960 &x86_64_frame_unwind
,
961 x86_64_frame_base_address
,
962 x86_64_frame_base_address
,
963 x86_64_frame_base_address
966 static struct frame_id
967 x86_64_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
972 frame_unwind_register (next_frame
, X86_64_RBP_REGNUM
, buf
);
973 fp
= extract_unsigned_integer (buf
, 8);
975 return frame_id_build (fp
+ 16, frame_pc_unwind (next_frame
));
978 /* 16 byte align the SP per frame requirements. */
981 x86_64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
983 return sp
& -(CORE_ADDR
)16;
987 /* Supply register REGNUM from the floating-point register set REGSET
988 to register cache REGCACHE. If REGNUM is -1, do this for all
989 registers in REGSET. */
992 x86_64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
993 int regnum
, const void *fpregs
, size_t len
)
995 const struct gdbarch_tdep
*tdep
= regset
->descr
;
997 gdb_assert (len
== tdep
->sizeof_fpregset
);
998 x86_64_supply_fxsave (regcache
, regnum
, fpregs
);
1001 /* Return the appropriate register set for the core section identified
1002 by SECT_NAME and SECT_SIZE. */
1004 static const struct regset
*
1005 x86_64_regset_from_core_section (struct gdbarch
*gdbarch
,
1006 const char *sect_name
, size_t sect_size
)
1008 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1010 if (strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
1012 if (tdep
->fpregset
== NULL
)
1014 tdep
->fpregset
= XMALLOC (struct regset
);
1015 tdep
->fpregset
->descr
= tdep
;
1016 tdep
->fpregset
->supply_regset
= x86_64_supply_fpregset
;
1019 return tdep
->fpregset
;
1022 return i386_regset_from_core_section (gdbarch
, sect_name
, sect_size
);
1027 x86_64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
1029 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1031 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
1032 floating-point registers. */
1033 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
1035 /* AMD64 has an FPU and 16 SSE registers. */
1036 tdep
->st0_regnum
= X86_64_ST0_REGNUM
;
1037 tdep
->num_xmm_regs
= 16;
1039 /* This is what all the fuss is about. */
1040 set_gdbarch_long_bit (gdbarch
, 64);
1041 set_gdbarch_long_long_bit (gdbarch
, 64);
1042 set_gdbarch_ptr_bit (gdbarch
, 64);
1044 /* In contrast to the i386, on the x86-64 a `long double' actually
1045 takes up 128 bits, even though it's still based on the i387
1046 extended floating-point format which has only 80 significant bits. */
1047 set_gdbarch_long_double_bit (gdbarch
, 128);
1049 set_gdbarch_num_regs (gdbarch
, X86_64_NUM_REGS
);
1050 set_gdbarch_register_name (gdbarch
, x86_64_register_name
);
1051 set_gdbarch_register_type (gdbarch
, x86_64_register_type
);
1053 /* Register numbers of various important registers. */
1054 set_gdbarch_sp_regnum (gdbarch
, X86_64_RSP_REGNUM
); /* %rsp */
1055 set_gdbarch_pc_regnum (gdbarch
, X86_64_RIP_REGNUM
); /* %rip */
1056 set_gdbarch_ps_regnum (gdbarch
, X86_64_EFLAGS_REGNUM
); /* %eflags */
1057 set_gdbarch_fp0_regnum (gdbarch
, X86_64_ST0_REGNUM
); /* %st(0) */
1059 /* The "default" register numbering scheme for the x86-64 is
1060 referred to as the "DWARF Register Number Mapping" in the System
1061 V psABI. The preferred debugging format for all known x86-64
1062 targets is actually DWARF2, and GCC doesn't seem to support DWARF
1063 (that is DWARF-1), but we provide the same mapping just in case.
1064 This mapping is also used for stabs, which GCC does support. */
1065 set_gdbarch_stab_reg_to_regnum (gdbarch
, x86_64_dwarf_reg_to_regnum
);
1066 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, x86_64_dwarf_reg_to_regnum
);
1067 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, x86_64_dwarf_reg_to_regnum
);
1069 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
1070 be in use on any of the supported x86-64 targets. */
1072 /* Call dummy code. */
1073 set_gdbarch_push_dummy_call (gdbarch
, x86_64_push_dummy_call
);
1074 set_gdbarch_frame_align (gdbarch
, x86_64_frame_align
);
1075 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
1077 set_gdbarch_convert_register_p (gdbarch
, x86_64_convert_register_p
);
1078 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
1079 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
1081 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
1082 /* Override, since this is handled by x86_64_extract_return_value. */
1083 set_gdbarch_extract_struct_value_address (gdbarch
, NULL
);
1085 set_gdbarch_skip_prologue (gdbarch
, x86_64_skip_prologue
);
1087 /* Avoid wiring in the MMX registers for now. */
1088 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
1089 tdep
->mm0_regnum
= -1;
1091 set_gdbarch_unwind_dummy_id (gdbarch
, x86_64_unwind_dummy_id
);
1093 /* FIXME: kettenis/20021026: This is ELF-specific. Fine for now,
1094 since all supported x86-64 targets are ELF, but that might change
1096 set_gdbarch_in_solib_call_trampoline (gdbarch
, in_plt_section
);
1098 frame_unwind_append_sniffer (gdbarch
, x86_64_sigtramp_frame_sniffer
);
1099 frame_unwind_append_sniffer (gdbarch
, x86_64_frame_sniffer
);
1100 frame_base_set_default (gdbarch
, &x86_64_frame_base
);
1102 /* If we have a register mapping, enable the generic core file support. */
1103 if (tdep
->gregset_reg_offset
)
1104 set_gdbarch_regset_from_core_section (gdbarch
,
1105 x86_64_regset_from_core_section
);
1109 #define I387_ST0_REGNUM X86_64_ST0_REGNUM
1111 /* The 64-bit FXSAVE format differs from the 32-bit format in the
1112 sense that the instruction pointer and data pointer are simply
1113 64-bit offsets into the code segment and the data segment instead
1114 of a selector offset pair. The functions below store the upper 32
1115 bits of these pointers (instead of just the 16-bits of the segment
1118 /* Fill register REGNUM in REGCACHE with the appropriate
1119 floating-point or SSE register value from *FXSAVE. If REGNUM is
1120 -1, do this for all registers. This function masks off any of the
1121 reserved bits in *FXSAVE. */
1124 x86_64_supply_fxsave (struct regcache
*regcache
, int regnum
,
1127 i387_supply_fxsave (regcache
, regnum
, fxsave
);
1131 const char *regs
= fxsave
;
1133 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM
)
1134 regcache_raw_supply (regcache
, I387_FISEG_REGNUM
, regs
+ 12);
1135 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM
)
1136 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM
, regs
+ 20);
1140 /* Fill register REGNUM (if it is a floating-point or SSE register) in
1141 *FXSAVE with the value in GDB's register cache. If REGNUM is -1, do
1142 this for all registers. This function doesn't touch any of the
1143 reserved bits in *FXSAVE. */
1146 x86_64_fill_fxsave (char *fxsave
, int regnum
)
1148 i387_fill_fxsave (fxsave
, regnum
);
1150 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM
)
1151 regcache_collect (I387_FISEG_REGNUM
, fxsave
+ 12);
1152 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM
)
1153 regcache_collect (I387_FOSEG_REGNUM
, fxsave
+ 20);