1 /* Target-dependent code for the x86-64 for GDB, the GNU debugger.
3 Copyright 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Jiri Smid, SuSE Labs.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "gdb_assert.h"
40 #include "x86-64-tdep.h"
41 #include "i387-tdep.h"
43 /* Register information. */
45 struct x86_64_register_info
51 static struct x86_64_register_info x86_64_register_info
[] =
53 { "rax", &builtin_type_int64
},
54 { "rbx", &builtin_type_int64
},
55 { "rcx", &builtin_type_int64
},
56 { "rdx", &builtin_type_int64
},
57 { "rsi", &builtin_type_int64
},
58 { "rdi", &builtin_type_int64
},
59 { "rbp", &builtin_type_void_data_ptr
},
60 { "rsp", &builtin_type_void_data_ptr
},
62 /* %r8 is indeed register number 8. */
63 { "r8", &builtin_type_int64
},
64 { "r9", &builtin_type_int64
},
65 { "r10", &builtin_type_int64
},
66 { "r11", &builtin_type_int64
},
67 { "r12", &builtin_type_int64
},
68 { "r13", &builtin_type_int64
},
69 { "r14", &builtin_type_int64
},
70 { "r15", &builtin_type_int64
},
71 { "rip", &builtin_type_void_func_ptr
},
72 { "eflags", &builtin_type_int32
},
73 { "ds", &builtin_type_int32
},
74 { "es", &builtin_type_int32
},
75 { "fs", &builtin_type_int32
},
76 { "gs", &builtin_type_int32
},
78 /* %st0 is register number 22. */
79 { "st0", &builtin_type_i387_ext
},
80 { "st1", &builtin_type_i387_ext
},
81 { "st2", &builtin_type_i387_ext
},
82 { "st3", &builtin_type_i387_ext
},
83 { "st4", &builtin_type_i387_ext
},
84 { "st5", &builtin_type_i387_ext
},
85 { "st6", &builtin_type_i387_ext
},
86 { "st7", &builtin_type_i387_ext
},
87 { "fctrl", &builtin_type_int32
},
88 { "fstat", &builtin_type_int32
},
89 { "ftag", &builtin_type_int32
},
90 { "fiseg", &builtin_type_int32
},
91 { "fioff", &builtin_type_int32
},
92 { "foseg", &builtin_type_int32
},
93 { "fooff", &builtin_type_int32
},
94 { "fop", &builtin_type_int32
},
96 /* %xmm0 is register number 38. */
97 { "xmm0", &builtin_type_v4sf
},
98 { "xmm1", &builtin_type_v4sf
},
99 { "xmm2", &builtin_type_v4sf
},
100 { "xmm3", &builtin_type_v4sf
},
101 { "xmm4", &builtin_type_v4sf
},
102 { "xmm5", &builtin_type_v4sf
},
103 { "xmm6", &builtin_type_v4sf
},
104 { "xmm7", &builtin_type_v4sf
},
105 { "xmm8", &builtin_type_v4sf
},
106 { "xmm9", &builtin_type_v4sf
},
107 { "xmm10", &builtin_type_v4sf
},
108 { "xmm11", &builtin_type_v4sf
},
109 { "xmm12", &builtin_type_v4sf
},
110 { "xmm13", &builtin_type_v4sf
},
111 { "xmm14", &builtin_type_v4sf
},
112 { "xmm15", &builtin_type_v4sf
},
113 { "mxcsr", &builtin_type_int32
}
116 /* Total number of registers. */
117 #define X86_64_NUM_REGS \
118 (sizeof (x86_64_register_info) / sizeof (x86_64_register_info[0]))
120 /* Return the name of register REGNUM. */
123 x86_64_register_name (int regnum
)
125 if (regnum
>= 0 && regnum
< X86_64_NUM_REGS
)
126 return x86_64_register_info
[regnum
].name
;
131 /* Return the GDB type object for the "standard" data type of data in
135 x86_64_register_type (struct gdbarch
*gdbarch
, int regnum
)
137 gdb_assert (regnum
>= 0 && regnum
< X86_64_NUM_REGS
);
139 return *x86_64_register_info
[regnum
].type
;
142 /* DWARF Register Number Mapping as defined in the System V psABI,
145 static int x86_64_dwarf_regmap
[] =
147 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
148 X86_64_RAX_REGNUM
, X86_64_RDX_REGNUM
, 2, 1,
149 4, X86_64_RDI_REGNUM
,
151 /* Frame Pointer Register RBP. */
154 /* Stack Pointer Register RSP. */
157 /* Extended Integer Registers 8 - 15. */
158 8, 9, 10, 11, 12, 13, 14, 15,
160 /* Return Address RA. Not mapped. */
163 /* SSE Registers 0 - 7. */
164 X86_64_XMM0_REGNUM
+ 0, X86_64_XMM1_REGNUM
,
165 X86_64_XMM0_REGNUM
+ 2, X86_64_XMM0_REGNUM
+ 3,
166 X86_64_XMM0_REGNUM
+ 4, X86_64_XMM0_REGNUM
+ 5,
167 X86_64_XMM0_REGNUM
+ 6, X86_64_XMM0_REGNUM
+ 7,
169 /* Extended SSE Registers 8 - 15. */
170 X86_64_XMM0_REGNUM
+ 8, X86_64_XMM0_REGNUM
+ 9,
171 X86_64_XMM0_REGNUM
+ 10, X86_64_XMM0_REGNUM
+ 11,
172 X86_64_XMM0_REGNUM
+ 12, X86_64_XMM0_REGNUM
+ 13,
173 X86_64_XMM0_REGNUM
+ 14, X86_64_XMM0_REGNUM
+ 15,
175 /* Floating Point Registers 0-7. */
176 X86_64_ST0_REGNUM
+ 0, X86_64_ST0_REGNUM
+ 1,
177 X86_64_ST0_REGNUM
+ 2, X86_64_ST0_REGNUM
+ 3,
178 X86_64_ST0_REGNUM
+ 4, X86_64_ST0_REGNUM
+ 5,
179 X86_64_ST0_REGNUM
+ 6, X86_64_ST0_REGNUM
+ 7
182 static const int x86_64_dwarf_regmap_len
=
183 (sizeof (x86_64_dwarf_regmap
) / sizeof (x86_64_dwarf_regmap
[0]));
185 /* Convert DWARF register number REG to the appropriate register
186 number used by GDB. */
189 x86_64_dwarf_reg_to_regnum (int reg
)
193 if (reg
>= 0 || reg
< x86_64_dwarf_regmap_len
)
194 regnum
= x86_64_dwarf_regmap
[reg
];
197 warning ("Unmapped DWARF Register #%d encountered\n", reg
);
202 /* Return nonzero if a value of type TYPE stored in register REGNUM
203 needs any special handling. */
206 x86_64_convert_register_p (int regnum
, struct type
*type
)
208 return i386_fp_regnum_p (regnum
);
212 /* The returning of values is done according to the special algorithm.
213 Some types are returned in registers an some (big structures) in
214 memory. See the System V psABI for details. */
216 #define MAX_CLASSES 4
218 enum x86_64_reg_class
221 X86_64_INTEGER_CLASS
,
222 X86_64_INTEGERSI_CLASS
,
232 /* Return the union class of CLASS1 and CLASS2.
233 See the System V psABI for details. */
235 static enum x86_64_reg_class
236 merge_classes (enum x86_64_reg_class class1
, enum x86_64_reg_class class2
)
238 /* Rule (a): If both classes are equal, this is the resulting class. */
239 if (class1
== class2
)
242 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
243 is the other class. */
244 if (class1
== X86_64_NO_CLASS
)
246 if (class2
== X86_64_NO_CLASS
)
249 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
250 if (class1
== X86_64_MEMORY_CLASS
|| class2
== X86_64_MEMORY_CLASS
)
251 return X86_64_MEMORY_CLASS
;
253 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
254 if ((class1
== X86_64_INTEGERSI_CLASS
&& class2
== X86_64_SSESF_CLASS
)
255 || (class2
== X86_64_INTEGERSI_CLASS
&& class1
== X86_64_SSESF_CLASS
))
256 return X86_64_INTEGERSI_CLASS
;
257 if (class1
== X86_64_INTEGER_CLASS
|| class1
== X86_64_INTEGERSI_CLASS
258 || class2
== X86_64_INTEGER_CLASS
|| class2
== X86_64_INTEGERSI_CLASS
)
259 return X86_64_INTEGER_CLASS
;
261 /* Rule (e): If one of the classes is X87 or X87UP class, MEMORY is
263 if (class1
== X86_64_X87_CLASS
|| class1
== X86_64_X87UP_CLASS
264 || class2
== X86_64_X87_CLASS
|| class2
== X86_64_X87UP_CLASS
)
265 return X86_64_MEMORY_CLASS
;
267 /* Rule (f): Otherwise class SSE is used. */
268 return X86_64_SSE_CLASS
;
271 /* Classify the argument type. CLASSES will be filled by the register
272 class used to pass each word of the operand. The number of words
273 is returned. In case the parameter should be passed in memory, 0
274 is returned. As a special case for zero sized containers,
275 classes[0] will be NO_CLASS and 1 is returned.
277 See the System V psABI for details. */
280 classify_argument (struct type
*type
,
281 enum x86_64_reg_class classes
[MAX_CLASSES
], int bit_offset
)
283 int bytes
= TYPE_LENGTH (type
);
284 int words
= (bytes
+ 8 - 1) / 8;
286 switch (TYPE_CODE (type
))
288 case TYPE_CODE_ARRAY
:
289 case TYPE_CODE_STRUCT
:
290 case TYPE_CODE_UNION
:
293 enum x86_64_reg_class subclasses
[MAX_CLASSES
];
295 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
299 for (i
= 0; i
< words
; i
++)
300 classes
[i
] = X86_64_NO_CLASS
;
302 /* Zero sized arrays or structures are NO_CLASS. We return 0
303 to signalize memory class, so handle it as special case. */
306 classes
[0] = X86_64_NO_CLASS
;
309 switch (TYPE_CODE (type
))
311 case TYPE_CODE_STRUCT
:
314 for (j
= 0; j
< TYPE_NFIELDS (type
); ++j
)
316 int num
= classify_argument (TYPE_FIELDS (type
)[j
].type
,
318 (TYPE_FIELDS (type
)[j
].loc
.
319 bitpos
+ bit_offset
) % 256);
322 for (i
= 0; i
< num
; i
++)
325 (TYPE_FIELDS (type
)[j
].loc
.bitpos
+
328 merge_classes (subclasses
[i
], classes
[i
+ pos
]);
333 case TYPE_CODE_ARRAY
:
337 num
= classify_argument (TYPE_TARGET_TYPE (type
),
338 subclasses
, bit_offset
);
342 /* The partial classes are now full classes. */
343 if (subclasses
[0] == X86_64_SSESF_CLASS
&& bytes
!= 4)
344 subclasses
[0] = X86_64_SSE_CLASS
;
345 if (subclasses
[0] == X86_64_INTEGERSI_CLASS
&& bytes
!= 4)
346 subclasses
[0] = X86_64_INTEGER_CLASS
;
348 for (i
= 0; i
< words
; i
++)
349 classes
[i
] = subclasses
[i
% num
];
352 case TYPE_CODE_UNION
:
356 for (j
= 0; j
< TYPE_NFIELDS (type
); ++j
)
359 num
= classify_argument (TYPE_FIELDS (type
)[j
].type
,
360 subclasses
, bit_offset
);
363 for (i
= 0; i
< num
; i
++)
364 classes
[i
] = merge_classes (subclasses
[i
], classes
[i
]);
372 /* Final merger cleanup. */
373 for (i
= 0; i
< words
; i
++)
375 /* If one class is MEMORY, everything should be passed in
377 if (classes
[i
] == X86_64_MEMORY_CLASS
)
380 /* The X86_64_SSEUP_CLASS should be always preceeded by
382 if (classes
[i
] == X86_64_SSEUP_CLASS
383 && (i
== 0 || classes
[i
- 1] != X86_64_SSE_CLASS
))
384 classes
[i
] = X86_64_SSE_CLASS
;
386 /* X86_64_X87UP_CLASS should be preceeded by X86_64_X87_CLASS. */
387 if (classes
[i
] == X86_64_X87UP_CLASS
388 && (i
== 0 || classes
[i
- 1] != X86_64_X87_CLASS
))
389 classes
[i
] = X86_64_SSE_CLASS
;
398 if (!(bit_offset
% 64))
399 classes
[0] = X86_64_SSESF_CLASS
;
401 classes
[0] = X86_64_SSE_CLASS
;
404 classes
[0] = X86_64_SSEDF_CLASS
;
407 classes
[0] = X86_64_X87_CLASS
;
408 classes
[1] = X86_64_X87UP_CLASS
;
422 if (bytes
* 8 + bit_offset
<= 32)
423 classes
[0] = X86_64_INTEGERSI_CLASS
;
425 classes
[0] = X86_64_INTEGER_CLASS
;
428 classes
[0] = classes
[1] = X86_64_INTEGER_CLASS
;
435 default: /* Avoid warning. */
438 internal_error (__FILE__
, __LINE__
,
439 "classify_argument: unknown argument type");
442 /* Examine the argument and set *INT_NREGS and *SSE_NREGS to the
443 number of registers required based on the information passed in
444 CLASSES. Return 0 if parameter should be passed in memory. */
447 examine_argument (enum x86_64_reg_class classes
[MAX_CLASSES
],
448 int n
, int *int_nregs
, int *sse_nregs
)
454 for (n
--; n
>= 0; n
--)
457 case X86_64_INTEGER_CLASS
:
458 case X86_64_INTEGERSI_CLASS
:
461 case X86_64_SSE_CLASS
:
462 case X86_64_SSESF_CLASS
:
463 case X86_64_SSEDF_CLASS
:
466 case X86_64_NO_CLASS
:
467 case X86_64_SSEUP_CLASS
:
468 case X86_64_X87_CLASS
:
469 case X86_64_X87UP_CLASS
:
471 case X86_64_MEMORY_CLASS
:
472 internal_error (__FILE__
, __LINE__
,
473 "examine_argument: unexpected memory class");
478 #define RET_INT_REGS 2
479 #define RET_SSE_REGS 2
481 /* Check if the structure in value_type is returned in registers or in
482 memory. If this function returns 1, GDB will call
483 STORE_STRUCT_RETURN and EXTRACT_STRUCT_VALUE_ADDRESS else
484 STORE_RETURN_VALUE and EXTRACT_RETURN_VALUE will be used. */
487 x86_64_use_struct_convention (int gcc_p
, struct type
*value_type
)
489 enum x86_64_reg_class
class[MAX_CLASSES
];
490 int n
= classify_argument (value_type
, class, 0);
495 !examine_argument (class, n
, &needed_intregs
, &needed_sseregs
) ||
496 needed_intregs
> RET_INT_REGS
|| needed_sseregs
> RET_SSE_REGS
);
499 /* Extract from an array REGBUF containing the (raw) register state, a
500 function return value of TYPE, and copy that, in virtual format,
504 x86_64_extract_return_value (struct type
*type
, struct regcache
*regcache
,
507 enum x86_64_reg_class
class[MAX_CLASSES
];
508 int n
= classify_argument (type
, class, 0);
514 int ret_int_r
[RET_INT_REGS
] = { X86_64_RAX_REGNUM
, X86_64_RDX_REGNUM
};
515 int ret_sse_r
[RET_SSE_REGS
] = { X86_64_XMM0_REGNUM
, X86_64_XMM1_REGNUM
};
518 !examine_argument (class, n
, &needed_intregs
, &needed_sseregs
) ||
519 needed_intregs
> RET_INT_REGS
|| needed_sseregs
> RET_SSE_REGS
)
522 regcache_cooked_read (regcache
, X86_64_RAX_REGNUM
, &addr
);
523 read_memory (addr
, valbuf
, TYPE_LENGTH (type
));
529 for (i
= 0; i
< n
; i
++)
533 case X86_64_NO_CLASS
:
535 case X86_64_INTEGER_CLASS
:
536 regcache_cooked_read (regcache
, ret_int_r
[(intreg
+ 1) / 2],
537 (char *) valbuf
+ offset
);
541 case X86_64_INTEGERSI_CLASS
:
542 regcache_cooked_read_part (regcache
, ret_int_r
[intreg
/ 2],
543 0, 4, (char *) valbuf
+ offset
);
547 case X86_64_SSEDF_CLASS
:
548 case X86_64_SSESF_CLASS
:
549 case X86_64_SSE_CLASS
:
550 regcache_cooked_read_part (regcache
,
551 ret_sse_r
[(ssereg
+ 1) / 2], 0, 8,
552 (char *) valbuf
+ offset
);
556 case X86_64_SSEUP_CLASS
:
557 regcache_cooked_read_part (regcache
, ret_sse_r
[ssereg
/ 2],
558 0, 8, (char *) valbuf
+ offset
);
562 case X86_64_X87_CLASS
:
563 regcache_cooked_read_part (regcache
, X86_64_ST0_REGNUM
,
564 0, 8, (char *) valbuf
+ offset
);
567 case X86_64_X87UP_CLASS
:
568 regcache_cooked_read_part (regcache
, X86_64_ST0_REGNUM
,
569 8, 2, (char *) valbuf
+ offset
);
572 case X86_64_MEMORY_CLASS
:
574 internal_error (__FILE__
, __LINE__
,
575 "Unexpected argument class");
585 x86_64_push_arguments (struct regcache
*regcache
, int nargs
,
586 struct value
**args
, CORE_ADDR sp
)
590 /* For varargs functions we have to pass the total number of SSE
591 registers used in %rax. So, let's count this number. */
592 int total_sse_args
= 0;
593 /* Once an SSE/int argument is passed on the stack, all subsequent
594 arguments are passed there. */
600 static int int_parameter_registers
[INT_REGS
] =
602 X86_64_RDI_REGNUM
, 4, /* %rdi, %rsi */
603 X86_64_RDX_REGNUM
, 2, /* %rdx, %rcx */
607 static int sse_parameter_registers
[SSE_REGS
] =
609 X86_64_XMM0_REGNUM
+ 0, X86_64_XMM1_REGNUM
,
610 X86_64_XMM0_REGNUM
+ 2, X86_64_XMM0_REGNUM
+ 3,
611 X86_64_XMM0_REGNUM
+ 4, X86_64_XMM0_REGNUM
+ 5,
612 X86_64_XMM0_REGNUM
+ 6, X86_64_XMM0_REGNUM
+ 7,
614 int stack_values_count
= 0;
616 stack_values
= alloca (nargs
* sizeof (int));
618 for (i
= 0; i
< nargs
; i
++)
620 enum x86_64_reg_class
class[MAX_CLASSES
];
621 int n
= classify_argument (args
[i
]->type
, class, 0);
626 !examine_argument (class, n
, &needed_intregs
, &needed_sseregs
))
628 stack_values
[stack_values_count
++] = i
;
635 if (intreg
/ 2 + needed_intregs
> INT_REGS
)
637 if (ssereg
/ 2 + needed_sseregs
> SSE_REGS
)
640 total_sse_args
+= needed_sseregs
;
642 for (j
= 0; j
< n
; j
++)
646 case X86_64_NO_CLASS
:
648 case X86_64_INTEGER_CLASS
:
650 stack_values
[stack_values_count
++] = i
;
653 regcache_cooked_write
654 (regcache
, int_parameter_registers
[(intreg
+ 1) / 2],
655 VALUE_CONTENTS_ALL (args
[i
]) + offset
);
660 case X86_64_INTEGERSI_CLASS
:
662 stack_values
[stack_values_count
++] = i
;
665 LONGEST val
= extract_signed_integer
666 (VALUE_CONTENTS_ALL (args
[i
]) + offset
, 4);
667 regcache_cooked_write_signed
668 (regcache
, int_parameter_registers
[intreg
/ 2], val
);
674 case X86_64_SSEDF_CLASS
:
675 case X86_64_SSESF_CLASS
:
676 case X86_64_SSE_CLASS
:
678 stack_values
[stack_values_count
++] = i
;
681 regcache_cooked_write
682 (regcache
, sse_parameter_registers
[(ssereg
+ 1) / 2],
683 VALUE_CONTENTS_ALL (args
[i
]) + offset
);
688 case X86_64_SSEUP_CLASS
:
690 stack_values
[stack_values_count
++] = i
;
693 regcache_cooked_write
694 (regcache
, sse_parameter_registers
[ssereg
/ 2],
695 VALUE_CONTENTS_ALL (args
[i
]) + offset
);
700 case X86_64_X87_CLASS
:
701 case X86_64_MEMORY_CLASS
:
702 stack_values
[stack_values_count
++] = i
;
704 case X86_64_X87UP_CLASS
:
707 internal_error (__FILE__
, __LINE__
,
708 "Unexpected argument class");
710 intreg
+= intreg
% 2;
711 ssereg
+= ssereg
% 2;
716 /* We have to make sure that the stack is 16-byte aligned after the
717 setup. Let's calculate size of arguments first, align stack and
718 then fill in the arguments. */
720 for (i
= 0; i
< stack_values_count
; i
++)
722 struct value
*arg
= args
[stack_values
[i
]];
723 int len
= TYPE_LENGTH (VALUE_ENCLOSING_TYPE (arg
));
724 total_sp
+= (len
+ 7) & ~7;
726 /* total_sp is now a multiple of 8, if it is not a multiple of 16,
727 change the stack pointer so that it will be afterwards correctly
732 /* Push any remaining arguments onto the stack. */
733 while (--stack_values_count
>= 0)
735 struct value
*arg
= args
[stack_values
[stack_values_count
]];
736 int len
= TYPE_LENGTH (VALUE_ENCLOSING_TYPE (arg
));
738 /* Make sure the stack is 8-byte-aligned. */
739 sp
-= (len
+ 7) & ~7;
740 write_memory (sp
, VALUE_CONTENTS_ALL (arg
), len
);
743 /* Write number of SSE type arguments to RAX to take care of varargs
745 store_unsigned_integer (buf
, 8, total_sse_args
);
746 regcache_cooked_write (regcache
, X86_64_RAX_REGNUM
, buf
);
751 /* Write into the appropriate registers a function return value stored
752 in VALBUF of type TYPE, given in virtual format. */
755 x86_64_store_return_value (struct type
*type
, struct regcache
*regcache
,
758 int len
= TYPE_LENGTH (type
);
760 /* First handle long doubles. */
761 if (TYPE_CODE_FLT
== TYPE_CODE (type
) && len
== 16)
764 char buf
[I386_MAX_REGISTER_SIZE
];
766 /* Returning floating-point values is a bit tricky. Apart from
767 storing the return value in %st(0), we have to simulate the
768 state of the FPU at function return point. */
770 /* Convert the value found in VALBUF to the extended
771 floating-point format used by the FPU. This is probably
772 not exactly how it would happen on the target itself, but
773 it is the best we can do. */
774 convert_typed_floating (valbuf
, type
, buf
, builtin_type_i387_ext
);
775 regcache_raw_write (regcache
, X86_64_ST0_REGNUM
, buf
);
777 /* Set the top of the floating-point register stack to 7. The
778 actual value doesn't really matter, but 7 is what a normal
779 function return would end up with if the program started out
780 with a freshly initialized FPU. */
781 regcache_raw_read_unsigned (regcache
, FSTAT_REGNUM
, &fstat
);
783 regcache_raw_write_unsigned (regcache
, FSTAT_REGNUM
, fstat
);
785 /* Mark %st(1) through %st(7) as empty. Since we set the top of
786 the floating-point register stack to 7, the appropriate value
787 for the tag word is 0x3fff. */
788 regcache_raw_write_unsigned (regcache
, FTAG_REGNUM
, 0x3fff);
790 else if (TYPE_CODE_FLT
== TYPE_CODE (type
))
792 /* Handle double and float variables. */
793 regcache_cooked_write_part (regcache
, X86_64_XMM0_REGNUM
,
796 /* XXX: What about complex floating point types? */
799 int low_size
= register_size (current_gdbarch
, X86_64_RAX_REGNUM
);
800 int high_size
= register_size (current_gdbarch
, X86_64_RDX_REGNUM
);
803 regcache_cooked_write_part (regcache
, 0, 0, len
, valbuf
);
804 else if (len
<= (low_size
+ high_size
))
806 regcache_cooked_write_part (regcache
, 0, 0, low_size
, valbuf
);
807 regcache_cooked_write_part (regcache
, 1, 0,
809 (const char *) valbuf
+ low_size
);
812 internal_error (__FILE__
, __LINE__
,
813 "Cannot store return value of %d bytes long.", len
);
819 x86_64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
820 struct regcache
*regcache
, CORE_ADDR bp_addr
,
821 int nargs
, struct value
**args
, CORE_ADDR sp
,
822 int struct_return
, CORE_ADDR struct_addr
)
826 /* Pass arguments. */
827 sp
= x86_64_push_arguments (regcache
, nargs
, args
, sp
);
829 /* Pass "hidden" argument". */
832 store_unsigned_integer (buf
, 8, struct_addr
);
833 regcache_cooked_write (regcache
, X86_64_RDI_REGNUM
, buf
);
836 /* Store return address. */
838 store_unsigned_integer (buf
, 8, bp_addr
);
839 write_memory (sp
, buf
, 8);
841 /* Finally, update the stack pointer... */
842 store_unsigned_integer (buf
, 8, sp
);
843 regcache_cooked_write (regcache
, X86_64_RSP_REGNUM
, buf
);
845 /* ...and fake a frame pointer. */
846 regcache_cooked_write (regcache
, X86_64_RBP_REGNUM
, buf
);
852 /* The maximum number of saved registers. This should include %rip. */
853 #define X86_64_NUM_SAVED_REGS X86_64_NUM_GREGS
855 struct x86_64_frame_cache
862 /* Saved registers. */
863 CORE_ADDR saved_regs
[X86_64_NUM_SAVED_REGS
];
866 /* Do we have a frame? */
870 /* Allocate and initialize a frame cache. */
872 static struct x86_64_frame_cache
*
873 x86_64_alloc_frame_cache (void)
875 struct x86_64_frame_cache
*cache
;
878 cache
= FRAME_OBSTACK_ZALLOC (struct x86_64_frame_cache
);
882 cache
->sp_offset
= -8;
885 /* Saved registers. We initialize these to -1 since zero is a valid
886 offset (that's where %rbp is supposed to be stored). */
887 for (i
= 0; i
< X86_64_NUM_SAVED_REGS
; i
++)
888 cache
->saved_regs
[i
] = -1;
891 /* Frameless until proven otherwise. */
892 cache
->frameless_p
= 1;
897 /* Do a limited analysis of the prologue at PC and update CACHE
898 accordingly. Bail out early if CURRENT_PC is reached. Return the
899 address where the analysis stopped.
901 We will handle only functions beginning with:
904 movq %rsp, %rbp 0x48 0x89 0xe5
906 Any function that doesn't start with this sequence will be assumed
907 to have no prologue and thus no valid frame pointer in %rbp. */
910 x86_64_analyze_prologue (CORE_ADDR pc
, CORE_ADDR current_pc
,
911 struct x86_64_frame_cache
*cache
)
913 static unsigned char proto
[3] = { 0x48, 0x89, 0xe5 };
914 unsigned char buf
[3];
917 if (current_pc
<= pc
)
920 op
= read_memory_unsigned_integer (pc
, 1);
922 if (op
== 0x55) /* pushq %rbp */
924 /* Take into account that we've executed the `pushq %rbp' that
925 starts this instruction sequence. */
926 cache
->saved_regs
[X86_64_RBP_REGNUM
] = 0;
927 cache
->sp_offset
+= 8;
929 /* If that's all, return now. */
930 if (current_pc
<= pc
+ 1)
933 /* Check for `movq %rsp, %rbp'. */
934 read_memory (pc
+ 1, buf
, 3);
935 if (memcmp (buf
, proto
, 3) != 0)
938 /* OK, we actually have a frame. */
939 cache
->frameless_p
= 0;
946 /* Return PC of first real instruction. */
949 x86_64_skip_prologue (CORE_ADDR start_pc
)
951 struct x86_64_frame_cache cache
;
954 pc
= x86_64_analyze_prologue (start_pc
, 0xffffffffffffffff, &cache
);
955 if (cache
.frameless_p
)
964 static struct x86_64_frame_cache
*
965 x86_64_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
967 struct x86_64_frame_cache
*cache
;
974 cache
= x86_64_alloc_frame_cache ();
977 frame_unwind_register (next_frame
, X86_64_RBP_REGNUM
, buf
);
978 cache
->base
= extract_unsigned_integer (buf
, 8);
979 if (cache
->base
== 0)
982 /* For normal frames, %rip is stored at 8(%rbp). */
983 cache
->saved_regs
[X86_64_RIP_REGNUM
] = 8;
985 cache
->pc
= frame_func_unwind (next_frame
);
987 x86_64_analyze_prologue (cache
->pc
, frame_pc_unwind (next_frame
), cache
);
989 if (cache
->frameless_p
)
991 /* We didn't find a valid frame, which means that CACHE->base
992 currently holds the frame pointer for our calling frame. If
993 we're at the start of a function, or somewhere half-way its
994 prologue, the function's frame probably hasn't been fully
995 setup yet. Try to reconstruct the base address for the stack
996 frame by looking at the stack pointer. For truly "frameless"
997 functions this might work too. */
999 frame_unwind_register (next_frame
, X86_64_RSP_REGNUM
, buf
);
1000 cache
->base
= extract_unsigned_integer (buf
, 8) + cache
->sp_offset
;
1003 /* Now that we have the base address for the stack frame we can
1004 calculate the value of %rsp in the calling frame. */
1005 cache
->saved_sp
= cache
->base
+ 16;
1007 /* Adjust all the saved registers such that they contain addresses
1008 instead of offsets. */
1009 for (i
= 0; i
< X86_64_NUM_SAVED_REGS
; i
++)
1010 if (cache
->saved_regs
[i
] != -1)
1011 cache
->saved_regs
[i
] += cache
->base
;
1017 x86_64_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1018 struct frame_id
*this_id
)
1020 struct x86_64_frame_cache
*cache
=
1021 x86_64_frame_cache (next_frame
, this_cache
);
1023 /* This marks the outermost frame. */
1024 if (cache
->base
== 0)
1027 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
1031 x86_64_frame_prev_register (struct frame_info
*next_frame
, void **this_cache
,
1032 int regnum
, int *optimizedp
,
1033 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1034 int *realnump
, void *valuep
)
1036 struct x86_64_frame_cache
*cache
=
1037 x86_64_frame_cache (next_frame
, this_cache
);
1039 gdb_assert (regnum
>= 0);
1041 if (regnum
== SP_REGNUM
&& cache
->saved_sp
)
1049 /* Store the value. */
1050 store_unsigned_integer (valuep
, 8, cache
->saved_sp
);
1055 if (regnum
< X86_64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1058 *lvalp
= lval_memory
;
1059 *addrp
= cache
->saved_regs
[regnum
];
1063 /* Read the value in from memory. */
1064 read_memory (*addrp
, valuep
,
1065 register_size (current_gdbarch
, regnum
));
1070 frame_register_unwind (next_frame
, regnum
,
1071 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1074 static const struct frame_unwind x86_64_frame_unwind
=
1077 x86_64_frame_this_id
,
1078 x86_64_frame_prev_register
1081 static const struct frame_unwind
*
1082 x86_64_frame_sniffer (struct frame_info
*next_frame
)
1084 return &x86_64_frame_unwind
;
1088 /* Signal trampolines. */
1090 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
1091 64-bit variants. This would require using identical frame caches
1092 on both platforms. */
1094 static struct x86_64_frame_cache
*
1095 x86_64_sigtramp_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1097 struct x86_64_frame_cache
*cache
;
1098 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1106 cache
= x86_64_alloc_frame_cache ();
1108 frame_unwind_register (next_frame
, X86_64_RSP_REGNUM
, buf
);
1109 cache
->base
= extract_unsigned_integer (buf
, 8) - 8;
1111 addr
= tdep
->sigcontext_addr (next_frame
);
1112 gdb_assert (tdep
->sc_reg_offset
);
1113 gdb_assert (tdep
->sc_num_regs
<= X86_64_NUM_SAVED_REGS
);
1114 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
1115 if (tdep
->sc_reg_offset
[i
] != -1)
1116 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
1118 *this_cache
= cache
;
1123 x86_64_sigtramp_frame_this_id (struct frame_info
*next_frame
,
1124 void **this_cache
, struct frame_id
*this_id
)
1126 struct x86_64_frame_cache
*cache
=
1127 x86_64_sigtramp_frame_cache (next_frame
, this_cache
);
1129 (*this_id
) = frame_id_build (cache
->base
+ 16, frame_pc_unwind (next_frame
));
1133 x86_64_sigtramp_frame_prev_register (struct frame_info
*next_frame
,
1135 int regnum
, int *optimizedp
,
1136 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1137 int *realnump
, void *valuep
)
1139 /* Make sure we've initialized the cache. */
1140 x86_64_sigtramp_frame_cache (next_frame
, this_cache
);
1142 x86_64_frame_prev_register (next_frame
, this_cache
, regnum
,
1143 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1146 static const struct frame_unwind x86_64_sigtramp_frame_unwind
=
1149 x86_64_sigtramp_frame_this_id
,
1150 x86_64_sigtramp_frame_prev_register
1153 static const struct frame_unwind
*
1154 x86_64_sigtramp_frame_sniffer (struct frame_info
*next_frame
)
1156 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1159 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
1160 if (PC_IN_SIGTRAMP (pc
, name
))
1162 gdb_assert (gdbarch_tdep (current_gdbarch
)->sigcontext_addr
);
1164 return &x86_64_sigtramp_frame_unwind
;
1172 x86_64_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1174 struct x86_64_frame_cache
*cache
=
1175 x86_64_frame_cache (next_frame
, this_cache
);
1180 static const struct frame_base x86_64_frame_base
=
1182 &x86_64_frame_unwind
,
1183 x86_64_frame_base_address
,
1184 x86_64_frame_base_address
,
1185 x86_64_frame_base_address
1188 static struct frame_id
1189 x86_64_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1194 frame_unwind_register (next_frame
, X86_64_RBP_REGNUM
, buf
);
1195 fp
= extract_unsigned_integer (buf
, 8);
1197 return frame_id_build (fp
+ 16, frame_pc_unwind (next_frame
));
1200 /* 16 byte align the SP per frame requirements. */
1203 x86_64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1205 return sp
& -(CORE_ADDR
)16;
1209 /* Supply register REGNUM from the floating-point register set REGSET
1210 to register cache REGCACHE. If REGNUM is -1, do this for all
1211 registers in REGSET. */
1214 x86_64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
1215 int regnum
, const void *fpregs
, size_t len
)
1217 const struct gdbarch_tdep
*tdep
= regset
->descr
;
1219 gdb_assert (len
== tdep
->sizeof_fpregset
);
1220 x86_64_supply_fxsave (regcache
, regnum
, fpregs
);
1223 /* Return the appropriate register set for the core section identified
1224 by SECT_NAME and SECT_SIZE. */
1226 static const struct regset
*
1227 x86_64_regset_from_core_section (struct gdbarch
*gdbarch
,
1228 const char *sect_name
, size_t sect_size
)
1230 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1232 if (strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
1234 if (tdep
->fpregset
== NULL
)
1236 tdep
->fpregset
= XMALLOC (struct regset
);
1237 tdep
->fpregset
->descr
= tdep
;
1238 tdep
->fpregset
->supply_regset
= x86_64_supply_fpregset
;
1241 return tdep
->fpregset
;
1244 return i386_regset_from_core_section (gdbarch
, sect_name
, sect_size
);
1249 x86_64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
1251 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1253 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
1254 floating-point registers. */
1255 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
1257 /* AMD64 has an FPU and 16 SSE registers. */
1258 tdep
->st0_regnum
= X86_64_ST0_REGNUM
;
1259 tdep
->num_xmm_regs
= 16;
1261 /* This is what all the fuss is about. */
1262 set_gdbarch_long_bit (gdbarch
, 64);
1263 set_gdbarch_long_long_bit (gdbarch
, 64);
1264 set_gdbarch_ptr_bit (gdbarch
, 64);
1266 /* In contrast to the i386, on the x86-64 a `long double' actually
1267 takes up 128 bits, even though it's still based on the i387
1268 extended floating-point format which has only 80 significant bits. */
1269 set_gdbarch_long_double_bit (gdbarch
, 128);
1271 set_gdbarch_num_regs (gdbarch
, X86_64_NUM_REGS
);
1272 set_gdbarch_register_name (gdbarch
, x86_64_register_name
);
1273 set_gdbarch_register_type (gdbarch
, x86_64_register_type
);
1275 /* Register numbers of various important registers. */
1276 set_gdbarch_sp_regnum (gdbarch
, X86_64_RSP_REGNUM
); /* %rsp */
1277 set_gdbarch_pc_regnum (gdbarch
, X86_64_RIP_REGNUM
); /* %rip */
1278 set_gdbarch_ps_regnum (gdbarch
, X86_64_EFLAGS_REGNUM
); /* %eflags */
1279 set_gdbarch_fp0_regnum (gdbarch
, X86_64_ST0_REGNUM
); /* %st(0) */
1281 /* The "default" register numbering scheme for the x86-64 is
1282 referred to as the "DWARF Register Number Mapping" in the System
1283 V psABI. The preferred debugging format for all known x86-64
1284 targets is actually DWARF2, and GCC doesn't seem to support DWARF
1285 (that is DWARF-1), but we provide the same mapping just in case.
1286 This mapping is also used for stabs, which GCC does support. */
1287 set_gdbarch_stab_reg_to_regnum (gdbarch
, x86_64_dwarf_reg_to_regnum
);
1288 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, x86_64_dwarf_reg_to_regnum
);
1289 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, x86_64_dwarf_reg_to_regnum
);
1291 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
1292 be in use on any of the supported x86-64 targets. */
1294 /* Call dummy code. */
1295 set_gdbarch_push_dummy_call (gdbarch
, x86_64_push_dummy_call
);
1296 set_gdbarch_frame_align (gdbarch
, x86_64_frame_align
);
1297 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
1299 set_gdbarch_convert_register_p (gdbarch
, x86_64_convert_register_p
);
1300 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
1301 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
1303 set_gdbarch_extract_return_value (gdbarch
, x86_64_extract_return_value
);
1304 set_gdbarch_store_return_value (gdbarch
, x86_64_store_return_value
);
1305 /* Override, since this is handled by x86_64_extract_return_value. */
1306 set_gdbarch_extract_struct_value_address (gdbarch
, NULL
);
1307 set_gdbarch_use_struct_convention (gdbarch
, x86_64_use_struct_convention
);
1309 set_gdbarch_skip_prologue (gdbarch
, x86_64_skip_prologue
);
1311 /* Avoid wiring in the MMX registers for now. */
1312 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
1313 tdep
->mm0_regnum
= -1;
1315 set_gdbarch_unwind_dummy_id (gdbarch
, x86_64_unwind_dummy_id
);
1317 /* FIXME: kettenis/20021026: This is ELF-specific. Fine for now,
1318 since all supported x86-64 targets are ELF, but that might change
1320 set_gdbarch_in_solib_call_trampoline (gdbarch
, in_plt_section
);
1322 frame_unwind_append_sniffer (gdbarch
, x86_64_sigtramp_frame_sniffer
);
1323 frame_unwind_append_sniffer (gdbarch
, x86_64_frame_sniffer
);
1324 frame_base_set_default (gdbarch
, &x86_64_frame_base
);
1326 /* If we have a register mapping, enable the generic core file support. */
1327 if (tdep
->gregset_reg_offset
)
1328 set_gdbarch_regset_from_core_section (gdbarch
,
1329 x86_64_regset_from_core_section
);
1333 #define I387_ST0_REGNUM X86_64_ST0_REGNUM
1335 /* The 64-bit FXSAVE format differs from the 32-bit format in the
1336 sense that the instruction pointer and data pointer are simply
1337 64-bit offsets into the code segment and the data segment instead
1338 of a selector offset pair. The functions below store the upper 32
1339 bits of these pointers (instead of just the 16-bits of the segment
1342 /* Fill register REGNUM in REGCACHE with the appropriate
1343 floating-point or SSE register value from *FXSAVE. If REGNUM is
1344 -1, do this for all registers. This function masks off any of the
1345 reserved bits in *FXSAVE. */
1348 x86_64_supply_fxsave (struct regcache
*regcache
, int regnum
,
1351 i387_supply_fxsave (regcache
, regnum
, fxsave
);
1355 const char *regs
= fxsave
;
1357 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM
)
1358 regcache_raw_supply (regcache
, I387_FISEG_REGNUM
, regs
+ 12);
1359 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM
)
1360 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM
, regs
+ 20);
1364 /* Fill register REGNUM (if it is a floating-point or SSE register) in
1365 *FXSAVE with the value in GDB's register cache. If REGNUM is -1, do
1366 this for all registers. This function doesn't touch any of the
1367 reserved bits in *FXSAVE. */
1370 x86_64_fill_fxsave (char *fxsave
, int regnum
)
1372 i387_fill_fxsave (fxsave
, regnum
);
1374 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM
)
1375 regcache_collect (I387_FISEG_REGNUM
, fxsave
+ 12);
1376 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM
)
1377 regcache_collect (I387_FOSEG_REGNUM
, fxsave
+ 20);