1 /* Target-dependent code for AMD64.
3 Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Jiri Smid, SuSE Labs.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "gdb_assert.h"
40 #include "x86-64-tdep.h"
41 #include "i387-tdep.h"
43 /* Note that the AMD64 architecture was previously known as x86-64.
44 The latter is (forever) engraved into the canonical system name as
45 returned bu config.guess, and used as the name for the AMD64 port
46 of GNU/Linux. The BSD's have renamed their ports to amd64; they
47 don't like to shout. For GDB we prefer the amd64_-prefix over the
48 x86_64_-prefix since it's so much easier to type. */
50 /* Register information. */
52 struct amd64_register_info
58 static struct amd64_register_info amd64_register_info
[] =
60 { "rax", &builtin_type_int64
},
61 { "rbx", &builtin_type_int64
},
62 { "rcx", &builtin_type_int64
},
63 { "rdx", &builtin_type_int64
},
64 { "rsi", &builtin_type_int64
},
65 { "rdi", &builtin_type_int64
},
66 { "rbp", &builtin_type_void_data_ptr
},
67 { "rsp", &builtin_type_void_data_ptr
},
69 /* %r8 is indeed register number 8. */
70 { "r8", &builtin_type_int64
},
71 { "r9", &builtin_type_int64
},
72 { "r10", &builtin_type_int64
},
73 { "r11", &builtin_type_int64
},
74 { "r12", &builtin_type_int64
},
75 { "r13", &builtin_type_int64
},
76 { "r14", &builtin_type_int64
},
77 { "r15", &builtin_type_int64
},
78 { "rip", &builtin_type_void_func_ptr
},
79 { "eflags", &builtin_type_int32
},
80 { "ds", &builtin_type_int32
},
81 { "es", &builtin_type_int32
},
82 { "fs", &builtin_type_int32
},
83 { "gs", &builtin_type_int32
},
85 /* %st0 is register number 22. */
86 { "st0", &builtin_type_i387_ext
},
87 { "st1", &builtin_type_i387_ext
},
88 { "st2", &builtin_type_i387_ext
},
89 { "st3", &builtin_type_i387_ext
},
90 { "st4", &builtin_type_i387_ext
},
91 { "st5", &builtin_type_i387_ext
},
92 { "st6", &builtin_type_i387_ext
},
93 { "st7", &builtin_type_i387_ext
},
94 { "fctrl", &builtin_type_int32
},
95 { "fstat", &builtin_type_int32
},
96 { "ftag", &builtin_type_int32
},
97 { "fiseg", &builtin_type_int32
},
98 { "fioff", &builtin_type_int32
},
99 { "foseg", &builtin_type_int32
},
100 { "fooff", &builtin_type_int32
},
101 { "fop", &builtin_type_int32
},
103 /* %xmm0 is register number 38. */
104 { "xmm0", &builtin_type_v4sf
},
105 { "xmm1", &builtin_type_v4sf
},
106 { "xmm2", &builtin_type_v4sf
},
107 { "xmm3", &builtin_type_v4sf
},
108 { "xmm4", &builtin_type_v4sf
},
109 { "xmm5", &builtin_type_v4sf
},
110 { "xmm6", &builtin_type_v4sf
},
111 { "xmm7", &builtin_type_v4sf
},
112 { "xmm8", &builtin_type_v4sf
},
113 { "xmm9", &builtin_type_v4sf
},
114 { "xmm10", &builtin_type_v4sf
},
115 { "xmm11", &builtin_type_v4sf
},
116 { "xmm12", &builtin_type_v4sf
},
117 { "xmm13", &builtin_type_v4sf
},
118 { "xmm14", &builtin_type_v4sf
},
119 { "xmm15", &builtin_type_v4sf
},
120 { "mxcsr", &builtin_type_int32
}
123 /* Total number of registers. */
124 #define AMD64_NUM_REGS \
125 (sizeof (amd64_register_info) / sizeof (amd64_register_info[0]))
127 /* Return the name of register REGNUM. */
130 amd64_register_name (int regnum
)
132 if (regnum
>= 0 && regnum
< AMD64_NUM_REGS
)
133 return amd64_register_info
[regnum
].name
;
138 /* Return the GDB type object for the "standard" data type of data in
142 amd64_register_type (struct gdbarch
*gdbarch
, int regnum
)
144 gdb_assert (regnum
>= 0 && regnum
< AMD64_NUM_REGS
);
146 return *amd64_register_info
[regnum
].type
;
149 /* DWARF Register Number Mapping as defined in the System V psABI,
152 static int amd64_dwarf_regmap
[] =
154 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
155 X86_64_RAX_REGNUM
, X86_64_RDX_REGNUM
, 2, 1,
156 4, X86_64_RDI_REGNUM
,
158 /* Frame Pointer Register RBP. */
161 /* Stack Pointer Register RSP. */
164 /* Extended Integer Registers 8 - 15. */
165 8, 9, 10, 11, 12, 13, 14, 15,
167 /* Return Address RA. Mapped to RIP. */
170 /* SSE Registers 0 - 7. */
171 X86_64_XMM0_REGNUM
+ 0, X86_64_XMM1_REGNUM
,
172 X86_64_XMM0_REGNUM
+ 2, X86_64_XMM0_REGNUM
+ 3,
173 X86_64_XMM0_REGNUM
+ 4, X86_64_XMM0_REGNUM
+ 5,
174 X86_64_XMM0_REGNUM
+ 6, X86_64_XMM0_REGNUM
+ 7,
176 /* Extended SSE Registers 8 - 15. */
177 X86_64_XMM0_REGNUM
+ 8, X86_64_XMM0_REGNUM
+ 9,
178 X86_64_XMM0_REGNUM
+ 10, X86_64_XMM0_REGNUM
+ 11,
179 X86_64_XMM0_REGNUM
+ 12, X86_64_XMM0_REGNUM
+ 13,
180 X86_64_XMM0_REGNUM
+ 14, X86_64_XMM0_REGNUM
+ 15,
182 /* Floating Point Registers 0-7. */
183 X86_64_ST0_REGNUM
+ 0, X86_64_ST0_REGNUM
+ 1,
184 X86_64_ST0_REGNUM
+ 2, X86_64_ST0_REGNUM
+ 3,
185 X86_64_ST0_REGNUM
+ 4, X86_64_ST0_REGNUM
+ 5,
186 X86_64_ST0_REGNUM
+ 6, X86_64_ST0_REGNUM
+ 7
189 static const int amd64_dwarf_regmap_len
=
190 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
192 /* Convert DWARF register number REG to the appropriate register
193 number used by GDB. */
196 amd64_dwarf_reg_to_regnum (int reg
)
200 if (reg
>= 0 || reg
< amd64_dwarf_regmap_len
)
201 regnum
= amd64_dwarf_regmap
[reg
];
204 warning ("Unmapped DWARF Register #%d encountered\n", reg
);
209 /* Return nonzero if a value of type TYPE stored in register REGNUM
210 needs any special handling. */
213 amd64_convert_register_p (int regnum
, struct type
*type
)
215 return i386_fp_regnum_p (regnum
);
219 /* Register classes as defined in the psABI. */
233 /* Return the union class of CLASS1 and CLASS2. See the psABI for
236 static enum amd64_reg_class
237 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
239 /* Rule (a): If both classes are equal, this is the resulting class. */
240 if (class1
== class2
)
243 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
244 is the other class. */
245 if (class1
== AMD64_NO_CLASS
)
247 if (class2
== AMD64_NO_CLASS
)
250 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
251 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
254 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
255 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
256 return AMD64_INTEGER
;
258 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
259 MEMORY is used as class. */
260 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
261 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
262 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
265 /* Rule (f): Otherwise class SSE is used. */
269 static void amd64_classify (struct type
*type
, enum amd64_reg_class
class[2]);
271 /* Classify TYPE according to the rules for aggregate (structures and
272 arrays) and union types, and store the result in CLASS. */
275 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class
class[2])
277 int len
= TYPE_LENGTH (type
);
279 /* 1. If the size of an object is larger than two eightbytes, or in
280 C++, is a non-POD structure or union type, or contains
281 unaligned fields, it has class memory. */
284 class[0] = class[1] = AMD64_MEMORY
;
288 /* 2. Both eightbytes get initialized to class NO_CLASS. */
289 class[0] = class[1] = AMD64_NO_CLASS
;
291 /* 3. Each field of an object is classified recursively so that
292 always two fields are considered. The resulting class is
293 calculated according to the classes of the fields in the
296 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
298 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
300 /* All fields in an array have the same type. */
301 amd64_classify (subtype
, class);
302 if (len
> 8 && class[1] == AMD64_NO_CLASS
)
309 /* Structure or union. */
310 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_STRUCT
311 || TYPE_CODE (type
) == TYPE_CODE_UNION
);
313 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
315 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
316 int pos
= TYPE_FIELD_BITPOS (type
, i
) / 64;
317 enum amd64_reg_class subclass
[2];
319 gdb_assert (pos
== 0 || pos
== 1);
321 amd64_classify (subtype
, subclass
);
322 class[pos
] = amd64_merge_classes (class[pos
], subclass
[0]);
324 class[1] = amd64_merge_classes (class[1], subclass
[1]);
328 /* 4. Then a post merger cleanup is done: */
330 /* Rule (a): If one of the classes is MEMORY, the whole argument is
332 if (class[0] == AMD64_MEMORY
|| class[1] == AMD64_MEMORY
)
333 class[0] = class[1] = AMD64_MEMORY
;
335 /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to
337 if (class[0] == AMD64_SSEUP
)
338 class[0] = AMD64_SSE
;
339 if (class[1] == AMD64_SSEUP
&& class[0] != AMD64_SSE
)
340 class[1] = AMD64_SSE
;
343 /* Classify TYPE, and store the result in CLASS. */
346 amd64_classify (struct type
*type
, enum amd64_reg_class
class[2])
348 enum type_code code
= TYPE_CODE (type
);
349 int len
= TYPE_LENGTH (type
);
351 class[0] = class[1] = AMD64_NO_CLASS
;
353 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
354 long, long long, and pointers are in the INTEGER class. */
355 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
356 || code
== TYPE_CODE_PTR
|| code
== TYPE_CODE_REF
)
357 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
358 class[0] = AMD64_INTEGER
;
360 /* Arguments of types float, double and __m64 are in class SSE. */
361 else if (code
== TYPE_CODE_FLT
&& (len
== 4 || len
== 8))
363 class[0] = AMD64_SSE
;
365 /* Arguments of types __float128 and __m128 are split into two
366 halves. The least significant ones belong to class SSE, the most
367 significant one to class SSEUP. */
368 /* FIXME: __float128, __m128. */
370 /* The 64-bit mantissa of arguments of type long double belongs to
371 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
373 else if (code
== TYPE_CODE_FLT
&& len
== 16)
374 /* Class X87 and X87UP. */
375 class[0] = AMD64_X87
, class[1] = AMD64_X87UP
;
378 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
379 || code
== TYPE_CODE_UNION
)
380 amd64_classify_aggregate (type
, class);
383 static enum return_value_convention
384 amd64_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
385 struct regcache
*regcache
,
386 void *readbuf
, const void *writebuf
)
388 enum amd64_reg_class
class[2];
389 int len
= TYPE_LENGTH (type
);
390 static int integer_regnum
[] = { X86_64_RAX_REGNUM
, X86_64_RDX_REGNUM
};
391 static int sse_regnum
[] = { X86_64_XMM0_REGNUM
, X86_64_XMM1_REGNUM
};
396 gdb_assert (!(readbuf
&& writebuf
));
398 /* 1. Classify the return type with the classification algorithm. */
399 amd64_classify (type
, class);
401 /* 2. If the type has class MEMORY, then the caller provides space
402 for the return value and passes the address of this storage in
403 %rdi as if it were the first argument to the function. In
404 effect, this address becomes a hidden first argument. */
405 if (class[0] == AMD64_MEMORY
)
406 return RETURN_VALUE_STRUCT_CONVENTION
;
408 gdb_assert (class[1] != AMD64_MEMORY
);
409 gdb_assert (len
<= 16);
411 for (i
= 0; len
> 0; i
++, len
-= 8)
419 /* 3. If the class is INTEGER, the next available register
420 of the sequence %rax, %rdx is used. */
421 regnum
= integer_regnum
[integer_reg
++];
425 /* 4. If the class is SSE, the next available SSE register
426 of the sequence %xmm0, %xmm1 is used. */
427 regnum
= sse_regnum
[sse_reg
++];
431 /* 5. If the class is SSEUP, the eightbyte is passed in the
432 upper half of the last used SSE register. */
433 gdb_assert (sse_reg
> 0);
434 regnum
= sse_regnum
[sse_reg
- 1];
439 /* 6. If the class is X87, the value is returned on the X87
440 stack in %st0 as 80-bit x87 number. */
441 regnum
= X86_64_ST0_REGNUM
;
443 i387_return_value (gdbarch
, regcache
);
447 /* 7. If the class is X87UP, the value is returned together
448 with the previous X87 value in %st0. */
449 gdb_assert (i
> 0 && class[0] == AMD64_X87
);
450 regnum
= X86_64_ST0_REGNUM
;
459 gdb_assert (!"Unexpected register class.");
462 gdb_assert (regnum
!= -1);
465 regcache_raw_read_part (regcache
, regnum
, offset
, min (len
, 8),
466 (char *) readbuf
+ i
* 8);
468 regcache_raw_write_part (regcache
, regnum
, offset
, min (len
, 8),
469 (const char *) writebuf
+ i
* 8);
472 return RETURN_VALUE_REGISTER_CONVENTION
;
477 amd64_push_arguments (struct regcache
*regcache
, int nargs
,
478 struct value
**args
, CORE_ADDR sp
)
480 static int integer_regnum
[] =
482 X86_64_RDI_REGNUM
, 4, /* %rdi, %rsi */
483 X86_64_RDX_REGNUM
, 2, /* %rdx, %rcx */
486 static int sse_regnum
[] =
488 /* %xmm0 ... %xmm7 */
489 X86_64_XMM0_REGNUM
+ 0, X86_64_XMM1_REGNUM
,
490 X86_64_XMM0_REGNUM
+ 2, X86_64_XMM0_REGNUM
+ 3,
491 X86_64_XMM0_REGNUM
+ 4, X86_64_XMM0_REGNUM
+ 5,
492 X86_64_XMM0_REGNUM
+ 6, X86_64_XMM0_REGNUM
+ 7,
494 struct value
**stack_args
= alloca (nargs
* sizeof (struct value
*));
495 int num_stack_args
= 0;
496 int num_elements
= 0;
502 for (i
= 0; i
< nargs
; i
++)
504 struct type
*type
= VALUE_TYPE (args
[i
]);
505 int len
= TYPE_LENGTH (type
);
506 enum amd64_reg_class
class[2];
507 int needed_integer_regs
= 0;
508 int needed_sse_regs
= 0;
511 /* Classify argument. */
512 amd64_classify (type
, class);
514 /* Calculate the number of integer and SSE registers needed for
516 for (j
= 0; j
< 2; j
++)
518 if (class[j
] == AMD64_INTEGER
)
519 needed_integer_regs
++;
520 else if (class[j
] == AMD64_SSE
)
524 /* Check whether enough registers are available, and if the
525 argument should be passed in registers at all. */
526 if (integer_reg
+ needed_integer_regs
> ARRAY_SIZE (integer_regnum
)
527 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
528 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
530 /* The argument will be passed on the stack. */
531 num_elements
+= ((len
+ 7) / 8);
532 stack_args
[num_stack_args
++] = args
[i
];
536 /* The argument will be passed in registers. */
537 char *valbuf
= VALUE_CONTENTS (args
[i
]);
540 gdb_assert (len
<= 16);
542 for (j
= 0; len
> 0; j
++, len
-= 8)
550 regnum
= integer_regnum
[integer_reg
++];
554 regnum
= sse_regnum
[sse_reg
++];
558 gdb_assert (sse_reg
> 0);
559 regnum
= sse_regnum
[sse_reg
- 1];
564 gdb_assert (!"Unexpected register class.");
567 gdb_assert (regnum
!= -1);
568 memset (buf
, 0, sizeof buf
);
569 memcpy (buf
, valbuf
+ j
* 8, min (len
, 8));
570 regcache_raw_write_part (regcache
, regnum
, offset
, 8, buf
);
575 /* Allocate space for the arguments on the stack. */
576 sp
-= num_elements
* 8;
578 /* The psABI says that "The end of the input argument area shall be
579 aligned on a 16 byte boundary." */
582 /* Write out the arguments to the stack. */
583 for (i
= 0; i
< num_stack_args
; i
++)
585 struct type
*type
= VALUE_TYPE (stack_args
[i
]);
586 char *valbuf
= VALUE_CONTENTS (stack_args
[i
]);
587 int len
= TYPE_LENGTH (type
);
589 write_memory (sp
+ element
* 8, valbuf
, len
);
590 element
+= ((len
+ 7) / 8);
593 /* The psABI says that "For calls that may call functions that use
594 varargs or stdargs (prototype-less calls or calls to functions
595 containing ellipsis (...) in the declaration) %al is used as
596 hidden argument to specify the number of SSE registers used. */
597 regcache_raw_write_unsigned (regcache
, X86_64_RAX_REGNUM
, sse_reg
);
602 amd64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
603 struct regcache
*regcache
, CORE_ADDR bp_addr
,
604 int nargs
, struct value
**args
, CORE_ADDR sp
,
605 int struct_return
, CORE_ADDR struct_addr
)
609 /* Pass arguments. */
610 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
);
612 /* Pass "hidden" argument". */
615 store_unsigned_integer (buf
, 8, struct_addr
);
616 regcache_cooked_write (regcache
, X86_64_RDI_REGNUM
, buf
);
619 /* Store return address. */
621 store_unsigned_integer (buf
, 8, bp_addr
);
622 write_memory (sp
, buf
, 8);
624 /* Finally, update the stack pointer... */
625 store_unsigned_integer (buf
, 8, sp
);
626 regcache_cooked_write (regcache
, X86_64_RSP_REGNUM
, buf
);
628 /* ...and fake a frame pointer. */
629 regcache_cooked_write (regcache
, X86_64_RBP_REGNUM
, buf
);
635 /* The maximum number of saved registers. This should include %rip. */
636 #define AMD64_NUM_SAVED_REGS X86_64_NUM_GREGS
638 struct amd64_frame_cache
645 /* Saved registers. */
646 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
649 /* Do we have a frame? */
653 /* Allocate and initialize a frame cache. */
655 static struct amd64_frame_cache
*
656 amd64_alloc_frame_cache (void)
658 struct amd64_frame_cache
*cache
;
661 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
665 cache
->sp_offset
= -8;
668 /* Saved registers. We initialize these to -1 since zero is a valid
669 offset (that's where %rbp is supposed to be stored). */
670 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
671 cache
->saved_regs
[i
] = -1;
674 /* Frameless until proven otherwise. */
675 cache
->frameless_p
= 1;
680 /* Do a limited analysis of the prologue at PC and update CACHE
681 accordingly. Bail out early if CURRENT_PC is reached. Return the
682 address where the analysis stopped.
684 We will handle only functions beginning with:
687 movq %rsp, %rbp 0x48 0x89 0xe5
689 Any function that doesn't start with this sequence will be assumed
690 to have no prologue and thus no valid frame pointer in %rbp. */
693 amd64_analyze_prologue (CORE_ADDR pc
, CORE_ADDR current_pc
,
694 struct amd64_frame_cache
*cache
)
696 static unsigned char proto
[3] = { 0x48, 0x89, 0xe5 };
697 unsigned char buf
[3];
700 if (current_pc
<= pc
)
703 op
= read_memory_unsigned_integer (pc
, 1);
705 if (op
== 0x55) /* pushq %rbp */
707 /* Take into account that we've executed the `pushq %rbp' that
708 starts this instruction sequence. */
709 cache
->saved_regs
[X86_64_RBP_REGNUM
] = 0;
710 cache
->sp_offset
+= 8;
712 /* If that's all, return now. */
713 if (current_pc
<= pc
+ 1)
716 /* Check for `movq %rsp, %rbp'. */
717 read_memory (pc
+ 1, buf
, 3);
718 if (memcmp (buf
, proto
, 3) != 0)
721 /* OK, we actually have a frame. */
722 cache
->frameless_p
= 0;
729 /* Return PC of first real instruction. */
732 amd64_skip_prologue (CORE_ADDR start_pc
)
734 struct amd64_frame_cache cache
;
737 pc
= amd64_analyze_prologue (start_pc
, 0xffffffffffffffff, &cache
);
738 if (cache
.frameless_p
)
747 static struct amd64_frame_cache
*
748 amd64_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
750 struct amd64_frame_cache
*cache
;
757 cache
= amd64_alloc_frame_cache ();
760 cache
->pc
= frame_func_unwind (next_frame
);
762 amd64_analyze_prologue (cache
->pc
, frame_pc_unwind (next_frame
), cache
);
764 if (cache
->frameless_p
)
766 /* We didn't find a valid frame, which means that CACHE->base
767 currently holds the frame pointer for our calling frame. If
768 we're at the start of a function, or somewhere half-way its
769 prologue, the function's frame probably hasn't been fully
770 setup yet. Try to reconstruct the base address for the stack
771 frame by looking at the stack pointer. For truly "frameless"
772 functions this might work too. */
774 frame_unwind_register (next_frame
, X86_64_RSP_REGNUM
, buf
);
775 cache
->base
= extract_unsigned_integer (buf
, 8) + cache
->sp_offset
;
779 frame_unwind_register (next_frame
, X86_64_RBP_REGNUM
, buf
);
780 cache
->base
= extract_unsigned_integer (buf
, 8);
783 /* Now that we have the base address for the stack frame we can
784 calculate the value of %rsp in the calling frame. */
785 cache
->saved_sp
= cache
->base
+ 16;
787 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
788 frame we find it at the same offset from the reconstructed base
790 cache
->saved_regs
[X86_64_RIP_REGNUM
] = 8;
792 /* Adjust all the saved registers such that they contain addresses
793 instead of offsets. */
794 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
795 if (cache
->saved_regs
[i
] != -1)
796 cache
->saved_regs
[i
] += cache
->base
;
802 amd64_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
803 struct frame_id
*this_id
)
805 struct amd64_frame_cache
*cache
=
806 amd64_frame_cache (next_frame
, this_cache
);
808 /* This marks the outermost frame. */
809 if (cache
->base
== 0)
812 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
816 amd64_frame_prev_register (struct frame_info
*next_frame
, void **this_cache
,
817 int regnum
, int *optimizedp
,
818 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
819 int *realnump
, void *valuep
)
821 struct amd64_frame_cache
*cache
=
822 amd64_frame_cache (next_frame
, this_cache
);
824 gdb_assert (regnum
>= 0);
826 if (regnum
== SP_REGNUM
&& cache
->saved_sp
)
834 /* Store the value. */
835 store_unsigned_integer (valuep
, 8, cache
->saved_sp
);
840 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
843 *lvalp
= lval_memory
;
844 *addrp
= cache
->saved_regs
[regnum
];
848 /* Read the value in from memory. */
849 read_memory (*addrp
, valuep
,
850 register_size (current_gdbarch
, regnum
));
855 frame_register_unwind (next_frame
, regnum
,
856 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
859 static const struct frame_unwind amd64_frame_unwind
=
863 amd64_frame_prev_register
866 static const struct frame_unwind
*
867 amd64_frame_sniffer (struct frame_info
*next_frame
)
869 return &amd64_frame_unwind
;
873 /* Signal trampolines. */
875 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
876 64-bit variants. This would require using identical frame caches
877 on both platforms. */
879 static struct amd64_frame_cache
*
880 amd64_sigtramp_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
882 struct amd64_frame_cache
*cache
;
883 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
891 cache
= amd64_alloc_frame_cache ();
893 frame_unwind_register (next_frame
, X86_64_RSP_REGNUM
, buf
);
894 cache
->base
= extract_unsigned_integer (buf
, 8) - 8;
896 addr
= tdep
->sigcontext_addr (next_frame
);
897 gdb_assert (tdep
->sc_reg_offset
);
898 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
899 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
900 if (tdep
->sc_reg_offset
[i
] != -1)
901 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
908 amd64_sigtramp_frame_this_id (struct frame_info
*next_frame
,
909 void **this_cache
, struct frame_id
*this_id
)
911 struct amd64_frame_cache
*cache
=
912 amd64_sigtramp_frame_cache (next_frame
, this_cache
);
914 (*this_id
) = frame_id_build (cache
->base
+ 16, frame_pc_unwind (next_frame
));
918 amd64_sigtramp_frame_prev_register (struct frame_info
*next_frame
,
920 int regnum
, int *optimizedp
,
921 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
922 int *realnump
, void *valuep
)
924 /* Make sure we've initialized the cache. */
925 amd64_sigtramp_frame_cache (next_frame
, this_cache
);
927 amd64_frame_prev_register (next_frame
, this_cache
, regnum
,
928 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
931 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
934 amd64_sigtramp_frame_this_id
,
935 amd64_sigtramp_frame_prev_register
938 static const struct frame_unwind
*
939 amd64_sigtramp_frame_sniffer (struct frame_info
*next_frame
)
941 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
944 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
945 if (PC_IN_SIGTRAMP (pc
, name
))
947 gdb_assert (gdbarch_tdep (current_gdbarch
)->sigcontext_addr
);
949 return &amd64_sigtramp_frame_unwind
;
957 amd64_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
959 struct amd64_frame_cache
*cache
=
960 amd64_frame_cache (next_frame
, this_cache
);
965 static const struct frame_base amd64_frame_base
=
968 amd64_frame_base_address
,
969 amd64_frame_base_address
,
970 amd64_frame_base_address
973 static struct frame_id
974 amd64_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
979 frame_unwind_register (next_frame
, X86_64_RBP_REGNUM
, buf
);
980 fp
= extract_unsigned_integer (buf
, 8);
982 return frame_id_build (fp
+ 16, frame_pc_unwind (next_frame
));
985 /* 16 byte align the SP per frame requirements. */
988 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
990 return sp
& -(CORE_ADDR
)16;
994 /* Supply register REGNUM from the floating-point register set REGSET
995 to register cache REGCACHE. If REGNUM is -1, do this for all
996 registers in REGSET. */
999 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
1000 int regnum
, const void *fpregs
, size_t len
)
1002 const struct gdbarch_tdep
*tdep
= regset
->descr
;
1004 gdb_assert (len
== tdep
->sizeof_fpregset
);
1005 x86_64_supply_fxsave (regcache
, regnum
, fpregs
);
1008 /* Return the appropriate register set for the core section identified
1009 by SECT_NAME and SECT_SIZE. */
1011 static const struct regset
*
1012 amd64_regset_from_core_section (struct gdbarch
*gdbarch
,
1013 const char *sect_name
, size_t sect_size
)
1015 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1017 if (strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
1019 if (tdep
->fpregset
== NULL
)
1021 tdep
->fpregset
= XMALLOC (struct regset
);
1022 tdep
->fpregset
->descr
= tdep
;
1023 tdep
->fpregset
->supply_regset
= amd64_supply_fpregset
;
1026 return tdep
->fpregset
;
1029 return i386_regset_from_core_section (gdbarch
, sect_name
, sect_size
);
1034 x86_64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
1036 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1038 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
1039 floating-point registers. */
1040 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
1042 /* AMD64 has an FPU and 16 SSE registers. */
1043 tdep
->st0_regnum
= X86_64_ST0_REGNUM
;
1044 tdep
->num_xmm_regs
= 16;
1046 /* This is what all the fuss is about. */
1047 set_gdbarch_long_bit (gdbarch
, 64);
1048 set_gdbarch_long_long_bit (gdbarch
, 64);
1049 set_gdbarch_ptr_bit (gdbarch
, 64);
1051 /* In contrast to the i386, on AMD64 a `long double' actually takes
1052 up 128 bits, even though it's still based on the i387 extended
1053 floating-point format which has only 80 significant bits. */
1054 set_gdbarch_long_double_bit (gdbarch
, 128);
1056 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
1057 set_gdbarch_register_name (gdbarch
, amd64_register_name
);
1058 set_gdbarch_register_type (gdbarch
, amd64_register_type
);
1060 /* Register numbers of various important registers. */
1061 set_gdbarch_sp_regnum (gdbarch
, X86_64_RSP_REGNUM
); /* %rsp */
1062 set_gdbarch_pc_regnum (gdbarch
, X86_64_RIP_REGNUM
); /* %rip */
1063 set_gdbarch_ps_regnum (gdbarch
, X86_64_EFLAGS_REGNUM
); /* %eflags */
1064 set_gdbarch_fp0_regnum (gdbarch
, X86_64_ST0_REGNUM
); /* %st(0) */
1066 /* The "default" register numbering scheme for AMD64 is referred to
1067 as the "DWARF Register Number Mapping" in the System V psABI.
1068 The preferred debugging format for all known AMD64 targets is
1069 actually DWARF2, and GCC doesn't seem to support DWARF (that is
1070 DWARF-1), but we provide the same mapping just in case. This
1071 mapping is also used for stabs, which GCC does support. */
1072 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
1073 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
1074 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
1076 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
1077 be in use on any of the supported AMD64 targets. */
1079 /* Call dummy code. */
1080 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
1081 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
1082 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
1084 set_gdbarch_convert_register_p (gdbarch
, amd64_convert_register_p
);
1085 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
1086 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
1088 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
1089 /* Override, since this is handled by amd64_extract_return_value. */
1090 set_gdbarch_extract_struct_value_address (gdbarch
, NULL
);
1092 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
1094 /* Avoid wiring in the MMX registers for now. */
1095 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
1096 tdep
->mm0_regnum
= -1;
1098 set_gdbarch_unwind_dummy_id (gdbarch
, amd64_unwind_dummy_id
);
1100 /* FIXME: kettenis/20021026: This is ELF-specific. Fine for now,
1101 since all supported AMD64 targets are ELF, but that might change
1103 set_gdbarch_in_solib_call_trampoline (gdbarch
, in_plt_section
);
1105 frame_unwind_append_sniffer (gdbarch
, amd64_sigtramp_frame_sniffer
);
1106 frame_unwind_append_sniffer (gdbarch
, amd64_frame_sniffer
);
1107 frame_base_set_default (gdbarch
, &amd64_frame_base
);
1109 /* If we have a register mapping, enable the generic core file support. */
1110 if (tdep
->gregset_reg_offset
)
1111 set_gdbarch_regset_from_core_section (gdbarch
,
1112 amd64_regset_from_core_section
);
1116 #define I387_ST0_REGNUM X86_64_ST0_REGNUM
1118 /* The 64-bit FXSAVE format differs from the 32-bit format in the
1119 sense that the instruction pointer and data pointer are simply
1120 64-bit offsets into the code segment and the data segment instead
1121 of a selector offset pair. The functions below store the upper 32
1122 bits of these pointers (instead of just the 16-bits of the segment
1125 /* Fill register REGNUM in REGCACHE with the appropriate
1126 floating-point or SSE register value from *FXSAVE. If REGNUM is
1127 -1, do this for all registers. This function masks off any of the
1128 reserved bits in *FXSAVE. */
1131 x86_64_supply_fxsave (struct regcache
*regcache
, int regnum
,
1134 i387_supply_fxsave (regcache
, regnum
, fxsave
);
1138 const char *regs
= fxsave
;
1140 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM
)
1141 regcache_raw_supply (regcache
, I387_FISEG_REGNUM
, regs
+ 12);
1142 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM
)
1143 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM
, regs
+ 20);
1147 /* Fill register REGNUM (if it is a floating-point or SSE register) in
1148 *FXSAVE with the value in GDB's register cache. If REGNUM is -1, do
1149 this for all registers. This function doesn't touch any of the
1150 reserved bits in *FXSAVE. */
1153 x86_64_fill_fxsave (char *fxsave
, int regnum
)
1155 i387_fill_fxsave (fxsave
, regnum
);
1157 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM
)
1158 regcache_collect (I387_FISEG_REGNUM
, fxsave
+ 12);
1159 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM
)
1160 regcache_collect (I387_FOSEG_REGNUM
, fxsave
+ 20);