1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "solib-svr4.h"
32 #include "floatformat.h"
34 #include "reggroups.h"
37 #include "dummy-frame.h"
39 #include "dwarf2-frame.h"
40 #include "dwarf2loc.h"
41 #include "frame-base.h"
42 #include "frame-unwind.h"
44 #include "arch-utils.h"
52 #include "xtensa-isa.h"
53 #include "xtensa-tdep.h"
54 #include "xtensa-config.h"
58 static unsigned int xtensa_debug_level
= 0;
60 #define DEBUGWARN(args...) \
61 if (xtensa_debug_level > 0) \
62 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
64 #define DEBUGINFO(args...) \
65 if (xtensa_debug_level > 1) \
66 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
68 #define DEBUGTRACE(args...) \
69 if (xtensa_debug_level > 2) \
70 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
72 #define DEBUGVERB(args...) \
73 if (xtensa_debug_level > 3) \
74 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
77 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
78 #define SP_ALIGNMENT 16
81 /* On Windowed ABI, we use a6 through a11 for passing arguments
82 to a function called by GDB because CALL4 is used. */
83 #define ARGS_NUM_REGS 6
84 #define REGISTER_SIZE 4
87 /* Extract the call size from the return address or PS register. */
88 #define PS_CALLINC_SHIFT 16
89 #define PS_CALLINC_MASK 0x00030000
90 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
91 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
93 /* On TX, hardware can be configured without Exception Option.
94 There is no PS register in this case. Inside XT-GDB, let us treat
95 it as a virtual read-only register always holding the same value. */
98 /* ABI-independent macros. */
99 #define ARG_NOF(gdbarch) \
100 (gdbarch_tdep (gdbarch)->call_abi \
101 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
102 #define ARG_1ST(gdbarch) \
103 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
104 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
105 : (gdbarch_tdep (gdbarch)->a0_base + 6))
107 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
108 indicates that the instruction is an ENTRY instruction. */
110 #define XTENSA_IS_ENTRY(gdbarch, op1) \
111 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
112 ? ((op1) == 0x6c) : ((op1) == 0x36))
114 #define XTENSA_ENTRY_LENGTH 3
116 /* windowing_enabled() returns true, if windowing is enabled.
117 WOE must be set to 1; EXCM to 0.
118 Note: We assume that EXCM is always 0 for XEA1. */
120 #define PS_WOE (1<<18)
121 #define PS_EXC (1<<4)
124 windowing_enabled (struct gdbarch
*gdbarch
, unsigned int ps
)
126 /* If we know CALL0 ABI is set explicitly, say it is Call0. */
127 if (gdbarch_tdep (gdbarch
)->call_abi
== CallAbiCall0Only
)
130 return ((ps
& PS_EXC
) == 0 && (ps
& PS_WOE
) != 0);
133 /* Convert a live A-register number to the corresponding AR-register
136 arreg_number (struct gdbarch
*gdbarch
, int a_regnum
, ULONGEST wb
)
138 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
141 arreg
= a_regnum
- tdep
->a0_base
;
142 arreg
+= (wb
& ((tdep
->num_aregs
- 1) >> 2)) << WB_SHIFT
;
143 arreg
&= tdep
->num_aregs
- 1;
145 return arreg
+ tdep
->ar_base
;
148 /* Convert a live AR-register number to the corresponding A-register order
149 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
151 areg_number (struct gdbarch
*gdbarch
, int ar_regnum
, unsigned int wb
)
153 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
156 areg
= ar_regnum
- tdep
->ar_base
;
157 if (areg
< 0 || areg
>= tdep
->num_aregs
)
159 areg
= (areg
- wb
* 4) & (tdep
->num_aregs
- 1);
160 return (areg
> 15) ? -1 : areg
;
163 /* Read Xtensa register directly from the hardware. */
165 xtensa_read_register (int regnum
)
169 regcache_raw_read_unsigned (get_current_regcache (), regnum
, &value
);
170 return (unsigned long) value
;
173 /* Write Xtensa register directly to the hardware. */
175 xtensa_write_register (int regnum
, ULONGEST value
)
177 regcache_raw_write_unsigned (get_current_regcache (), regnum
, value
);
180 /* Return the window size of the previous call to the function from which we
183 This function is used to extract the return value after a called function
184 has returned to the caller. On Xtensa, the register that holds the return
185 value (from the perspective of the caller) depends on what call
186 instruction was used. For now, we are assuming that the call instruction
187 precedes the current address, so we simply analyze the call instruction.
188 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
189 method to call the inferior function. */
192 extract_call_winsize (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
194 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
199 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc
);
201 /* Read the previous instruction (should be a call[x]{4|8|12}. */
202 read_memory (pc
-3, buf
, 3);
203 insn
= extract_unsigned_integer (buf
, 3, byte_order
);
205 /* Decode call instruction:
207 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
208 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
210 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
211 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
213 if (byte_order
== BFD_ENDIAN_LITTLE
)
215 if (((insn
& 0xf) == 0x5) || ((insn
& 0xcf) == 0xc0))
216 winsize
= (insn
& 0x30) >> 2; /* 0, 4, 8, 12. */
220 if (((insn
>> 20) == 0x5) || (((insn
>> 16) & 0xf3) == 0x03))
221 winsize
= (insn
>> 16) & 0xc; /* 0, 4, 8, 12. */
227 /* REGISTER INFORMATION */
229 /* Find register by name. */
231 xtensa_find_register_by_name (struct gdbarch
*gdbarch
, char *name
)
235 for (i
= 0; i
< gdbarch_num_regs (gdbarch
)
236 + gdbarch_num_pseudo_regs (gdbarch
);
239 if (strcasecmp (gdbarch_tdep (gdbarch
)->regmap
[i
].name
, name
) == 0)
245 /* Returns the name of a register. */
247 xtensa_register_name (struct gdbarch
*gdbarch
, int regnum
)
249 /* Return the name stored in the register map. */
250 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
)
251 + gdbarch_num_pseudo_regs (gdbarch
))
252 return gdbarch_tdep (gdbarch
)->regmap
[regnum
].name
;
254 internal_error (__FILE__
, __LINE__
, _("invalid register %d"), regnum
);
258 /* Return the type of a register. Create a new type, if necessary. */
261 xtensa_register_type (struct gdbarch
*gdbarch
, int regnum
)
263 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
265 /* Return signed integer for ARx and Ax registers. */
266 if ((regnum
>= tdep
->ar_base
267 && regnum
< tdep
->ar_base
+ tdep
->num_aregs
)
268 || (regnum
>= tdep
->a0_base
269 && regnum
< tdep
->a0_base
+ 16))
270 return builtin_type (gdbarch
)->builtin_int
;
272 if (regnum
== gdbarch_pc_regnum (gdbarch
)
273 || regnum
== tdep
->a0_base
+ 1)
274 return builtin_type (gdbarch
)->builtin_data_ptr
;
276 /* Return the stored type for all other registers. */
277 else if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
)
278 + gdbarch_num_pseudo_regs (gdbarch
))
280 xtensa_register_t
* reg
= &tdep
->regmap
[regnum
];
282 /* Set ctype for this register (only the first time). */
286 struct ctype_cache
*tp
;
287 int size
= reg
->byte_size
;
289 /* We always use the memory representation,
290 even if the register width is smaller. */
294 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint8
;
298 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint16
;
302 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint32
;
306 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint64
;
310 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint128
;
314 for (tp
= tdep
->type_entries
; tp
!= NULL
; tp
= tp
->next
)
315 if (tp
->size
== size
)
320 char *name
= xstrprintf ("int%d", size
* 8);
322 tp
= XNEW (struct ctype_cache
);
323 tp
->next
= tdep
->type_entries
;
324 tdep
->type_entries
= tp
;
327 = arch_integer_type (gdbarch
, size
* 8, 1, name
);
331 reg
->ctype
= tp
->virtual_type
;
337 internal_error (__FILE__
, __LINE__
, _("invalid register number %d"), regnum
);
342 /* Return the 'local' register number for stubs, dwarf2, etc.
343 The debugging information enumerates registers starting from 0 for A0
344 to n for An. So, we only have to add the base number for A0. */
347 xtensa_reg_to_regnum (struct gdbarch
*gdbarch
, int regnum
)
351 if (regnum
>= 0 && regnum
< 16)
352 return gdbarch_tdep (gdbarch
)->a0_base
+ regnum
;
355 i
< gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
357 if (regnum
== gdbarch_tdep (gdbarch
)->regmap
[i
].target_number
)
364 /* Write the bits of a masked register to the various registers.
365 Only the masked areas of these registers are modified; the other
366 fields are untouched. The size of masked registers is always less
367 than or equal to 32 bits. */
370 xtensa_register_write_masked (struct regcache
*regcache
,
371 xtensa_register_t
*reg
, const gdb_byte
*buffer
)
373 unsigned int value
[(MAX_REGISTER_SIZE
+ 3) / 4];
374 const xtensa_mask_t
*mask
= reg
->mask
;
376 int shift
= 0; /* Shift for next mask (mod 32). */
377 int start
, size
; /* Start bit and size of current mask. */
379 unsigned int *ptr
= value
;
380 unsigned int regval
, m
, mem
= 0;
382 int bytesize
= reg
->byte_size
;
383 int bitsize
= bytesize
* 8;
386 DEBUGTRACE ("xtensa_register_write_masked ()\n");
388 /* Copy the masked register to host byte-order. */
389 if (gdbarch_byte_order (get_regcache_arch (regcache
)) == BFD_ENDIAN_BIG
)
390 for (i
= 0; i
< bytesize
; i
++)
393 mem
|= (buffer
[bytesize
- i
- 1] << 24);
398 for (i
= 0; i
< bytesize
; i
++)
401 mem
|= (buffer
[i
] << 24);
406 /* We might have to shift the final value:
407 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
408 bytesize & 3 == x -> shift (4-x) * 8. */
410 *ptr
= mem
>> (((0 - bytesize
) & 3) * 8);
414 /* Write the bits to the masked areas of the other registers. */
415 for (i
= 0; i
< mask
->count
; i
++)
417 start
= mask
->mask
[i
].bit_start
;
418 size
= mask
->mask
[i
].bit_size
;
419 regval
= mem
>> shift
;
421 if ((shift
+= size
) > bitsize
)
422 error (_("size of all masks is larger than the register"));
431 regval
|= mem
<< (size
- shift
);
434 /* Make sure we have a valid register. */
435 r
= mask
->mask
[i
].reg_num
;
436 if (r
>= 0 && size
> 0)
438 /* Don't overwrite the unmasked areas. */
440 regcache_cooked_read_unsigned (regcache
, r
, &old_val
);
441 m
= 0xffffffff >> (32 - size
) << start
;
443 regval
= (regval
& m
) | (old_val
& ~m
);
444 regcache_cooked_write_unsigned (regcache
, r
, regval
);
450 /* Read a tie state or mapped registers. Read the masked areas
451 of the registers and assemble them into a single value. */
453 static enum register_status
454 xtensa_register_read_masked (struct regcache
*regcache
,
455 xtensa_register_t
*reg
, gdb_byte
*buffer
)
457 unsigned int value
[(MAX_REGISTER_SIZE
+ 3) / 4];
458 const xtensa_mask_t
*mask
= reg
->mask
;
463 unsigned int *ptr
= value
;
464 unsigned int regval
, mem
= 0;
466 int bytesize
= reg
->byte_size
;
467 int bitsize
= bytesize
* 8;
470 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
471 reg
->name
== 0 ? "" : reg
->name
);
473 /* Assemble the register from the masked areas of other registers. */
474 for (i
= 0; i
< mask
->count
; i
++)
476 int r
= mask
->mask
[i
].reg_num
;
479 enum register_status status
;
482 status
= regcache_cooked_read_unsigned (regcache
, r
, &val
);
483 if (status
!= REG_VALID
)
485 regval
= (unsigned int) val
;
490 start
= mask
->mask
[i
].bit_start
;
491 size
= mask
->mask
[i
].bit_size
;
496 regval
&= (0xffffffff >> (32 - size
));
498 mem
|= regval
<< shift
;
500 if ((shift
+= size
) > bitsize
)
501 error (_("size of all masks is larger than the register"));
512 mem
= regval
>> (size
- shift
);
519 /* Copy value to target byte order. */
523 if (gdbarch_byte_order (get_regcache_arch (regcache
)) == BFD_ENDIAN_BIG
)
524 for (i
= 0; i
< bytesize
; i
++)
528 buffer
[bytesize
- i
- 1] = mem
& 0xff;
532 for (i
= 0; i
< bytesize
; i
++)
536 buffer
[i
] = mem
& 0xff;
544 /* Read pseudo registers. */
546 static enum register_status
547 xtensa_pseudo_register_read (struct gdbarch
*gdbarch
,
548 struct regcache
*regcache
,
552 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
554 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
555 regnum
, xtensa_register_name (gdbarch
, regnum
));
557 /* Read aliases a0..a15, if this is a Windowed ABI. */
558 if (gdbarch_tdep (gdbarch
)->isa_use_windowed_registers
559 && (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
)
560 && (regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15))
562 gdb_byte
*buf
= (gdb_byte
*) alloca (MAX_REGISTER_SIZE
);
563 enum register_status status
;
565 status
= regcache_raw_read (regcache
,
566 gdbarch_tdep (gdbarch
)->wb_regnum
,
568 if (status
!= REG_VALID
)
570 regnum
= arreg_number (gdbarch
, regnum
,
571 extract_unsigned_integer (buf
, 4, byte_order
));
574 /* We can always read non-pseudo registers. */
575 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
576 return regcache_raw_read (regcache
, regnum
, buffer
);
578 /* We have to find out how to deal with priveleged registers.
579 Let's treat them as pseudo-registers, but we cannot read/write them. */
581 else if (regnum
< gdbarch_tdep (gdbarch
)->a0_base
)
583 buffer
[0] = (gdb_byte
)0;
584 buffer
[1] = (gdb_byte
)0;
585 buffer
[2] = (gdb_byte
)0;
586 buffer
[3] = (gdb_byte
)0;
589 /* Pseudo registers. */
591 && regnum
< gdbarch_num_regs (gdbarch
)
592 + gdbarch_num_pseudo_regs (gdbarch
))
594 xtensa_register_t
*reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
595 xtensa_register_type_t type
= reg
->type
;
596 int flags
= gdbarch_tdep (gdbarch
)->target_flags
;
598 /* We cannot read Unknown or Unmapped registers. */
599 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
601 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
603 warning (_("cannot read register %s"),
604 xtensa_register_name (gdbarch
, regnum
));
609 /* Some targets cannot read TIE register files. */
610 else if (type
== xtRegisterTypeTieRegfile
)
612 /* Use 'fetch' to get register? */
613 if (flags
& xtTargetFlagsUseFetchStore
)
615 warning (_("cannot read register"));
619 /* On some targets (esp. simulators), we can always read the reg. */
620 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
622 warning (_("cannot read register"));
627 /* We can always read mapped registers. */
628 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
629 return xtensa_register_read_masked (regcache
, reg
, buffer
);
631 /* Assume that we can read the register. */
632 return regcache_raw_read (regcache
, regnum
, buffer
);
635 internal_error (__FILE__
, __LINE__
,
636 _("invalid register number %d"), regnum
);
640 /* Write pseudo registers. */
643 xtensa_pseudo_register_write (struct gdbarch
*gdbarch
,
644 struct regcache
*regcache
,
646 const gdb_byte
*buffer
)
648 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
650 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
651 regnum
, xtensa_register_name (gdbarch
, regnum
));
653 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
654 if (gdbarch_tdep (gdbarch
)->isa_use_windowed_registers
655 && (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
)
656 && (regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15))
658 gdb_byte
*buf
= (gdb_byte
*) alloca (MAX_REGISTER_SIZE
);
660 regcache_raw_read (regcache
,
661 gdbarch_tdep (gdbarch
)->wb_regnum
, buf
);
662 regnum
= arreg_number (gdbarch
, regnum
,
663 extract_unsigned_integer (buf
, 4, byte_order
));
666 /* We can always write 'core' registers.
667 Note: We might have converted Ax->ARy. */
668 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
669 regcache_raw_write (regcache
, regnum
, buffer
);
671 /* We have to find out how to deal with priveleged registers.
672 Let's treat them as pseudo-registers, but we cannot read/write them. */
674 else if (regnum
< gdbarch_tdep (gdbarch
)->a0_base
)
678 /* Pseudo registers. */
680 && regnum
< gdbarch_num_regs (gdbarch
)
681 + gdbarch_num_pseudo_regs (gdbarch
))
683 xtensa_register_t
*reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
684 xtensa_register_type_t type
= reg
->type
;
685 int flags
= gdbarch_tdep (gdbarch
)->target_flags
;
687 /* On most targets, we cannot write registers
688 of type "Unknown" or "Unmapped". */
689 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
691 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
693 warning (_("cannot write register %s"),
694 xtensa_register_name (gdbarch
, regnum
));
699 /* Some targets cannot read TIE register files. */
700 else if (type
== xtRegisterTypeTieRegfile
)
702 /* Use 'store' to get register? */
703 if (flags
& xtTargetFlagsUseFetchStore
)
705 warning (_("cannot write register"));
709 /* On some targets (esp. simulators), we can always write
711 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
713 warning (_("cannot write register"));
718 /* We can always write mapped registers. */
719 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
721 xtensa_register_write_masked (regcache
, reg
, buffer
);
725 /* Assume that we can write the register. */
726 regcache_raw_write (regcache
, regnum
, buffer
);
729 internal_error (__FILE__
, __LINE__
,
730 _("invalid register number %d"), regnum
);
733 static struct reggroup
*xtensa_ar_reggroup
;
734 static struct reggroup
*xtensa_user_reggroup
;
735 static struct reggroup
*xtensa_vectra_reggroup
;
736 static struct reggroup
*xtensa_cp
[XTENSA_MAX_COPROCESSOR
];
739 xtensa_init_reggroups (void)
742 char cpname
[] = "cp0";
744 xtensa_ar_reggroup
= reggroup_new ("ar", USER_REGGROUP
);
745 xtensa_user_reggroup
= reggroup_new ("user", USER_REGGROUP
);
746 xtensa_vectra_reggroup
= reggroup_new ("vectra", USER_REGGROUP
);
748 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
751 xtensa_cp
[i
] = reggroup_new (cpname
, USER_REGGROUP
);
756 xtensa_add_reggroups (struct gdbarch
*gdbarch
)
760 /* Predefined groups. */
761 reggroup_add (gdbarch
, all_reggroup
);
762 reggroup_add (gdbarch
, save_reggroup
);
763 reggroup_add (gdbarch
, restore_reggroup
);
764 reggroup_add (gdbarch
, system_reggroup
);
765 reggroup_add (gdbarch
, vector_reggroup
);
766 reggroup_add (gdbarch
, general_reggroup
);
767 reggroup_add (gdbarch
, float_reggroup
);
769 /* Xtensa-specific groups. */
770 reggroup_add (gdbarch
, xtensa_ar_reggroup
);
771 reggroup_add (gdbarch
, xtensa_user_reggroup
);
772 reggroup_add (gdbarch
, xtensa_vectra_reggroup
);
774 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
775 reggroup_add (gdbarch
, xtensa_cp
[i
]);
779 xtensa_coprocessor_register_group (struct reggroup
*group
)
783 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
784 if (group
== xtensa_cp
[i
])
790 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
791 | XTENSA_REGISTER_FLAGS_WRITABLE \
792 | XTENSA_REGISTER_FLAGS_VOLATILE)
794 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
795 | XTENSA_REGISTER_FLAGS_WRITABLE)
798 xtensa_register_reggroup_p (struct gdbarch
*gdbarch
,
800 struct reggroup
*group
)
802 xtensa_register_t
* reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
803 xtensa_register_type_t type
= reg
->type
;
804 xtensa_register_group_t rg
= reg
->group
;
807 if (group
== save_reggroup
)
808 /* Every single register should be included into the list of registers
809 to be watched for changes while using -data-list-changed-registers. */
812 /* First, skip registers that are not visible to this target
813 (unknown and unmapped registers when not using ISS). */
815 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
817 if (group
== all_reggroup
)
819 if (group
== xtensa_ar_reggroup
)
820 return rg
& xtRegisterGroupAddrReg
;
821 if (group
== xtensa_user_reggroup
)
822 return rg
& xtRegisterGroupUser
;
823 if (group
== float_reggroup
)
824 return rg
& xtRegisterGroupFloat
;
825 if (group
== general_reggroup
)
826 return rg
& xtRegisterGroupGeneral
;
827 if (group
== system_reggroup
)
828 return rg
& xtRegisterGroupState
;
829 if (group
== vector_reggroup
|| group
== xtensa_vectra_reggroup
)
830 return rg
& xtRegisterGroupVectra
;
831 if (group
== restore_reggroup
)
832 return (regnum
< gdbarch_num_regs (gdbarch
)
833 && (reg
->flags
& SAVE_REST_FLAGS
) == SAVE_REST_VALID
);
834 cp_number
= xtensa_coprocessor_register_group (group
);
836 return rg
& (xtRegisterGroupCP0
<< cp_number
);
842 /* Supply register REGNUM from the buffer specified by GREGS and LEN
843 in the general-purpose register set REGSET to register cache
844 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
847 xtensa_supply_gregset (const struct regset
*regset
,
853 const xtensa_elf_gregset_t
*regs
= (const xtensa_elf_gregset_t
*) gregs
;
854 struct gdbarch
*gdbarch
= get_regcache_arch (rc
);
857 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum
);
859 if (regnum
== gdbarch_pc_regnum (gdbarch
) || regnum
== -1)
860 regcache_raw_supply (rc
, gdbarch_pc_regnum (gdbarch
), (char *) ®s
->pc
);
861 if (regnum
== gdbarch_ps_regnum (gdbarch
) || regnum
== -1)
862 regcache_raw_supply (rc
, gdbarch_ps_regnum (gdbarch
), (char *) ®s
->ps
);
863 if (regnum
== gdbarch_tdep (gdbarch
)->wb_regnum
|| regnum
== -1)
864 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->wb_regnum
,
865 (char *) ®s
->windowbase
);
866 if (regnum
== gdbarch_tdep (gdbarch
)->ws_regnum
|| regnum
== -1)
867 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->ws_regnum
,
868 (char *) ®s
->windowstart
);
869 if (regnum
== gdbarch_tdep (gdbarch
)->lbeg_regnum
|| regnum
== -1)
870 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lbeg_regnum
,
871 (char *) ®s
->lbeg
);
872 if (regnum
== gdbarch_tdep (gdbarch
)->lend_regnum
|| regnum
== -1)
873 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lend_regnum
,
874 (char *) ®s
->lend
);
875 if (regnum
== gdbarch_tdep (gdbarch
)->lcount_regnum
|| regnum
== -1)
876 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lcount_regnum
,
877 (char *) ®s
->lcount
);
878 if (regnum
== gdbarch_tdep (gdbarch
)->sar_regnum
|| regnum
== -1)
879 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->sar_regnum
,
880 (char *) ®s
->sar
);
881 if (regnum
>=gdbarch_tdep (gdbarch
)->ar_base
882 && regnum
< gdbarch_tdep (gdbarch
)->ar_base
883 + gdbarch_tdep (gdbarch
)->num_aregs
)
884 regcache_raw_supply (rc
, regnum
,
885 (char *) ®s
->ar
[regnum
- gdbarch_tdep
886 (gdbarch
)->ar_base
]);
887 else if (regnum
== -1)
889 for (i
= 0; i
< gdbarch_tdep (gdbarch
)->num_aregs
; ++i
)
890 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->ar_base
+ i
,
891 (char *) ®s
->ar
[i
]);
896 /* Xtensa register set. */
902 xtensa_supply_gregset
906 /* Iterate over supported core file register note sections. */
909 xtensa_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
910 iterate_over_regset_sections_cb
*cb
,
912 const struct regcache
*regcache
)
914 DEBUGTRACE ("xtensa_iterate_over_regset_sections\n");
916 cb (".reg", sizeof (xtensa_elf_gregset_t
), &xtensa_gregset
,
921 /* Handling frames. */
923 /* Number of registers to save in case of Windowed ABI. */
924 #define XTENSA_NUM_SAVED_AREGS 12
926 /* Frame cache part for Windowed ABI. */
927 typedef struct xtensa_windowed_frame_cache
929 int wb
; /* WINDOWBASE of the previous frame. */
930 int callsize
; /* Call size of this frame. */
931 int ws
; /* WINDOWSTART of the previous frame. It keeps track of
932 life windows only. If there is no bit set for the
933 window, that means it had been already spilled
934 because of window overflow. */
936 /* Addresses of spilled A-registers.
937 AREGS[i] == -1, if corresponding AR is alive. */
938 CORE_ADDR aregs
[XTENSA_NUM_SAVED_AREGS
];
939 } xtensa_windowed_frame_cache_t
;
941 /* Call0 ABI Definitions. */
943 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue
945 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
946 #define C0_SP 1 /* Register used as SP. */
947 #define C0_FP 15 /* Register used as FP. */
948 #define C0_RA 0 /* Register used as return address. */
949 #define C0_ARGS 2 /* Register used as first arg/retval. */
950 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
952 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
953 A-register where the current content of the reg came from (in terms
954 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
955 mean that the orignal content of the register was saved to the stack.
956 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
957 know where SP will end up until the entire prologue has been analyzed. */
959 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
960 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
961 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
963 extern xtensa_isa xtensa_default_isa
;
965 typedef struct xtensa_c0reg
967 int fr_reg
; /* original register from which register content
968 is derived, or C0_CONST, or C0_INEXP. */
969 int fr_ofs
; /* constant offset from reg, or immediate value. */
970 int to_stk
; /* offset from original SP to register (4-byte aligned),
971 or C0_NOSTK if register has not been saved. */
974 /* Frame cache part for Call0 ABI. */
975 typedef struct xtensa_call0_frame_cache
977 int c0_frmsz
; /* Stack frame size. */
978 int c0_hasfp
; /* Current frame uses frame pointer. */
979 int fp_regnum
; /* A-register used as FP. */
980 int c0_fp
; /* Actual value of frame pointer. */
981 int c0_fpalign
; /* Dinamic adjustment for the stack
982 pointer. It's an AND mask. Zero,
983 if alignment was not adjusted. */
984 int c0_old_sp
; /* In case of dynamic adjustment, it is
985 a register holding unaligned sp.
986 C0_INEXP, when undefined. */
987 int c0_sp_ofs
; /* If "c0_old_sp" was spilled it's a
988 stack offset. C0_NOSTK otherwise. */
990 xtensa_c0reg_t c0_rt
[C0_NREGS
]; /* Register tracking information. */
991 } xtensa_call0_frame_cache_t
;
993 typedef struct xtensa_frame_cache
995 CORE_ADDR base
; /* Stack pointer of this frame. */
996 CORE_ADDR pc
; /* PC of this frame at the function entry point. */
997 CORE_ADDR ra
; /* The raw return address of this frame. */
998 CORE_ADDR ps
; /* The PS register of the previous (older) frame. */
999 CORE_ADDR prev_sp
; /* Stack Pointer of the previous (older) frame. */
1000 int call0
; /* It's a call0 framework (else windowed). */
1003 xtensa_windowed_frame_cache_t wd
; /* call0 == false. */
1004 xtensa_call0_frame_cache_t c0
; /* call0 == true. */
1006 } xtensa_frame_cache_t
;
1009 static struct xtensa_frame_cache
*
1010 xtensa_alloc_frame_cache (int windowed
)
1012 xtensa_frame_cache_t
*cache
;
1015 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
1017 cache
= FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t
);
1024 cache
->call0
= !windowed
;
1027 cache
->c0
.c0_frmsz
= -1;
1028 cache
->c0
.c0_hasfp
= 0;
1029 cache
->c0
.fp_regnum
= -1;
1030 cache
->c0
.c0_fp
= -1;
1031 cache
->c0
.c0_fpalign
= 0;
1032 cache
->c0
.c0_old_sp
= C0_INEXP
;
1033 cache
->c0
.c0_sp_ofs
= C0_NOSTK
;
1035 for (i
= 0; i
< C0_NREGS
; i
++)
1037 cache
->c0
.c0_rt
[i
].fr_reg
= i
;
1038 cache
->c0
.c0_rt
[i
].fr_ofs
= 0;
1039 cache
->c0
.c0_rt
[i
].to_stk
= C0_NOSTK
;
1046 cache
->wd
.callsize
= -1;
1048 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
1049 cache
->wd
.aregs
[i
] = -1;
1056 xtensa_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
1058 return address
& ~15;
1063 xtensa_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1068 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1069 host_address_to_string (next_frame
));
1071 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1072 pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1074 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc
);
1080 static struct frame_id
1081 xtensa_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1085 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1087 pc
= get_frame_pc (this_frame
);
1088 fp
= get_frame_register_unsigned
1089 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1091 /* Make dummy frame ID unique by adding a constant. */
1092 return frame_id_build (fp
+ SP_ALIGNMENT
, pc
);
1095 /* Returns true, if instruction to execute next is unique to Xtensa Window
1096 Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
1099 xtensa_window_interrupt_insn (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1101 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1102 unsigned int insn
= read_memory_integer (pc
, 4, byte_order
);
1105 if (byte_order
== BFD_ENDIAN_BIG
)
1107 /* Check, if this is L32E or S32E. */
1108 code
= insn
& 0xf000ff00;
1109 if ((code
== 0x00009000) || (code
== 0x00009400))
1111 /* Check, if this is RFWU or RFWO. */
1112 code
= insn
& 0xffffff00;
1113 return ((code
== 0x00430000) || (code
== 0x00530000));
1117 /* Check, if this is L32E or S32E. */
1118 code
= insn
& 0x00ff000f;
1119 if ((code
== 0x090000) || (code
== 0x490000))
1121 /* Check, if this is RFWU or RFWO. */
1122 code
= insn
& 0x00ffffff;
1123 return ((code
== 0x00003400) || (code
== 0x00003500));
1127 /* Returns the best guess about which register is a frame pointer
1128 for the function containing CURRENT_PC. */
1130 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1131 #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1134 xtensa_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
)
1136 #define RETURN_FP goto done
1138 unsigned int fp_regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ 1;
1139 CORE_ADDR start_addr
;
1141 xtensa_insnbuf ins
, slot
;
1142 gdb_byte ibuf
[XTENSA_ISA_BSZ
];
1143 CORE_ADDR ia
, bt
, ba
;
1145 int ilen
, islots
, is
;
1147 const char *opcname
;
1149 find_pc_partial_function (current_pc
, NULL
, &start_addr
, NULL
);
1150 if (start_addr
== 0)
1153 isa
= xtensa_default_isa
;
1154 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
1155 ins
= xtensa_insnbuf_alloc (isa
);
1156 slot
= xtensa_insnbuf_alloc (isa
);
1159 for (ia
= start_addr
, bt
= ia
; ia
< current_pc
; ia
+= ilen
)
1161 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
1164 bt
= (ba
+ XTENSA_ISA_BSZ
) < current_pc
1165 ? ba
+ XTENSA_ISA_BSZ
: current_pc
;
1166 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0)
1170 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
1171 ifmt
= xtensa_format_decode (isa
, ins
);
1172 if (ifmt
== XTENSA_UNDEFINED
)
1174 ilen
= xtensa_format_length (isa
, ifmt
);
1175 if (ilen
== XTENSA_UNDEFINED
)
1177 islots
= xtensa_format_num_slots (isa
, ifmt
);
1178 if (islots
== XTENSA_UNDEFINED
)
1181 for (is
= 0; is
< islots
; ++is
)
1183 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
1186 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
1187 if (opc
== XTENSA_UNDEFINED
)
1190 opcname
= xtensa_opcode_name (isa
, opc
);
1192 if (strcasecmp (opcname
, "mov.n") == 0
1193 || strcasecmp (opcname
, "or") == 0)
1195 unsigned int register_operand
;
1197 /* Possible candidate for setting frame pointer
1198 from A1. This is what we are looking for. */
1200 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
,
1201 is
, slot
, ®ister_operand
) != 0)
1203 if (xtensa_operand_decode (isa
, opc
, 1, ®ister_operand
) != 0)
1205 if (register_operand
== 1) /* Mov{.n} FP A1. */
1207 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
,
1208 ®ister_operand
) != 0)
1210 if (xtensa_operand_decode (isa
, opc
, 0,
1211 ®ister_operand
) != 0)
1215 = gdbarch_tdep (gdbarch
)->a0_base
+ register_operand
;
1221 /* We have problems decoding the memory. */
1223 || strcasecmp (opcname
, "ill") == 0
1224 || strcasecmp (opcname
, "ill.n") == 0
1225 /* Hit planted breakpoint. */
1226 || strcasecmp (opcname
, "break") == 0
1227 || strcasecmp (opcname
, "break.n") == 0
1228 /* Flow control instructions finish prologue. */
1229 || xtensa_opcode_is_branch (isa
, opc
) > 0
1230 || xtensa_opcode_is_jump (isa
, opc
) > 0
1231 || xtensa_opcode_is_loop (isa
, opc
) > 0
1232 || xtensa_opcode_is_call (isa
, opc
) > 0
1233 || strcasecmp (opcname
, "simcall") == 0
1234 || strcasecmp (opcname
, "syscall") == 0)
1235 /* Can not continue analysis. */
1240 xtensa_insnbuf_free(isa
, slot
);
1241 xtensa_insnbuf_free(isa
, ins
);
1245 /* The key values to identify the frame using "cache" are
1247 cache->base = SP (or best guess about FP) of this frame;
1248 cache->pc = entry-PC (entry point of the frame function);
1249 cache->prev_sp = SP of the previous frame. */
1252 call0_frame_cache (struct frame_info
*this_frame
,
1253 xtensa_frame_cache_t
*cache
, CORE_ADDR pc
);
1256 xtensa_window_interrupt_frame_cache (struct frame_info
*this_frame
,
1257 xtensa_frame_cache_t
*cache
,
1260 static struct xtensa_frame_cache
*
1261 xtensa_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1263 xtensa_frame_cache_t
*cache
;
1264 CORE_ADDR ra
, wb
, ws
, pc
, sp
, ps
;
1265 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1266 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1267 unsigned int fp_regnum
;
1268 int windowed
, ps_regnum
;
1271 return (struct xtensa_frame_cache
*) *this_cache
;
1273 pc
= get_frame_register_unsigned (this_frame
, gdbarch_pc_regnum (gdbarch
));
1274 ps_regnum
= gdbarch_ps_regnum (gdbarch
);
1275 ps
= (ps_regnum
>= 0
1276 ? get_frame_register_unsigned (this_frame
, ps_regnum
) : TX_PS
);
1278 windowed
= windowing_enabled (gdbarch
, ps
);
1280 /* Get pristine xtensa-frame. */
1281 cache
= xtensa_alloc_frame_cache (windowed
);
1282 *this_cache
= cache
;
1288 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1289 wb
= get_frame_register_unsigned (this_frame
,
1290 gdbarch_tdep (gdbarch
)->wb_regnum
);
1291 ws
= get_frame_register_unsigned (this_frame
,
1292 gdbarch_tdep (gdbarch
)->ws_regnum
);
1294 if (safe_read_memory_integer (pc
, 1, byte_order
, &op1
)
1295 && XTENSA_IS_ENTRY (gdbarch
, op1
))
1297 int callinc
= CALLINC (ps
);
1298 ra
= get_frame_register_unsigned
1299 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ callinc
* 4);
1301 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1302 cache
->wd
.callsize
= 0;
1305 cache
->prev_sp
= get_frame_register_unsigned
1306 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1308 /* This only can be the outermost frame since we are
1309 just about to execute ENTRY. SP hasn't been set yet.
1310 We can assume any frame size, because it does not
1311 matter, and, let's fake frame base in cache. */
1312 cache
->base
= cache
->prev_sp
- 16;
1315 cache
->ra
= (cache
->pc
& 0xc0000000) | (ra
& 0x3fffffff);
1316 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1317 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1323 fp_regnum
= xtensa_scan_prologue (gdbarch
, pc
);
1324 ra
= get_frame_register_unsigned (this_frame
,
1325 gdbarch_tdep (gdbarch
)->a0_base
);
1326 cache
->wd
.callsize
= WINSIZE (ra
);
1327 cache
->wd
.wb
= (wb
- cache
->wd
.callsize
/ 4)
1328 & (gdbarch_tdep (gdbarch
)->num_aregs
/ 4 - 1);
1329 cache
->wd
.ws
= ws
& ~(1 << wb
);
1331 cache
->pc
= get_frame_func (this_frame
);
1332 cache
->ra
= (pc
& 0xc0000000) | (ra
& 0x3fffffff);
1333 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1334 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1337 if (cache
->wd
.ws
== 0)
1342 sp
= get_frame_register_unsigned
1343 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1) - 16;
1345 for (i
= 0; i
< 4; i
++, sp
+= 4)
1347 cache
->wd
.aregs
[i
] = sp
;
1350 if (cache
->wd
.callsize
> 4)
1352 /* Set A4...A7/A11. */
1353 /* Get the SP of the frame previous to the previous one.
1354 To achieve this, we have to dereference SP twice. */
1355 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4, byte_order
);
1356 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4, byte_order
);
1357 sp
-= cache
->wd
.callsize
* 4;
1359 for ( i
= 4; i
< cache
->wd
.callsize
; i
++, sp
+= 4)
1361 cache
->wd
.aregs
[i
] = sp
;
1366 if ((cache
->prev_sp
== 0) && ( ra
!= 0 ))
1367 /* If RA is equal to 0 this frame is an outermost frame. Leave
1368 cache->prev_sp unchanged marking the boundary of the frame stack. */
1370 if ((cache
->wd
.ws
& (1 << cache
->wd
.wb
)) == 0)
1372 /* Register window overflow already happened.
1373 We can read caller's SP from the proper spill loction. */
1374 sp
= get_frame_register_unsigned
1375 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1376 cache
->prev_sp
= read_memory_integer (sp
- 12, 4, byte_order
);
1380 /* Read caller's frame SP directly from the previous window. */
1381 int regnum
= arreg_number
1382 (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ 1,
1385 cache
->prev_sp
= xtensa_read_register (regnum
);
1389 else if (xtensa_window_interrupt_insn (gdbarch
, pc
))
1391 /* Execution stopped inside Xtensa Window Interrupt Handler. */
1393 xtensa_window_interrupt_frame_cache (this_frame
, cache
, pc
);
1394 /* Everything was set already, including cache->base. */
1397 else /* Call0 framework. */
1399 call0_frame_cache (this_frame
, cache
, pc
);
1400 fp_regnum
= cache
->c0
.fp_regnum
;
1403 cache
->base
= get_frame_register_unsigned (this_frame
, fp_regnum
);
1408 static int xtensa_session_once_reported
= 1;
1410 /* Report a problem with prologue analysis while doing backtracing.
1411 But, do it only once to avoid annoyng repeated messages. */
1416 if (xtensa_session_once_reported
== 0)
1418 \nUnrecognised function prologue. Stack trace cannot be resolved. \
1419 This message will not be repeated in this session.\n"));
1421 xtensa_session_once_reported
= 1;
1426 xtensa_frame_this_id (struct frame_info
*this_frame
,
1428 struct frame_id
*this_id
)
1430 struct xtensa_frame_cache
*cache
=
1431 xtensa_frame_cache (this_frame
, this_cache
);
1433 if (cache
->prev_sp
== 0)
1436 (*this_id
) = frame_id_build (cache
->prev_sp
, cache
->pc
);
1439 static struct value
*
1440 xtensa_frame_prev_register (struct frame_info
*this_frame
,
1444 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1445 struct xtensa_frame_cache
*cache
;
1446 ULONGEST saved_reg
= 0;
1449 if (*this_cache
== NULL
)
1450 *this_cache
= xtensa_frame_cache (this_frame
, this_cache
);
1451 cache
= (struct xtensa_frame_cache
*) *this_cache
;
1453 if (regnum
==gdbarch_pc_regnum (gdbarch
))
1454 saved_reg
= cache
->ra
;
1455 else if (regnum
== gdbarch_tdep (gdbarch
)->a0_base
+ 1)
1456 saved_reg
= cache
->prev_sp
;
1457 else if (!cache
->call0
)
1459 if (regnum
== gdbarch_tdep (gdbarch
)->ws_regnum
)
1460 saved_reg
= cache
->wd
.ws
;
1461 else if (regnum
== gdbarch_tdep (gdbarch
)->wb_regnum
)
1462 saved_reg
= cache
->wd
.wb
;
1463 else if (regnum
== gdbarch_ps_regnum (gdbarch
))
1464 saved_reg
= cache
->ps
;
1472 return frame_unwind_got_constant (this_frame
, regnum
, saved_reg
);
1474 if (!cache
->call0
) /* Windowed ABI. */
1476 /* Convert A-register numbers to AR-register numbers,
1477 if we deal with A-register. */
1478 if (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
1479 && regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15)
1480 regnum
= arreg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1482 /* Check, if we deal with AR-register saved on stack. */
1483 if (regnum
>= gdbarch_tdep (gdbarch
)->ar_base
1484 && regnum
<= (gdbarch_tdep (gdbarch
)->ar_base
1485 + gdbarch_tdep (gdbarch
)->num_aregs
))
1487 int areg
= areg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1490 && areg
< XTENSA_NUM_SAVED_AREGS
1491 && cache
->wd
.aregs
[areg
] != -1)
1492 return frame_unwind_got_memory (this_frame
, regnum
,
1493 cache
->wd
.aregs
[areg
]);
1496 else /* Call0 ABI. */
1498 int reg
= (regnum
>= gdbarch_tdep (gdbarch
)->ar_base
1499 && regnum
<= (gdbarch_tdep (gdbarch
)->ar_base
1501 ? regnum
- gdbarch_tdep (gdbarch
)->ar_base
: regnum
;
1508 /* If register was saved in the prologue, retrieve it. */
1509 stkofs
= cache
->c0
.c0_rt
[reg
].to_stk
;
1510 if (stkofs
!= C0_NOSTK
)
1512 /* Determine SP on entry based on FP. */
1513 spe
= cache
->c0
.c0_fp
1514 - cache
->c0
.c0_rt
[cache
->c0
.fp_regnum
].fr_ofs
;
1516 return frame_unwind_got_memory (this_frame
, regnum
,
1522 /* All other registers have been either saved to
1523 the stack or are still alive in the processor. */
1525 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1529 static const struct frame_unwind
1533 default_frame_unwind_stop_reason
,
1534 xtensa_frame_this_id
,
1535 xtensa_frame_prev_register
,
1537 default_frame_sniffer
1541 xtensa_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1543 struct xtensa_frame_cache
*cache
=
1544 xtensa_frame_cache (this_frame
, this_cache
);
1549 static const struct frame_base
1553 xtensa_frame_base_address
,
1554 xtensa_frame_base_address
,
1555 xtensa_frame_base_address
1560 xtensa_extract_return_value (struct type
*type
,
1561 struct regcache
*regcache
,
1564 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1565 bfd_byte
*valbuf
= (bfd_byte
*) dst
;
1566 int len
= TYPE_LENGTH (type
);
1571 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1573 gdb_assert(len
> 0);
1575 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1577 /* First, we have to find the caller window in the register file. */
1578 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1579 callsize
= extract_call_winsize (gdbarch
, pc
);
1581 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1582 if (len
> (callsize
> 8 ? 8 : 16))
1583 internal_error (__FILE__
, __LINE__
,
1584 _("cannot extract return value of %d bytes long"),
1587 /* Get the register offset of the return
1588 register (A2) in the caller window. */
1589 regcache_raw_read_unsigned
1590 (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, &wb
);
1591 areg
= arreg_number (gdbarch
,
1592 gdbarch_tdep (gdbarch
)->a0_base
+ 2 + callsize
, wb
);
1596 /* No windowing hardware - Call0 ABI. */
1597 areg
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_ARGS
;
1600 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg
, len
);
1602 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1605 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1608 regcache_raw_read_part (regcache
, areg
, offset
, len
, valbuf
);
1610 regcache_raw_read (regcache
, areg
, valbuf
);
1616 xtensa_store_return_value (struct type
*type
,
1617 struct regcache
*regcache
,
1620 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1621 const bfd_byte
*valbuf
= (const bfd_byte
*) dst
;
1625 int len
= TYPE_LENGTH (type
);
1628 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1630 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1632 regcache_raw_read_unsigned
1633 (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, &wb
);
1634 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1635 callsize
= extract_call_winsize (gdbarch
, pc
);
1637 if (len
> (callsize
> 8 ? 8 : 16))
1638 internal_error (__FILE__
, __LINE__
,
1639 _("unimplemented for this length: %d"),
1640 TYPE_LENGTH (type
));
1641 areg
= arreg_number (gdbarch
,
1642 gdbarch_tdep (gdbarch
)->a0_base
+ 2 + callsize
, wb
);
1644 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1645 callsize
, (int) wb
);
1649 areg
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_ARGS
;
1652 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1655 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1658 regcache_raw_write_part (regcache
, areg
, offset
, len
, valbuf
);
1660 regcache_raw_write (regcache
, areg
, valbuf
);
1665 static enum return_value_convention
1666 xtensa_return_value (struct gdbarch
*gdbarch
,
1667 struct value
*function
,
1668 struct type
*valtype
,
1669 struct regcache
*regcache
,
1671 const gdb_byte
*writebuf
)
1673 /* Structures up to 16 bytes are returned in registers. */
1675 int struct_return
= ((TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
1676 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
1677 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
1678 && TYPE_LENGTH (valtype
) > 16);
1681 return RETURN_VALUE_STRUCT_CONVENTION
;
1683 DEBUGTRACE ("xtensa_return_value(...)\n");
1685 if (writebuf
!= NULL
)
1687 xtensa_store_return_value (valtype
, regcache
, writebuf
);
1690 if (readbuf
!= NULL
)
1692 gdb_assert (!struct_return
);
1693 xtensa_extract_return_value (valtype
, regcache
, readbuf
);
1695 return RETURN_VALUE_REGISTER_CONVENTION
;
1702 xtensa_push_dummy_call (struct gdbarch
*gdbarch
,
1703 struct value
*function
,
1704 struct regcache
*regcache
,
1707 struct value
**args
,
1710 CORE_ADDR struct_addr
)
1712 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1714 int size
, onstack_size
;
1715 gdb_byte
*buf
= (gdb_byte
*) alloca (16);
1717 struct argument_info
1719 const bfd_byte
*contents
;
1721 int onstack
; /* onstack == 0 => in reg */
1722 int align
; /* alignment */
1725 int offset
; /* stack offset if on stack. */
1726 int regno
; /* regno if in register. */
1730 struct argument_info
*arg_info
=
1731 (struct argument_info
*) alloca (nargs
* sizeof (struct argument_info
));
1735 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1737 if (xtensa_debug_level
> 3)
1740 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs
);
1741 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1742 "struct_addr=0x%x\n",
1743 (int) sp
, (int) struct_return
, (int) struct_addr
);
1745 for (i
= 0; i
< nargs
; i
++)
1747 struct value
*arg
= args
[i
];
1748 struct type
*arg_type
= check_typedef (value_type (arg
));
1749 fprintf_unfiltered (gdb_stdlog
, "%2d: %s %3d ", i
,
1750 host_address_to_string (arg
),
1751 TYPE_LENGTH (arg_type
));
1752 switch (TYPE_CODE (arg_type
))
1755 fprintf_unfiltered (gdb_stdlog
, "int");
1757 case TYPE_CODE_STRUCT
:
1758 fprintf_unfiltered (gdb_stdlog
, "struct");
1761 fprintf_unfiltered (gdb_stdlog
, "%3d", TYPE_CODE (arg_type
));
1764 fprintf_unfiltered (gdb_stdlog
, " %s\n",
1765 host_address_to_string (value_contents (arg
)));
1769 /* First loop: collect information.
1770 Cast into type_long. (This shouldn't happen often for C because
1771 GDB already does this earlier.) It's possible that GDB could
1772 do it all the time but it's harmless to leave this code here. */
1779 size
= REGISTER_SIZE
;
1781 for (i
= 0; i
< nargs
; i
++)
1783 struct argument_info
*info
= &arg_info
[i
];
1784 struct value
*arg
= args
[i
];
1785 struct type
*arg_type
= check_typedef (value_type (arg
));
1787 switch (TYPE_CODE (arg_type
))
1790 case TYPE_CODE_BOOL
:
1791 case TYPE_CODE_CHAR
:
1792 case TYPE_CODE_RANGE
:
1793 case TYPE_CODE_ENUM
:
1795 /* Cast argument to long if necessary as the mask does it too. */
1796 if (TYPE_LENGTH (arg_type
)
1797 < TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
))
1799 arg_type
= builtin_type (gdbarch
)->builtin_long
;
1800 arg
= value_cast (arg_type
, arg
);
1802 /* Aligment is equal to the type length for the basic types. */
1803 info
->align
= TYPE_LENGTH (arg_type
);
1808 /* Align doubles correctly. */
1809 if (TYPE_LENGTH (arg_type
)
1810 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
))
1811 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
);
1813 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
);
1816 case TYPE_CODE_STRUCT
:
1818 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
);
1821 info
->length
= TYPE_LENGTH (arg_type
);
1822 info
->contents
= value_contents (arg
);
1824 /* Align size and onstack_size. */
1825 size
= (size
+ info
->align
- 1) & ~(info
->align
- 1);
1826 onstack_size
= (onstack_size
+ info
->align
- 1) & ~(info
->align
- 1);
1828 if (size
+ info
->length
> REGISTER_SIZE
* ARG_NOF (gdbarch
))
1831 info
->u
.offset
= onstack_size
;
1832 onstack_size
+= info
->length
;
1837 info
->u
.regno
= ARG_1ST (gdbarch
) + size
/ REGISTER_SIZE
;
1839 size
+= info
->length
;
1842 /* Adjust the stack pointer and align it. */
1843 sp
= align_down (sp
- onstack_size
, SP_ALIGNMENT
);
1845 /* Simulate MOVSP, if Windowed ABI. */
1846 if ((gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1849 read_memory (osp
- 16, buf
, 16);
1850 write_memory (sp
- 16, buf
, 16);
1853 /* Second Loop: Load arguments. */
1857 store_unsigned_integer (buf
, REGISTER_SIZE
, byte_order
, struct_addr
);
1858 regcache_cooked_write (regcache
, ARG_1ST (gdbarch
), buf
);
1861 for (i
= 0; i
< nargs
; i
++)
1863 struct argument_info
*info
= &arg_info
[i
];
1867 int n
= info
->length
;
1868 CORE_ADDR offset
= sp
+ info
->u
.offset
;
1870 /* Odd-sized structs are aligned to the lower side of a memory
1871 word in big-endian mode and require a shift. This only
1872 applies for structures smaller than one word. */
1874 if (n
< REGISTER_SIZE
1875 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1876 offset
+= (REGISTER_SIZE
- n
);
1878 write_memory (offset
, info
->contents
, info
->length
);
1883 int n
= info
->length
;
1884 const bfd_byte
*cp
= info
->contents
;
1885 int r
= info
->u
.regno
;
1887 /* Odd-sized structs are aligned to the lower side of registers in
1888 big-endian mode and require a shift. The odd-sized leftover will
1889 be at the end. Note that this is only true for structures smaller
1890 than REGISTER_SIZE; for larger odd-sized structures the excess
1891 will be left-aligned in the register on both endiannesses. */
1893 if (n
< REGISTER_SIZE
&& byte_order
== BFD_ENDIAN_BIG
)
1896 v
= extract_unsigned_integer (cp
, REGISTER_SIZE
, byte_order
);
1897 v
= v
>> ((REGISTER_SIZE
- n
) * TARGET_CHAR_BIT
);
1899 store_unsigned_integer (buf
, REGISTER_SIZE
, byte_order
, v
);
1900 regcache_cooked_write (regcache
, r
, buf
);
1902 cp
+= REGISTER_SIZE
;
1909 regcache_cooked_write (regcache
, r
, cp
);
1911 cp
+= REGISTER_SIZE
;
1918 /* Set the return address of dummy frame to the dummy address.
1919 The return address for the current function (in A0) is
1920 saved in the dummy frame, so we can savely overwrite A0 here. */
1922 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1926 ra
= (bp_addr
& 0x3fffffff) | 0x40000000;
1927 regcache_raw_read_unsigned (regcache
, gdbarch_ps_regnum (gdbarch
), &val
);
1928 ps
= (unsigned long) val
& ~0x00030000;
1929 regcache_cooked_write_unsigned
1930 (regcache
, gdbarch_tdep (gdbarch
)->a0_base
+ 4, ra
);
1931 regcache_cooked_write_unsigned (regcache
,
1932 gdbarch_ps_regnum (gdbarch
),
1935 /* All the registers have been saved. After executing
1936 dummy call, they all will be restored. So it's safe
1937 to modify WINDOWSTART register to make it look like there
1938 is only one register window corresponding to WINDOWEBASE. */
1940 regcache_raw_read (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, buf
);
1941 regcache_cooked_write_unsigned
1942 (regcache
, gdbarch_tdep (gdbarch
)->ws_regnum
,
1943 1 << extract_unsigned_integer (buf
, 4, byte_order
));
1947 /* Simulate CALL0: write RA into A0 register. */
1948 regcache_cooked_write_unsigned
1949 (regcache
, gdbarch_tdep (gdbarch
)->a0_base
, bp_addr
);
1952 /* Set new stack pointer and return it. */
1953 regcache_cooked_write_unsigned (regcache
,
1954 gdbarch_tdep (gdbarch
)->a0_base
+ 1, sp
);
1955 /* Make dummy frame ID unique by adding a constant. */
1956 return sp
+ SP_ALIGNMENT
;
1959 /* Implement the breakpoint_kind_from_pc gdbarch method. */
1962 xtensa_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
1964 if (gdbarch_tdep (gdbarch
)->isa_use_density_instructions
)
1970 /* Return a breakpoint for the current location of PC. We always use
1971 the density version if we have density instructions (regardless of the
1972 current instruction at PC), and use regular instructions otherwise. */
1974 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1975 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1976 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1977 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1979 /* Implement the sw_breakpoint_from_kind gdbarch method. */
1981 static const gdb_byte
*
1982 xtensa_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
1988 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
1989 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
1991 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1992 return big_breakpoint
;
1994 return little_breakpoint
;
1998 static unsigned char density_big_breakpoint
[] = DENSITY_BIG_BREAKPOINT
;
1999 static unsigned char density_little_breakpoint
[]
2000 = DENSITY_LITTLE_BREAKPOINT
;
2002 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2003 return density_big_breakpoint
;
2005 return density_little_breakpoint
;
2009 /* Call0 ABI support routines. */
2011 /* Return true, if PC points to "ret" or "ret.n". */
2014 call0_ret (CORE_ADDR start_pc
, CORE_ADDR finish_pc
)
2016 #define RETURN_RET goto done
2018 xtensa_insnbuf ins
, slot
;
2019 gdb_byte ibuf
[XTENSA_ISA_BSZ
];
2020 CORE_ADDR ia
, bt
, ba
;
2022 int ilen
, islots
, is
;
2024 const char *opcname
;
2027 isa
= xtensa_default_isa
;
2028 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2029 ins
= xtensa_insnbuf_alloc (isa
);
2030 slot
= xtensa_insnbuf_alloc (isa
);
2033 for (ia
= start_pc
, bt
= ia
; ia
< finish_pc
; ia
+= ilen
)
2035 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2038 bt
= (ba
+ XTENSA_ISA_BSZ
) < finish_pc
2039 ? ba
+ XTENSA_ISA_BSZ
: finish_pc
;
2040 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0 )
2044 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2045 ifmt
= xtensa_format_decode (isa
, ins
);
2046 if (ifmt
== XTENSA_UNDEFINED
)
2048 ilen
= xtensa_format_length (isa
, ifmt
);
2049 if (ilen
== XTENSA_UNDEFINED
)
2051 islots
= xtensa_format_num_slots (isa
, ifmt
);
2052 if (islots
== XTENSA_UNDEFINED
)
2055 for (is
= 0; is
< islots
; ++is
)
2057 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
2060 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2061 if (opc
== XTENSA_UNDEFINED
)
2064 opcname
= xtensa_opcode_name (isa
, opc
);
2066 if ((strcasecmp (opcname
, "ret.n") == 0)
2067 || (strcasecmp (opcname
, "ret") == 0))
2075 xtensa_insnbuf_free(isa
, slot
);
2076 xtensa_insnbuf_free(isa
, ins
);
2080 /* Call0 opcode class. Opcodes are preclassified according to what they
2081 mean for Call0 prologue analysis, and their number of significant operands.
2082 The purpose of this is to simplify prologue analysis by separating
2083 instruction decoding (libisa) from the semantics of prologue analysis. */
2087 c0opc_illegal
, /* Unknown to libisa (invalid) or 'ill' opcode. */
2088 c0opc_uninteresting
, /* Not interesting for Call0 prologue analysis. */
2089 c0opc_flow
, /* Flow control insn. */
2090 c0opc_entry
, /* ENTRY indicates non-Call0 prologue. */
2091 c0opc_break
, /* Debugger software breakpoints. */
2092 c0opc_add
, /* Adding two registers. */
2093 c0opc_addi
, /* Adding a register and an immediate. */
2094 c0opc_and
, /* Bitwise "and"-ing two registers. */
2095 c0opc_sub
, /* Subtracting a register from a register. */
2096 c0opc_mov
, /* Moving a register to a register. */
2097 c0opc_movi
, /* Moving an immediate to a register. */
2098 c0opc_l32r
, /* Loading a literal. */
2099 c0opc_s32i
, /* Storing word at fixed offset from a base register. */
2100 c0opc_rwxsr
, /* RSR, WRS, or XSR instructions. */
2101 c0opc_l32e
, /* L32E instruction. */
2102 c0opc_s32e
, /* S32E instruction. */
2103 c0opc_rfwo
, /* RFWO instruction. */
2104 c0opc_rfwu
, /* RFWU instruction. */
2105 c0opc_NrOf
/* Number of opcode classifications. */
2108 /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
2111 rwx_special_register (const char *opcname
)
2113 char ch
= *opcname
++;
2115 if ((ch
!= 'r') && (ch
!= 'w') && (ch
!= 'x'))
2117 if (*opcname
++ != 's')
2119 if (*opcname
++ != 'r')
2121 if (*opcname
++ != '.')
2127 /* Classify an opcode based on what it means for Call0 prologue analysis. */
2129 static xtensa_insn_kind
2130 call0_classify_opcode (xtensa_isa isa
, xtensa_opcode opc
)
2132 const char *opcname
;
2133 xtensa_insn_kind opclass
= c0opc_uninteresting
;
2135 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc
);
2137 /* Get opcode name and handle special classifications. */
2139 opcname
= xtensa_opcode_name (isa
, opc
);
2142 || strcasecmp (opcname
, "ill") == 0
2143 || strcasecmp (opcname
, "ill.n") == 0)
2144 opclass
= c0opc_illegal
;
2145 else if (strcasecmp (opcname
, "break") == 0
2146 || strcasecmp (opcname
, "break.n") == 0)
2147 opclass
= c0opc_break
;
2148 else if (strcasecmp (opcname
, "entry") == 0)
2149 opclass
= c0opc_entry
;
2150 else if (strcasecmp (opcname
, "rfwo") == 0)
2151 opclass
= c0opc_rfwo
;
2152 else if (strcasecmp (opcname
, "rfwu") == 0)
2153 opclass
= c0opc_rfwu
;
2154 else if (xtensa_opcode_is_branch (isa
, opc
) > 0
2155 || xtensa_opcode_is_jump (isa
, opc
) > 0
2156 || xtensa_opcode_is_loop (isa
, opc
) > 0
2157 || xtensa_opcode_is_call (isa
, opc
) > 0
2158 || strcasecmp (opcname
, "simcall") == 0
2159 || strcasecmp (opcname
, "syscall") == 0)
2160 opclass
= c0opc_flow
;
2162 /* Also, classify specific opcodes that need to be tracked. */
2163 else if (strcasecmp (opcname
, "add") == 0
2164 || strcasecmp (opcname
, "add.n") == 0)
2165 opclass
= c0opc_add
;
2166 else if (strcasecmp (opcname
, "and") == 0)
2167 opclass
= c0opc_and
;
2168 else if (strcasecmp (opcname
, "addi") == 0
2169 || strcasecmp (opcname
, "addi.n") == 0
2170 || strcasecmp (opcname
, "addmi") == 0)
2171 opclass
= c0opc_addi
;
2172 else if (strcasecmp (opcname
, "sub") == 0)
2173 opclass
= c0opc_sub
;
2174 else if (strcasecmp (opcname
, "mov.n") == 0
2175 || strcasecmp (opcname
, "or") == 0) /* Could be 'mov' asm macro. */
2176 opclass
= c0opc_mov
;
2177 else if (strcasecmp (opcname
, "movi") == 0
2178 || strcasecmp (opcname
, "movi.n") == 0)
2179 opclass
= c0opc_movi
;
2180 else if (strcasecmp (opcname
, "l32r") == 0)
2181 opclass
= c0opc_l32r
;
2182 else if (strcasecmp (opcname
, "s32i") == 0
2183 || strcasecmp (opcname
, "s32i.n") == 0)
2184 opclass
= c0opc_s32i
;
2185 else if (strcasecmp (opcname
, "l32e") == 0)
2186 opclass
= c0opc_l32e
;
2187 else if (strcasecmp (opcname
, "s32e") == 0)
2188 opclass
= c0opc_s32e
;
2189 else if (rwx_special_register (opcname
))
2190 opclass
= c0opc_rwxsr
;
2195 /* Tracks register movement/mutation for a given operation, which may
2196 be within a bundle. Updates the destination register tracking info
2197 accordingly. The pc is needed only for pc-relative load instructions
2198 (eg. l32r). The SP register number is needed to identify stores to
2199 the stack frame. Returns 0, if analysis was succesfull, non-zero
2203 call0_track_op (struct gdbarch
*gdbarch
, xtensa_c0reg_t dst
[], xtensa_c0reg_t src
[],
2204 xtensa_insn_kind opclass
, int nods
, unsigned odv
[],
2205 CORE_ADDR pc
, int spreg
, xtensa_frame_cache_t
*cache
)
2207 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2208 unsigned litbase
, litaddr
, litval
;
2213 /* 3 operands: dst, src, imm. */
2214 gdb_assert (nods
== 3);
2215 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2216 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ odv
[2];
2219 /* 3 operands: dst, src1, src2. */
2220 gdb_assert (nods
== 3);
2221 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2223 dst
[odv
[0]].fr_reg
= src
[odv
[2]].fr_reg
;
2224 dst
[odv
[0]].fr_ofs
= src
[odv
[2]].fr_ofs
+ src
[odv
[1]].fr_ofs
;
2226 else if (src
[odv
[2]].fr_reg
== C0_CONST
)
2228 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2229 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ src
[odv
[2]].fr_ofs
;
2231 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2234 /* 3 operands: dst, src1, src2. */
2235 gdb_assert (nods
== 3);
2236 if (cache
->c0
.c0_fpalign
== 0)
2238 /* Handle dynamic stack alignment. */
2239 if ((src
[odv
[0]].fr_reg
== spreg
) && (src
[odv
[1]].fr_reg
== spreg
))
2241 if (src
[odv
[2]].fr_reg
== C0_CONST
)
2242 cache
->c0
.c0_fpalign
= src
[odv
[2]].fr_ofs
;
2245 else if ((src
[odv
[0]].fr_reg
== spreg
)
2246 && (src
[odv
[2]].fr_reg
== spreg
))
2248 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2249 cache
->c0
.c0_fpalign
= src
[odv
[1]].fr_ofs
;
2252 /* else fall through. */
2254 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2256 dst
[odv
[0]].fr_reg
= src
[odv
[2]].fr_reg
;
2257 dst
[odv
[0]].fr_ofs
= src
[odv
[2]].fr_ofs
& src
[odv
[1]].fr_ofs
;
2259 else if (src
[odv
[2]].fr_reg
== C0_CONST
)
2261 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2262 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
& src
[odv
[2]].fr_ofs
;
2264 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2267 /* 3 operands: dst, src1, src2. */
2268 gdb_assert (nods
== 3);
2269 if (src
[odv
[2]].fr_reg
== C0_CONST
)
2271 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2272 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
- src
[odv
[2]].fr_ofs
;
2274 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2277 /* 2 operands: dst, src [, src]. */
2278 gdb_assert (nods
== 2);
2279 /* First, check if it's a special case of saving unaligned SP
2280 to a spare register in case of dynamic stack adjustment.
2281 But, only do it one time. The second time could be initializing
2282 frame pointer. We don't want to overwrite the first one. */
2283 if ((odv
[1] == spreg
) && (cache
->c0
.c0_old_sp
== C0_INEXP
))
2284 cache
->c0
.c0_old_sp
= odv
[0];
2286 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2287 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
;
2290 /* 2 operands: dst, imm. */
2291 gdb_assert (nods
== 2);
2292 dst
[odv
[0]].fr_reg
= C0_CONST
;
2293 dst
[odv
[0]].fr_ofs
= odv
[1];
2296 /* 2 operands: dst, literal offset. */
2297 gdb_assert (nods
== 2);
2298 /* litbase = xtensa_get_litbase (pc); can be also used. */
2299 litbase
= (gdbarch_tdep (gdbarch
)->litbase_regnum
== -1)
2300 ? 0 : xtensa_read_register
2301 (gdbarch_tdep (gdbarch
)->litbase_regnum
);
2302 litaddr
= litbase
& 1
2303 ? (litbase
& ~1) + (signed)odv
[1]
2304 : (pc
+ 3 + (signed)odv
[1]) & ~3;
2305 litval
= read_memory_integer (litaddr
, 4, byte_order
);
2306 dst
[odv
[0]].fr_reg
= C0_CONST
;
2307 dst
[odv
[0]].fr_ofs
= litval
;
2310 /* 3 operands: value, base, offset. */
2311 gdb_assert (nods
== 3 && spreg
>= 0 && spreg
< C0_NREGS
);
2312 /* First, check if it's a spill for saved unaligned SP,
2313 when dynamic stack adjustment was applied to this frame. */
2314 if ((cache
->c0
.c0_fpalign
!= 0) /* Dynamic stack adjustment. */
2315 && (odv
[1] == spreg
) /* SP usage indicates spill. */
2316 && (odv
[0] == cache
->c0
.c0_old_sp
)) /* Old SP register spilled. */
2317 cache
->c0
.c0_sp_ofs
= odv
[2];
2319 if (src
[odv
[1]].fr_reg
== spreg
/* Store to stack frame. */
2320 && (src
[odv
[1]].fr_ofs
& 3) == 0 /* Alignment preserved. */
2321 && src
[odv
[0]].fr_reg
>= 0 /* Value is from a register. */
2322 && src
[odv
[0]].fr_ofs
== 0 /* Value hasn't been modified. */
2323 && src
[src
[odv
[0]].fr_reg
].to_stk
== C0_NOSTK
) /* First time. */
2325 /* ISA encoding guarantees alignment. But, check it anyway. */
2326 gdb_assert ((odv
[2] & 3) == 0);
2327 dst
[src
[odv
[0]].fr_reg
].to_stk
= src
[odv
[1]].fr_ofs
+ odv
[2];
2330 /* If we end up inside Window Overflow / Underflow interrupt handler
2331 report an error because these handlers should have been handled
2332 already in a different way. */
2344 /* Analyze prologue of the function at start address to determine if it uses
2345 the Call0 ABI, and if so track register moves and linear modifications
2346 in the prologue up to the PC or just beyond the prologue, whichever is
2347 first. An 'entry' instruction indicates non-Call0 ABI and the end of the
2348 prologue. The prologue may overlap non-prologue instructions but is
2349 guaranteed to end by the first flow-control instruction (jump, branch,
2350 call or return). Since an optimized function may move information around
2351 and change the stack frame arbitrarily during the prologue, the information
2352 is guaranteed valid only at the point in the function indicated by the PC.
2353 May be used to skip the prologue or identify the ABI, w/o tracking.
2355 Returns: Address of first instruction after prologue, or PC (whichever
2356 is first), or 0, if decoding failed (in libisa).
2358 start Start address of function/prologue.
2359 pc Program counter to stop at. Use 0 to continue to end of prologue.
2360 If 0, avoids infinite run-on in corrupt code memory by bounding
2361 the scan to the end of the function if that can be determined.
2362 nregs Number of general registers to track.
2364 cache Xtensa frame cache.
2366 Note that these may produce useful results even if decoding fails
2367 because they begin with default assumptions that analysis may change. */
2370 call0_analyze_prologue (struct gdbarch
*gdbarch
,
2371 CORE_ADDR start
, CORE_ADDR pc
,
2372 int nregs
, xtensa_frame_cache_t
*cache
)
2374 CORE_ADDR ia
; /* Current insn address in prologue. */
2375 CORE_ADDR ba
= 0; /* Current address at base of insn buffer. */
2376 CORE_ADDR bt
; /* Current address at top+1 of insn buffer. */
2377 gdb_byte ibuf
[XTENSA_ISA_BSZ
];/* Instruction buffer for decoding prologue. */
2378 xtensa_isa isa
; /* libisa ISA handle. */
2379 xtensa_insnbuf ins
, slot
; /* libisa handle to decoded insn, slot. */
2380 xtensa_format ifmt
; /* libisa instruction format. */
2381 int ilen
, islots
, is
; /* Instruction length, nbr slots, current slot. */
2382 xtensa_opcode opc
; /* Opcode in current slot. */
2383 xtensa_insn_kind opclass
; /* Opcode class for Call0 prologue analysis. */
2384 int nods
; /* Opcode number of operands. */
2385 unsigned odv
[C0_MAXOPDS
]; /* Operand values in order provided by libisa. */
2386 xtensa_c0reg_t
*rtmp
; /* Register tracking info snapshot. */
2387 int j
; /* General loop counter. */
2388 int fail
= 0; /* Set non-zero and exit, if decoding fails. */
2389 CORE_ADDR body_pc
; /* The PC for the first non-prologue insn. */
2390 CORE_ADDR end_pc
; /* The PC for the lust function insn. */
2392 struct symtab_and_line prologue_sal
;
2394 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2395 (int)start
, (int)pc
);
2397 /* Try to limit the scan to the end of the function if a non-zero pc
2398 arg was not supplied to avoid probing beyond the end of valid memory.
2399 If memory is full of garbage that classifies as c0opc_uninteresting.
2400 If this fails (eg. if no symbols) pc ends up 0 as it was.
2401 Initialize the Call0 frame and register tracking info.
2402 Assume it's Call0 until an 'entry' instruction is encountered.
2403 Assume we may be in the prologue until we hit a flow control instr. */
2409 /* Find out, if we have an information about the prologue from DWARF. */
2410 prologue_sal
= find_pc_line (start
, 0);
2411 if (prologue_sal
.line
!= 0) /* Found debug info. */
2412 body_pc
= prologue_sal
.end
;
2414 /* If we are going to analyze the prologue in general without knowing about
2415 the current PC, make the best assumtion for the end of the prologue. */
2418 find_pc_partial_function (start
, 0, NULL
, &end_pc
);
2419 body_pc
= std::min (end_pc
, body_pc
);
2422 body_pc
= std::min (pc
, body_pc
);
2425 rtmp
= (xtensa_c0reg_t
*) alloca(nregs
* sizeof(xtensa_c0reg_t
));
2427 isa
= xtensa_default_isa
;
2428 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2429 ins
= xtensa_insnbuf_alloc (isa
);
2430 slot
= xtensa_insnbuf_alloc (isa
);
2432 for (ia
= start
, bt
= ia
; ia
< body_pc
; ia
+= ilen
)
2434 /* (Re)fill instruction buffer from memory if necessary, but do not
2435 read memory beyond PC to be sure we stay within text section
2436 (this protection only works if a non-zero pc is supplied). */
2438 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2441 bt
= (ba
+ XTENSA_ISA_BSZ
) < body_pc
? ba
+ XTENSA_ISA_BSZ
: body_pc
;
2442 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0 )
2443 error (_("Unable to read target memory ..."));
2446 /* Decode format information. */
2448 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2449 ifmt
= xtensa_format_decode (isa
, ins
);
2450 if (ifmt
== XTENSA_UNDEFINED
)
2455 ilen
= xtensa_format_length (isa
, ifmt
);
2456 if (ilen
== XTENSA_UNDEFINED
)
2461 islots
= xtensa_format_num_slots (isa
, ifmt
);
2462 if (islots
== XTENSA_UNDEFINED
)
2468 /* Analyze a bundle or a single instruction, using a snapshot of
2469 the register tracking info as input for the entire bundle so that
2470 register changes do not take effect within this bundle. */
2472 for (j
= 0; j
< nregs
; ++j
)
2473 rtmp
[j
] = cache
->c0
.c0_rt
[j
];
2475 for (is
= 0; is
< islots
; ++is
)
2477 /* Decode a slot and classify the opcode. */
2479 fail
= xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
);
2483 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2484 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2486 if (opc
== XTENSA_UNDEFINED
)
2487 opclass
= c0opc_illegal
;
2489 opclass
= call0_classify_opcode (isa
, opc
);
2491 /* Decide whether to track this opcode, ignore it, or bail out. */
2500 case c0opc_uninteresting
:
2503 case c0opc_flow
: /* Flow control instructions stop analysis. */
2504 case c0opc_rwxsr
: /* RSR, WSR, XSR instructions stop analysis. */
2509 ia
+= ilen
; /* Skip over 'entry' insn. */
2516 /* Only expected opcodes should get this far. */
2518 /* Extract and decode the operands. */
2519 nods
= xtensa_opcode_num_operands (isa
, opc
);
2520 if (nods
== XTENSA_UNDEFINED
)
2526 for (j
= 0; j
< nods
&& j
< C0_MAXOPDS
; ++j
)
2528 fail
= xtensa_operand_get_field (isa
, opc
, j
, ifmt
,
2533 fail
= xtensa_operand_decode (isa
, opc
, j
, &odv
[j
]);
2538 /* Check operands to verify use of 'mov' assembler macro. */
2539 if (opclass
== c0opc_mov
&& nods
== 3)
2541 if (odv
[2] == odv
[1])
2544 if ((odv
[0] == 1) && (odv
[1] != 1))
2545 /* OR A1, An, An , where n != 1.
2546 This means we are inside epilogue already. */
2551 opclass
= c0opc_uninteresting
;
2556 /* Track register movement and modification for this operation. */
2557 fail
= call0_track_op (gdbarch
, cache
->c0
.c0_rt
, rtmp
,
2558 opclass
, nods
, odv
, ia
, 1, cache
);
2564 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2565 (unsigned)ia
, fail
? "failed" : "succeeded");
2566 xtensa_insnbuf_free(isa
, slot
);
2567 xtensa_insnbuf_free(isa
, ins
);
2568 return fail
? XTENSA_ISA_BADPC
: ia
;
2571 /* Initialize frame cache for the current frame in CALL0 ABI. */
2574 call0_frame_cache (struct frame_info
*this_frame
,
2575 xtensa_frame_cache_t
*cache
, CORE_ADDR pc
)
2577 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2578 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2579 CORE_ADDR start_pc
; /* The beginning of the function. */
2580 CORE_ADDR body_pc
=UINT_MAX
; /* PC, where prologue analysis stopped. */
2581 CORE_ADDR sp
, fp
, ra
;
2582 int fp_regnum
= C0_SP
, c0_hasfp
= 0, c0_frmsz
= 0, prev_sp
= 0, to_stk
;
2584 sp
= get_frame_register_unsigned
2585 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
2586 fp
= sp
; /* Assume FP == SP until proven otherwise. */
2588 /* Find the beginning of the prologue of the function containing the PC
2589 and analyze it up to the PC or the end of the prologue. */
2591 if (find_pc_partial_function (pc
, NULL
, &start_pc
, NULL
))
2593 body_pc
= call0_analyze_prologue (gdbarch
, start_pc
, pc
, C0_NREGS
, cache
);
2595 if (body_pc
== XTENSA_ISA_BADPC
)
2599 goto finish_frame_analysis
;
2603 /* Get the frame information and FP (if used) at the current PC.
2604 If PC is in the prologue, the prologue analysis is more reliable
2605 than DWARF info. We don't not know for sure, if PC is in the prologue,
2606 but we do know no calls have yet taken place, so we can almost
2607 certainly rely on the prologue analysis. */
2611 /* Prologue analysis was successful up to the PC.
2612 It includes the cases when PC == START_PC. */
2613 c0_hasfp
= cache
->c0
.c0_rt
[C0_FP
].fr_reg
== C0_SP
;
2614 /* c0_hasfp == true means there is a frame pointer because
2615 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2616 was derived from SP. Otherwise, it would be C0_FP. */
2617 fp_regnum
= c0_hasfp
? C0_FP
: C0_SP
;
2618 c0_frmsz
= - cache
->c0
.c0_rt
[fp_regnum
].fr_ofs
;
2619 fp_regnum
+= gdbarch_tdep (gdbarch
)->a0_base
;
2621 else /* No data from the prologue analysis. */
2624 fp_regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_SP
;
2629 if (cache
->c0
.c0_fpalign
)
2631 /* This frame has a special prologue with a dynamic stack adjustment
2632 to force an alignment, which is bigger than standard 16 bytes. */
2634 CORE_ADDR unaligned_sp
;
2636 if (cache
->c0
.c0_old_sp
== C0_INEXP
)
2637 /* This can't be. Prologue code should be consistent.
2638 Unaligned stack pointer should be saved in a spare register. */
2642 goto finish_frame_analysis
;
2645 if (cache
->c0
.c0_sp_ofs
== C0_NOSTK
)
2646 /* Saved unaligned value of SP is kept in a register. */
2647 unaligned_sp
= get_frame_register_unsigned
2648 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ cache
->c0
.c0_old_sp
);
2650 /* Get the value from stack. */
2651 unaligned_sp
= (CORE_ADDR
)
2652 read_memory_integer (fp
+ cache
->c0
.c0_sp_ofs
, 4, byte_order
);
2654 prev_sp
= unaligned_sp
+ c0_frmsz
;
2657 prev_sp
= fp
+ c0_frmsz
;
2659 /* Frame size from debug info or prologue tracking does not account for
2660 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2663 fp
= get_frame_register_unsigned (this_frame
, fp_regnum
);
2665 /* Update the stack frame size. */
2666 c0_frmsz
+= fp
- sp
;
2669 /* Get the return address (RA) from the stack if saved,
2670 or try to get it from a register. */
2672 to_stk
= cache
->c0
.c0_rt
[C0_RA
].to_stk
;
2673 if (to_stk
!= C0_NOSTK
)
2675 read_memory_integer (sp
+ c0_frmsz
+ cache
->c0
.c0_rt
[C0_RA
].to_stk
,
2678 else if (cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_CONST
2679 && cache
->c0
.c0_rt
[C0_RA
].fr_ofs
== 0)
2681 /* Special case for terminating backtrace at a function that wants to
2682 be seen as the outermost one. Such a function will clear it's RA (A0)
2683 register to 0 in the prologue instead of saving its original value. */
2688 /* RA was copied to another register or (before any function call) may
2689 still be in the original RA register. This is not always reliable:
2690 even in a leaf function, register tracking stops after prologue, and
2691 even in prologue, non-prologue instructions (not tracked) may overwrite
2692 RA or any register it was copied to. If likely in prologue or before
2693 any call, use retracking info and hope for the best (compiler should
2694 have saved RA in stack if not in a leaf function). If not in prologue,
2700 && (i
== C0_RA
|| cache
->c0
.c0_rt
[i
].fr_reg
!= C0_RA
);
2702 if (i
>= C0_NREGS
&& cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_RA
)
2706 ra
= get_frame_register_unsigned
2708 gdbarch_tdep (gdbarch
)->a0_base
+ cache
->c0
.c0_rt
[i
].fr_reg
);
2713 finish_frame_analysis
:
2714 cache
->pc
= start_pc
;
2716 /* RA == 0 marks the outermost frame. Do not go past it. */
2717 cache
->prev_sp
= (ra
!= 0) ? prev_sp
: 0;
2718 cache
->c0
.fp_regnum
= fp_regnum
;
2719 cache
->c0
.c0_frmsz
= c0_frmsz
;
2720 cache
->c0
.c0_hasfp
= c0_hasfp
;
2721 cache
->c0
.c0_fp
= fp
;
2724 static CORE_ADDR a0_saved
;
2725 static CORE_ADDR a7_saved
;
2726 static CORE_ADDR a11_saved
;
2727 static int a0_was_saved
;
2728 static int a7_was_saved
;
2729 static int a11_was_saved
;
2731 /* Simulate L32E instruction: AT <-- ref (AS + offset). */
2733 execute_l32e (struct gdbarch
*gdbarch
, int at
, int as
, int offset
, CORE_ADDR wb
)
2735 int atreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ at
, wb
);
2736 int asreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ as
, wb
);
2737 CORE_ADDR addr
= xtensa_read_register (asreg
) + offset
;
2738 unsigned int spilled_value
2739 = read_memory_unsigned_integer (addr
, 4, gdbarch_byte_order (gdbarch
));
2741 if ((at
== 0) && !a0_was_saved
)
2743 a0_saved
= xtensa_read_register (atreg
);
2746 else if ((at
== 7) && !a7_was_saved
)
2748 a7_saved
= xtensa_read_register (atreg
);
2751 else if ((at
== 11) && !a11_was_saved
)
2753 a11_saved
= xtensa_read_register (atreg
);
2757 xtensa_write_register (atreg
, spilled_value
);
2760 /* Simulate S32E instruction: AT --> ref (AS + offset). */
2762 execute_s32e (struct gdbarch
*gdbarch
, int at
, int as
, int offset
, CORE_ADDR wb
)
2764 int atreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ at
, wb
);
2765 int asreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ as
, wb
);
2766 CORE_ADDR addr
= xtensa_read_register (asreg
) + offset
;
2767 ULONGEST spilled_value
= xtensa_read_register (atreg
);
2769 write_memory_unsigned_integer (addr
, 4,
2770 gdbarch_byte_order (gdbarch
),
2774 #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2780 xtNoExceptionHandler
2781 } xtensa_exception_handler_t
;
2783 /* Execute instruction stream from current PC until hitting RFWU or RFWO.
2784 Return type of Xtensa Window Interrupt Handler on success. */
2785 static xtensa_exception_handler_t
2786 execute_code (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
, CORE_ADDR wb
)
2789 xtensa_insnbuf ins
, slot
;
2790 gdb_byte ibuf
[XTENSA_ISA_BSZ
];
2791 CORE_ADDR ia
, bt
, ba
;
2793 int ilen
, islots
, is
;
2796 void (*func
) (struct gdbarch
*, int, int, int, CORE_ADDR
);
2798 uint32_t at
, as
, offset
;
2800 /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
2801 int WindowUnderflow12
= (current_pc
& 0x1ff) >= 0x140;
2803 isa
= xtensa_default_isa
;
2804 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2805 ins
= xtensa_insnbuf_alloc (isa
);
2806 slot
= xtensa_insnbuf_alloc (isa
);
2815 while (insn_num
++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN
)
2817 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2820 bt
= (ba
+ XTENSA_ISA_BSZ
);
2821 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0)
2822 return xtNoExceptionHandler
;
2824 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2825 ifmt
= xtensa_format_decode (isa
, ins
);
2826 if (ifmt
== XTENSA_UNDEFINED
)
2827 return xtNoExceptionHandler
;
2828 ilen
= xtensa_format_length (isa
, ifmt
);
2829 if (ilen
== XTENSA_UNDEFINED
)
2830 return xtNoExceptionHandler
;
2831 islots
= xtensa_format_num_slots (isa
, ifmt
);
2832 if (islots
== XTENSA_UNDEFINED
)
2833 return xtNoExceptionHandler
;
2834 for (is
= 0; is
< islots
; ++is
)
2836 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
2837 return xtNoExceptionHandler
;
2838 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2839 if (opc
== XTENSA_UNDEFINED
)
2840 return xtNoExceptionHandler
;
2841 switch (call0_classify_opcode (isa
, opc
))
2847 /* We expect none of them here. */
2848 return xtNoExceptionHandler
;
2850 func
= execute_l32e
;
2853 func
= execute_s32e
;
2855 case c0opc_rfwo
: /* RFWO. */
2856 /* Here, we return from WindowOverflow handler and,
2857 if we stopped at the very beginning, which means
2858 A0 was saved, we have to restore it now. */
2861 int arreg
= arreg_number (gdbarch
,
2862 gdbarch_tdep (gdbarch
)->a0_base
,
2864 xtensa_write_register (arreg
, a0_saved
);
2866 return xtWindowOverflow
;
2867 case c0opc_rfwu
: /* RFWU. */
2868 /* Here, we return from WindowUnderflow handler.
2869 Let's see if either A7 or A11 has to be restored. */
2870 if (WindowUnderflow12
)
2874 int arreg
= arreg_number (gdbarch
,
2875 gdbarch_tdep (gdbarch
)->a0_base
+ 11,
2877 xtensa_write_register (arreg
, a11_saved
);
2880 else if (a7_was_saved
)
2882 int arreg
= arreg_number (gdbarch
,
2883 gdbarch_tdep (gdbarch
)->a0_base
+ 7,
2885 xtensa_write_register (arreg
, a7_saved
);
2887 return xtWindowUnderflow
;
2888 default: /* Simply skip this insns. */
2892 /* Decode arguments for L32E / S32E and simulate their execution. */
2893 if ( xtensa_opcode_num_operands (isa
, opc
) != 3 )
2894 return xtNoExceptionHandler
;
2895 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
, &at
))
2896 return xtNoExceptionHandler
;
2897 if (xtensa_operand_decode (isa
, opc
, 0, &at
))
2898 return xtNoExceptionHandler
;
2899 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
, is
, slot
, &as
))
2900 return xtNoExceptionHandler
;
2901 if (xtensa_operand_decode (isa
, opc
, 1, &as
))
2902 return xtNoExceptionHandler
;
2903 if (xtensa_operand_get_field (isa
, opc
, 2, ifmt
, is
, slot
, &offset
))
2904 return xtNoExceptionHandler
;
2905 if (xtensa_operand_decode (isa
, opc
, 2, &offset
))
2906 return xtNoExceptionHandler
;
2908 (*func
) (gdbarch
, at
, as
, offset
, wb
);
2913 return xtNoExceptionHandler
;
2916 /* Handle Window Overflow / Underflow exception frames. */
2919 xtensa_window_interrupt_frame_cache (struct frame_info
*this_frame
,
2920 xtensa_frame_cache_t
*cache
,
2923 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2924 CORE_ADDR ps
, wb
, ws
, ra
;
2925 int epc1_regnum
, i
, regnum
;
2926 xtensa_exception_handler_t eh_type
;
2928 /* Read PS, WB, and WS from the hardware. Note that PS register
2929 must be present, if Windowed ABI is supported. */
2930 ps
= xtensa_read_register (gdbarch_ps_regnum (gdbarch
));
2931 wb
= xtensa_read_register (gdbarch_tdep (gdbarch
)->wb_regnum
);
2932 ws
= xtensa_read_register (gdbarch_tdep (gdbarch
)->ws_regnum
);
2934 /* Execute all the remaining instructions from Window Interrupt Handler
2935 by simulating them on the remote protocol level. On return, set the
2936 type of Xtensa Window Interrupt Handler, or report an error. */
2937 eh_type
= execute_code (gdbarch
, pc
, wb
);
2938 if (eh_type
== xtNoExceptionHandler
)
2940 Unable to decode Xtensa Window Interrupt Handler's code."));
2942 cache
->ps
= ps
^ PS_EXC
; /* Clear the exception bit in PS. */
2943 cache
->call0
= 0; /* It's Windowed ABI. */
2945 /* All registers for the cached frame will be alive. */
2946 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
2947 cache
->wd
.aregs
[i
] = -1;
2949 if (eh_type
== xtWindowOverflow
)
2950 cache
->wd
.ws
= ws
^ (1 << wb
);
2951 else /* eh_type == xtWindowUnderflow. */
2952 cache
->wd
.ws
= ws
| (1 << wb
);
2954 cache
->wd
.wb
= (ps
& 0xf00) >> 8; /* Set WB to OWB. */
2955 regnum
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
,
2957 ra
= xtensa_read_register (regnum
);
2958 cache
->wd
.callsize
= WINSIZE (ra
);
2959 cache
->prev_sp
= xtensa_read_register (regnum
+ 1);
2960 /* Set regnum to a frame pointer of the frame being cached. */
2961 regnum
= xtensa_scan_prologue (gdbarch
, pc
);
2962 regnum
= arreg_number (gdbarch
,
2963 gdbarch_tdep (gdbarch
)->a0_base
+ regnum
,
2965 cache
->base
= get_frame_register_unsigned (this_frame
, regnum
);
2967 /* Read PC of interrupted function from EPC1 register. */
2968 epc1_regnum
= xtensa_find_register_by_name (gdbarch
,"epc1");
2969 if (epc1_regnum
< 0)
2970 error(_("Unable to read Xtensa register EPC1"));
2971 cache
->ra
= xtensa_read_register (epc1_regnum
);
2972 cache
->pc
= get_frame_func (this_frame
);
2976 /* Skip function prologue.
2978 Return the pc of the first instruction after prologue. GDB calls this to
2979 find the address of the first line of the function or (if there is no line
2980 number information) to skip the prologue for planting breakpoints on
2981 function entries. Use debug info (if present) or prologue analysis to skip
2982 the prologue to achieve reliable debugging behavior. For windowed ABI,
2983 only the 'entry' instruction is skipped. It is not strictly necessary to
2984 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2985 backtrace at any point in the prologue, however certain potential hazards
2986 are avoided and a more "normal" debugging experience is ensured by
2987 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2988 For example, if we don't skip the prologue:
2989 - Some args may not yet have been saved to the stack where the debug
2990 info expects to find them (true anyway when only 'entry' is skipped);
2991 - Software breakpoints ('break' instrs) may not have been unplanted
2992 when the prologue analysis is done on initializing the frame cache,
2993 and breaks in the prologue will throw off the analysis.
2995 If we have debug info ( line-number info, in particular ) we simply skip
2996 the code associated with the first function line effectively skipping
2997 the prologue code. It works even in cases like
3000 { int local_var = 1;
3004 because, for this source code, both Xtensa compilers will generate two
3005 separate entries ( with the same line number ) in dwarf line-number
3006 section to make sure there is a boundary between the prologue code and
3007 the rest of the function.
3009 If there is no debug info, we need to analyze the code. */
3011 /* #define DONT_SKIP_PROLOGUE */
3014 xtensa_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
3016 struct symtab_and_line prologue_sal
;
3019 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc
);
3021 #if DONT_SKIP_PROLOGUE
3025 /* Try to find first body line from debug info. */
3027 prologue_sal
= find_pc_line (start_pc
, 0);
3028 if (prologue_sal
.line
!= 0) /* Found debug info. */
3030 /* In Call0, it is possible to have a function with only one instruction
3031 ('ret') resulting from a one-line optimized function that does nothing.
3032 In that case, prologue_sal.end may actually point to the start of the
3033 next function in the text section, causing a breakpoint to be set at
3034 the wrong place. Check, if the end address is within a different
3035 function, and if so return the start PC. We know we have symbol
3040 if ((gdbarch_tdep (gdbarch
)->call_abi
== CallAbiCall0Only
)
3041 && call0_ret (start_pc
, prologue_sal
.end
))
3044 find_pc_partial_function (prologue_sal
.end
, NULL
, &end_func
, NULL
);
3045 if (end_func
!= start_pc
)
3048 return prologue_sal
.end
;
3051 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
3052 body_pc
= call0_analyze_prologue (gdbarch
, start_pc
, 0, 0,
3053 xtensa_alloc_frame_cache (0));
3054 return body_pc
!= 0 ? body_pc
: start_pc
;
3057 /* Verify the current configuration. */
3059 xtensa_verify_config (struct gdbarch
*gdbarch
)
3061 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3064 /* Verify that we got a reasonable number of AREGS. */
3065 if ((tdep
->num_aregs
& -tdep
->num_aregs
) != tdep
->num_aregs
)
3067 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
3070 /* Verify that certain registers exist. */
3072 if (tdep
->pc_regnum
== -1)
3073 log
.printf (_("\n\tpc_regnum: No PC register"));
3074 if (tdep
->isa_use_exceptions
&& tdep
->ps_regnum
== -1)
3075 log
.printf (_("\n\tps_regnum: No PS register"));
3077 if (tdep
->isa_use_windowed_registers
)
3079 if (tdep
->wb_regnum
== -1)
3080 log
.printf (_("\n\twb_regnum: No WB register"));
3081 if (tdep
->ws_regnum
== -1)
3082 log
.printf (_("\n\tws_regnum: No WS register"));
3083 if (tdep
->ar_base
== -1)
3084 log
.printf (_("\n\tar_base: No AR registers"));
3087 if (tdep
->a0_base
== -1)
3088 log
.printf (_("\n\ta0_base: No Ax registers"));
3091 internal_error (__FILE__
, __LINE__
,
3092 _("the following are invalid: %s"), log
.c_str ());
3096 /* Derive specific register numbers from the array of registers. */
3099 xtensa_derive_tdep (struct gdbarch_tdep
*tdep
)
3101 xtensa_register_t
* rmap
;
3102 int n
, max_size
= 4;
3105 tdep
->num_nopriv_regs
= 0;
3107 /* Special registers 0..255 (core). */
3108 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
3110 for (rmap
= tdep
->regmap
, n
= 0; rmap
->target_number
!= -1; n
++, rmap
++)
3112 if (rmap
->target_number
== 0x0020)
3113 tdep
->pc_regnum
= n
;
3114 else if (rmap
->target_number
== 0x0100)
3116 else if (rmap
->target_number
== 0x0000)
3118 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(72))
3119 tdep
->wb_regnum
= n
;
3120 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(73))
3121 tdep
->ws_regnum
= n
;
3122 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(233))
3123 tdep
->debugcause_regnum
= n
;
3124 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(232))
3125 tdep
->exccause_regnum
= n
;
3126 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(238))
3127 tdep
->excvaddr_regnum
= n
;
3128 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(0))
3129 tdep
->lbeg_regnum
= n
;
3130 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(1))
3131 tdep
->lend_regnum
= n
;
3132 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(2))
3133 tdep
->lcount_regnum
= n
;
3134 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(3))
3135 tdep
->sar_regnum
= n
;
3136 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(5))
3137 tdep
->litbase_regnum
= n
;
3138 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(230))
3139 tdep
->ps_regnum
= n
;
3141 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(226))
3142 tdep
->interrupt_regnum
= n
;
3143 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(227))
3144 tdep
->interrupt2_regnum
= n
;
3145 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(224))
3146 tdep
->cpenable_regnum
= n
;
3149 if (rmap
->byte_size
> max_size
)
3150 max_size
= rmap
->byte_size
;
3151 if (rmap
->mask
!= 0 && tdep
->num_regs
== 0)
3153 /* Find out out how to deal with priveleged registers.
3155 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3156 && tdep->num_nopriv_regs == 0)
3157 tdep->num_nopriv_regs = n;
3159 if ((rmap
->flags
& XTENSA_REGISTER_FLAGS_PRIVILEGED
) != 0
3160 && tdep
->num_regs
== 0)
3164 /* Number of pseudo registers. */
3165 tdep
->num_pseudo_regs
= n
- tdep
->num_regs
;
3167 /* Empirically determined maximum sizes. */
3168 tdep
->max_register_raw_size
= max_size
;
3169 tdep
->max_register_virtual_size
= max_size
;
3172 /* Module "constructor" function. */
3174 extern struct gdbarch_tdep xtensa_tdep
;
3176 static struct gdbarch
*
3177 xtensa_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3179 struct gdbarch_tdep
*tdep
;
3180 struct gdbarch
*gdbarch
;
3182 DEBUGTRACE ("gdbarch_init()\n");
3184 if (!xtensa_default_isa
)
3185 xtensa_default_isa
= xtensa_isa_init (0, 0);
3187 /* We have to set the byte order before we call gdbarch_alloc. */
3188 info
.byte_order
= XCHAL_HAVE_BE
? BFD_ENDIAN_BIG
: BFD_ENDIAN_LITTLE
;
3190 tdep
= &xtensa_tdep
;
3191 gdbarch
= gdbarch_alloc (&info
, tdep
);
3192 xtensa_derive_tdep (tdep
);
3194 /* Verify our configuration. */
3195 xtensa_verify_config (gdbarch
);
3196 xtensa_session_once_reported
= 0;
3198 /* Pseudo-Register read/write. */
3199 set_gdbarch_pseudo_register_read (gdbarch
, xtensa_pseudo_register_read
);
3200 set_gdbarch_pseudo_register_write (gdbarch
, xtensa_pseudo_register_write
);
3202 /* Set target information. */
3203 set_gdbarch_num_regs (gdbarch
, tdep
->num_regs
);
3204 set_gdbarch_num_pseudo_regs (gdbarch
, tdep
->num_pseudo_regs
);
3205 set_gdbarch_sp_regnum (gdbarch
, tdep
->a0_base
+ 1);
3206 set_gdbarch_pc_regnum (gdbarch
, tdep
->pc_regnum
);
3207 set_gdbarch_ps_regnum (gdbarch
, tdep
->ps_regnum
);
3209 /* Renumber registers for known formats (stabs and dwarf2). */
3210 set_gdbarch_stab_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
3211 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
3213 /* We provide our own function to get register information. */
3214 set_gdbarch_register_name (gdbarch
, xtensa_register_name
);
3215 set_gdbarch_register_type (gdbarch
, xtensa_register_type
);
3217 /* To call functions from GDB using dummy frame. */
3218 set_gdbarch_push_dummy_call (gdbarch
, xtensa_push_dummy_call
);
3220 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
3222 set_gdbarch_return_value (gdbarch
, xtensa_return_value
);
3224 /* Advance PC across any prologue instructions to reach "real" code. */
3225 set_gdbarch_skip_prologue (gdbarch
, xtensa_skip_prologue
);
3227 /* Stack grows downward. */
3228 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3230 /* Set breakpoints. */
3231 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
3232 xtensa_breakpoint_kind_from_pc
);
3233 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
3234 xtensa_sw_breakpoint_from_kind
);
3236 /* After breakpoint instruction or illegal instruction, pc still
3237 points at break instruction, so don't decrement. */
3238 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
3240 /* We don't skip args. */
3241 set_gdbarch_frame_args_skip (gdbarch
, 0);
3243 set_gdbarch_unwind_pc (gdbarch
, xtensa_unwind_pc
);
3245 set_gdbarch_frame_align (gdbarch
, xtensa_frame_align
);
3247 set_gdbarch_dummy_id (gdbarch
, xtensa_dummy_id
);
3249 /* Frame handling. */
3250 frame_base_set_default (gdbarch
, &xtensa_frame_base
);
3251 frame_unwind_append_unwinder (gdbarch
, &xtensa_unwind
);
3252 dwarf2_append_unwinders (gdbarch
);
3254 set_gdbarch_print_insn (gdbarch
, print_insn_xtensa
);
3256 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3258 xtensa_add_reggroups (gdbarch
);
3259 set_gdbarch_register_reggroup_p (gdbarch
, xtensa_register_reggroup_p
);
3261 set_gdbarch_iterate_over_regset_sections
3262 (gdbarch
, xtensa_iterate_over_regset_sections
);
3264 set_solib_svr4_fetch_link_map_offsets
3265 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
3267 /* Hook in the ABI-specific overrides, if they have been registered. */
3268 gdbarch_init_osabi (info
, gdbarch
);
3274 xtensa_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3276 error (_("xtensa_dump_tdep(): not implemented"));
3279 /* Provide a prototype to silence -Wmissing-prototypes. */
3280 extern initialize_file_ftype _initialize_xtensa_tdep
;
3283 _initialize_xtensa_tdep (void)
3285 gdbarch_register (bfd_arch_xtensa
, xtensa_gdbarch_init
, xtensa_dump_tdep
);
3286 xtensa_init_reggroups ();
3288 add_setshow_zuinteger_cmd ("xtensa",
3290 &xtensa_debug_level
,
3291 _("Set Xtensa debugging."),
3292 _("Show Xtensa debugging."), _("\
3293 When non-zero, Xtensa-specific debugging is enabled. \
3294 Can be 1, 2, 3, or 4 indicating the level of debugging."),
3297 &setdebuglist
, &showdebuglist
);