1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "solib-svr4.h"
32 #include "floatformat.h"
34 #include "reggroups.h"
37 #include "dummy-frame.h"
39 #include "dwarf2-frame.h"
40 #include "dwarf2loc.h"
42 #include "frame-base.h"
43 #include "frame-unwind.h"
45 #include "arch-utils.h"
52 #include "gdb_assert.h"
54 #include "xtensa-isa.h"
55 #include "xtensa-tdep.h"
56 #include "xtensa-config.h"
59 static int xtensa_debug_level
= 0;
61 #define DEBUGWARN(args...) \
62 if (xtensa_debug_level > 0) \
63 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
65 #define DEBUGINFO(args...) \
66 if (xtensa_debug_level > 1) \
67 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
69 #define DEBUGTRACE(args...) \
70 if (xtensa_debug_level > 2) \
71 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
73 #define DEBUGVERB(args...) \
74 if (xtensa_debug_level > 3) \
75 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
78 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
79 #define SP_ALIGNMENT 16
82 /* On Windowed ABI, we use a6 through a11 for passing arguments
83 to a function called by GDB because CALL4 is used. */
84 #define ARGS_NUM_REGS 6
85 #define REGISTER_SIZE 4
88 /* Extract the call size from the return address or PS register. */
89 #define PS_CALLINC_SHIFT 16
90 #define PS_CALLINC_MASK 0x00030000
91 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
92 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
94 /* On TX, hardware can be configured without Exception Option.
95 There is no PS register in this case. Inside XT-GDB, let us treat
96 it as a virtual read-only register always holding the same value. */
99 /* ABI-independent macros. */
100 #define ARG_NOF(gdbarch) \
101 (gdbarch_tdep (gdbarch)->call_abi \
102 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
103 #define ARG_1ST(gdbarch) \
104 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
105 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
106 : (gdbarch_tdep (gdbarch)->a0_base + 6))
108 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
109 indicates that the instruction is an ENTRY instruction. */
111 #define XTENSA_IS_ENTRY(gdbarch, op1) \
112 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
113 ? ((op1) == 0x6c) : ((op1) == 0x36))
115 #define XTENSA_ENTRY_LENGTH 3
117 /* windowing_enabled() returns true, if windowing is enabled.
118 WOE must be set to 1; EXCM to 0.
119 Note: We assume that EXCM is always 0 for XEA1. */
121 #define PS_WOE (1<<18)
122 #define PS_EXC (1<<4)
125 windowing_enabled (struct gdbarch
*gdbarch
, unsigned int ps
)
127 /* If we know CALL0 ABI is set explicitly, say it is Call0. */
128 if (gdbarch_tdep (gdbarch
)->call_abi
== CallAbiCall0Only
)
131 return ((ps
& PS_EXC
) == 0 && (ps
& PS_WOE
) != 0);
134 /* Convert a live A-register number to the corresponding AR-register
137 arreg_number (struct gdbarch
*gdbarch
, int a_regnum
, ULONGEST wb
)
139 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
142 arreg
= a_regnum
- tdep
->a0_base
;
143 arreg
+= (wb
& ((tdep
->num_aregs
- 1) >> 2)) << WB_SHIFT
;
144 arreg
&= tdep
->num_aregs
- 1;
146 return arreg
+ tdep
->ar_base
;
149 /* Convert a live AR-register number to the corresponding A-register order
150 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
152 areg_number (struct gdbarch
*gdbarch
, int ar_regnum
, unsigned int wb
)
154 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
157 areg
= ar_regnum
- tdep
->ar_base
;
158 if (areg
< 0 || areg
>= tdep
->num_aregs
)
160 areg
= (areg
- wb
* 4) & (tdep
->num_aregs
- 1);
161 return (areg
> 15) ? -1 : areg
;
164 /* Read Xtensa register directly from the hardware. */
166 xtensa_read_register (int regnum
)
170 regcache_raw_read_unsigned (get_current_regcache (), regnum
, &value
);
171 return (unsigned long) value
;
174 /* Write Xtensa register directly to the hardware. */
176 xtensa_write_register (int regnum
, ULONGEST value
)
178 regcache_raw_write_unsigned (get_current_regcache (), regnum
, value
);
181 /* Return the window size of the previous call to the function from which we
184 This function is used to extract the return value after a called function
185 has returned to the caller. On Xtensa, the register that holds the return
186 value (from the perspective of the caller) depends on what call
187 instruction was used. For now, we are assuming that the call instruction
188 precedes the current address, so we simply analyze the call instruction.
189 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
190 method to call the inferior function. */
193 extract_call_winsize (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
195 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
200 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc
);
202 /* Read the previous instruction (should be a call[x]{4|8|12}. */
203 read_memory (pc
-3, buf
, 3);
204 insn
= extract_unsigned_integer (buf
, 3, byte_order
);
206 /* Decode call instruction:
208 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
209 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
211 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
212 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
214 if (byte_order
== BFD_ENDIAN_LITTLE
)
216 if (((insn
& 0xf) == 0x5) || ((insn
& 0xcf) == 0xc0))
217 winsize
= (insn
& 0x30) >> 2; /* 0, 4, 8, 12. */
221 if (((insn
>> 20) == 0x5) || (((insn
>> 16) & 0xf3) == 0x03))
222 winsize
= (insn
>> 16) & 0xc; /* 0, 4, 8, 12. */
228 /* REGISTER INFORMATION */
230 /* Find register by name. */
232 xtensa_find_register_by_name (struct gdbarch
*gdbarch
, char *name
)
236 for (i
= 0; i
< gdbarch_num_regs (gdbarch
)
237 + gdbarch_num_pseudo_regs (gdbarch
);
240 if (strcasecmp (gdbarch_tdep (gdbarch
)->regmap
[i
].name
, name
) == 0)
246 /* Returns the name of a register. */
248 xtensa_register_name (struct gdbarch
*gdbarch
, int regnum
)
250 /* Return the name stored in the register map. */
251 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
)
252 + gdbarch_num_pseudo_regs (gdbarch
))
253 return gdbarch_tdep (gdbarch
)->regmap
[regnum
].name
;
255 internal_error (__FILE__
, __LINE__
, _("invalid register %d"), regnum
);
259 /* Return the type of a register. Create a new type, if necessary. */
262 xtensa_register_type (struct gdbarch
*gdbarch
, int regnum
)
264 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
266 /* Return signed integer for ARx and Ax registers. */
267 if ((regnum
>= tdep
->ar_base
268 && regnum
< tdep
->ar_base
+ tdep
->num_aregs
)
269 || (regnum
>= tdep
->a0_base
270 && regnum
< tdep
->a0_base
+ 16))
271 return builtin_type (gdbarch
)->builtin_int
;
273 if (regnum
== gdbarch_pc_regnum (gdbarch
)
274 || regnum
== tdep
->a0_base
+ 1)
275 return builtin_type (gdbarch
)->builtin_data_ptr
;
277 /* Return the stored type for all other registers. */
278 else if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
)
279 + gdbarch_num_pseudo_regs (gdbarch
))
281 xtensa_register_t
* reg
= &tdep
->regmap
[regnum
];
283 /* Set ctype for this register (only the first time). */
287 struct ctype_cache
*tp
;
288 int size
= reg
->byte_size
;
290 /* We always use the memory representation,
291 even if the register width is smaller. */
295 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint8
;
299 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint16
;
303 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint32
;
307 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint64
;
311 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint128
;
315 for (tp
= tdep
->type_entries
; tp
!= NULL
; tp
= tp
->next
)
316 if (tp
->size
== size
)
321 char *name
= xmalloc (16);
322 tp
= xmalloc (sizeof (struct ctype_cache
));
323 tp
->next
= tdep
->type_entries
;
324 tdep
->type_entries
= tp
;
327 sprintf (name
, "int%d", size
* 8);
329 = arch_integer_type (gdbarch
, size
* 8, 1, xstrdup (name
));
332 reg
->ctype
= tp
->virtual_type
;
338 internal_error (__FILE__
, __LINE__
, _("invalid register number %d"), regnum
);
343 /* Return the 'local' register number for stubs, dwarf2, etc.
344 The debugging information enumerates registers starting from 0 for A0
345 to n for An. So, we only have to add the base number for A0. */
348 xtensa_reg_to_regnum (struct gdbarch
*gdbarch
, int regnum
)
352 if (regnum
>= 0 && regnum
< 16)
353 return gdbarch_tdep (gdbarch
)->a0_base
+ regnum
;
356 i
< gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
358 if (regnum
== gdbarch_tdep (gdbarch
)->regmap
[i
].target_number
)
361 internal_error (__FILE__
, __LINE__
,
362 _("invalid dwarf/stabs register number %d"), regnum
);
367 /* Write the bits of a masked register to the various registers.
368 Only the masked areas of these registers are modified; the other
369 fields are untouched. The size of masked registers is always less
370 than or equal to 32 bits. */
373 xtensa_register_write_masked (struct regcache
*regcache
,
374 xtensa_register_t
*reg
, const gdb_byte
*buffer
)
376 unsigned int value
[(MAX_REGISTER_SIZE
+ 3) / 4];
377 const xtensa_mask_t
*mask
= reg
->mask
;
379 int shift
= 0; /* Shift for next mask (mod 32). */
380 int start
, size
; /* Start bit and size of current mask. */
382 unsigned int *ptr
= value
;
383 unsigned int regval
, m
, mem
= 0;
385 int bytesize
= reg
->byte_size
;
386 int bitsize
= bytesize
* 8;
389 DEBUGTRACE ("xtensa_register_write_masked ()\n");
391 /* Copy the masked register to host byte-order. */
392 if (gdbarch_byte_order (get_regcache_arch (regcache
)) == BFD_ENDIAN_BIG
)
393 for (i
= 0; i
< bytesize
; i
++)
396 mem
|= (buffer
[bytesize
- i
- 1] << 24);
401 for (i
= 0; i
< bytesize
; i
++)
404 mem
|= (buffer
[i
] << 24);
409 /* We might have to shift the final value:
410 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
411 bytesize & 3 == x -> shift (4-x) * 8. */
413 *ptr
= mem
>> (((0 - bytesize
) & 3) * 8);
417 /* Write the bits to the masked areas of the other registers. */
418 for (i
= 0; i
< mask
->count
; i
++)
420 start
= mask
->mask
[i
].bit_start
;
421 size
= mask
->mask
[i
].bit_size
;
422 regval
= mem
>> shift
;
424 if ((shift
+= size
) > bitsize
)
425 error (_("size of all masks is larger than the register"));
434 regval
|= mem
<< (size
- shift
);
437 /* Make sure we have a valid register. */
438 r
= mask
->mask
[i
].reg_num
;
439 if (r
>= 0 && size
> 0)
441 /* Don't overwrite the unmasked areas. */
443 regcache_cooked_read_unsigned (regcache
, r
, &old_val
);
444 m
= 0xffffffff >> (32 - size
) << start
;
446 regval
= (regval
& m
) | (old_val
& ~m
);
447 regcache_cooked_write_unsigned (regcache
, r
, regval
);
453 /* Read a tie state or mapped registers. Read the masked areas
454 of the registers and assemble them into a single value. */
456 static enum register_status
457 xtensa_register_read_masked (struct regcache
*regcache
,
458 xtensa_register_t
*reg
, gdb_byte
*buffer
)
460 unsigned int value
[(MAX_REGISTER_SIZE
+ 3) / 4];
461 const xtensa_mask_t
*mask
= reg
->mask
;
466 unsigned int *ptr
= value
;
467 unsigned int regval
, mem
= 0;
469 int bytesize
= reg
->byte_size
;
470 int bitsize
= bytesize
* 8;
473 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
474 reg
->name
== 0 ? "" : reg
->name
);
476 /* Assemble the register from the masked areas of other registers. */
477 for (i
= 0; i
< mask
->count
; i
++)
479 int r
= mask
->mask
[i
].reg_num
;
482 enum register_status status
;
485 status
= regcache_cooked_read_unsigned (regcache
, r
, &val
);
486 if (status
!= REG_VALID
)
488 regval
= (unsigned int) val
;
493 start
= mask
->mask
[i
].bit_start
;
494 size
= mask
->mask
[i
].bit_size
;
499 regval
&= (0xffffffff >> (32 - size
));
501 mem
|= regval
<< shift
;
503 if ((shift
+= size
) > bitsize
)
504 error (_("size of all masks is larger than the register"));
515 mem
= regval
>> (size
- shift
);
522 /* Copy value to target byte order. */
526 if (gdbarch_byte_order (get_regcache_arch (regcache
)) == BFD_ENDIAN_BIG
)
527 for (i
= 0; i
< bytesize
; i
++)
531 buffer
[bytesize
- i
- 1] = mem
& 0xff;
535 for (i
= 0; i
< bytesize
; i
++)
539 buffer
[i
] = mem
& 0xff;
547 /* Read pseudo registers. */
549 static enum register_status
550 xtensa_pseudo_register_read (struct gdbarch
*gdbarch
,
551 struct regcache
*regcache
,
555 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
557 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
558 regnum
, xtensa_register_name (gdbarch
, regnum
));
560 if (regnum
== gdbarch_num_regs (gdbarch
)
561 + gdbarch_num_pseudo_regs (gdbarch
) - 1)
562 regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ 1;
564 /* Read aliases a0..a15, if this is a Windowed ABI. */
565 if (gdbarch_tdep (gdbarch
)->isa_use_windowed_registers
566 && (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
)
567 && (regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15))
569 gdb_byte
*buf
= (gdb_byte
*) alloca (MAX_REGISTER_SIZE
);
570 enum register_status status
;
572 status
= regcache_raw_read (regcache
,
573 gdbarch_tdep (gdbarch
)->wb_regnum
,
575 if (status
!= REG_VALID
)
577 regnum
= arreg_number (gdbarch
, regnum
,
578 extract_unsigned_integer (buf
, 4, byte_order
));
581 /* We can always read non-pseudo registers. */
582 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
583 return regcache_raw_read (regcache
, regnum
, buffer
);
585 /* We have to find out how to deal with priveleged registers.
586 Let's treat them as pseudo-registers, but we cannot read/write them. */
588 else if (regnum
< gdbarch_tdep (gdbarch
)->a0_base
)
590 buffer
[0] = (gdb_byte
)0;
591 buffer
[1] = (gdb_byte
)0;
592 buffer
[2] = (gdb_byte
)0;
593 buffer
[3] = (gdb_byte
)0;
596 /* Pseudo registers. */
598 && regnum
< gdbarch_num_regs (gdbarch
)
599 + gdbarch_num_pseudo_regs (gdbarch
))
601 xtensa_register_t
*reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
602 xtensa_register_type_t type
= reg
->type
;
603 int flags
= gdbarch_tdep (gdbarch
)->target_flags
;
605 /* We cannot read Unknown or Unmapped registers. */
606 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
608 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
610 warning (_("cannot read register %s"),
611 xtensa_register_name (gdbarch
, regnum
));
616 /* Some targets cannot read TIE register files. */
617 else if (type
== xtRegisterTypeTieRegfile
)
619 /* Use 'fetch' to get register? */
620 if (flags
& xtTargetFlagsUseFetchStore
)
622 warning (_("cannot read register"));
626 /* On some targets (esp. simulators), we can always read the reg. */
627 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
629 warning (_("cannot read register"));
634 /* We can always read mapped registers. */
635 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
636 return xtensa_register_read_masked (regcache
, reg
, buffer
);
638 /* Assume that we can read the register. */
639 return regcache_raw_read (regcache
, regnum
, buffer
);
642 internal_error (__FILE__
, __LINE__
,
643 _("invalid register number %d"), regnum
);
647 /* Write pseudo registers. */
650 xtensa_pseudo_register_write (struct gdbarch
*gdbarch
,
651 struct regcache
*regcache
,
653 const gdb_byte
*buffer
)
655 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
657 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
658 regnum
, xtensa_register_name (gdbarch
, regnum
));
660 if (regnum
== gdbarch_num_regs (gdbarch
)
661 + gdbarch_num_pseudo_regs (gdbarch
) -1)
662 regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ 1;
664 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
665 if (gdbarch_tdep (gdbarch
)->isa_use_windowed_registers
666 && (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
)
667 && (regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15))
669 gdb_byte
*buf
= (gdb_byte
*) alloca (MAX_REGISTER_SIZE
);
672 regcache_raw_read (regcache
,
673 gdbarch_tdep (gdbarch
)->wb_regnum
, buf
);
674 regnum
= arreg_number (gdbarch
, regnum
,
675 extract_unsigned_integer (buf
, 4, byte_order
));
678 /* We can always write 'core' registers.
679 Note: We might have converted Ax->ARy. */
680 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
681 regcache_raw_write (regcache
, regnum
, buffer
);
683 /* We have to find out how to deal with priveleged registers.
684 Let's treat them as pseudo-registers, but we cannot read/write them. */
686 else if (regnum
< gdbarch_tdep (gdbarch
)->a0_base
)
690 /* Pseudo registers. */
692 && regnum
< gdbarch_num_regs (gdbarch
)
693 + gdbarch_num_pseudo_regs (gdbarch
))
695 xtensa_register_t
*reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
696 xtensa_register_type_t type
= reg
->type
;
697 int flags
= gdbarch_tdep (gdbarch
)->target_flags
;
699 /* On most targets, we cannot write registers
700 of type "Unknown" or "Unmapped". */
701 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
703 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
705 warning (_("cannot write register %s"),
706 xtensa_register_name (gdbarch
, regnum
));
711 /* Some targets cannot read TIE register files. */
712 else if (type
== xtRegisterTypeTieRegfile
)
714 /* Use 'store' to get register? */
715 if (flags
& xtTargetFlagsUseFetchStore
)
717 warning (_("cannot write register"));
721 /* On some targets (esp. simulators), we can always write
723 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
725 warning (_("cannot write register"));
730 /* We can always write mapped registers. */
731 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
733 xtensa_register_write_masked (regcache
, reg
, buffer
);
737 /* Assume that we can write the register. */
738 regcache_raw_write (regcache
, regnum
, buffer
);
741 internal_error (__FILE__
, __LINE__
,
742 _("invalid register number %d"), regnum
);
745 static struct reggroup
*xtensa_ar_reggroup
;
746 static struct reggroup
*xtensa_user_reggroup
;
747 static struct reggroup
*xtensa_vectra_reggroup
;
748 static struct reggroup
*xtensa_cp
[XTENSA_MAX_COPROCESSOR
];
751 xtensa_init_reggroups (void)
754 char cpname
[] = "cp0";
756 xtensa_ar_reggroup
= reggroup_new ("ar", USER_REGGROUP
);
757 xtensa_user_reggroup
= reggroup_new ("user", USER_REGGROUP
);
758 xtensa_vectra_reggroup
= reggroup_new ("vectra", USER_REGGROUP
);
760 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
763 xtensa_cp
[i
] = reggroup_new (cpname
, USER_REGGROUP
);
768 xtensa_add_reggroups (struct gdbarch
*gdbarch
)
772 /* Predefined groups. */
773 reggroup_add (gdbarch
, all_reggroup
);
774 reggroup_add (gdbarch
, save_reggroup
);
775 reggroup_add (gdbarch
, restore_reggroup
);
776 reggroup_add (gdbarch
, system_reggroup
);
777 reggroup_add (gdbarch
, vector_reggroup
);
778 reggroup_add (gdbarch
, general_reggroup
);
779 reggroup_add (gdbarch
, float_reggroup
);
781 /* Xtensa-specific groups. */
782 reggroup_add (gdbarch
, xtensa_ar_reggroup
);
783 reggroup_add (gdbarch
, xtensa_user_reggroup
);
784 reggroup_add (gdbarch
, xtensa_vectra_reggroup
);
786 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
787 reggroup_add (gdbarch
, xtensa_cp
[i
]);
791 xtensa_coprocessor_register_group (struct reggroup
*group
)
795 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
796 if (group
== xtensa_cp
[i
])
802 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
803 | XTENSA_REGISTER_FLAGS_WRITABLE \
804 | XTENSA_REGISTER_FLAGS_VOLATILE)
806 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
807 | XTENSA_REGISTER_FLAGS_WRITABLE)
810 xtensa_register_reggroup_p (struct gdbarch
*gdbarch
,
812 struct reggroup
*group
)
814 xtensa_register_t
* reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
815 xtensa_register_type_t type
= reg
->type
;
816 xtensa_register_group_t rg
= reg
->group
;
819 if (group
== save_reggroup
)
820 /* Every single register should be included into the list of registers
821 to be watched for changes while using -data-list-changed-registers. */
824 /* First, skip registers that are not visible to this target
825 (unknown and unmapped registers when not using ISS). */
827 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
829 if (group
== all_reggroup
)
831 if (group
== xtensa_ar_reggroup
)
832 return rg
& xtRegisterGroupAddrReg
;
833 if (group
== xtensa_user_reggroup
)
834 return rg
& xtRegisterGroupUser
;
835 if (group
== float_reggroup
)
836 return rg
& xtRegisterGroupFloat
;
837 if (group
== general_reggroup
)
838 return rg
& xtRegisterGroupGeneral
;
839 if (group
== system_reggroup
)
840 return rg
& xtRegisterGroupState
;
841 if (group
== vector_reggroup
|| group
== xtensa_vectra_reggroup
)
842 return rg
& xtRegisterGroupVectra
;
843 if (group
== restore_reggroup
)
844 return (regnum
< gdbarch_num_regs (gdbarch
)
845 && (reg
->flags
& SAVE_REST_FLAGS
) == SAVE_REST_VALID
);
846 if ((cp_number
= xtensa_coprocessor_register_group (group
)) >= 0)
847 return rg
& (xtRegisterGroupCP0
<< cp_number
);
853 /* Supply register REGNUM from the buffer specified by GREGS and LEN
854 in the general-purpose register set REGSET to register cache
855 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
858 xtensa_supply_gregset (const struct regset
*regset
,
864 const xtensa_elf_gregset_t
*regs
= gregs
;
865 struct gdbarch
*gdbarch
= get_regcache_arch (rc
);
868 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum
);
870 if (regnum
== gdbarch_pc_regnum (gdbarch
) || regnum
== -1)
871 regcache_raw_supply (rc
, gdbarch_pc_regnum (gdbarch
), (char *) ®s
->pc
);
872 if (regnum
== gdbarch_ps_regnum (gdbarch
) || regnum
== -1)
873 regcache_raw_supply (rc
, gdbarch_ps_regnum (gdbarch
), (char *) ®s
->ps
);
874 if (regnum
== gdbarch_tdep (gdbarch
)->wb_regnum
|| regnum
== -1)
875 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->wb_regnum
,
876 (char *) ®s
->windowbase
);
877 if (regnum
== gdbarch_tdep (gdbarch
)->ws_regnum
|| regnum
== -1)
878 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->ws_regnum
,
879 (char *) ®s
->windowstart
);
880 if (regnum
== gdbarch_tdep (gdbarch
)->lbeg_regnum
|| regnum
== -1)
881 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lbeg_regnum
,
882 (char *) ®s
->lbeg
);
883 if (regnum
== gdbarch_tdep (gdbarch
)->lend_regnum
|| regnum
== -1)
884 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lend_regnum
,
885 (char *) ®s
->lend
);
886 if (regnum
== gdbarch_tdep (gdbarch
)->lcount_regnum
|| regnum
== -1)
887 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lcount_regnum
,
888 (char *) ®s
->lcount
);
889 if (regnum
== gdbarch_tdep (gdbarch
)->sar_regnum
|| regnum
== -1)
890 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->sar_regnum
,
891 (char *) ®s
->sar
);
892 if (regnum
>=gdbarch_tdep (gdbarch
)->ar_base
893 && regnum
< gdbarch_tdep (gdbarch
)->ar_base
894 + gdbarch_tdep (gdbarch
)->num_aregs
)
895 regcache_raw_supply (rc
, regnum
,
896 (char *) ®s
->ar
[regnum
- gdbarch_tdep
897 (gdbarch
)->ar_base
]);
898 else if (regnum
== -1)
900 for (i
= 0; i
< gdbarch_tdep (gdbarch
)->num_aregs
; ++i
)
901 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->ar_base
+ i
,
902 (char *) ®s
->ar
[i
]);
907 /* Xtensa register set. */
913 xtensa_supply_gregset
917 /* Return the appropriate register set for the core
918 section identified by SECT_NAME and SECT_SIZE. */
920 static const struct regset
*
921 xtensa_regset_from_core_section (struct gdbarch
*core_arch
,
922 const char *sect_name
,
925 DEBUGTRACE ("xtensa_regset_from_core_section "
926 "(..., sect_name==\"%s\", sect_size==%x)\n",
927 sect_name
, (unsigned int) sect_size
);
929 if (strcmp (sect_name
, ".reg") == 0
930 && sect_size
>= sizeof(xtensa_elf_gregset_t
))
931 return &xtensa_gregset
;
937 /* Handling frames. */
939 /* Number of registers to save in case of Windowed ABI. */
940 #define XTENSA_NUM_SAVED_AREGS 12
942 /* Frame cache part for Windowed ABI. */
943 typedef struct xtensa_windowed_frame_cache
945 int wb
; /* WINDOWBASE of the previous frame. */
946 int callsize
; /* Call size of this frame. */
947 int ws
; /* WINDOWSTART of the previous frame. It keeps track of
948 life windows only. If there is no bit set for the
949 window, that means it had been already spilled
950 because of window overflow. */
952 /* Addresses of spilled A-registers.
953 AREGS[i] == -1, if corresponding AR is alive. */
954 CORE_ADDR aregs
[XTENSA_NUM_SAVED_AREGS
];
955 } xtensa_windowed_frame_cache_t
;
957 /* Call0 ABI Definitions. */
959 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue
961 #define C0_NREGS 16 /* Number of A-registers to track. */
962 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
963 #define C0_SP 1 /* Register used as SP. */
964 #define C0_FP 15 /* Register used as FP. */
965 #define C0_RA 0 /* Register used as return address. */
966 #define C0_ARGS 2 /* Register used as first arg/retval. */
967 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
969 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
970 A-register where the current content of the reg came from (in terms
971 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
972 mean that the orignal content of the register was saved to the stack.
973 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
974 know where SP will end up until the entire prologue has been analyzed. */
976 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
977 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
978 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
980 extern xtensa_isa xtensa_default_isa
;
982 typedef struct xtensa_c0reg
984 int fr_reg
; /* original register from which register content
985 is derived, or C0_CONST, or C0_INEXP. */
986 int fr_ofs
; /* constant offset from reg, or immediate value. */
987 int to_stk
; /* offset from original SP to register (4-byte aligned),
988 or C0_NOSTK if register has not been saved. */
991 /* Frame cache part for Call0 ABI. */
992 typedef struct xtensa_call0_frame_cache
994 int c0_frmsz
; /* Stack frame size. */
995 int c0_hasfp
; /* Current frame uses frame pointer. */
996 int fp_regnum
; /* A-register used as FP. */
997 int c0_fp
; /* Actual value of frame pointer. */
998 int c0_fpalign
; /* Dinamic adjustment for the stack
999 pointer. It's an AND mask. Zero,
1000 if alignment was not adjusted. */
1001 int c0_old_sp
; /* In case of dynamic adjustment, it is
1002 a register holding unaligned sp.
1003 C0_INEXP, when undefined. */
1004 int c0_sp_ofs
; /* If "c0_old_sp" was spilled it's a
1005 stack offset. C0_NOSTK otherwise. */
1007 xtensa_c0reg_t c0_rt
[C0_NREGS
]; /* Register tracking information. */
1008 } xtensa_call0_frame_cache_t
;
1010 typedef struct xtensa_frame_cache
1012 CORE_ADDR base
; /* Stack pointer of this frame. */
1013 CORE_ADDR pc
; /* PC of this frame at the function entry point. */
1014 CORE_ADDR ra
; /* The raw return address of this frame. */
1015 CORE_ADDR ps
; /* The PS register of the previous (older) frame. */
1016 CORE_ADDR prev_sp
; /* Stack Pointer of the previous (older) frame. */
1017 int call0
; /* It's a call0 framework (else windowed). */
1020 xtensa_windowed_frame_cache_t wd
; /* call0 == false. */
1021 xtensa_call0_frame_cache_t c0
; /* call0 == true. */
1023 } xtensa_frame_cache_t
;
1026 static struct xtensa_frame_cache
*
1027 xtensa_alloc_frame_cache (int windowed
)
1029 xtensa_frame_cache_t
*cache
;
1032 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
1034 cache
= FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t
);
1041 cache
->call0
= !windowed
;
1044 cache
->c0
.c0_frmsz
= -1;
1045 cache
->c0
.c0_hasfp
= 0;
1046 cache
->c0
.fp_regnum
= -1;
1047 cache
->c0
.c0_fp
= -1;
1048 cache
->c0
.c0_fpalign
= 0;
1049 cache
->c0
.c0_old_sp
= C0_INEXP
;
1050 cache
->c0
.c0_sp_ofs
= C0_NOSTK
;
1052 for (i
= 0; i
< C0_NREGS
; i
++)
1054 cache
->c0
.c0_rt
[i
].fr_reg
= i
;
1055 cache
->c0
.c0_rt
[i
].fr_ofs
= 0;
1056 cache
->c0
.c0_rt
[i
].to_stk
= C0_NOSTK
;
1063 cache
->wd
.callsize
= -1;
1065 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
1066 cache
->wd
.aregs
[i
] = -1;
1073 xtensa_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
1075 return address
& ~15;
1080 xtensa_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1085 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1086 host_address_to_string (next_frame
));
1088 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1089 pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1091 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc
);
1097 static struct frame_id
1098 xtensa_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1102 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1104 pc
= get_frame_pc (this_frame
);
1105 fp
= get_frame_register_unsigned
1106 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1108 /* Make dummy frame ID unique by adding a constant. */
1109 return frame_id_build (fp
+ SP_ALIGNMENT
, pc
);
1112 /* Returns true, if instruction to execute next is unique to Xtensa Window
1113 Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
1116 xtensa_window_interrupt_insn (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1118 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1119 unsigned int insn
= read_memory_integer (pc
, 4, byte_order
);
1122 if (byte_order
== BFD_ENDIAN_BIG
)
1124 /* Check, if this is L32E or S32E. */
1125 code
= insn
& 0xf000ff00;
1126 if ((code
== 0x00009000) || (code
== 0x00009400))
1128 /* Check, if this is RFWU or RFWO. */
1129 code
= insn
& 0xffffff00;
1130 return ((code
== 0x00430000) || (code
== 0x00530000));
1134 /* Check, if this is L32E or S32E. */
1135 code
= insn
& 0x00ff000f;
1136 if ((code
== 0x090000) || (code
== 0x490000))
1138 /* Check, if this is RFWU or RFWO. */
1139 code
= insn
& 0x00ffffff;
1140 return ((code
== 0x00003400) || (code
== 0x00003500));
1144 /* Returns the best guess about which register is a frame pointer
1145 for the function containing CURRENT_PC. */
1147 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1148 #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1151 xtensa_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
)
1153 #define RETURN_FP goto done
1155 unsigned int fp_regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ 1;
1156 CORE_ADDR start_addr
;
1158 xtensa_insnbuf ins
, slot
;
1159 char ibuf
[XTENSA_ISA_BSZ
];
1160 CORE_ADDR ia
, bt
, ba
;
1162 int ilen
, islots
, is
;
1164 const char *opcname
;
1166 find_pc_partial_function (current_pc
, NULL
, &start_addr
, NULL
);
1167 if (start_addr
== 0)
1170 if (!xtensa_default_isa
)
1171 xtensa_default_isa
= xtensa_isa_init (0, 0);
1172 isa
= xtensa_default_isa
;
1173 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
1174 ins
= xtensa_insnbuf_alloc (isa
);
1175 slot
= xtensa_insnbuf_alloc (isa
);
1178 for (ia
= start_addr
, bt
= ia
; ia
< current_pc
; ia
+= ilen
)
1180 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
1183 bt
= (ba
+ XTENSA_ISA_BSZ
) < current_pc
1184 ? ba
+ XTENSA_ISA_BSZ
: current_pc
;
1185 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0)
1189 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
1190 ifmt
= xtensa_format_decode (isa
, ins
);
1191 if (ifmt
== XTENSA_UNDEFINED
)
1193 ilen
= xtensa_format_length (isa
, ifmt
);
1194 if (ilen
== XTENSA_UNDEFINED
)
1196 islots
= xtensa_format_num_slots (isa
, ifmt
);
1197 if (islots
== XTENSA_UNDEFINED
)
1200 for (is
= 0; is
< islots
; ++is
)
1202 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
1205 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
1206 if (opc
== XTENSA_UNDEFINED
)
1209 opcname
= xtensa_opcode_name (isa
, opc
);
1211 if (strcasecmp (opcname
, "mov.n") == 0
1212 || strcasecmp (opcname
, "or") == 0)
1214 unsigned int register_operand
;
1216 /* Possible candidate for setting frame pointer
1217 from A1. This is what we are looking for. */
1219 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
,
1220 is
, slot
, ®ister_operand
) != 0)
1222 if (xtensa_operand_decode (isa
, opc
, 1, ®ister_operand
) != 0)
1224 if (register_operand
== 1) /* Mov{.n} FP A1. */
1226 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
,
1227 ®ister_operand
) != 0)
1229 if (xtensa_operand_decode (isa
, opc
, 0,
1230 ®ister_operand
) != 0)
1234 = gdbarch_tdep (gdbarch
)->a0_base
+ register_operand
;
1240 /* We have problems decoding the memory. */
1242 || strcasecmp (opcname
, "ill") == 0
1243 || strcasecmp (opcname
, "ill.n") == 0
1244 /* Hit planted breakpoint. */
1245 || strcasecmp (opcname
, "break") == 0
1246 || strcasecmp (opcname
, "break.n") == 0
1247 /* Flow control instructions finish prologue. */
1248 || xtensa_opcode_is_branch (isa
, opc
) > 0
1249 || xtensa_opcode_is_jump (isa
, opc
) > 0
1250 || xtensa_opcode_is_loop (isa
, opc
) > 0
1251 || xtensa_opcode_is_call (isa
, opc
) > 0
1252 || strcasecmp (opcname
, "simcall") == 0
1253 || strcasecmp (opcname
, "syscall") == 0)
1254 /* Can not continue analysis. */
1259 xtensa_insnbuf_free(isa
, slot
);
1260 xtensa_insnbuf_free(isa
, ins
);
1264 /* The key values to identify the frame using "cache" are
1266 cache->base = SP (or best guess about FP) of this frame;
1267 cache->pc = entry-PC (entry point of the frame function);
1268 cache->prev_sp = SP of the previous frame. */
1271 call0_frame_cache (struct frame_info
*this_frame
,
1272 xtensa_frame_cache_t
*cache
, CORE_ADDR pc
);
1275 xtensa_window_interrupt_frame_cache (struct frame_info
*this_frame
,
1276 xtensa_frame_cache_t
*cache
,
1279 static struct xtensa_frame_cache
*
1280 xtensa_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1282 xtensa_frame_cache_t
*cache
;
1283 CORE_ADDR ra
, wb
, ws
, pc
, sp
, ps
;
1284 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1285 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1286 unsigned int fp_regnum
;
1287 int windowed
, ps_regnum
;
1292 pc
= get_frame_register_unsigned (this_frame
, gdbarch_pc_regnum (gdbarch
));
1293 ps_regnum
= gdbarch_ps_regnum (gdbarch
);
1294 ps
= (ps_regnum
>= 0
1295 ? get_frame_register_unsigned (this_frame
, ps_regnum
) : TX_PS
);
1297 windowed
= windowing_enabled (gdbarch
, ps
);
1299 /* Get pristine xtensa-frame. */
1300 cache
= xtensa_alloc_frame_cache (windowed
);
1301 *this_cache
= cache
;
1307 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1308 wb
= get_frame_register_unsigned (this_frame
,
1309 gdbarch_tdep (gdbarch
)->wb_regnum
);
1310 ws
= get_frame_register_unsigned (this_frame
,
1311 gdbarch_tdep (gdbarch
)->ws_regnum
);
1313 op1
= read_memory_integer (pc
, 1, byte_order
);
1314 if (XTENSA_IS_ENTRY (gdbarch
, op1
))
1316 int callinc
= CALLINC (ps
);
1317 ra
= get_frame_register_unsigned
1318 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ callinc
* 4);
1320 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1321 cache
->wd
.callsize
= 0;
1324 cache
->prev_sp
= get_frame_register_unsigned
1325 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1327 /* This only can be the outermost frame since we are
1328 just about to execute ENTRY. SP hasn't been set yet.
1329 We can assume any frame size, because it does not
1330 matter, and, let's fake frame base in cache. */
1331 cache
->base
= cache
->prev_sp
- 16;
1334 cache
->ra
= (cache
->pc
& 0xc0000000) | (ra
& 0x3fffffff);
1335 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1336 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1342 fp_regnum
= xtensa_scan_prologue (gdbarch
, pc
);
1343 ra
= get_frame_register_unsigned (this_frame
,
1344 gdbarch_tdep (gdbarch
)->a0_base
);
1345 cache
->wd
.callsize
= WINSIZE (ra
);
1346 cache
->wd
.wb
= (wb
- cache
->wd
.callsize
/ 4)
1347 & (gdbarch_tdep (gdbarch
)->num_aregs
/ 4 - 1);
1348 cache
->wd
.ws
= ws
& ~(1 << wb
);
1350 cache
->pc
= get_frame_func (this_frame
);
1351 cache
->ra
= (pc
& 0xc0000000) | (ra
& 0x3fffffff);
1352 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1353 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1356 if (cache
->wd
.ws
== 0)
1361 sp
= get_frame_register_unsigned
1362 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1) - 16;
1364 for (i
= 0; i
< 4; i
++, sp
+= 4)
1366 cache
->wd
.aregs
[i
] = sp
;
1369 if (cache
->wd
.callsize
> 4)
1371 /* Set A4...A7/A11. */
1372 /* Get the SP of the frame previous to the previous one.
1373 To achieve this, we have to dereference SP twice. */
1374 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4, byte_order
);
1375 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4, byte_order
);
1376 sp
-= cache
->wd
.callsize
* 4;
1378 for ( i
= 4; i
< cache
->wd
.callsize
; i
++, sp
+= 4)
1380 cache
->wd
.aregs
[i
] = sp
;
1385 if ((cache
->prev_sp
== 0) && ( ra
!= 0 ))
1386 /* If RA is equal to 0 this frame is an outermost frame. Leave
1387 cache->prev_sp unchanged marking the boundary of the frame stack. */
1389 if ((cache
->wd
.ws
& (1 << cache
->wd
.wb
)) == 0)
1391 /* Register window overflow already happened.
1392 We can read caller's SP from the proper spill loction. */
1393 sp
= get_frame_register_unsigned
1394 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1395 cache
->prev_sp
= read_memory_integer (sp
- 12, 4, byte_order
);
1399 /* Read caller's frame SP directly from the previous window. */
1400 int regnum
= arreg_number
1401 (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ 1,
1404 cache
->prev_sp
= xtensa_read_register (regnum
);
1408 else if (xtensa_window_interrupt_insn (gdbarch
, pc
))
1410 /* Execution stopped inside Xtensa Window Interrupt Handler. */
1412 xtensa_window_interrupt_frame_cache (this_frame
, cache
, pc
);
1413 /* Everything was set already, including cache->base. */
1416 else /* Call0 framework. */
1418 call0_frame_cache (this_frame
, cache
, pc
);
1419 fp_regnum
= cache
->c0
.fp_regnum
;
1422 cache
->base
= get_frame_register_unsigned (this_frame
, fp_regnum
);
1427 static int xtensa_session_once_reported
= 1;
1429 /* Report a problem with prologue analysis while doing backtracing.
1430 But, do it only once to avoid annoyng repeated messages. */
1435 if (xtensa_session_once_reported
== 0)
1437 \nUnrecognised function prologue. Stack trace cannot be resolved. \
1438 This message will not be repeated in this session.\n"));
1440 xtensa_session_once_reported
= 1;
1445 xtensa_frame_this_id (struct frame_info
*this_frame
,
1447 struct frame_id
*this_id
)
1449 struct xtensa_frame_cache
*cache
=
1450 xtensa_frame_cache (this_frame
, this_cache
);
1452 if (cache
->prev_sp
== 0)
1455 (*this_id
) = frame_id_build (cache
->prev_sp
, cache
->pc
);
1458 static struct value
*
1459 xtensa_frame_prev_register (struct frame_info
*this_frame
,
1463 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1464 struct xtensa_frame_cache
*cache
;
1465 ULONGEST saved_reg
= 0;
1468 if (*this_cache
== NULL
)
1469 *this_cache
= xtensa_frame_cache (this_frame
, this_cache
);
1470 cache
= *this_cache
;
1472 if (regnum
==gdbarch_pc_regnum (gdbarch
))
1473 saved_reg
= cache
->ra
;
1474 else if (regnum
== gdbarch_tdep (gdbarch
)->a0_base
+ 1)
1475 saved_reg
= cache
->prev_sp
;
1476 else if (!cache
->call0
)
1478 if (regnum
== gdbarch_tdep (gdbarch
)->ws_regnum
)
1479 saved_reg
= cache
->wd
.ws
;
1480 else if (regnum
== gdbarch_tdep (gdbarch
)->wb_regnum
)
1481 saved_reg
= cache
->wd
.wb
;
1482 else if (regnum
== gdbarch_ps_regnum (gdbarch
))
1483 saved_reg
= cache
->ps
;
1491 return frame_unwind_got_constant (this_frame
, regnum
, saved_reg
);
1493 if (!cache
->call0
) /* Windowed ABI. */
1495 /* Convert A-register numbers to AR-register numbers,
1496 if we deal with A-register. */
1497 if (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
1498 && regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15)
1499 regnum
= arreg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1501 /* Check, if we deal with AR-register saved on stack. */
1502 if (regnum
>= gdbarch_tdep (gdbarch
)->ar_base
1503 && regnum
<= (gdbarch_tdep (gdbarch
)->ar_base
1504 + gdbarch_tdep (gdbarch
)->num_aregs
))
1506 int areg
= areg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1509 && areg
< XTENSA_NUM_SAVED_AREGS
1510 && cache
->wd
.aregs
[areg
] != -1)
1511 return frame_unwind_got_memory (this_frame
, regnum
,
1512 cache
->wd
.aregs
[areg
]);
1515 else /* Call0 ABI. */
1517 int reg
= (regnum
>= gdbarch_tdep (gdbarch
)->ar_base
1518 && regnum
<= (gdbarch_tdep (gdbarch
)->ar_base
1520 ? regnum
- gdbarch_tdep (gdbarch
)->ar_base
: regnum
;
1527 /* If register was saved in the prologue, retrieve it. */
1528 stkofs
= cache
->c0
.c0_rt
[reg
].to_stk
;
1529 if (stkofs
!= C0_NOSTK
)
1531 /* Determine SP on entry based on FP. */
1532 spe
= cache
->c0
.c0_fp
1533 - cache
->c0
.c0_rt
[cache
->c0
.fp_regnum
].fr_ofs
;
1535 return frame_unwind_got_memory (this_frame
, regnum
,
1541 /* All other registers have been either saved to
1542 the stack or are still alive in the processor. */
1544 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1548 static const struct frame_unwind
1552 default_frame_unwind_stop_reason
,
1553 xtensa_frame_this_id
,
1554 xtensa_frame_prev_register
,
1556 default_frame_sniffer
1560 xtensa_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1562 struct xtensa_frame_cache
*cache
=
1563 xtensa_frame_cache (this_frame
, this_cache
);
1568 static const struct frame_base
1572 xtensa_frame_base_address
,
1573 xtensa_frame_base_address
,
1574 xtensa_frame_base_address
1579 xtensa_extract_return_value (struct type
*type
,
1580 struct regcache
*regcache
,
1583 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1584 bfd_byte
*valbuf
= dst
;
1585 int len
= TYPE_LENGTH (type
);
1590 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1592 gdb_assert(len
> 0);
1594 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1596 /* First, we have to find the caller window in the register file. */
1597 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1598 callsize
= extract_call_winsize (gdbarch
, pc
);
1600 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1601 if (len
> (callsize
> 8 ? 8 : 16))
1602 internal_error (__FILE__
, __LINE__
,
1603 _("cannot extract return value of %d bytes long"),
1606 /* Get the register offset of the return
1607 register (A2) in the caller window. */
1608 regcache_raw_read_unsigned
1609 (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, &wb
);
1610 areg
= arreg_number (gdbarch
,
1611 gdbarch_tdep (gdbarch
)->a0_base
+ 2 + callsize
, wb
);
1615 /* No windowing hardware - Call0 ABI. */
1616 areg
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_ARGS
;
1619 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg
, len
);
1621 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1624 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1627 regcache_raw_read_part (regcache
, areg
, offset
, len
, valbuf
);
1629 regcache_raw_read (regcache
, areg
, valbuf
);
1635 xtensa_store_return_value (struct type
*type
,
1636 struct regcache
*regcache
,
1639 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1640 const bfd_byte
*valbuf
= dst
;
1644 int len
= TYPE_LENGTH (type
);
1647 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1649 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1651 regcache_raw_read_unsigned
1652 (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, &wb
);
1653 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1654 callsize
= extract_call_winsize (gdbarch
, pc
);
1656 if (len
> (callsize
> 8 ? 8 : 16))
1657 internal_error (__FILE__
, __LINE__
,
1658 _("unimplemented for this length: %d"),
1659 TYPE_LENGTH (type
));
1660 areg
= arreg_number (gdbarch
,
1661 gdbarch_tdep (gdbarch
)->a0_base
+ 2 + callsize
, wb
);
1663 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1664 callsize
, (int) wb
);
1668 areg
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_ARGS
;
1671 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1674 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1677 regcache_raw_write_part (regcache
, areg
, offset
, len
, valbuf
);
1679 regcache_raw_write (regcache
, areg
, valbuf
);
1684 static enum return_value_convention
1685 xtensa_return_value (struct gdbarch
*gdbarch
,
1686 struct type
*func_type
,
1687 struct type
*valtype
,
1688 struct regcache
*regcache
,
1690 const gdb_byte
*writebuf
)
1692 /* Structures up to 16 bytes are returned in registers. */
1694 int struct_return
= ((TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
1695 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
1696 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
1697 && TYPE_LENGTH (valtype
) > 16);
1700 return RETURN_VALUE_STRUCT_CONVENTION
;
1702 DEBUGTRACE ("xtensa_return_value(...)\n");
1704 if (writebuf
!= NULL
)
1706 xtensa_store_return_value (valtype
, regcache
, writebuf
);
1709 if (readbuf
!= NULL
)
1711 gdb_assert (!struct_return
);
1712 xtensa_extract_return_value (valtype
, regcache
, readbuf
);
1714 return RETURN_VALUE_REGISTER_CONVENTION
;
1721 xtensa_push_dummy_call (struct gdbarch
*gdbarch
,
1722 struct value
*function
,
1723 struct regcache
*regcache
,
1726 struct value
**args
,
1729 CORE_ADDR struct_addr
)
1731 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1733 int size
, onstack_size
;
1734 gdb_byte
*buf
= (gdb_byte
*) alloca (16);
1736 struct argument_info
1738 const bfd_byte
*contents
;
1740 int onstack
; /* onstack == 0 => in reg */
1741 int align
; /* alignment */
1744 int offset
; /* stack offset if on stack. */
1745 int regno
; /* regno if in register. */
1749 struct argument_info
*arg_info
=
1750 (struct argument_info
*) alloca (nargs
* sizeof (struct argument_info
));
1754 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1756 if (xtensa_debug_level
> 3)
1759 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs
);
1760 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1761 "struct_addr=0x%x\n",
1762 (int) sp
, (int) struct_return
, (int) struct_addr
);
1764 for (i
= 0; i
< nargs
; i
++)
1766 struct value
*arg
= args
[i
];
1767 struct type
*arg_type
= check_typedef (value_type (arg
));
1768 fprintf_unfiltered (gdb_stdlog
, "%2d: %s %3d ", i
,
1769 host_address_to_string (arg
),
1770 TYPE_LENGTH (arg_type
));
1771 switch (TYPE_CODE (arg_type
))
1774 fprintf_unfiltered (gdb_stdlog
, "int");
1776 case TYPE_CODE_STRUCT
:
1777 fprintf_unfiltered (gdb_stdlog
, "struct");
1780 fprintf_unfiltered (gdb_stdlog
, "%3d", TYPE_CODE (arg_type
));
1783 fprintf_unfiltered (gdb_stdlog
, " %s\n",
1784 host_address_to_string (value_contents (arg
)));
1788 /* First loop: collect information.
1789 Cast into type_long. (This shouldn't happen often for C because
1790 GDB already does this earlier.) It's possible that GDB could
1791 do it all the time but it's harmless to leave this code here. */
1798 size
= REGISTER_SIZE
;
1800 for (i
= 0; i
< nargs
; i
++)
1802 struct argument_info
*info
= &arg_info
[i
];
1803 struct value
*arg
= args
[i
];
1804 struct type
*arg_type
= check_typedef (value_type (arg
));
1806 switch (TYPE_CODE (arg_type
))
1809 case TYPE_CODE_BOOL
:
1810 case TYPE_CODE_CHAR
:
1811 case TYPE_CODE_RANGE
:
1812 case TYPE_CODE_ENUM
:
1814 /* Cast argument to long if necessary as the mask does it too. */
1815 if (TYPE_LENGTH (arg_type
)
1816 < TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
))
1818 arg_type
= builtin_type (gdbarch
)->builtin_long
;
1819 arg
= value_cast (arg_type
, arg
);
1821 /* Aligment is equal to the type length for the basic types. */
1822 info
->align
= TYPE_LENGTH (arg_type
);
1827 /* Align doubles correctly. */
1828 if (TYPE_LENGTH (arg_type
)
1829 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
))
1830 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
);
1832 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
);
1835 case TYPE_CODE_STRUCT
:
1837 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
);
1840 info
->length
= TYPE_LENGTH (arg_type
);
1841 info
->contents
= value_contents (arg
);
1843 /* Align size and onstack_size. */
1844 size
= (size
+ info
->align
- 1) & ~(info
->align
- 1);
1845 onstack_size
= (onstack_size
+ info
->align
- 1) & ~(info
->align
- 1);
1847 if (size
+ info
->length
> REGISTER_SIZE
* ARG_NOF (gdbarch
))
1850 info
->u
.offset
= onstack_size
;
1851 onstack_size
+= info
->length
;
1856 info
->u
.regno
= ARG_1ST (gdbarch
) + size
/ REGISTER_SIZE
;
1858 size
+= info
->length
;
1861 /* Adjust the stack pointer and align it. */
1862 sp
= align_down (sp
- onstack_size
, SP_ALIGNMENT
);
1864 /* Simulate MOVSP, if Windowed ABI. */
1865 if ((gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1868 read_memory (osp
- 16, buf
, 16);
1869 write_memory (sp
- 16, buf
, 16);
1872 /* Second Loop: Load arguments. */
1876 store_unsigned_integer (buf
, REGISTER_SIZE
, byte_order
, struct_addr
);
1877 regcache_cooked_write (regcache
, ARG_1ST (gdbarch
), buf
);
1880 for (i
= 0; i
< nargs
; i
++)
1882 struct argument_info
*info
= &arg_info
[i
];
1886 int n
= info
->length
;
1887 CORE_ADDR offset
= sp
+ info
->u
.offset
;
1889 /* Odd-sized structs are aligned to the lower side of a memory
1890 word in big-endian mode and require a shift. This only
1891 applies for structures smaller than one word. */
1893 if (n
< REGISTER_SIZE
1894 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1895 offset
+= (REGISTER_SIZE
- n
);
1897 write_memory (offset
, info
->contents
, info
->length
);
1902 int n
= info
->length
;
1903 const bfd_byte
*cp
= info
->contents
;
1904 int r
= info
->u
.regno
;
1906 /* Odd-sized structs are aligned to the lower side of registers in
1907 big-endian mode and require a shift. The odd-sized leftover will
1908 be at the end. Note that this is only true for structures smaller
1909 than REGISTER_SIZE; for larger odd-sized structures the excess
1910 will be left-aligned in the register on both endiannesses. */
1912 if (n
< REGISTER_SIZE
&& byte_order
== BFD_ENDIAN_BIG
)
1915 v
= extract_unsigned_integer (cp
, REGISTER_SIZE
, byte_order
);
1916 v
= v
>> ((REGISTER_SIZE
- n
) * TARGET_CHAR_BIT
);
1918 store_unsigned_integer (buf
, REGISTER_SIZE
, byte_order
, v
);
1919 regcache_cooked_write (regcache
, r
, buf
);
1921 cp
+= REGISTER_SIZE
;
1928 regcache_cooked_write (regcache
, r
, cp
);
1930 cp
+= REGISTER_SIZE
;
1937 /* Set the return address of dummy frame to the dummy address.
1938 The return address for the current function (in A0) is
1939 saved in the dummy frame, so we can savely overwrite A0 here. */
1941 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1945 ra
= (bp_addr
& 0x3fffffff) | 0x40000000;
1946 regcache_raw_read_unsigned (regcache
, gdbarch_ps_regnum (gdbarch
), &val
);
1947 ps
= (unsigned long) val
& ~0x00030000;
1948 regcache_cooked_write_unsigned
1949 (regcache
, gdbarch_tdep (gdbarch
)->a0_base
+ 4, ra
);
1950 regcache_cooked_write_unsigned (regcache
,
1951 gdbarch_ps_regnum (gdbarch
),
1954 /* All the registers have been saved. After executing
1955 dummy call, they all will be restored. So it's safe
1956 to modify WINDOWSTART register to make it look like there
1957 is only one register window corresponding to WINDOWEBASE. */
1959 regcache_raw_read (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, buf
);
1960 regcache_cooked_write_unsigned
1961 (regcache
, gdbarch_tdep (gdbarch
)->ws_regnum
,
1962 1 << extract_unsigned_integer (buf
, 4, byte_order
));
1966 /* Simulate CALL0: write RA into A0 register. */
1967 regcache_cooked_write_unsigned
1968 (regcache
, gdbarch_tdep (gdbarch
)->a0_base
, bp_addr
);
1971 /* Set new stack pointer and return it. */
1972 regcache_cooked_write_unsigned (regcache
,
1973 gdbarch_tdep (gdbarch
)->a0_base
+ 1, sp
);
1974 /* Make dummy frame ID unique by adding a constant. */
1975 return sp
+ SP_ALIGNMENT
;
1979 /* Return a breakpoint for the current location of PC. We always use
1980 the density version if we have density instructions (regardless of the
1981 current instruction at PC), and use regular instructions otherwise. */
1983 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1984 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1985 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1986 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1988 static const unsigned char *
1989 xtensa_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
1992 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
1993 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
1994 static unsigned char density_big_breakpoint
[] = DENSITY_BIG_BREAKPOINT
;
1995 static unsigned char density_little_breakpoint
[] = DENSITY_LITTLE_BREAKPOINT
;
1997 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr
);
1999 if (gdbarch_tdep (gdbarch
)->isa_use_density_instructions
)
2001 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2003 *lenptr
= sizeof (density_big_breakpoint
);
2004 return density_big_breakpoint
;
2008 *lenptr
= sizeof (density_little_breakpoint
);
2009 return density_little_breakpoint
;
2014 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2016 *lenptr
= sizeof (big_breakpoint
);
2017 return big_breakpoint
;
2021 *lenptr
= sizeof (little_breakpoint
);
2022 return little_breakpoint
;
2027 /* Call0 ABI support routines. */
2029 /* Return true, if PC points to "ret" or "ret.n". */
2032 call0_ret (CORE_ADDR start_pc
, CORE_ADDR finish_pc
)
2034 #define RETURN_RET goto done
2036 xtensa_insnbuf ins
, slot
;
2037 char ibuf
[XTENSA_ISA_BSZ
];
2038 CORE_ADDR ia
, bt
, ba
;
2040 int ilen
, islots
, is
;
2042 const char *opcname
;
2045 isa
= xtensa_default_isa
;
2046 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2047 ins
= xtensa_insnbuf_alloc (isa
);
2048 slot
= xtensa_insnbuf_alloc (isa
);
2051 for (ia
= start_pc
, bt
= ia
; ia
< finish_pc
; ia
+= ilen
)
2053 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2056 bt
= (ba
+ XTENSA_ISA_BSZ
) < finish_pc
2057 ? ba
+ XTENSA_ISA_BSZ
: finish_pc
;
2058 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0 )
2062 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2063 ifmt
= xtensa_format_decode (isa
, ins
);
2064 if (ifmt
== XTENSA_UNDEFINED
)
2066 ilen
= xtensa_format_length (isa
, ifmt
);
2067 if (ilen
== XTENSA_UNDEFINED
)
2069 islots
= xtensa_format_num_slots (isa
, ifmt
);
2070 if (islots
== XTENSA_UNDEFINED
)
2073 for (is
= 0; is
< islots
; ++is
)
2075 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
2078 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2079 if (opc
== XTENSA_UNDEFINED
)
2082 opcname
= xtensa_opcode_name (isa
, opc
);
2084 if ((strcasecmp (opcname
, "ret.n") == 0)
2085 || (strcasecmp (opcname
, "ret") == 0))
2093 xtensa_insnbuf_free(isa
, slot
);
2094 xtensa_insnbuf_free(isa
, ins
);
2098 /* Call0 opcode class. Opcodes are preclassified according to what they
2099 mean for Call0 prologue analysis, and their number of significant operands.
2100 The purpose of this is to simplify prologue analysis by separating
2101 instruction decoding (libisa) from the semantics of prologue analysis. */
2105 c0opc_illegal
, /* Unknown to libisa (invalid) or 'ill' opcode. */
2106 c0opc_uninteresting
, /* Not interesting for Call0 prologue analysis. */
2107 c0opc_flow
, /* Flow control insn. */
2108 c0opc_entry
, /* ENTRY indicates non-Call0 prologue. */
2109 c0opc_break
, /* Debugger software breakpoints. */
2110 c0opc_add
, /* Adding two registers. */
2111 c0opc_addi
, /* Adding a register and an immediate. */
2112 c0opc_and
, /* Bitwise "and"-ing two registers. */
2113 c0opc_sub
, /* Subtracting a register from a register. */
2114 c0opc_mov
, /* Moving a register to a register. */
2115 c0opc_movi
, /* Moving an immediate to a register. */
2116 c0opc_l32r
, /* Loading a literal. */
2117 c0opc_s32i
, /* Storing word at fixed offset from a base register. */
2118 c0opc_rwxsr
, /* RSR, WRS, or XSR instructions. */
2119 c0opc_l32e
, /* L32E instruction. */
2120 c0opc_s32e
, /* S32E instruction. */
2121 c0opc_rfwo
, /* RFWO instruction. */
2122 c0opc_rfwu
, /* RFWU instruction. */
2123 c0opc_NrOf
/* Number of opcode classifications. */
2126 /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
2129 rwx_special_register (const char *opcname
)
2131 char ch
= *opcname
++;
2133 if ((ch
!= 'r') && (ch
!= 'w') && (ch
!= 'x'))
2135 if (*opcname
++ != 's')
2137 if (*opcname
++ != 'r')
2139 if (*opcname
++ != '.')
2145 /* Classify an opcode based on what it means for Call0 prologue analysis. */
2147 static xtensa_insn_kind
2148 call0_classify_opcode (xtensa_isa isa
, xtensa_opcode opc
)
2150 const char *opcname
;
2151 xtensa_insn_kind opclass
= c0opc_uninteresting
;
2153 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc
);
2155 /* Get opcode name and handle special classifications. */
2157 opcname
= xtensa_opcode_name (isa
, opc
);
2160 || strcasecmp (opcname
, "ill") == 0
2161 || strcasecmp (opcname
, "ill.n") == 0)
2162 opclass
= c0opc_illegal
;
2163 else if (strcasecmp (opcname
, "break") == 0
2164 || strcasecmp (opcname
, "break.n") == 0)
2165 opclass
= c0opc_break
;
2166 else if (strcasecmp (opcname
, "entry") == 0)
2167 opclass
= c0opc_entry
;
2168 else if (strcasecmp (opcname
, "rfwo") == 0)
2169 opclass
= c0opc_rfwo
;
2170 else if (strcasecmp (opcname
, "rfwu") == 0)
2171 opclass
= c0opc_rfwu
;
2172 else if (xtensa_opcode_is_branch (isa
, opc
) > 0
2173 || xtensa_opcode_is_jump (isa
, opc
) > 0
2174 || xtensa_opcode_is_loop (isa
, opc
) > 0
2175 || xtensa_opcode_is_call (isa
, opc
) > 0
2176 || strcasecmp (opcname
, "simcall") == 0
2177 || strcasecmp (opcname
, "syscall") == 0)
2178 opclass
= c0opc_flow
;
2180 /* Also, classify specific opcodes that need to be tracked. */
2181 else if (strcasecmp (opcname
, "add") == 0
2182 || strcasecmp (opcname
, "add.n") == 0)
2183 opclass
= c0opc_add
;
2184 else if (strcasecmp (opcname
, "and") == 0)
2185 opclass
= c0opc_and
;
2186 else if (strcasecmp (opcname
, "addi") == 0
2187 || strcasecmp (opcname
, "addi.n") == 0
2188 || strcasecmp (opcname
, "addmi") == 0)
2189 opclass
= c0opc_addi
;
2190 else if (strcasecmp (opcname
, "sub") == 0)
2191 opclass
= c0opc_sub
;
2192 else if (strcasecmp (opcname
, "mov.n") == 0
2193 || strcasecmp (opcname
, "or") == 0) /* Could be 'mov' asm macro. */
2194 opclass
= c0opc_mov
;
2195 else if (strcasecmp (opcname
, "movi") == 0
2196 || strcasecmp (opcname
, "movi.n") == 0)
2197 opclass
= c0opc_movi
;
2198 else if (strcasecmp (opcname
, "l32r") == 0)
2199 opclass
= c0opc_l32r
;
2200 else if (strcasecmp (opcname
, "s32i") == 0
2201 || strcasecmp (opcname
, "s32i.n") == 0)
2202 opclass
= c0opc_s32i
;
2203 else if (strcasecmp (opcname
, "l32e") == 0)
2204 opclass
= c0opc_l32e
;
2205 else if (strcasecmp (opcname
, "s32e") == 0)
2206 opclass
= c0opc_s32e
;
2207 else if (rwx_special_register (opcname
))
2208 opclass
= c0opc_rwxsr
;
2213 /* Tracks register movement/mutation for a given operation, which may
2214 be within a bundle. Updates the destination register tracking info
2215 accordingly. The pc is needed only for pc-relative load instructions
2216 (eg. l32r). The SP register number is needed to identify stores to
2217 the stack frame. Returns 0, if analysis was succesfull, non-zero
2221 call0_track_op (struct gdbarch
*gdbarch
, xtensa_c0reg_t dst
[], xtensa_c0reg_t src
[],
2222 xtensa_insn_kind opclass
, int nods
, unsigned odv
[],
2223 CORE_ADDR pc
, int spreg
, xtensa_frame_cache_t
*cache
)
2225 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2226 unsigned litbase
, litaddr
, litval
;
2231 /* 3 operands: dst, src, imm. */
2232 gdb_assert (nods
== 3);
2233 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2234 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ odv
[2];
2237 /* 3 operands: dst, src1, src2. */
2238 gdb_assert (nods
== 3);
2239 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2241 dst
[odv
[0]].fr_reg
= src
[odv
[2]].fr_reg
;
2242 dst
[odv
[0]].fr_ofs
= src
[odv
[2]].fr_ofs
+ src
[odv
[1]].fr_ofs
;
2244 else if (src
[odv
[2]].fr_reg
== C0_CONST
)
2246 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2247 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ src
[odv
[2]].fr_ofs
;
2249 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2252 /* 3 operands: dst, src1, src2. */
2253 gdb_assert (nods
== 3);
2254 if (cache
->c0
.c0_fpalign
== 0)
2256 /* Handle dynamic stack alignment. */
2257 if ((src
[odv
[0]].fr_reg
== spreg
) && (src
[odv
[1]].fr_reg
== spreg
))
2259 if (src
[odv
[2]].fr_reg
== C0_CONST
)
2260 cache
->c0
.c0_fpalign
= src
[odv
[2]].fr_ofs
;
2263 else if ((src
[odv
[0]].fr_reg
== spreg
)
2264 && (src
[odv
[2]].fr_reg
== spreg
))
2266 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2267 cache
->c0
.c0_fpalign
= src
[odv
[1]].fr_ofs
;
2270 /* else fall through. */
2272 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2274 dst
[odv
[0]].fr_reg
= src
[odv
[2]].fr_reg
;
2275 dst
[odv
[0]].fr_ofs
= src
[odv
[2]].fr_ofs
& src
[odv
[1]].fr_ofs
;
2277 else if (src
[odv
[2]].fr_reg
== C0_CONST
)
2279 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2280 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
& src
[odv
[2]].fr_ofs
;
2282 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2285 /* 3 operands: dst, src1, src2. */
2286 gdb_assert (nods
== 3);
2287 if (src
[odv
[2]].fr_reg
== C0_CONST
)
2289 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2290 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
- src
[odv
[2]].fr_ofs
;
2292 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2295 /* 2 operands: dst, src [, src]. */
2296 gdb_assert (nods
== 2);
2297 /* First, check if it's a special case of saving unaligned SP
2298 to a spare register in case of dynamic stack adjustment.
2299 But, only do it one time. The second time could be initializing
2300 frame pointer. We don't want to overwrite the first one. */
2301 if ((odv
[1] == spreg
) && (cache
->c0
.c0_old_sp
== C0_INEXP
))
2302 cache
->c0
.c0_old_sp
= odv
[0];
2304 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2305 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
;
2308 /* 2 operands: dst, imm. */
2309 gdb_assert (nods
== 2);
2310 dst
[odv
[0]].fr_reg
= C0_CONST
;
2311 dst
[odv
[0]].fr_ofs
= odv
[1];
2314 /* 2 operands: dst, literal offset. */
2315 gdb_assert (nods
== 2);
2316 /* litbase = xtensa_get_litbase (pc); can be also used. */
2317 litbase
= (gdbarch_tdep (gdbarch
)->litbase_regnum
== -1)
2318 ? 0 : xtensa_read_register
2319 (gdbarch_tdep (gdbarch
)->litbase_regnum
);
2320 litaddr
= litbase
& 1
2321 ? (litbase
& ~1) + (signed)odv
[1]
2322 : (pc
+ 3 + (signed)odv
[1]) & ~3;
2323 litval
= read_memory_integer (litaddr
, 4, byte_order
);
2324 dst
[odv
[0]].fr_reg
= C0_CONST
;
2325 dst
[odv
[0]].fr_ofs
= litval
;
2328 /* 3 operands: value, base, offset. */
2329 gdb_assert (nods
== 3 && spreg
>= 0 && spreg
< C0_NREGS
);
2330 /* First, check if it's a spill for saved unaligned SP,
2331 when dynamic stack adjustment was applied to this frame. */
2332 if ((cache
->c0
.c0_fpalign
!= 0) /* Dynamic stack adjustment. */
2333 && (odv
[1] == spreg
) /* SP usage indicates spill. */
2334 && (odv
[0] == cache
->c0
.c0_old_sp
)) /* Old SP register spilled. */
2335 cache
->c0
.c0_sp_ofs
= odv
[2];
2337 if (src
[odv
[1]].fr_reg
== spreg
/* Store to stack frame. */
2338 && (src
[odv
[1]].fr_ofs
& 3) == 0 /* Alignment preserved. */
2339 && src
[odv
[0]].fr_reg
>= 0 /* Value is from a register. */
2340 && src
[odv
[0]].fr_ofs
== 0 /* Value hasn't been modified. */
2341 && src
[src
[odv
[0]].fr_reg
].to_stk
== C0_NOSTK
) /* First time. */
2343 /* ISA encoding guarantees alignment. But, check it anyway. */
2344 gdb_assert ((odv
[2] & 3) == 0);
2345 dst
[src
[odv
[0]].fr_reg
].to_stk
= src
[odv
[1]].fr_ofs
+ odv
[2];
2348 /* If we end up inside Window Overflow / Underflow interrupt handler
2349 report an error because these handlers should have been handled
2350 already in a different way. */
2362 /* Analyze prologue of the function at start address to determine if it uses
2363 the Call0 ABI, and if so track register moves and linear modifications
2364 in the prologue up to the PC or just beyond the prologue, whichever is
2365 first. An 'entry' instruction indicates non-Call0 ABI and the end of the
2366 prologue. The prologue may overlap non-prologue instructions but is
2367 guaranteed to end by the first flow-control instruction (jump, branch,
2368 call or return). Since an optimized function may move information around
2369 and change the stack frame arbitrarily during the prologue, the information
2370 is guaranteed valid only at the point in the function indicated by the PC.
2371 May be used to skip the prologue or identify the ABI, w/o tracking.
2373 Returns: Address of first instruction after prologue, or PC (whichever
2374 is first), or 0, if decoding failed (in libisa).
2376 start Start address of function/prologue.
2377 pc Program counter to stop at. Use 0 to continue to end of prologue.
2378 If 0, avoids infinite run-on in corrupt code memory by bounding
2379 the scan to the end of the function if that can be determined.
2380 nregs Number of general registers to track.
2382 cache Xtensa frame cache.
2384 Note that these may produce useful results even if decoding fails
2385 because they begin with default assumptions that analysis may change. */
2388 call0_analyze_prologue (struct gdbarch
*gdbarch
,
2389 CORE_ADDR start
, CORE_ADDR pc
,
2390 int nregs
, xtensa_frame_cache_t
*cache
)
2392 CORE_ADDR ia
; /* Current insn address in prologue. */
2393 CORE_ADDR ba
= 0; /* Current address at base of insn buffer. */
2394 CORE_ADDR bt
; /* Current address at top+1 of insn buffer. */
2395 char ibuf
[XTENSA_ISA_BSZ
];/* Instruction buffer for decoding prologue. */
2396 xtensa_isa isa
; /* libisa ISA handle. */
2397 xtensa_insnbuf ins
, slot
; /* libisa handle to decoded insn, slot. */
2398 xtensa_format ifmt
; /* libisa instruction format. */
2399 int ilen
, islots
, is
; /* Instruction length, nbr slots, current slot. */
2400 xtensa_opcode opc
; /* Opcode in current slot. */
2401 xtensa_insn_kind opclass
; /* Opcode class for Call0 prologue analysis. */
2402 int nods
; /* Opcode number of operands. */
2403 unsigned odv
[C0_MAXOPDS
]; /* Operand values in order provided by libisa. */
2404 xtensa_c0reg_t
*rtmp
; /* Register tracking info snapshot. */
2405 int j
; /* General loop counter. */
2406 int fail
= 0; /* Set non-zero and exit, if decoding fails. */
2407 CORE_ADDR body_pc
; /* The PC for the first non-prologue insn. */
2408 CORE_ADDR end_pc
; /* The PC for the lust function insn. */
2410 struct symtab_and_line prologue_sal
;
2412 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2413 (int)start
, (int)pc
);
2415 /* Try to limit the scan to the end of the function if a non-zero pc
2416 arg was not supplied to avoid probing beyond the end of valid memory.
2417 If memory is full of garbage that classifies as c0opc_uninteresting.
2418 If this fails (eg. if no symbols) pc ends up 0 as it was.
2419 Intialize the Call0 frame and register tracking info.
2420 Assume it's Call0 until an 'entry' instruction is encountered.
2421 Assume we may be in the prologue until we hit a flow control instr. */
2427 /* Find out, if we have an information about the prologue from DWARF. */
2428 prologue_sal
= find_pc_line (start
, 0);
2429 if (prologue_sal
.line
!= 0) /* Found debug info. */
2430 body_pc
= prologue_sal
.end
;
2432 /* If we are going to analyze the prologue in general without knowing about
2433 the current PC, make the best assumtion for the end of the prologue. */
2436 find_pc_partial_function (start
, 0, NULL
, &end_pc
);
2437 body_pc
= min (end_pc
, body_pc
);
2440 body_pc
= min (pc
, body_pc
);
2443 rtmp
= (xtensa_c0reg_t
*) alloca(nregs
* sizeof(xtensa_c0reg_t
));
2445 if (!xtensa_default_isa
)
2446 xtensa_default_isa
= xtensa_isa_init (0, 0);
2447 isa
= xtensa_default_isa
;
2448 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2449 ins
= xtensa_insnbuf_alloc (isa
);
2450 slot
= xtensa_insnbuf_alloc (isa
);
2452 for (ia
= start
, bt
= ia
; ia
< body_pc
; ia
+= ilen
)
2454 /* (Re)fill instruction buffer from memory if necessary, but do not
2455 read memory beyond PC to be sure we stay within text section
2456 (this protection only works if a non-zero pc is supplied). */
2458 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2461 bt
= (ba
+ XTENSA_ISA_BSZ
) < body_pc
? ba
+ XTENSA_ISA_BSZ
: body_pc
;
2462 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0 )
2463 error (_("Unable to read target memory ..."));
2466 /* Decode format information. */
2468 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2469 ifmt
= xtensa_format_decode (isa
, ins
);
2470 if (ifmt
== XTENSA_UNDEFINED
)
2475 ilen
= xtensa_format_length (isa
, ifmt
);
2476 if (ilen
== XTENSA_UNDEFINED
)
2481 islots
= xtensa_format_num_slots (isa
, ifmt
);
2482 if (islots
== XTENSA_UNDEFINED
)
2488 /* Analyze a bundle or a single instruction, using a snapshot of
2489 the register tracking info as input for the entire bundle so that
2490 register changes do not take effect within this bundle. */
2492 for (j
= 0; j
< nregs
; ++j
)
2493 rtmp
[j
] = cache
->c0
.c0_rt
[j
];
2495 for (is
= 0; is
< islots
; ++is
)
2497 /* Decode a slot and classify the opcode. */
2499 fail
= xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
);
2503 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2504 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2506 if (opc
== XTENSA_UNDEFINED
)
2507 opclass
= c0opc_illegal
;
2509 opclass
= call0_classify_opcode (isa
, opc
);
2511 /* Decide whether to track this opcode, ignore it, or bail out. */
2520 case c0opc_uninteresting
:
2523 case c0opc_flow
: /* Flow control instructions stop analysis. */
2524 case c0opc_rwxsr
: /* RSR, WSR, XSR instructions stop analysis. */
2529 ia
+= ilen
; /* Skip over 'entry' insn. */
2536 /* Only expected opcodes should get this far. */
2538 /* Extract and decode the operands. */
2539 nods
= xtensa_opcode_num_operands (isa
, opc
);
2540 if (nods
== XTENSA_UNDEFINED
)
2546 for (j
= 0; j
< nods
&& j
< C0_MAXOPDS
; ++j
)
2548 fail
= xtensa_operand_get_field (isa
, opc
, j
, ifmt
,
2553 fail
= xtensa_operand_decode (isa
, opc
, j
, &odv
[j
]);
2558 /* Check operands to verify use of 'mov' assembler macro. */
2559 if (opclass
== c0opc_mov
&& nods
== 3)
2561 if (odv
[2] == odv
[1])
2564 if ((odv
[0] == 1) && (odv
[1] != 1))
2565 /* OR A1, An, An , where n != 1.
2566 This means we are inside epilogue already. */
2571 opclass
= c0opc_uninteresting
;
2576 /* Track register movement and modification for this operation. */
2577 fail
= call0_track_op (gdbarch
, cache
->c0
.c0_rt
, rtmp
,
2578 opclass
, nods
, odv
, ia
, 1, cache
);
2584 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2585 (unsigned)ia
, fail
? "failed" : "succeeded");
2586 xtensa_insnbuf_free(isa
, slot
);
2587 xtensa_insnbuf_free(isa
, ins
);
2588 return fail
? XTENSA_ISA_BADPC
: ia
;
2591 /* Initialize frame cache for the current frame in CALL0 ABI. */
2594 call0_frame_cache (struct frame_info
*this_frame
,
2595 xtensa_frame_cache_t
*cache
, CORE_ADDR pc
)
2597 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2598 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2599 CORE_ADDR start_pc
; /* The beginning of the function. */
2600 CORE_ADDR body_pc
=UINT_MAX
; /* PC, where prologue analysis stopped. */
2601 CORE_ADDR sp
, fp
, ra
;
2602 int fp_regnum
= C0_SP
, c0_hasfp
= 0, c0_frmsz
= 0, prev_sp
= 0, to_stk
;
2604 sp
= get_frame_register_unsigned
2605 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
2606 fp
= sp
; /* Assume FP == SP until proven otherwise. */
2608 /* Find the beginning of the prologue of the function containing the PC
2609 and analyze it up to the PC or the end of the prologue. */
2611 if (find_pc_partial_function (pc
, NULL
, &start_pc
, NULL
))
2613 body_pc
= call0_analyze_prologue (gdbarch
, start_pc
, pc
, C0_NREGS
, cache
);
2615 if (body_pc
== XTENSA_ISA_BADPC
)
2619 goto finish_frame_analysis
;
2623 /* Get the frame information and FP (if used) at the current PC.
2624 If PC is in the prologue, the prologue analysis is more reliable
2625 than DWARF info. We don't not know for sure, if PC is in the prologue,
2626 but we do know no calls have yet taken place, so we can almost
2627 certainly rely on the prologue analysis. */
2631 /* Prologue analysis was successful up to the PC.
2632 It includes the cases when PC == START_PC. */
2633 c0_hasfp
= cache
->c0
.c0_rt
[C0_FP
].fr_reg
== C0_SP
;
2634 /* c0_hasfp == true means there is a frame pointer because
2635 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2636 was derived from SP. Otherwise, it would be C0_FP. */
2637 fp_regnum
= c0_hasfp
? C0_FP
: C0_SP
;
2638 c0_frmsz
= - cache
->c0
.c0_rt
[fp_regnum
].fr_ofs
;
2639 fp_regnum
+= gdbarch_tdep (gdbarch
)->a0_base
;
2641 else /* No data from the prologue analysis. */
2644 fp_regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_SP
;
2649 if (cache
->c0
.c0_fpalign
)
2651 /* This frame has a special prologue with a dynamic stack adjustment
2652 to force an alignment, which is bigger than standard 16 bytes. */
2654 CORE_ADDR unaligned_sp
;
2656 if (cache
->c0
.c0_old_sp
== C0_INEXP
)
2657 /* This can't be. Prologue code should be consistent.
2658 Unaligned stack pointer should be saved in a spare register. */
2662 goto finish_frame_analysis
;
2665 if (cache
->c0
.c0_sp_ofs
== C0_NOSTK
)
2666 /* Saved unaligned value of SP is kept in a register. */
2667 unaligned_sp
= get_frame_register_unsigned
2668 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ cache
->c0
.c0_old_sp
);
2670 /* Get the value from stack. */
2671 unaligned_sp
= (CORE_ADDR
)
2672 read_memory_integer (fp
+ cache
->c0
.c0_sp_ofs
, 4, byte_order
);
2674 prev_sp
= unaligned_sp
+ c0_frmsz
;
2677 prev_sp
= fp
+ c0_frmsz
;
2679 /* Frame size from debug info or prologue tracking does not account for
2680 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2683 fp
= get_frame_register_unsigned (this_frame
, fp_regnum
);
2685 /* Update the stack frame size. */
2686 c0_frmsz
+= fp
- sp
;
2689 /* Get the return address (RA) from the stack if saved,
2690 or try to get it from a register. */
2692 to_stk
= cache
->c0
.c0_rt
[C0_RA
].to_stk
;
2693 if (to_stk
!= C0_NOSTK
)
2695 read_memory_integer (sp
+ c0_frmsz
+ cache
->c0
.c0_rt
[C0_RA
].to_stk
,
2698 else if (cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_CONST
2699 && cache
->c0
.c0_rt
[C0_RA
].fr_ofs
== 0)
2701 /* Special case for terminating backtrace at a function that wants to
2702 be seen as the outermost one. Such a function will clear it's RA (A0)
2703 register to 0 in the prologue instead of saving its original value. */
2708 /* RA was copied to another register or (before any function call) may
2709 still be in the original RA register. This is not always reliable:
2710 even in a leaf function, register tracking stops after prologue, and
2711 even in prologue, non-prologue instructions (not tracked) may overwrite
2712 RA or any register it was copied to. If likely in prologue or before
2713 any call, use retracking info and hope for the best (compiler should
2714 have saved RA in stack if not in a leaf function). If not in prologue,
2720 (i
== C0_RA
|| cache
->c0
.c0_rt
[i
].fr_reg
!= C0_RA
);
2722 if (i
>= C0_NREGS
&& cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_RA
)
2726 ra
= get_frame_register_unsigned
2728 gdbarch_tdep (gdbarch
)->a0_base
+ cache
->c0
.c0_rt
[i
].fr_reg
);
2733 finish_frame_analysis
:
2734 cache
->pc
= start_pc
;
2736 /* RA == 0 marks the outermost frame. Do not go past it. */
2737 cache
->prev_sp
= (ra
!= 0) ? prev_sp
: 0;
2738 cache
->c0
.fp_regnum
= fp_regnum
;
2739 cache
->c0
.c0_frmsz
= c0_frmsz
;
2740 cache
->c0
.c0_hasfp
= c0_hasfp
;
2741 cache
->c0
.c0_fp
= fp
;
2744 static CORE_ADDR a0_saved
;
2745 static CORE_ADDR a7_saved
;
2746 static CORE_ADDR a11_saved
;
2747 static int a0_was_saved
;
2748 static int a7_was_saved
;
2749 static int a11_was_saved
;
2751 /* Simulate L32E instruction: AT <-- ref (AS + offset). */
2753 execute_l32e (struct gdbarch
*gdbarch
, int at
, int as
, int offset
, CORE_ADDR wb
)
2755 int atreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ at
, wb
);
2756 int asreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ as
, wb
);
2757 CORE_ADDR addr
= xtensa_read_register (asreg
) + offset
;
2758 unsigned int spilled_value
2759 = read_memory_unsigned_integer (addr
, 4, gdbarch_byte_order (gdbarch
));
2761 if ((at
== 0) && !a0_was_saved
)
2763 a0_saved
= xtensa_read_register (atreg
);
2766 else if ((at
== 7) && !a7_was_saved
)
2768 a7_saved
= xtensa_read_register (atreg
);
2771 else if ((at
== 11) && !a11_was_saved
)
2773 a11_saved
= xtensa_read_register (atreg
);
2777 xtensa_write_register (atreg
, spilled_value
);
2780 /* Simulate S32E instruction: AT --> ref (AS + offset). */
2782 execute_s32e (struct gdbarch
*gdbarch
, int at
, int as
, int offset
, CORE_ADDR wb
)
2784 int atreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ at
, wb
);
2785 int asreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ as
, wb
);
2786 CORE_ADDR addr
= xtensa_read_register (asreg
) + offset
;
2787 ULONGEST spilled_value
= xtensa_read_register (atreg
);
2789 write_memory_unsigned_integer (addr
, 4,
2790 gdbarch_byte_order (gdbarch
),
2794 #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2800 xtNoExceptionHandler
2801 } xtensa_exception_handler_t
;
2803 /* Execute instruction stream from current PC until hitting RFWU or RFWO.
2804 Return type of Xtensa Window Interrupt Handler on success. */
2805 static xtensa_exception_handler_t
2806 execute_code (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
, CORE_ADDR wb
)
2809 xtensa_insnbuf ins
, slot
;
2810 char ibuf
[XTENSA_ISA_BSZ
];
2811 CORE_ADDR ia
, bt
, ba
;
2813 int ilen
, islots
, is
;
2817 void (*func
) (struct gdbarch
*, int, int, int, CORE_ADDR
);
2822 /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
2823 int WindowUnderflow12
= (current_pc
& 0x1ff) >= 0x140;
2825 isa
= xtensa_default_isa
;
2826 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2827 ins
= xtensa_insnbuf_alloc (isa
);
2828 slot
= xtensa_insnbuf_alloc (isa
);
2837 while (insn_num
++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN
)
2839 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2842 bt
= (ba
+ XTENSA_ISA_BSZ
);
2843 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0)
2844 return xtNoExceptionHandler
;
2846 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2847 ifmt
= xtensa_format_decode (isa
, ins
);
2848 if (ifmt
== XTENSA_UNDEFINED
)
2849 return xtNoExceptionHandler
;
2850 ilen
= xtensa_format_length (isa
, ifmt
);
2851 if (ilen
== XTENSA_UNDEFINED
)
2852 return xtNoExceptionHandler
;
2853 islots
= xtensa_format_num_slots (isa
, ifmt
);
2854 if (islots
== XTENSA_UNDEFINED
)
2855 return xtNoExceptionHandler
;
2856 for (is
= 0; is
< islots
; ++is
)
2858 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
2859 return xtNoExceptionHandler
;
2860 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2861 if (opc
== XTENSA_UNDEFINED
)
2862 return xtNoExceptionHandler
;
2863 switch (call0_classify_opcode (isa
, opc
))
2869 /* We expect none of them here. */
2870 return xtNoExceptionHandler
;
2872 func
= execute_l32e
;
2875 func
= execute_s32e
;
2877 case c0opc_rfwo
: /* RFWO. */
2878 /* Here, we return from WindowOverflow handler and,
2879 if we stopped at the very beginning, which means
2880 A0 was saved, we have to restore it now. */
2883 int arreg
= arreg_number (gdbarch
,
2884 gdbarch_tdep (gdbarch
)->a0_base
,
2886 xtensa_write_register (arreg
, a0_saved
);
2888 return xtWindowOverflow
;
2889 case c0opc_rfwu
: /* RFWU. */
2890 /* Here, we return from WindowUnderflow handler.
2891 Let's see if either A7 or A11 has to be restored. */
2892 if (WindowUnderflow12
)
2896 int arreg
= arreg_number (gdbarch
,
2897 gdbarch_tdep (gdbarch
)->a0_base
+ 11,
2899 xtensa_write_register (arreg
, a11_saved
);
2902 else if (a7_was_saved
)
2904 int arreg
= arreg_number (gdbarch
,
2905 gdbarch_tdep (gdbarch
)->a0_base
+ 7,
2907 xtensa_write_register (arreg
, a7_saved
);
2909 return xtWindowUnderflow
;
2910 default: /* Simply skip this insns. */
2914 /* Decode arguments for L32E / S32E and simulate their execution. */
2915 if ( xtensa_opcode_num_operands (isa
, opc
) != 3 )
2916 return xtNoExceptionHandler
;
2917 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
, &at
))
2918 return xtNoExceptionHandler
;
2919 if (xtensa_operand_decode (isa
, opc
, 0, &at
))
2920 return xtNoExceptionHandler
;
2921 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
, is
, slot
, &as
))
2922 return xtNoExceptionHandler
;
2923 if (xtensa_operand_decode (isa
, opc
, 1, &as
))
2924 return xtNoExceptionHandler
;
2925 if (xtensa_operand_get_field (isa
, opc
, 2, ifmt
, is
, slot
, &offset
))
2926 return xtNoExceptionHandler
;
2927 if (xtensa_operand_decode (isa
, opc
, 2, &offset
))
2928 return xtNoExceptionHandler
;
2930 (*func
) (gdbarch
, at
, as
, offset
, wb
);
2935 return xtNoExceptionHandler
;
2938 /* Handle Window Overflow / Underflow exception frames. */
2941 xtensa_window_interrupt_frame_cache (struct frame_info
*this_frame
,
2942 xtensa_frame_cache_t
*cache
,
2945 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2946 CORE_ADDR ps
, wb
, ws
, ra
;
2947 int epc1_regnum
, i
, regnum
;
2948 xtensa_exception_handler_t eh_type
;
2950 /* Read PS, WB, and WS from the hardware. Note that PS register
2951 must be present, if Windowed ABI is supported. */
2952 ps
= xtensa_read_register (gdbarch_ps_regnum (gdbarch
));
2953 wb
= xtensa_read_register (gdbarch_tdep (gdbarch
)->wb_regnum
);
2954 ws
= xtensa_read_register (gdbarch_tdep (gdbarch
)->ws_regnum
);
2956 /* Execute all the remaining instructions from Window Interrupt Handler
2957 by simulating them on the remote protocol level. On return, set the
2958 type of Xtensa Window Interrupt Handler, or report an error. */
2959 eh_type
= execute_code (gdbarch
, pc
, wb
);
2960 if (eh_type
== xtNoExceptionHandler
)
2962 Unable to decode Xtensa Window Interrupt Handler's code."));
2964 cache
->ps
= ps
^ PS_EXC
; /* Clear the exception bit in PS. */
2965 cache
->call0
= 0; /* It's Windowed ABI. */
2967 /* All registers for the cached frame will be alive. */
2968 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
2969 cache
->wd
.aregs
[i
] = -1;
2971 if (eh_type
== xtWindowOverflow
)
2972 cache
->wd
.ws
= ws
^ (1 << wb
);
2973 else /* eh_type == xtWindowUnderflow. */
2974 cache
->wd
.ws
= ws
| (1 << wb
);
2976 cache
->wd
.wb
= (ps
& 0xf00) >> 8; /* Set WB to OWB. */
2977 regnum
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
,
2979 ra
= xtensa_read_register (regnum
);
2980 cache
->wd
.callsize
= WINSIZE (ra
);
2981 cache
->prev_sp
= xtensa_read_register (regnum
+ 1);
2982 /* Set regnum to a frame pointer of the frame being cached. */
2983 regnum
= xtensa_scan_prologue (gdbarch
, pc
);
2984 regnum
= arreg_number (gdbarch
,
2985 gdbarch_tdep (gdbarch
)->a0_base
+ regnum
,
2987 cache
->base
= get_frame_register_unsigned (this_frame
, regnum
);
2989 /* Read PC of interrupted function from EPC1 register. */
2990 epc1_regnum
= xtensa_find_register_by_name (gdbarch
,"epc1");
2991 if (epc1_regnum
< 0)
2992 error(_("Unable to read Xtensa register EPC1"));
2993 cache
->ra
= xtensa_read_register (epc1_regnum
);
2994 cache
->pc
= get_frame_func (this_frame
);
2998 /* Skip function prologue.
3000 Return the pc of the first instruction after prologue. GDB calls this to
3001 find the address of the first line of the function or (if there is no line
3002 number information) to skip the prologue for planting breakpoints on
3003 function entries. Use debug info (if present) or prologue analysis to skip
3004 the prologue to achieve reliable debugging behavior. For windowed ABI,
3005 only the 'entry' instruction is skipped. It is not strictly necessary to
3006 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
3007 backtrace at any point in the prologue, however certain potential hazards
3008 are avoided and a more "normal" debugging experience is ensured by
3009 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
3010 For example, if we don't skip the prologue:
3011 - Some args may not yet have been saved to the stack where the debug
3012 info expects to find them (true anyway when only 'entry' is skipped);
3013 - Software breakpoints ('break' instrs) may not have been unplanted
3014 when the prologue analysis is done on initializing the frame cache,
3015 and breaks in the prologue will throw off the analysis.
3017 If we have debug info ( line-number info, in particular ) we simply skip
3018 the code associated with the first function line effectively skipping
3019 the prologue code. It works even in cases like
3022 { int local_var = 1;
3026 because, for this source code, both Xtensa compilers will generate two
3027 separate entries ( with the same line number ) in dwarf line-number
3028 section to make sure there is a boundary between the prologue code and
3029 the rest of the function.
3031 If there is no debug info, we need to analyze the code. */
3033 /* #define DONT_SKIP_PROLOGUE */
3036 xtensa_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
3038 struct symtab_and_line prologue_sal
;
3041 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc
);
3043 #if DONT_SKIP_PROLOGUE
3047 /* Try to find first body line from debug info. */
3049 prologue_sal
= find_pc_line (start_pc
, 0);
3050 if (prologue_sal
.line
!= 0) /* Found debug info. */
3052 /* In Call0, it is possible to have a function with only one instruction
3053 ('ret') resulting from a one-line optimized function that does nothing.
3054 In that case, prologue_sal.end may actually point to the start of the
3055 next function in the text section, causing a breakpoint to be set at
3056 the wrong place. Check, if the end address is within a different
3057 function, and if so return the start PC. We know we have symbol
3062 if ((gdbarch_tdep (gdbarch
)->call_abi
== CallAbiCall0Only
)
3063 && call0_ret (start_pc
, prologue_sal
.end
))
3066 find_pc_partial_function (prologue_sal
.end
, NULL
, &end_func
, NULL
);
3067 if (end_func
!= start_pc
)
3070 return prologue_sal
.end
;
3073 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
3074 body_pc
= call0_analyze_prologue (gdbarch
, start_pc
, 0, 0,
3075 xtensa_alloc_frame_cache (0));
3076 return body_pc
!= 0 ? body_pc
: start_pc
;
3079 /* Verify the current configuration. */
3081 xtensa_verify_config (struct gdbarch
*gdbarch
)
3083 struct ui_file
*log
;
3084 struct cleanup
*cleanups
;
3085 struct gdbarch_tdep
*tdep
;
3089 tdep
= gdbarch_tdep (gdbarch
);
3090 log
= mem_fileopen ();
3091 cleanups
= make_cleanup_ui_file_delete (log
);
3093 /* Verify that we got a reasonable number of AREGS. */
3094 if ((tdep
->num_aregs
& -tdep
->num_aregs
) != tdep
->num_aregs
)
3095 fprintf_unfiltered (log
, _("\
3096 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
3099 /* Verify that certain registers exist. */
3101 if (tdep
->pc_regnum
== -1)
3102 fprintf_unfiltered (log
, _("\n\tpc_regnum: No PC register"));
3103 if (tdep
->isa_use_exceptions
&& tdep
->ps_regnum
== -1)
3104 fprintf_unfiltered (log
, _("\n\tps_regnum: No PS register"));
3106 if (tdep
->isa_use_windowed_registers
)
3108 if (tdep
->wb_regnum
== -1)
3109 fprintf_unfiltered (log
, _("\n\twb_regnum: No WB register"));
3110 if (tdep
->ws_regnum
== -1)
3111 fprintf_unfiltered (log
, _("\n\tws_regnum: No WS register"));
3112 if (tdep
->ar_base
== -1)
3113 fprintf_unfiltered (log
, _("\n\tar_base: No AR registers"));
3116 if (tdep
->a0_base
== -1)
3117 fprintf_unfiltered (log
, _("\n\ta0_base: No Ax registers"));
3119 buf
= ui_file_xstrdup (log
, &length
);
3120 make_cleanup (xfree
, buf
);
3122 internal_error (__FILE__
, __LINE__
,
3123 _("the following are invalid: %s"), buf
);
3124 do_cleanups (cleanups
);
3128 /* Derive specific register numbers from the array of registers. */
3131 xtensa_derive_tdep (struct gdbarch_tdep
*tdep
)
3133 xtensa_register_t
* rmap
;
3134 int n
, max_size
= 4;
3137 tdep
->num_nopriv_regs
= 0;
3139 /* Special registers 0..255 (core). */
3140 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
3142 for (rmap
= tdep
->regmap
, n
= 0; rmap
->target_number
!= -1; n
++, rmap
++)
3144 if (rmap
->target_number
== 0x0020)
3145 tdep
->pc_regnum
= n
;
3146 else if (rmap
->target_number
== 0x0100)
3148 else if (rmap
->target_number
== 0x0000)
3150 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(72))
3151 tdep
->wb_regnum
= n
;
3152 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(73))
3153 tdep
->ws_regnum
= n
;
3154 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(233))
3155 tdep
->debugcause_regnum
= n
;
3156 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(232))
3157 tdep
->exccause_regnum
= n
;
3158 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(238))
3159 tdep
->excvaddr_regnum
= n
;
3160 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(0))
3161 tdep
->lbeg_regnum
= n
;
3162 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(1))
3163 tdep
->lend_regnum
= n
;
3164 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(2))
3165 tdep
->lcount_regnum
= n
;
3166 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(3))
3167 tdep
->sar_regnum
= n
;
3168 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(5))
3169 tdep
->litbase_regnum
= n
;
3170 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(230))
3171 tdep
->ps_regnum
= n
;
3173 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(226))
3174 tdep
->interrupt_regnum
= n
;
3175 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(227))
3176 tdep
->interrupt2_regnum
= n
;
3177 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(224))
3178 tdep
->cpenable_regnum
= n
;
3181 if (rmap
->byte_size
> max_size
)
3182 max_size
= rmap
->byte_size
;
3183 if (rmap
->mask
!= 0 && tdep
->num_regs
== 0)
3185 /* Find out out how to deal with priveleged registers.
3187 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3188 && tdep->num_nopriv_regs == 0)
3189 tdep->num_nopriv_regs = n;
3191 if ((rmap
->flags
& XTENSA_REGISTER_FLAGS_PRIVILEGED
) != 0
3192 && tdep
->num_regs
== 0)
3196 /* Number of pseudo registers. */
3197 tdep
->num_pseudo_regs
= n
- tdep
->num_regs
;
3199 /* Empirically determined maximum sizes. */
3200 tdep
->max_register_raw_size
= max_size
;
3201 tdep
->max_register_virtual_size
= max_size
;
3204 /* Module "constructor" function. */
3206 extern struct gdbarch_tdep xtensa_tdep
;
3208 static struct gdbarch
*
3209 xtensa_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3211 struct gdbarch_tdep
*tdep
;
3212 struct gdbarch
*gdbarch
;
3213 struct xtensa_abi_handler
*abi_handler
;
3215 DEBUGTRACE ("gdbarch_init()\n");
3217 /* We have to set the byte order before we call gdbarch_alloc. */
3218 info
.byte_order
= XCHAL_HAVE_BE
? BFD_ENDIAN_BIG
: BFD_ENDIAN_LITTLE
;
3220 tdep
= &xtensa_tdep
;
3221 gdbarch
= gdbarch_alloc (&info
, tdep
);
3222 xtensa_derive_tdep (tdep
);
3224 /* Verify our configuration. */
3225 xtensa_verify_config (gdbarch
);
3226 xtensa_session_once_reported
= 0;
3228 /* Pseudo-Register read/write. */
3229 set_gdbarch_pseudo_register_read (gdbarch
, xtensa_pseudo_register_read
);
3230 set_gdbarch_pseudo_register_write (gdbarch
, xtensa_pseudo_register_write
);
3232 /* Set target information. */
3233 set_gdbarch_num_regs (gdbarch
, tdep
->num_regs
);
3234 set_gdbarch_num_pseudo_regs (gdbarch
, tdep
->num_pseudo_regs
);
3235 set_gdbarch_sp_regnum (gdbarch
, tdep
->a0_base
+ 1);
3236 set_gdbarch_pc_regnum (gdbarch
, tdep
->pc_regnum
);
3237 set_gdbarch_ps_regnum (gdbarch
, tdep
->ps_regnum
);
3239 /* Renumber registers for known formats (stabs and dwarf2). */
3240 set_gdbarch_stab_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
3241 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
3243 /* We provide our own function to get register information. */
3244 set_gdbarch_register_name (gdbarch
, xtensa_register_name
);
3245 set_gdbarch_register_type (gdbarch
, xtensa_register_type
);
3247 /* To call functions from GDB using dummy frame. */
3248 set_gdbarch_push_dummy_call (gdbarch
, xtensa_push_dummy_call
);
3250 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
3252 set_gdbarch_return_value (gdbarch
, xtensa_return_value
);
3254 /* Advance PC across any prologue instructions to reach "real" code. */
3255 set_gdbarch_skip_prologue (gdbarch
, xtensa_skip_prologue
);
3257 /* Stack grows downward. */
3258 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3260 /* Set breakpoints. */
3261 set_gdbarch_breakpoint_from_pc (gdbarch
, xtensa_breakpoint_from_pc
);
3263 /* After breakpoint instruction or illegal instruction, pc still
3264 points at break instruction, so don't decrement. */
3265 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
3267 /* We don't skip args. */
3268 set_gdbarch_frame_args_skip (gdbarch
, 0);
3270 set_gdbarch_unwind_pc (gdbarch
, xtensa_unwind_pc
);
3272 set_gdbarch_frame_align (gdbarch
, xtensa_frame_align
);
3274 set_gdbarch_dummy_id (gdbarch
, xtensa_dummy_id
);
3276 /* Frame handling. */
3277 frame_base_set_default (gdbarch
, &xtensa_frame_base
);
3278 frame_unwind_append_unwinder (gdbarch
, &xtensa_unwind
);
3279 dwarf2_append_unwinders (gdbarch
);
3281 set_gdbarch_print_insn (gdbarch
, print_insn_xtensa
);
3283 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3285 xtensa_add_reggroups (gdbarch
);
3286 set_gdbarch_register_reggroup_p (gdbarch
, xtensa_register_reggroup_p
);
3288 set_gdbarch_regset_from_core_section (gdbarch
,
3289 xtensa_regset_from_core_section
);
3291 set_solib_svr4_fetch_link_map_offsets
3292 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
3298 xtensa_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3300 error (_("xtensa_dump_tdep(): not implemented"));
3303 /* Provide a prototype to silence -Wmissing-prototypes. */
3304 extern initialize_file_ftype _initialize_xtensa_tdep
;
3307 _initialize_xtensa_tdep (void)
3309 struct cmd_list_element
*c
;
3311 gdbarch_register (bfd_arch_xtensa
, xtensa_gdbarch_init
, xtensa_dump_tdep
);
3312 xtensa_init_reggroups ();
3314 add_setshow_zinteger_cmd ("xtensa",
3316 &xtensa_debug_level
,
3317 _("Set Xtensa debugging."),
3318 _("Show Xtensa debugging."), _("\
3319 When non-zero, Xtensa-specific debugging is enabled. \
3320 Can be 1, 2, 3, or 4 indicating the level of debugging."),
3323 &setdebuglist
, &showdebuglist
);