1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "solib-svr4.h"
32 #include "floatformat.h"
34 #include "reggroups.h"
37 #include "dummy-frame.h"
39 #include "dwarf2-frame.h"
40 #include "dwarf2loc.h"
42 #include "frame-base.h"
43 #include "frame-unwind.h"
45 #include "arch-utils.h"
52 #include "gdb_assert.h"
54 #include "xtensa-isa.h"
55 #include "xtensa-tdep.h"
56 #include "xtensa-config.h"
59 static int xtensa_debug_level
= 0;
61 #define DEBUGWARN(args...) \
62 if (xtensa_debug_level > 0) \
63 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
65 #define DEBUGINFO(args...) \
66 if (xtensa_debug_level > 1) \
67 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
69 #define DEBUGTRACE(args...) \
70 if (xtensa_debug_level > 2) \
71 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
73 #define DEBUGVERB(args...) \
74 if (xtensa_debug_level > 3) \
75 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
78 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
79 #define SP_ALIGNMENT 16
82 /* On Windowed ABI, we use a6 through a11 for passing arguments
83 to a function called by GDB because CALL4 is used. */
84 #define ARGS_NUM_REGS 6
85 #define REGISTER_SIZE 4
88 /* Extract the call size from the return address or PS register. */
89 #define PS_CALLINC_SHIFT 16
90 #define PS_CALLINC_MASK 0x00030000
91 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
92 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
94 /* On TX, hardware can be configured without Exception Option.
95 There is no PS register in this case. Inside XT-GDB, let us treat
96 it as a virtual read-only register always holding the same value. */
99 /* ABI-independent macros. */
100 #define ARG_NOF(gdbarch) \
101 (gdbarch_tdep (gdbarch)->call_abi \
102 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
103 #define ARG_1ST(gdbarch) \
104 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
105 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
106 : (gdbarch_tdep (gdbarch)->a0_base + 6))
108 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
109 indicates that the instruction is an ENTRY instruction. */
111 #define XTENSA_IS_ENTRY(gdbarch, op1) \
112 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
113 ? ((op1) == 0x6c) : ((op1) == 0x36))
115 #define XTENSA_ENTRY_LENGTH 3
117 /* windowing_enabled() returns true, if windowing is enabled.
118 WOE must be set to 1; EXCM to 0.
119 Note: We assume that EXCM is always 0 for XEA1. */
121 #define PS_WOE (1<<18)
122 #define PS_EXC (1<<4)
125 windowing_enabled (struct gdbarch
*gdbarch
, unsigned int ps
)
127 /* If we know CALL0 ABI is set explicitly, say it is Call0. */
128 if (gdbarch_tdep (gdbarch
)->call_abi
== CallAbiCall0Only
)
131 return ((ps
& PS_EXC
) == 0 && (ps
& PS_WOE
) != 0);
134 /* Convert a live A-register number to the corresponding AR-register
137 arreg_number (struct gdbarch
*gdbarch
, int a_regnum
, ULONGEST wb
)
139 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
142 arreg
= a_regnum
- tdep
->a0_base
;
143 arreg
+= (wb
& ((tdep
->num_aregs
- 1) >> 2)) << WB_SHIFT
;
144 arreg
&= tdep
->num_aregs
- 1;
146 return arreg
+ tdep
->ar_base
;
149 /* Convert a live AR-register number to the corresponding A-register order
150 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
152 areg_number (struct gdbarch
*gdbarch
, int ar_regnum
, unsigned int wb
)
154 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
157 areg
= ar_regnum
- tdep
->ar_base
;
158 if (areg
< 0 || areg
>= tdep
->num_aregs
)
160 areg
= (areg
- wb
* 4) & (tdep
->num_aregs
- 1);
161 return (areg
> 15) ? -1 : areg
;
164 static inline unsigned long
165 xtensa_read_register (int regnum
)
169 regcache_raw_read_unsigned (get_current_regcache (), regnum
, &value
);
170 return (unsigned long) value
;
174 xtensa_write_register (int regnum
, ULONGEST value
)
176 regcache_raw_write_unsigned (get_current_regcache (), regnum
, value
);
179 /* Return the window size of the previous call to the function from which we
182 This function is used to extract the return value after a called function
183 has returned to the caller. On Xtensa, the register that holds the return
184 value (from the perspective of the caller) depends on what call
185 instruction was used. For now, we are assuming that the call instruction
186 precedes the current address, so we simply analyze the call instruction.
187 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
188 method to call the inferior function. */
191 extract_call_winsize (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
193 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
198 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc
);
200 /* Read the previous instruction (should be a call[x]{4|8|12}. */
201 read_memory (pc
-3, buf
, 3);
202 insn
= extract_unsigned_integer (buf
, 3, byte_order
);
204 /* Decode call instruction:
206 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
207 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
209 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
210 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
212 if (byte_order
== BFD_ENDIAN_LITTLE
)
214 if (((insn
& 0xf) == 0x5) || ((insn
& 0xcf) == 0xc0))
215 winsize
= (insn
& 0x30) >> 2; /* 0, 4, 8, 12. */
219 if (((insn
>> 20) == 0x5) || (((insn
>> 16) & 0xf3) == 0x03))
220 winsize
= (insn
>> 16) & 0xc; /* 0, 4, 8, 12. */
226 /* REGISTER INFORMATION */
228 /* Find register by name. */
230 xtensa_find_register_by_name (struct gdbarch
*gdbarch
, char *name
)
234 for (i
= 0; i
< gdbarch_num_regs (gdbarch
)
235 + gdbarch_num_pseudo_regs (gdbarch
);
238 if (strcasecmp (gdbarch_tdep (gdbarch
)->regmap
[i
].name
, name
) == 0)
244 /* Returns the name of a register. */
246 xtensa_register_name (struct gdbarch
*gdbarch
, int regnum
)
248 /* Return the name stored in the register map. */
249 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
)
250 + gdbarch_num_pseudo_regs (gdbarch
))
251 return gdbarch_tdep (gdbarch
)->regmap
[regnum
].name
;
253 internal_error (__FILE__
, __LINE__
, _("invalid register %d"), regnum
);
257 /* Return the type of a register. Create a new type, if necessary. */
260 xtensa_register_type (struct gdbarch
*gdbarch
, int regnum
)
262 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
264 /* Return signed integer for ARx and Ax registers. */
265 if ((regnum
>= tdep
->ar_base
266 && regnum
< tdep
->ar_base
+ tdep
->num_aregs
)
267 || (regnum
>= tdep
->a0_base
268 && regnum
< tdep
->a0_base
+ 16))
269 return builtin_type (gdbarch
)->builtin_int
;
271 if (regnum
== gdbarch_pc_regnum (gdbarch
)
272 || regnum
== tdep
->a0_base
+ 1)
273 return builtin_type (gdbarch
)->builtin_data_ptr
;
275 /* Return the stored type for all other registers. */
276 else if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
)
277 + gdbarch_num_pseudo_regs (gdbarch
))
279 xtensa_register_t
* reg
= &tdep
->regmap
[regnum
];
281 /* Set ctype for this register (only the first time). */
285 struct ctype_cache
*tp
;
286 int size
= reg
->byte_size
;
288 /* We always use the memory representation,
289 even if the register width is smaller. */
293 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint8
;
297 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint16
;
301 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint32
;
305 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint64
;
309 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint128
;
313 for (tp
= tdep
->type_entries
; tp
!= NULL
; tp
= tp
->next
)
314 if (tp
->size
== size
)
319 char *name
= xmalloc (16);
320 tp
= xmalloc (sizeof (struct ctype_cache
));
321 tp
->next
= tdep
->type_entries
;
322 tdep
->type_entries
= tp
;
325 sprintf (name
, "int%d", size
* 8);
327 = arch_integer_type (gdbarch
, size
* 8, 1, xstrdup (name
));
330 reg
->ctype
= tp
->virtual_type
;
336 internal_error (__FILE__
, __LINE__
, _("invalid register number %d"), regnum
);
341 /* Return the 'local' register number for stubs, dwarf2, etc.
342 The debugging information enumerates registers starting from 0 for A0
343 to n for An. So, we only have to add the base number for A0. */
346 xtensa_reg_to_regnum (struct gdbarch
*gdbarch
, int regnum
)
350 if (regnum
>= 0 && regnum
< 16)
351 return gdbarch_tdep (gdbarch
)->a0_base
+ regnum
;
354 i
< gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
356 if (regnum
== gdbarch_tdep (gdbarch
)->regmap
[i
].target_number
)
359 internal_error (__FILE__
, __LINE__
,
360 _("invalid dwarf/stabs register number %d"), regnum
);
365 /* Write the bits of a masked register to the various registers.
366 Only the masked areas of these registers are modified; the other
367 fields are untouched. The size of masked registers is always less
368 than or equal to 32 bits. */
371 xtensa_register_write_masked (struct regcache
*regcache
,
372 xtensa_register_t
*reg
, const gdb_byte
*buffer
)
374 unsigned int value
[(MAX_REGISTER_SIZE
+ 3) / 4];
375 const xtensa_mask_t
*mask
= reg
->mask
;
377 int shift
= 0; /* Shift for next mask (mod 32). */
378 int start
, size
; /* Start bit and size of current mask. */
380 unsigned int *ptr
= value
;
381 unsigned int regval
, m
, mem
= 0;
383 int bytesize
= reg
->byte_size
;
384 int bitsize
= bytesize
* 8;
387 DEBUGTRACE ("xtensa_register_write_masked ()\n");
389 /* Copy the masked register to host byte-order. */
390 if (gdbarch_byte_order (get_regcache_arch (regcache
)) == BFD_ENDIAN_BIG
)
391 for (i
= 0; i
< bytesize
; i
++)
394 mem
|= (buffer
[bytesize
- i
- 1] << 24);
399 for (i
= 0; i
< bytesize
; i
++)
402 mem
|= (buffer
[i
] << 24);
407 /* We might have to shift the final value:
408 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
409 bytesize & 3 == x -> shift (4-x) * 8. */
411 *ptr
= mem
>> (((0 - bytesize
) & 3) * 8);
415 /* Write the bits to the masked areas of the other registers. */
416 for (i
= 0; i
< mask
->count
; i
++)
418 start
= mask
->mask
[i
].bit_start
;
419 size
= mask
->mask
[i
].bit_size
;
420 regval
= mem
>> shift
;
422 if ((shift
+= size
) > bitsize
)
423 error (_("size of all masks is larger than the register"));
432 regval
|= mem
<< (size
- shift
);
435 /* Make sure we have a valid register. */
436 r
= mask
->mask
[i
].reg_num
;
437 if (r
>= 0 && size
> 0)
439 /* Don't overwrite the unmasked areas. */
441 regcache_cooked_read_unsigned (regcache
, r
, &old_val
);
442 m
= 0xffffffff >> (32 - size
) << start
;
444 regval
= (regval
& m
) | (old_val
& ~m
);
445 regcache_cooked_write_unsigned (regcache
, r
, regval
);
451 /* Read a tie state or mapped registers. Read the masked areas
452 of the registers and assemble them into a single value. */
455 xtensa_register_read_masked (struct regcache
*regcache
,
456 xtensa_register_t
*reg
, gdb_byte
*buffer
)
458 unsigned int value
[(MAX_REGISTER_SIZE
+ 3) / 4];
459 const xtensa_mask_t
*mask
= reg
->mask
;
464 unsigned int *ptr
= value
;
465 unsigned int regval
, mem
= 0;
467 int bytesize
= reg
->byte_size
;
468 int bitsize
= bytesize
* 8;
471 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
472 reg
->name
== 0 ? "" : reg
->name
);
474 /* Assemble the register from the masked areas of other registers. */
475 for (i
= 0; i
< mask
->count
; i
++)
477 int r
= mask
->mask
[i
].reg_num
;
481 regcache_cooked_read_unsigned (regcache
, r
, &val
);
482 regval
= (unsigned int) val
;
487 start
= mask
->mask
[i
].bit_start
;
488 size
= mask
->mask
[i
].bit_size
;
493 regval
&= (0xffffffff >> (32 - size
));
495 mem
|= regval
<< shift
;
497 if ((shift
+= size
) > bitsize
)
498 error (_("size of all masks is larger than the register"));
509 mem
= regval
>> (size
- shift
);
516 /* Copy value to target byte order. */
520 if (gdbarch_byte_order (get_regcache_arch (regcache
)) == BFD_ENDIAN_BIG
)
521 for (i
= 0; i
< bytesize
; i
++)
525 buffer
[bytesize
- i
- 1] = mem
& 0xff;
529 for (i
= 0; i
< bytesize
; i
++)
533 buffer
[i
] = mem
& 0xff;
539 /* Read pseudo registers. */
542 xtensa_pseudo_register_read (struct gdbarch
*gdbarch
,
543 struct regcache
*regcache
,
547 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
549 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
550 regnum
, xtensa_register_name (gdbarch
, regnum
));
552 if (regnum
== gdbarch_num_regs (gdbarch
)
553 + gdbarch_num_pseudo_regs (gdbarch
) - 1)
554 regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ 1;
556 /* Read aliases a0..a15, if this is a Windowed ABI. */
557 if (gdbarch_tdep (gdbarch
)->isa_use_windowed_registers
558 && (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
)
559 && (regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15))
561 gdb_byte
*buf
= (gdb_byte
*) alloca (MAX_REGISTER_SIZE
);
563 regcache_raw_read (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, buf
);
564 regnum
= arreg_number (gdbarch
, regnum
,
565 extract_unsigned_integer (buf
, 4, byte_order
));
568 /* We can always read non-pseudo registers. */
569 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
570 regcache_raw_read (regcache
, regnum
, buffer
);
573 /* We have to find out how to deal with priveleged registers.
574 Let's treat them as pseudo-registers, but we cannot read/write them. */
576 else if (regnum
< gdbarch_tdep (gdbarch
)->a0_base
)
578 buffer
[0] = (gdb_byte
)0;
579 buffer
[1] = (gdb_byte
)0;
580 buffer
[2] = (gdb_byte
)0;
581 buffer
[3] = (gdb_byte
)0;
583 /* Pseudo registers. */
585 && regnum
< gdbarch_num_regs (gdbarch
)
586 + gdbarch_num_pseudo_regs (gdbarch
))
588 xtensa_register_t
*reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
589 xtensa_register_type_t type
= reg
->type
;
590 int flags
= gdbarch_tdep (gdbarch
)->target_flags
;
592 /* We cannot read Unknown or Unmapped registers. */
593 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
595 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
597 warning (_("cannot read register %s"),
598 xtensa_register_name (gdbarch
, regnum
));
603 /* Some targets cannot read TIE register files. */
604 else if (type
== xtRegisterTypeTieRegfile
)
606 /* Use 'fetch' to get register? */
607 if (flags
& xtTargetFlagsUseFetchStore
)
609 warning (_("cannot read register"));
613 /* On some targets (esp. simulators), we can always read the reg. */
614 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
616 warning (_("cannot read register"));
621 /* We can always read mapped registers. */
622 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
624 xtensa_register_read_masked (regcache
, reg
, buffer
);
628 /* Assume that we can read the register. */
629 regcache_raw_read (regcache
, regnum
, buffer
);
632 internal_error (__FILE__
, __LINE__
,
633 _("invalid register number %d"), regnum
);
637 /* Write pseudo registers. */
640 xtensa_pseudo_register_write (struct gdbarch
*gdbarch
,
641 struct regcache
*regcache
,
643 const gdb_byte
*buffer
)
645 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
647 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
648 regnum
, xtensa_register_name (gdbarch
, regnum
));
650 if (regnum
== gdbarch_num_regs (gdbarch
)
651 + gdbarch_num_pseudo_regs (gdbarch
) -1)
652 regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ 1;
654 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
655 if (gdbarch_tdep (gdbarch
)->isa_use_windowed_registers
656 && (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
)
657 && (regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15))
659 gdb_byte
*buf
= (gdb_byte
*) alloca (MAX_REGISTER_SIZE
);
662 regcache_raw_read (regcache
,
663 gdbarch_tdep (gdbarch
)->wb_regnum
, buf
);
664 regnum
= arreg_number (gdbarch
, regnum
,
665 extract_unsigned_integer (buf
, 4, byte_order
));
668 /* We can always write 'core' registers.
669 Note: We might have converted Ax->ARy. */
670 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
671 regcache_raw_write (regcache
, regnum
, buffer
);
673 /* We have to find out how to deal with priveleged registers.
674 Let's treat them as pseudo-registers, but we cannot read/write them. */
676 else if (regnum
< gdbarch_tdep (gdbarch
)->a0_base
)
680 /* Pseudo registers. */
682 && regnum
< gdbarch_num_regs (gdbarch
)
683 + gdbarch_num_pseudo_regs (gdbarch
))
685 xtensa_register_t
*reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
686 xtensa_register_type_t type
= reg
->type
;
687 int flags
= gdbarch_tdep (gdbarch
)->target_flags
;
689 /* On most targets, we cannot write registers
690 of type "Unknown" or "Unmapped". */
691 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
693 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
695 warning (_("cannot write register %s"),
696 xtensa_register_name (gdbarch
, regnum
));
701 /* Some targets cannot read TIE register files. */
702 else if (type
== xtRegisterTypeTieRegfile
)
704 /* Use 'store' to get register? */
705 if (flags
& xtTargetFlagsUseFetchStore
)
707 warning (_("cannot write register"));
711 /* On some targets (esp. simulators), we can always write
713 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
715 warning (_("cannot write register"));
720 /* We can always write mapped registers. */
721 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
723 xtensa_register_write_masked (regcache
, reg
, buffer
);
727 /* Assume that we can write the register. */
728 regcache_raw_write (regcache
, regnum
, buffer
);
731 internal_error (__FILE__
, __LINE__
,
732 _("invalid register number %d"), regnum
);
735 static inline char xtensa_hextochar (int xdigit
)
737 static char hex
[]="0123456789abcdef";
739 return hex
[xdigit
& 0x0f];
742 static struct reggroup
*xtensa_ar_reggroup
;
743 static struct reggroup
*xtensa_user_reggroup
;
744 static struct reggroup
*xtensa_vectra_reggroup
;
745 static struct reggroup
*xtensa_cp
[XTENSA_MAX_COPROCESSOR
];
748 xtensa_init_reggroups (void)
751 char cpname
[] = "cp0";
753 xtensa_ar_reggroup
= reggroup_new ("ar", USER_REGGROUP
);
754 xtensa_user_reggroup
= reggroup_new ("user", USER_REGGROUP
);
755 xtensa_vectra_reggroup
= reggroup_new ("vectra", USER_REGGROUP
);
757 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
759 cpname
[2] = xtensa_hextochar (i
);
760 xtensa_cp
[i
] = reggroup_new (cpname
, USER_REGGROUP
);
765 xtensa_add_reggroups (struct gdbarch
*gdbarch
)
769 /* Predefined groups. */
770 reggroup_add (gdbarch
, all_reggroup
);
771 reggroup_add (gdbarch
, save_reggroup
);
772 reggroup_add (gdbarch
, restore_reggroup
);
773 reggroup_add (gdbarch
, system_reggroup
);
774 reggroup_add (gdbarch
, vector_reggroup
);
775 reggroup_add (gdbarch
, general_reggroup
);
776 reggroup_add (gdbarch
, float_reggroup
);
778 /* Xtensa-specific groups. */
779 reggroup_add (gdbarch
, xtensa_ar_reggroup
);
780 reggroup_add (gdbarch
, xtensa_user_reggroup
);
781 reggroup_add (gdbarch
, xtensa_vectra_reggroup
);
783 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
784 reggroup_add (gdbarch
, xtensa_cp
[i
]);
788 xtensa_coprocessor_register_group (struct reggroup
*group
)
792 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
793 if (group
== xtensa_cp
[i
])
799 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
800 | XTENSA_REGISTER_FLAGS_WRITABLE \
801 | XTENSA_REGISTER_FLAGS_VOLATILE)
803 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
804 | XTENSA_REGISTER_FLAGS_WRITABLE)
807 xtensa_register_reggroup_p (struct gdbarch
*gdbarch
,
809 struct reggroup
*group
)
811 xtensa_register_t
* reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
812 xtensa_register_type_t type
= reg
->type
;
813 xtensa_register_group_t rg
= reg
->group
;
816 /* First, skip registers that are not visible to this target
817 (unknown and unmapped registers when not using ISS). */
819 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
821 if (group
== all_reggroup
)
823 if (group
== xtensa_ar_reggroup
)
824 return rg
& xtRegisterGroupAddrReg
;
825 if (group
== xtensa_user_reggroup
)
826 return rg
& xtRegisterGroupUser
;
827 if (group
== float_reggroup
)
828 return rg
& xtRegisterGroupFloat
;
829 if (group
== general_reggroup
)
830 return rg
& xtRegisterGroupGeneral
;
831 if (group
== float_reggroup
)
832 return rg
& xtRegisterGroupFloat
;
833 if (group
== system_reggroup
)
834 return rg
& xtRegisterGroupState
;
835 if (group
== vector_reggroup
|| group
== xtensa_vectra_reggroup
)
836 return rg
& xtRegisterGroupVectra
;
837 if (group
== save_reggroup
|| group
== restore_reggroup
)
838 return (regnum
< gdbarch_num_regs (gdbarch
)
839 && (reg
->flags
& SAVE_REST_FLAGS
) == SAVE_REST_VALID
);
840 if ((cp_number
= xtensa_coprocessor_register_group (group
)) >= 0)
841 return rg
& (xtRegisterGroupCP0
<< cp_number
);
847 /* Supply register REGNUM from the buffer specified by GREGS and LEN
848 in the general-purpose register set REGSET to register cache
849 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
852 xtensa_supply_gregset (const struct regset
*regset
,
858 const xtensa_elf_gregset_t
*regs
= gregs
;
859 struct gdbarch
*gdbarch
= get_regcache_arch (rc
);
862 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum
);
864 if (regnum
== gdbarch_pc_regnum (gdbarch
) || regnum
== -1)
865 regcache_raw_supply (rc
, gdbarch_pc_regnum (gdbarch
), (char *) ®s
->pc
);
866 if (regnum
== gdbarch_ps_regnum (gdbarch
) || regnum
== -1)
867 regcache_raw_supply (rc
, gdbarch_ps_regnum (gdbarch
), (char *) ®s
->ps
);
868 if (regnum
== gdbarch_tdep (gdbarch
)->wb_regnum
|| regnum
== -1)
869 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->wb_regnum
,
870 (char *) ®s
->windowbase
);
871 if (regnum
== gdbarch_tdep (gdbarch
)->ws_regnum
|| regnum
== -1)
872 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->ws_regnum
,
873 (char *) ®s
->windowstart
);
874 if (regnum
== gdbarch_tdep (gdbarch
)->lbeg_regnum
|| regnum
== -1)
875 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lbeg_regnum
,
876 (char *) ®s
->lbeg
);
877 if (regnum
== gdbarch_tdep (gdbarch
)->lend_regnum
|| regnum
== -1)
878 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lend_regnum
,
879 (char *) ®s
->lend
);
880 if (regnum
== gdbarch_tdep (gdbarch
)->lcount_regnum
|| regnum
== -1)
881 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lcount_regnum
,
882 (char *) ®s
->lcount
);
883 if (regnum
== gdbarch_tdep (gdbarch
)->sar_regnum
|| regnum
== -1)
884 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->sar_regnum
,
885 (char *) ®s
->sar
);
886 if (regnum
>=gdbarch_tdep (gdbarch
)->ar_base
887 && regnum
< gdbarch_tdep (gdbarch
)->ar_base
888 + gdbarch_tdep (gdbarch
)->num_aregs
)
889 regcache_raw_supply (rc
, regnum
,
890 (char *) ®s
->ar
[regnum
- gdbarch_tdep
891 (gdbarch
)->ar_base
]);
892 else if (regnum
== -1)
894 for (i
= 0; i
< gdbarch_tdep (gdbarch
)->num_aregs
; ++i
)
895 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->ar_base
+ i
,
896 (char *) ®s
->ar
[i
]);
901 /* Xtensa register set. */
907 xtensa_supply_gregset
911 /* Return the appropriate register set for the core
912 section identified by SECT_NAME and SECT_SIZE. */
914 static const struct regset
*
915 xtensa_regset_from_core_section (struct gdbarch
*core_arch
,
916 const char *sect_name
,
919 DEBUGTRACE ("xtensa_regset_from_core_section "
920 "(..., sect_name==\"%s\", sect_size==%x)\n",
921 sect_name
, (unsigned int) sect_size
);
923 if (strcmp (sect_name
, ".reg") == 0
924 && sect_size
>= sizeof(xtensa_elf_gregset_t
))
925 return &xtensa_gregset
;
931 /* Handling frames. */
933 /* Number of registers to save in case of Windowed ABI. */
934 #define XTENSA_NUM_SAVED_AREGS 12
936 /* Frame cache part for Windowed ABI. */
937 typedef struct xtensa_windowed_frame_cache
939 int wb
; /* WINDOWBASE of the previous frame. */
940 int callsize
; /* Call size of this frame. */
941 int ws
; /* WINDOWSTART of the previous frame. It keeps track of
942 life windows only. If there is no bit set for the
943 window, that means it had been already spilled
944 because of window overflow. */
946 /* Addresses of spilled A-registers.
947 AREGS[i] == -1, if corresponding AR is alive. */
948 CORE_ADDR aregs
[XTENSA_NUM_SAVED_AREGS
];
949 } xtensa_windowed_frame_cache_t
;
951 /* Call0 ABI Definitions. */
953 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue
955 #define C0_NREGS 16 /* Number of A-registers to track. */
956 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
957 #define C0_SP 1 /* Register used as SP. */
958 #define C0_FP 15 /* Register used as FP. */
959 #define C0_RA 0 /* Register used as return address. */
960 #define C0_ARGS 2 /* Register used as first arg/retval. */
961 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
963 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
964 A-register where the current content of the reg came from (in terms
965 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
966 mean that the orignal content of the register was saved to the stack.
967 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
968 know where SP will end up until the entire prologue has been analyzed. */
970 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
971 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
972 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
974 extern xtensa_isa xtensa_default_isa
;
976 typedef struct xtensa_c0reg
978 int fr_reg
; /* original register from which register content
979 is derived, or C0_CONST, or C0_INEXP. */
980 int fr_ofs
; /* constant offset from reg, or immediate value. */
981 int to_stk
; /* offset from original SP to register (4-byte
982 aligned), or C0_NOSTK if register has not
987 /* Frame cache part for Call0 ABI. */
988 typedef struct xtensa_call0_frame_cache
990 int c0_frmsz
; /* Stack frame size. */
991 int c0_hasfp
; /* Current frame uses frame
993 int fp_regnum
; /* A-register used as FP. */
994 int c0_fp
; /* Actual value of frame pointer. */
995 xtensa_c0reg_t c0_rt
[C0_NREGS
]; /* Register tracking information. */
996 } xtensa_call0_frame_cache_t
;
998 typedef struct xtensa_frame_cache
1000 CORE_ADDR base
; /* Stack pointer of this frame. */
1001 CORE_ADDR pc
; /* PC of this frame at the function entry point. */
1002 CORE_ADDR ra
; /* The raw return address of this frame. */
1003 CORE_ADDR ps
; /* The PS register of the previous (older) frame. */
1004 CORE_ADDR prev_sp
; /* Stack Pointer of the previous (older) frame. */
1005 int call0
; /* It's a call0 framework (else windowed). */
1008 xtensa_windowed_frame_cache_t wd
; /* call0 == false. */
1009 xtensa_call0_frame_cache_t c0
; /* call0 == true. */
1011 } xtensa_frame_cache_t
;
1014 static struct xtensa_frame_cache
*
1015 xtensa_alloc_frame_cache (int windowed
)
1017 xtensa_frame_cache_t
*cache
;
1020 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
1022 cache
= FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t
);
1029 cache
->call0
= !windowed
;
1032 cache
->c0
.c0_frmsz
= -1;
1033 cache
->c0
.c0_hasfp
= 0;
1034 cache
->c0
.fp_regnum
= -1;
1035 cache
->c0
.c0_fp
= -1;
1037 for (i
= 0; i
< C0_NREGS
; i
++)
1039 cache
->c0
.c0_rt
[i
].fr_reg
= i
;
1040 cache
->c0
.c0_rt
[i
].fr_ofs
= 0;
1041 cache
->c0
.c0_rt
[i
].to_stk
= C0_NOSTK
;
1048 cache
->wd
.callsize
= -1;
1050 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
1051 cache
->wd
.aregs
[i
] = -1;
1058 xtensa_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
1060 return address
& ~15;
1065 xtensa_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1070 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1071 host_address_to_string (next_frame
));
1073 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1074 pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1076 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc
);
1082 static struct frame_id
1083 xtensa_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1087 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1089 pc
= get_frame_pc (this_frame
);
1090 fp
= get_frame_register_unsigned
1091 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1093 /* Make dummy frame ID unique by adding a constant. */
1094 return frame_id_build (fp
+ SP_ALIGNMENT
, pc
);
1097 /* Returns true, if instruction to execute next is unique to Xtensa Window
1098 Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
1101 xtensa_window_interrupt_insn (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1103 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1104 unsigned int insn
= read_memory_integer (pc
, 4, byte_order
);
1107 if (byte_order
== BFD_ENDIAN_BIG
)
1109 /* Check, if this is L32E or S32E. */
1110 code
= insn
& 0xf000ff00;
1111 if ((code
== 0x00009000) || (code
== 0x00009400))
1113 /* Check, if this is RFWU or RFWO. */
1114 code
= insn
& 0xffffff00;
1115 return ((code
== 0x00430000) || (code
== 0x00530000));
1119 /* Check, if this is L32E or S32E. */
1120 code
= insn
& 0x00ff000f;
1121 if ((code
== 0x090000) || (code
== 0x490000))
1123 /* Check, if this is RFWU or RFWO. */
1124 code
= insn
& 0x00ffffff;
1125 return ((code
== 0x00003400) || (code
== 0x00003500));
1129 /* Returns the best guess about which register is a frame pointer
1130 for the function containing CURRENT_PC. */
1132 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1133 #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1136 xtensa_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
)
1138 #define RETURN_FP goto done
1140 unsigned int fp_regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ 1;
1141 CORE_ADDR start_addr
;
1143 xtensa_insnbuf ins
, slot
;
1144 char ibuf
[XTENSA_ISA_BSZ
];
1145 CORE_ADDR ia
, bt
, ba
;
1147 int ilen
, islots
, is
;
1149 const char *opcname
;
1151 find_pc_partial_function (current_pc
, NULL
, &start_addr
, NULL
);
1152 if (start_addr
== 0)
1155 if (!xtensa_default_isa
)
1156 xtensa_default_isa
= xtensa_isa_init (0, 0);
1157 isa
= xtensa_default_isa
;
1158 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
1159 ins
= xtensa_insnbuf_alloc (isa
);
1160 slot
= xtensa_insnbuf_alloc (isa
);
1163 for (ia
= start_addr
, bt
= ia
; ia
< current_pc
; ia
+= ilen
)
1165 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
1168 bt
= (ba
+ XTENSA_ISA_BSZ
) < current_pc
1169 ? ba
+ XTENSA_ISA_BSZ
: current_pc
;
1170 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0)
1174 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
1175 ifmt
= xtensa_format_decode (isa
, ins
);
1176 if (ifmt
== XTENSA_UNDEFINED
)
1178 ilen
= xtensa_format_length (isa
, ifmt
);
1179 if (ilen
== XTENSA_UNDEFINED
)
1181 islots
= xtensa_format_num_slots (isa
, ifmt
);
1182 if (islots
== XTENSA_UNDEFINED
)
1185 for (is
= 0; is
< islots
; ++is
)
1187 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
1190 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
1191 if (opc
== XTENSA_UNDEFINED
)
1194 opcname
= xtensa_opcode_name (isa
, opc
);
1196 if (strcasecmp (opcname
, "mov.n") == 0
1197 || strcasecmp (opcname
, "or") == 0)
1199 unsigned int register_operand
;
1201 /* Possible candidate for setting frame pointer
1202 from A1. This is what we are looking for. */
1204 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
,
1205 is
, slot
, ®ister_operand
) != 0)
1207 if (xtensa_operand_decode (isa
, opc
, 1, ®ister_operand
) != 0)
1209 if (register_operand
== 1) /* Mov{.n} FP A1. */
1211 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
,
1212 ®ister_operand
) != 0)
1214 if (xtensa_operand_decode (isa
, opc
, 0,
1215 ®ister_operand
) != 0)
1219 = gdbarch_tdep (gdbarch
)->a0_base
+ register_operand
;
1225 /* We have problems decoding the memory. */
1227 || strcasecmp (opcname
, "ill") == 0
1228 || strcasecmp (opcname
, "ill.n") == 0
1229 /* Hit planted breakpoint. */
1230 || strcasecmp (opcname
, "break") == 0
1231 || strcasecmp (opcname
, "break.n") == 0
1232 /* Flow control instructions finish prologue. */
1233 || xtensa_opcode_is_branch (isa
, opc
) > 0
1234 || xtensa_opcode_is_jump (isa
, opc
) > 0
1235 || xtensa_opcode_is_loop (isa
, opc
) > 0
1236 || xtensa_opcode_is_call (isa
, opc
) > 0
1237 || strcasecmp (opcname
, "simcall") == 0
1238 || strcasecmp (opcname
, "syscall") == 0)
1239 /* Can not continue analysis. */
1244 xtensa_insnbuf_free(isa
, slot
);
1245 xtensa_insnbuf_free(isa
, ins
);
1249 /* The key values to identify the frame using "cache" are
1251 cache->base = SP (or best guess about FP) of this frame;
1252 cache->pc = entry-PC (entry point of the frame function);
1253 cache->prev_sp = SP of the previous frame. */
1256 call0_frame_cache (struct frame_info
*this_frame
,
1257 xtensa_frame_cache_t
*cache
,
1258 CORE_ADDR pc
, CORE_ADDR litbase
);
1261 xtensa_window_interrupt_frame_cache (struct frame_info
*this_frame
,
1262 xtensa_frame_cache_t
*cache
,
1265 static struct xtensa_frame_cache
*
1266 xtensa_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1268 xtensa_frame_cache_t
*cache
;
1269 CORE_ADDR ra
, wb
, ws
, pc
, sp
, ps
;
1270 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1271 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1272 unsigned int fp_regnum
;
1273 int windowed
, ps_regnum
;
1278 pc
= get_frame_register_unsigned (this_frame
, gdbarch_pc_regnum (gdbarch
));
1279 ps_regnum
= gdbarch_ps_regnum (gdbarch
);
1280 ps
= (ps_regnum
>= 0)
1281 ? get_frame_register_unsigned (this_frame
, ps_regnum
) : TX_PS
;
1283 windowed
= windowing_enabled (gdbarch
, ps
);
1285 /* Get pristine xtensa-frame. */
1286 cache
= xtensa_alloc_frame_cache (windowed
);
1287 *this_cache
= cache
;
1293 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1294 wb
= get_frame_register_unsigned (this_frame
,
1295 gdbarch_tdep (gdbarch
)->wb_regnum
);
1296 ws
= get_frame_register_unsigned (this_frame
,
1297 gdbarch_tdep (gdbarch
)->ws_regnum
);
1299 op1
= read_memory_integer (pc
, 1, byte_order
);
1300 if (XTENSA_IS_ENTRY (gdbarch
, op1
))
1302 int callinc
= CALLINC (ps
);
1303 ra
= get_frame_register_unsigned
1304 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ callinc
* 4);
1306 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1307 cache
->wd
.callsize
= 0;
1310 cache
->prev_sp
= get_frame_register_unsigned
1311 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1313 /* This only can be the outermost frame since we are
1314 just about to execute ENTRY. SP hasn't been set yet.
1315 We can assume any frame size, because it does not
1316 matter, and, let's fake frame base in cache. */
1317 cache
->base
= cache
->prev_sp
- 16;
1320 cache
->ra
= (cache
->pc
& 0xc0000000) | (ra
& 0x3fffffff);
1321 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1322 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1328 fp_regnum
= xtensa_scan_prologue (gdbarch
, pc
);
1329 ra
= get_frame_register_unsigned (this_frame
,
1330 gdbarch_tdep (gdbarch
)->a0_base
);
1331 cache
->wd
.callsize
= WINSIZE (ra
);
1332 cache
->wd
.wb
= (wb
- cache
->wd
.callsize
/ 4)
1333 & (gdbarch_tdep (gdbarch
)->num_aregs
/ 4 - 1);
1334 cache
->wd
.ws
= ws
& ~(1 << wb
);
1336 cache
->pc
= get_frame_func (this_frame
);
1337 cache
->ra
= (pc
& 0xc0000000) | (ra
& 0x3fffffff);
1338 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1339 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1342 if (cache
->wd
.ws
== 0)
1347 sp
= get_frame_register_unsigned
1348 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1) - 16;
1350 for (i
= 0; i
< 4; i
++, sp
+= 4)
1352 cache
->wd
.aregs
[i
] = sp
;
1355 if (cache
->wd
.callsize
> 4)
1357 /* Set A4...A7/A11. */
1358 /* Get the SP of the frame previous to the previous one.
1359 To achieve this, we have to dereference SP twice. */
1360 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4, byte_order
);
1361 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4, byte_order
);
1362 sp
-= cache
->wd
.callsize
* 4;
1364 for ( i
= 4; i
< cache
->wd
.callsize
; i
++, sp
+= 4)
1366 cache
->wd
.aregs
[i
] = sp
;
1371 if ((cache
->prev_sp
== 0) && ( ra
!= 0 ))
1372 /* If RA is equal to 0 this frame is an outermost frame. Leave
1373 cache->prev_sp unchanged marking the boundary of the frame stack. */
1375 if ((cache
->wd
.ws
& (1 << cache
->wd
.wb
)) == 0)
1377 /* Register window overflow already happened.
1378 We can read caller's SP from the proper spill loction. */
1379 sp
= get_frame_register_unsigned
1380 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1381 cache
->prev_sp
= read_memory_integer (sp
- 12, 4, byte_order
);
1385 /* Read caller's frame SP directly from the previous window. */
1386 int regnum
= arreg_number
1387 (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ 1,
1390 cache
->prev_sp
= xtensa_read_register (regnum
);
1394 else if (xtensa_window_interrupt_insn (gdbarch
, pc
))
1396 /* Execution stopped inside Xtensa Window Interrupt Handler. */
1398 xtensa_window_interrupt_frame_cache (this_frame
, cache
, pc
);
1399 /* Everything was set already, including cache->base. */
1402 else /* Call0 framework. */
1404 unsigned int litbase_regnum
= gdbarch_tdep (gdbarch
)->litbase_regnum
;
1405 CORE_ADDR litbase
= (litbase_regnum
== -1)
1406 ? 0 : get_frame_register_unsigned (this_frame
, litbase_regnum
);
1408 call0_frame_cache (this_frame
, cache
, pc
, litbase
);
1409 fp_regnum
= cache
->c0
.fp_regnum
;
1412 cache
->base
= get_frame_register_unsigned (this_frame
, fp_regnum
);
1418 xtensa_frame_this_id (struct frame_info
*this_frame
,
1420 struct frame_id
*this_id
)
1422 struct xtensa_frame_cache
*cache
=
1423 xtensa_frame_cache (this_frame
, this_cache
);
1425 if (cache
->prev_sp
== 0)
1428 (*this_id
) = frame_id_build (cache
->prev_sp
, cache
->pc
);
1431 static struct value
*
1432 xtensa_frame_prev_register (struct frame_info
*this_frame
,
1436 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1437 struct xtensa_frame_cache
*cache
;
1438 ULONGEST saved_reg
= 0;
1441 if (*this_cache
== NULL
)
1442 *this_cache
= xtensa_frame_cache (this_frame
, this_cache
);
1443 cache
= *this_cache
;
1445 if (regnum
==gdbarch_pc_regnum (gdbarch
))
1446 saved_reg
= cache
->ra
;
1447 else if (regnum
== gdbarch_tdep (gdbarch
)->a0_base
+ 1)
1448 saved_reg
= cache
->prev_sp
;
1449 else if (!cache
->call0
)
1451 if (regnum
== gdbarch_tdep (gdbarch
)->ws_regnum
)
1452 saved_reg
= cache
->wd
.ws
;
1453 else if (regnum
== gdbarch_tdep (gdbarch
)->wb_regnum
)
1454 saved_reg
= cache
->wd
.wb
;
1455 else if (regnum
== gdbarch_ps_regnum (gdbarch
))
1456 saved_reg
= cache
->ps
;
1464 return frame_unwind_got_constant (this_frame
, regnum
, saved_reg
);
1466 if (!cache
->call0
) /* Windowed ABI. */
1468 /* Convert A-register numbers to AR-register numbers,
1469 if we deal with A-register. */
1470 if (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
1471 && regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15)
1472 regnum
= arreg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1474 /* Check, if we deal with AR-register saved on stack. */
1475 if (regnum
>= gdbarch_tdep (gdbarch
)->ar_base
1476 && regnum
<= (gdbarch_tdep (gdbarch
)->ar_base
1477 + gdbarch_tdep (gdbarch
)->num_aregs
))
1479 int areg
= areg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1482 && areg
< XTENSA_NUM_SAVED_AREGS
1483 && cache
->wd
.aregs
[areg
] != -1)
1484 return frame_unwind_got_memory (this_frame
, regnum
,
1485 cache
->wd
.aregs
[areg
]);
1488 else /* Call0 ABI. */
1490 int reg
= (regnum
>= gdbarch_tdep (gdbarch
)->ar_base
1491 && regnum
<= (gdbarch_tdep (gdbarch
)->ar_base
1493 ? regnum
- gdbarch_tdep (gdbarch
)->ar_base
: regnum
;
1500 /* If register was saved in the prologue, retrieve it. */
1501 stkofs
= cache
->c0
.c0_rt
[reg
].to_stk
;
1502 if (stkofs
!= C0_NOSTK
)
1504 /* Determine SP on entry based on FP. */
1505 spe
= cache
->c0
.c0_fp
1506 - cache
->c0
.c0_rt
[cache
->c0
.fp_regnum
].fr_ofs
;
1508 return frame_unwind_got_memory (this_frame
, regnum
,
1514 /* All other registers have been either saved to
1515 the stack or are still alive in the processor. */
1517 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1521 static const struct frame_unwind
1525 xtensa_frame_this_id
,
1526 xtensa_frame_prev_register
,
1528 default_frame_sniffer
1532 xtensa_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1534 struct xtensa_frame_cache
*cache
=
1535 xtensa_frame_cache (this_frame
, this_cache
);
1540 static const struct frame_base
1544 xtensa_frame_base_address
,
1545 xtensa_frame_base_address
,
1546 xtensa_frame_base_address
1551 xtensa_extract_return_value (struct type
*type
,
1552 struct regcache
*regcache
,
1555 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1556 bfd_byte
*valbuf
= dst
;
1557 int len
= TYPE_LENGTH (type
);
1562 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1564 gdb_assert(len
> 0);
1566 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1568 /* First, we have to find the caller window in the register file. */
1569 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1570 callsize
= extract_call_winsize (gdbarch
, pc
);
1572 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1573 if (len
> (callsize
> 8 ? 8 : 16))
1574 internal_error (__FILE__
, __LINE__
,
1575 _("cannot extract return value of %d bytes long"),
1578 /* Get the register offset of the return
1579 register (A2) in the caller window. */
1580 regcache_raw_read_unsigned
1581 (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, &wb
);
1582 areg
= arreg_number (gdbarch
,
1583 gdbarch_tdep (gdbarch
)->a0_base
+ 2 + callsize
, wb
);
1587 /* No windowing hardware - Call0 ABI. */
1588 areg
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_ARGS
;
1591 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg
, len
);
1593 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1596 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1599 regcache_raw_read_part (regcache
, areg
, offset
, len
, valbuf
);
1601 regcache_raw_read (regcache
, areg
, valbuf
);
1607 xtensa_store_return_value (struct type
*type
,
1608 struct regcache
*regcache
,
1611 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1612 const bfd_byte
*valbuf
= dst
;
1616 int len
= TYPE_LENGTH (type
);
1619 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1621 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1623 regcache_raw_read_unsigned
1624 (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, &wb
);
1625 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1626 callsize
= extract_call_winsize (gdbarch
, pc
);
1628 if (len
> (callsize
> 8 ? 8 : 16))
1629 internal_error (__FILE__
, __LINE__
,
1630 _("unimplemented for this length: %d"),
1631 TYPE_LENGTH (type
));
1632 areg
= arreg_number (gdbarch
,
1633 gdbarch_tdep (gdbarch
)->a0_base
+ 2 + callsize
, wb
);
1635 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1636 callsize
, (int) wb
);
1640 areg
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_ARGS
;
1643 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1646 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1649 regcache_raw_write_part (regcache
, areg
, offset
, len
, valbuf
);
1651 regcache_raw_write (regcache
, areg
, valbuf
);
1656 static enum return_value_convention
1657 xtensa_return_value (struct gdbarch
*gdbarch
,
1658 struct type
*func_type
,
1659 struct type
*valtype
,
1660 struct regcache
*regcache
,
1662 const gdb_byte
*writebuf
)
1664 /* Structures up to 16 bytes are returned in registers. */
1666 int struct_return
= ((TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
1667 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
1668 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
1669 && TYPE_LENGTH (valtype
) > 16);
1672 return RETURN_VALUE_STRUCT_CONVENTION
;
1674 DEBUGTRACE ("xtensa_return_value(...)\n");
1676 if (writebuf
!= NULL
)
1678 xtensa_store_return_value (valtype
, regcache
, writebuf
);
1681 if (readbuf
!= NULL
)
1683 gdb_assert (!struct_return
);
1684 xtensa_extract_return_value (valtype
, regcache
, readbuf
);
1686 return RETURN_VALUE_REGISTER_CONVENTION
;
1693 xtensa_push_dummy_call (struct gdbarch
*gdbarch
,
1694 struct value
*function
,
1695 struct regcache
*regcache
,
1698 struct value
**args
,
1701 CORE_ADDR struct_addr
)
1703 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1705 int size
, onstack_size
;
1706 gdb_byte
*buf
= (gdb_byte
*) alloca (16);
1708 struct argument_info
1710 const bfd_byte
*contents
;
1712 int onstack
; /* onstack == 0 => in reg */
1713 int align
; /* alignment */
1716 int offset
; /* stack offset if on stack. */
1717 int regno
; /* regno if in register. */
1721 struct argument_info
*arg_info
=
1722 (struct argument_info
*) alloca (nargs
* sizeof (struct argument_info
));
1726 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1728 if (xtensa_debug_level
> 3)
1731 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs
);
1732 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1733 "struct_addr=0x%x\n",
1734 (int) sp
, (int) struct_return
, (int) struct_addr
);
1736 for (i
= 0; i
< nargs
; i
++)
1738 struct value
*arg
= args
[i
];
1739 struct type
*arg_type
= check_typedef (value_type (arg
));
1740 fprintf_unfiltered (gdb_stdlog
, "%2d: %s %3d ", i
,
1741 host_address_to_string (arg
),
1742 TYPE_LENGTH (arg_type
));
1743 switch (TYPE_CODE (arg_type
))
1746 fprintf_unfiltered (gdb_stdlog
, "int");
1748 case TYPE_CODE_STRUCT
:
1749 fprintf_unfiltered (gdb_stdlog
, "struct");
1752 fprintf_unfiltered (gdb_stdlog
, "%3d", TYPE_CODE (arg_type
));
1755 fprintf_unfiltered (gdb_stdlog
, " %s\n",
1756 host_address_to_string (value_contents (arg
)));
1760 /* First loop: collect information.
1761 Cast into type_long. (This shouldn't happen often for C because
1762 GDB already does this earlier.) It's possible that GDB could
1763 do it all the time but it's harmless to leave this code here. */
1770 size
= REGISTER_SIZE
;
1772 for (i
= 0; i
< nargs
; i
++)
1774 struct argument_info
*info
= &arg_info
[i
];
1775 struct value
*arg
= args
[i
];
1776 struct type
*arg_type
= check_typedef (value_type (arg
));
1778 switch (TYPE_CODE (arg_type
))
1781 case TYPE_CODE_BOOL
:
1782 case TYPE_CODE_CHAR
:
1783 case TYPE_CODE_RANGE
:
1784 case TYPE_CODE_ENUM
:
1786 /* Cast argument to long if necessary as the mask does it too. */
1787 if (TYPE_LENGTH (arg_type
)
1788 < TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
))
1790 arg_type
= builtin_type (gdbarch
)->builtin_long
;
1791 arg
= value_cast (arg_type
, arg
);
1793 /* Aligment is equal to the type length for the basic types. */
1794 info
->align
= TYPE_LENGTH (arg_type
);
1799 /* Align doubles correctly. */
1800 if (TYPE_LENGTH (arg_type
)
1801 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
))
1802 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
);
1804 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
);
1807 case TYPE_CODE_STRUCT
:
1809 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
);
1812 info
->length
= TYPE_LENGTH (arg_type
);
1813 info
->contents
= value_contents (arg
);
1815 /* Align size and onstack_size. */
1816 size
= (size
+ info
->align
- 1) & ~(info
->align
- 1);
1817 onstack_size
= (onstack_size
+ info
->align
- 1) & ~(info
->align
- 1);
1819 if (size
+ info
->length
> REGISTER_SIZE
* ARG_NOF (gdbarch
))
1822 info
->u
.offset
= onstack_size
;
1823 onstack_size
+= info
->length
;
1828 info
->u
.regno
= ARG_1ST (gdbarch
) + size
/ REGISTER_SIZE
;
1830 size
+= info
->length
;
1833 /* Adjust the stack pointer and align it. */
1834 sp
= align_down (sp
- onstack_size
, SP_ALIGNMENT
);
1836 /* Simulate MOVSP, if Windowed ABI. */
1837 if ((gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1840 read_memory (osp
- 16, buf
, 16);
1841 write_memory (sp
- 16, buf
, 16);
1844 /* Second Loop: Load arguments. */
1848 store_unsigned_integer (buf
, REGISTER_SIZE
, byte_order
, struct_addr
);
1849 regcache_cooked_write (regcache
, ARG_1ST (gdbarch
), buf
);
1852 for (i
= 0; i
< nargs
; i
++)
1854 struct argument_info
*info
= &arg_info
[i
];
1858 int n
= info
->length
;
1859 CORE_ADDR offset
= sp
+ info
->u
.offset
;
1861 /* Odd-sized structs are aligned to the lower side of a memory
1862 word in big-endian mode and require a shift. This only
1863 applies for structures smaller than one word. */
1865 if (n
< REGISTER_SIZE
1866 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1867 offset
+= (REGISTER_SIZE
- n
);
1869 write_memory (offset
, info
->contents
, info
->length
);
1874 int n
= info
->length
;
1875 const bfd_byte
*cp
= info
->contents
;
1876 int r
= info
->u
.regno
;
1878 /* Odd-sized structs are aligned to the lower side of registers in
1879 big-endian mode and require a shift. The odd-sized leftover will
1880 be at the end. Note that this is only true for structures smaller
1881 than REGISTER_SIZE; for larger odd-sized structures the excess
1882 will be left-aligned in the register on both endiannesses. */
1884 if (n
< REGISTER_SIZE
&& byte_order
== BFD_ENDIAN_BIG
)
1887 v
= extract_unsigned_integer (cp
, REGISTER_SIZE
, byte_order
);
1888 v
= v
>> ((REGISTER_SIZE
- n
) * TARGET_CHAR_BIT
);
1890 store_unsigned_integer (buf
, REGISTER_SIZE
, byte_order
, v
);
1891 regcache_cooked_write (regcache
, r
, buf
);
1893 cp
+= REGISTER_SIZE
;
1900 regcache_cooked_write (regcache
, r
, cp
);
1902 cp
+= REGISTER_SIZE
;
1909 /* Set the return address of dummy frame to the dummy address.
1910 The return address for the current function (in A0) is
1911 saved in the dummy frame, so we can savely overwrite A0 here. */
1913 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1916 ra
= (bp_addr
& 0x3fffffff) | 0x40000000;
1917 regcache_raw_read_unsigned (regcache
, gdbarch_ps_regnum (gdbarch
), &val
);
1918 ps
= (unsigned long) val
& ~0x00030000;
1919 regcache_cooked_write_unsigned
1920 (regcache
, gdbarch_tdep (gdbarch
)->a0_base
+ 4, ra
);
1921 regcache_cooked_write_unsigned (regcache
,
1922 gdbarch_ps_regnum (gdbarch
),
1925 /* All the registers have been saved. After executing
1926 dummy call, they all will be restored. So it's safe
1927 to modify WINDOWSTART register to make it look like there
1928 is only one register window corresponding to WINDOWEBASE. */
1930 regcache_raw_read (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, buf
);
1931 regcache_cooked_write_unsigned
1932 (regcache
, gdbarch_tdep (gdbarch
)->ws_regnum
,
1933 1 << extract_unsigned_integer (buf
, 4, byte_order
));
1937 /* Simulate CALL0: write RA into A0 register. */
1938 regcache_cooked_write_unsigned
1939 (regcache
, gdbarch_tdep (gdbarch
)->a0_base
, bp_addr
);
1942 /* Set new stack pointer and return it. */
1943 regcache_cooked_write_unsigned (regcache
,
1944 gdbarch_tdep (gdbarch
)->a0_base
+ 1, sp
);
1945 /* Make dummy frame ID unique by adding a constant. */
1946 return sp
+ SP_ALIGNMENT
;
1950 /* Return a breakpoint for the current location of PC. We always use
1951 the density version if we have density instructions (regardless of the
1952 current instruction at PC), and use regular instructions otherwise. */
1954 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1955 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1956 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1957 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1959 static const unsigned char *
1960 xtensa_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
1963 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
1964 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
1965 static unsigned char density_big_breakpoint
[] = DENSITY_BIG_BREAKPOINT
;
1966 static unsigned char density_little_breakpoint
[] = DENSITY_LITTLE_BREAKPOINT
;
1968 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr
);
1970 if (gdbarch_tdep (gdbarch
)->isa_use_density_instructions
)
1972 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1974 *lenptr
= sizeof (density_big_breakpoint
);
1975 return density_big_breakpoint
;
1979 *lenptr
= sizeof (density_little_breakpoint
);
1980 return density_little_breakpoint
;
1985 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1987 *lenptr
= sizeof (big_breakpoint
);
1988 return big_breakpoint
;
1992 *lenptr
= sizeof (little_breakpoint
);
1993 return little_breakpoint
;
1998 /* Call0 ABI support routines. */
2000 /* Call0 opcode class. Opcodes are preclassified according to what they
2001 mean for Call0 prologue analysis, and their number of significant operands.
2002 The purpose of this is to simplify prologue analysis by separating
2003 instruction decoding (libisa) from the semantics of prologue analysis. */
2006 c0opc_illegal
, /* Unknown to libisa (invalid) or 'ill' opcode. */
2007 c0opc_uninteresting
, /* Not interesting for Call0 prologue analysis. */
2008 c0opc_flow
, /* Flow control insn. */
2009 c0opc_entry
, /* ENTRY indicates non-Call0 prologue. */
2010 c0opc_break
, /* Debugger software breakpoints. */
2011 c0opc_add
, /* Adding two registers. */
2012 c0opc_addi
, /* Adding a register and an immediate. */
2013 c0opc_sub
, /* Subtracting a register from a register. */
2014 c0opc_mov
, /* Moving a register to a register. */
2015 c0opc_movi
, /* Moving an immediate to a register. */
2016 c0opc_l32r
, /* Loading a literal. */
2017 c0opc_s32i
, /* Storing word at fixed offset from a base register. */
2018 c0opc_rwxsr
, /* RSR, WRS, or XSR instructions. */
2019 c0opc_l32e
, /* L32E instruction. */
2020 c0opc_s32e
, /* S32E instruction. */
2021 c0opc_rfwo
, /* RFWO instruction. */
2022 c0opc_rfwu
, /* RFWU instruction. */
2023 c0opc_NrOf
/* Number of opcode classifications. */
2026 /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
2029 rwx_special_register (const char *opcname
)
2031 char ch
= *opcname
++;
2033 if ((ch
!= 'r') && (ch
!= 'w') && (ch
!= 'x'))
2035 if (*opcname
++ != 's')
2037 if (*opcname
++ != 'r')
2039 if (*opcname
++ != '.')
2045 /* Classify an opcode based on what it means for Call0 prologue analysis. */
2047 static xtensa_insn_kind
2048 call0_classify_opcode (xtensa_isa isa
, xtensa_opcode opc
)
2050 const char *opcname
;
2051 xtensa_insn_kind opclass
= c0opc_uninteresting
;
2053 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc
);
2055 /* Get opcode name and handle special classifications. */
2057 opcname
= xtensa_opcode_name (isa
, opc
);
2060 || strcasecmp (opcname
, "ill") == 0
2061 || strcasecmp (opcname
, "ill.n") == 0)
2062 opclass
= c0opc_illegal
;
2063 else if (strcasecmp (opcname
, "break") == 0
2064 || strcasecmp (opcname
, "break.n") == 0)
2065 opclass
= c0opc_break
;
2066 else if (strcasecmp (opcname
, "entry") == 0)
2067 opclass
= c0opc_entry
;
2068 else if (strcasecmp (opcname
, "rfwo") == 0)
2069 opclass
= c0opc_rfwo
;
2070 else if (strcasecmp (opcname
, "rfwu") == 0)
2071 opclass
= c0opc_rfwu
;
2072 else if (xtensa_opcode_is_branch (isa
, opc
) > 0
2073 || xtensa_opcode_is_jump (isa
, opc
) > 0
2074 || xtensa_opcode_is_loop (isa
, opc
) > 0
2075 || xtensa_opcode_is_call (isa
, opc
) > 0
2076 || strcasecmp (opcname
, "simcall") == 0
2077 || strcasecmp (opcname
, "syscall") == 0)
2078 opclass
= c0opc_flow
;
2080 /* Also, classify specific opcodes that need to be tracked. */
2081 else if (strcasecmp (opcname
, "add") == 0
2082 || strcasecmp (opcname
, "add.n") == 0)
2083 opclass
= c0opc_add
;
2084 else if (strcasecmp (opcname
, "addi") == 0
2085 || strcasecmp (opcname
, "addi.n") == 0
2086 || strcasecmp (opcname
, "addmi") == 0)
2087 opclass
= c0opc_addi
;
2088 else if (strcasecmp (opcname
, "sub") == 0)
2089 opclass
= c0opc_sub
;
2090 else if (strcasecmp (opcname
, "mov.n") == 0
2091 || strcasecmp (opcname
, "or") == 0) /* Could be 'mov' asm macro. */
2092 opclass
= c0opc_mov
;
2093 else if (strcasecmp (opcname
, "movi") == 0
2094 || strcasecmp (opcname
, "movi.n") == 0)
2095 opclass
= c0opc_movi
;
2096 else if (strcasecmp (opcname
, "l32r") == 0)
2097 opclass
= c0opc_l32r
;
2098 else if (strcasecmp (opcname
, "s32i") == 0
2099 || strcasecmp (opcname
, "s32i.n") == 0)
2100 opclass
= c0opc_s32i
;
2101 else if (strcasecmp (opcname
, "l32e") == 0)
2102 opclass
= c0opc_l32e
;
2103 else if (strcasecmp (opcname
, "s32e") == 0)
2104 opclass
= c0opc_s32e
;
2105 else if (rwx_special_register (opcname
))
2106 opclass
= c0opc_rwxsr
;
2111 /* Tracks register movement/mutation for a given operation, which may
2112 be within a bundle. Updates the destination register tracking info
2113 accordingly. The pc is needed only for pc-relative load instructions
2114 (eg. l32r). The SP register number is needed to identify stores to
2118 call0_track_op (struct gdbarch
*gdbarch
,
2119 xtensa_c0reg_t dst
[], xtensa_c0reg_t src
[],
2120 xtensa_insn_kind opclass
, int nods
, unsigned odv
[],
2121 CORE_ADDR pc
, CORE_ADDR litbase
, int spreg
)
2123 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2124 unsigned litaddr
, litval
;
2129 /* 3 operands: dst, src, imm. */
2130 gdb_assert (nods
== 3);
2131 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2132 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ odv
[2];
2135 /* 3 operands: dst, src1, src2. */
2136 gdb_assert (nods
== 3);
2137 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2139 dst
[odv
[0]].fr_reg
= src
[odv
[2]].fr_reg
;
2140 dst
[odv
[0]].fr_ofs
= src
[odv
[2]].fr_ofs
+ src
[odv
[1]].fr_ofs
;
2142 else if (src
[odv
[2]].fr_reg
== C0_CONST
)
2144 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2145 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ src
[odv
[2]].fr_ofs
;
2147 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2150 /* 3 operands: dst, src1, src2. */
2151 gdb_assert (nods
== 3);
2152 if (src
[odv
[2]].fr_reg
== C0_CONST
)
2154 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2155 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
- src
[odv
[2]].fr_ofs
;
2157 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2160 /* 2 operands: dst, src [, src]. */
2161 gdb_assert (nods
== 2);
2162 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2163 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
;
2166 /* 2 operands: dst, imm. */
2167 gdb_assert (nods
== 2);
2168 dst
[odv
[0]].fr_reg
= C0_CONST
;
2169 dst
[odv
[0]].fr_ofs
= odv
[1];
2172 /* 2 operands: dst, literal offset. */
2173 gdb_assert (nods
== 2);
2174 litaddr
= litbase
& 1
2175 ? (litbase
& ~1) + (signed)odv
[1]
2176 : (pc
+ 3 + (signed)odv
[1]) & ~3;
2177 litval
= read_memory_integer (litaddr
, 4, byte_order
);
2178 dst
[odv
[0]].fr_reg
= C0_CONST
;
2179 dst
[odv
[0]].fr_ofs
= litval
;
2182 /* 3 operands: value, base, offset. */
2183 gdb_assert (nods
== 3 && spreg
>= 0 && spreg
< C0_NREGS
);
2184 if (src
[odv
[1]].fr_reg
== spreg
/* Store to stack frame. */
2185 && (src
[odv
[1]].fr_ofs
& 3) == 0 /* Alignment preserved. */
2186 && src
[odv
[0]].fr_reg
>= 0 /* Value is from a register. */
2187 && src
[odv
[0]].fr_ofs
== 0 /* Value hasn't been modified. */
2188 && src
[src
[odv
[0]].fr_reg
].to_stk
== C0_NOSTK
) /* First time. */
2190 /* ISA encoding guarantees alignment. But, check it anyway. */
2191 gdb_assert ((odv
[2] & 3) == 0);
2192 dst
[src
[odv
[0]].fr_reg
].to_stk
= src
[odv
[1]].fr_ofs
+ odv
[2];
2196 gdb_assert_not_reached ("unexpected instruction kind");
2200 /* Analyze prologue of the function at start address to determine if it uses
2201 the Call0 ABI, and if so track register moves and linear modifications
2202 in the prologue up to the PC or just beyond the prologue, whichever is first.
2203 An 'entry' instruction indicates non-Call0 ABI and the end of the prologue.
2204 The prologue may overlap non-prologue instructions but is guaranteed to end
2205 by the first flow-control instruction (jump, branch, call or return).
2206 Since an optimized function may move information around and change the
2207 stack frame arbitrarily during the prologue, the information is guaranteed
2208 valid only at the point in the function indicated by the PC.
2209 May be used to skip the prologue or identify the ABI, w/o tracking.
2211 Returns: Address of first instruction after prologue, or PC (whichever
2212 is first), or 0, if decoding failed (in libisa).
2214 start Start address of function/prologue.
2215 pc Program counter to stop at. Use 0 to continue to end of prologue.
2216 If 0, avoids infinite run-on in corrupt code memory by bounding
2217 the scan to the end of the function if that can be determined.
2218 nregs Number of general registers to track (size of rt[] array).
2220 rt[] Array[nregs] of xtensa_c0reg structures for register tracking info.
2221 If NULL, registers are not tracked.
2223 call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0
2224 (more accurately, non-zero until 'entry' insn is encountered).
2226 Note that these may produce useful results even if decoding fails
2227 because they begin with default assumptions that analysis may change. */
2230 call0_analyze_prologue (struct gdbarch
*gdbarch
,
2231 CORE_ADDR start
, CORE_ADDR pc
, CORE_ADDR litbase
,
2232 int nregs
, xtensa_c0reg_t rt
[], int *call0
)
2234 CORE_ADDR ia
; /* Current insn address in prologue. */
2235 CORE_ADDR ba
= 0; /* Current address at base of insn buffer. */
2236 CORE_ADDR bt
; /* Current address at top+1 of insn buffer. */
2237 char ibuf
[XTENSA_ISA_BSZ
];/* Instruction buffer for decoding prologue. */
2238 xtensa_isa isa
; /* libisa ISA handle. */
2239 xtensa_insnbuf ins
, slot
; /* libisa handle to decoded insn, slot. */
2240 xtensa_format ifmt
; /* libisa instruction format. */
2241 int ilen
, islots
, is
; /* Instruction length, nbr slots, current slot. */
2242 xtensa_opcode opc
; /* Opcode in current slot. */
2243 xtensa_insn_kind opclass
; /* Opcode class for Call0 prologue analysis. */
2244 int nods
; /* Opcode number of operands. */
2245 unsigned odv
[C0_MAXOPDS
]; /* Operand values in order provided by libisa. */
2246 xtensa_c0reg_t
*rtmp
; /* Register tracking info snapshot. */
2247 int j
; /* General loop counter. */
2248 int fail
= 0; /* Set non-zero and exit, if decoding fails. */
2249 CORE_ADDR body_pc
; /* The PC for the first non-prologue insn. */
2250 CORE_ADDR end_pc
; /* The PC for the lust function insn. */
2252 struct symtab_and_line prologue_sal
;
2254 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2255 (int)start
, (int)pc
);
2257 /* Try to limit the scan to the end of the function if a non-zero pc
2258 arg was not supplied to avoid probing beyond the end of valid memory.
2259 If memory is full of garbage that classifies as c0opc_uninteresting.
2260 If this fails (eg. if no symbols) pc ends up 0 as it was.
2261 Intialize the Call0 frame and register tracking info.
2262 Assume it's Call0 until an 'entry' instruction is encountered.
2263 Assume we may be in the prologue until we hit a flow control instr. */
2269 /* Find out, if we have an information about the prologue from DWARF. */
2270 prologue_sal
= find_pc_line (start
, 0);
2271 if (prologue_sal
.line
!= 0) /* Found debug info. */
2272 body_pc
= prologue_sal
.end
;
2274 /* If we are going to analyze the prologue in general without knowing about
2275 the current PC, make the best assumtion for the end of the prologue. */
2278 find_pc_partial_function (start
, 0, NULL
, &end_pc
);
2279 body_pc
= min (end_pc
, body_pc
);
2282 body_pc
= min (pc
, body_pc
);
2289 rtmp
= (xtensa_c0reg_t
*) alloca(nregs
* sizeof(xtensa_c0reg_t
));
2290 /* rt is already initialized in xtensa_alloc_frame_cache(). */
2294 if (!xtensa_default_isa
)
2295 xtensa_default_isa
= xtensa_isa_init (0, 0);
2296 isa
= xtensa_default_isa
;
2297 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2298 ins
= xtensa_insnbuf_alloc (isa
);
2299 slot
= xtensa_insnbuf_alloc (isa
);
2301 for (ia
= start
, bt
= ia
; ia
< body_pc
; ia
+= ilen
)
2303 /* (Re)fill instruction buffer from memory if necessary, but do not
2304 read memory beyond PC to be sure we stay within text section
2305 (this protection only works if a non-zero pc is supplied). */
2307 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2310 bt
= (ba
+ XTENSA_ISA_BSZ
) < body_pc
? ba
+ XTENSA_ISA_BSZ
: body_pc
;
2311 read_memory (ba
, ibuf
, bt
- ba
);
2312 /* If there is a memory reading error read_memory () will report it
2313 and then throw an exception, stopping command execution. */
2316 /* Decode format information. */
2318 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2319 ifmt
= xtensa_format_decode (isa
, ins
);
2320 if (ifmt
== XTENSA_UNDEFINED
)
2325 ilen
= xtensa_format_length (isa
, ifmt
);
2326 if (ilen
== XTENSA_UNDEFINED
)
2331 islots
= xtensa_format_num_slots (isa
, ifmt
);
2332 if (islots
== XTENSA_UNDEFINED
)
2338 /* Analyze a bundle or a single instruction, using a snapshot of
2339 the register tracking info as input for the entire bundle so that
2340 register changes do not take effect within this bundle. */
2342 for (j
= 0; j
< nregs
; ++j
)
2345 for (is
= 0; is
< islots
; ++is
)
2347 /* Decode a slot and classify the opcode. */
2349 fail
= xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
);
2353 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2354 DEBUGVERB ("[call0_analyze_prologue] instr "
2355 "addr = 0x%08x, opc = %d\n",
2357 if (opc
== XTENSA_UNDEFINED
)
2358 opclass
= c0opc_illegal
;
2360 opclass
= call0_classify_opcode (isa
, opc
);
2362 /* Decide whether to track this opcode, ignore it, or bail out. */
2371 case c0opc_uninteresting
:
2380 ia
+= ilen
; /* Skip over 'entry' insn. */
2388 /* Only expected opcodes should get this far. */
2392 /* Extract and decode the operands. */
2393 nods
= xtensa_opcode_num_operands (isa
, opc
);
2394 if (nods
== XTENSA_UNDEFINED
)
2400 for (j
= 0; j
< nods
&& j
< C0_MAXOPDS
; ++j
)
2402 fail
= xtensa_operand_get_field (isa
, opc
, j
, ifmt
,
2407 fail
= xtensa_operand_decode (isa
, opc
, j
, &odv
[j
]);
2412 /* Check operands to verify use of 'mov' assembler macro. */
2413 if (opclass
== c0opc_mov
&& nods
== 3)
2415 if (odv
[2] == odv
[1])
2419 opclass
= c0opc_uninteresting
;
2424 /* Track register movement and modification for this operation. */
2425 call0_track_op (gdbarch
, rt
, rtmp
, opclass
,
2426 nods
, odv
, ia
, litbase
, 1);
2430 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2431 (unsigned)ia
, fail
? "failed" : "succeeded");
2432 xtensa_insnbuf_free(isa
, slot
);
2433 xtensa_insnbuf_free(isa
, ins
);
2434 return fail
? XTENSA_ISA_BADPC
: ia
;
2437 /* Initialize frame cache for the current frame in CALL0 ABI. */
2440 call0_frame_cache (struct frame_info
*this_frame
,
2441 xtensa_frame_cache_t
*cache
,
2442 CORE_ADDR pc
, CORE_ADDR litbase
)
2444 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2445 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2446 CORE_ADDR start_pc
; /* The beginning of the function. */
2447 CORE_ADDR body_pc
=UINT_MAX
; /* PC, where prologue analysis stopped. */
2448 CORE_ADDR sp
, fp
, ra
;
2449 int fp_regnum
, c0_hasfp
, c0_frmsz
, prev_sp
, to_stk
;
2451 /* Find the beginning of the prologue of the function containing the PC
2452 and analyze it up to the PC or the end of the prologue. */
2454 if (find_pc_partial_function (pc
, NULL
, &start_pc
, NULL
))
2456 body_pc
= call0_analyze_prologue (gdbarch
, start_pc
, pc
, litbase
,
2458 &cache
->c0
.c0_rt
[0],
2461 if (body_pc
== XTENSA_ISA_BADPC
)
2462 error (_("Xtensa-specific internal error: CALL0 prologue \
2463 analysis failed in this frame. GDB command execution stopped."));
2466 sp
= get_frame_register_unsigned
2467 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
2468 fp
= sp
; /* Assume FP == SP until proven otherwise. */
2470 /* Get the frame information and FP (if used) at the current PC.
2471 If PC is in the prologue, the prologue analysis is more reliable
2472 than DWARF info. We don't not know for sure if PC is in the prologue,
2473 but we know no calls have yet taken place, so we can almost
2474 certainly rely on the prologue analysis. */
2478 /* Prologue analysis was successful up to the PC.
2479 It includes the cases when PC == START_PC. */
2480 c0_hasfp
= cache
->c0
.c0_rt
[C0_FP
].fr_reg
== C0_SP
;
2481 /* c0_hasfp == true means there is a frame pointer because
2482 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2483 was derived from SP. Otherwise, it would be C0_FP. */
2484 fp_regnum
= c0_hasfp
? C0_FP
: C0_SP
;
2485 c0_frmsz
= - cache
->c0
.c0_rt
[fp_regnum
].fr_ofs
;
2486 fp_regnum
+= gdbarch_tdep (gdbarch
)->a0_base
;
2488 else /* No data from the prologue analysis. */
2491 fp_regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_SP
;
2496 prev_sp
= fp
+ c0_frmsz
;
2498 /* Frame size from debug info or prologue tracking does not account for
2499 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2502 fp
= get_frame_register_unsigned (this_frame
, fp_regnum
);
2504 /* Recalculate previous SP. */
2505 prev_sp
= fp
+ c0_frmsz
;
2506 /* Update the stack frame size. */
2507 c0_frmsz
+= fp
- sp
;
2510 /* Get the return address (RA) from the stack if saved,
2511 or try to get it from a register. */
2513 to_stk
= cache
->c0
.c0_rt
[C0_RA
].to_stk
;
2514 if (to_stk
!= C0_NOSTK
)
2516 read_memory_integer (sp
+ c0_frmsz
+ cache
->c0
.c0_rt
[C0_RA
].to_stk
,
2519 else if (cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_CONST
2520 && cache
->c0
.c0_rt
[C0_RA
].fr_ofs
== 0)
2522 /* Special case for terminating backtrace at a function that
2523 wants to be seen as the outermost. Such a function will
2524 clear it's RA (A0) register to 0 in the prologue instead of
2525 saving its original value. */
2530 /* RA was copied to another register or (before any function
2531 call) may still be in the original RA register. This is not
2532 always reliable: even in a leaf function, register tracking
2533 stops after prologue, and even in prologue, non-prologue
2534 instructions (not tracked) may overwrite RA or any register
2535 it was copied to. If likely in prologue or before any call,
2536 use retracking info and hope for the best (compiler should
2537 have saved RA in stack if not in a leaf function). If not in
2538 prologue, too bad. */
2543 (i
== C0_RA
|| cache
->c0
.c0_rt
[i
].fr_reg
!= C0_RA
);
2545 if (i
>= C0_NREGS
&& cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_RA
)
2549 ra
= get_frame_register_unsigned
2551 gdbarch_tdep (gdbarch
)->a0_base
+ cache
->c0
.c0_rt
[i
].fr_reg
);
2556 cache
->pc
= start_pc
;
2558 /* RA == 0 marks the outermost frame. Do not go past it. */
2559 cache
->prev_sp
= (ra
!= 0) ? prev_sp
: 0;
2560 cache
->c0
.fp_regnum
= fp_regnum
;
2561 cache
->c0
.c0_frmsz
= c0_frmsz
;
2562 cache
->c0
.c0_hasfp
= c0_hasfp
;
2563 cache
->c0
.c0_fp
= fp
;
2566 static CORE_ADDR a0_saved
;
2567 static CORE_ADDR a7_saved
;
2568 static CORE_ADDR a11_saved
;
2569 static int a0_was_saved
;
2570 static int a7_was_saved
;
2571 static int a11_was_saved
;
2573 /* Simulate L32E insn: AT <-- ref (AS + offset). */
2575 execute_l32e (struct gdbarch
*gdbarch
, int at
, int as
, int offset
, CORE_ADDR wb
)
2577 int atreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ at
, wb
);
2578 int asreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ as
, wb
);
2579 CORE_ADDR addr
= xtensa_read_register (asreg
) + offset
;
2580 unsigned int spilled_value
2581 = read_memory_unsigned_integer (addr
, 4, gdbarch_byte_order (gdbarch
));
2583 if ((at
== 0) && !a0_was_saved
)
2585 a0_saved
= xtensa_read_register (atreg
);
2588 else if ((at
== 7) && !a7_was_saved
)
2590 a7_saved
= xtensa_read_register (atreg
);
2593 else if ((at
== 11) && !a11_was_saved
)
2595 a11_saved
= xtensa_read_register (atreg
);
2599 xtensa_write_register (atreg
, spilled_value
);
2602 /* Simulate S32E insn: AT --> ref (AS + offset). */
2604 execute_s32e (struct gdbarch
*gdbarch
, int at
, int as
, int offset
, CORE_ADDR wb
)
2606 int atreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ at
, wb
);
2607 int asreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ as
, wb
);
2608 CORE_ADDR addr
= xtensa_read_register (asreg
) + offset
;
2609 ULONGEST spilled_value
= xtensa_read_register (atreg
);
2611 write_memory_unsigned_integer (addr
, 4,
2612 gdbarch_byte_order (gdbarch
),
2616 #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2621 xtNoExceptionHandler
2622 } xtensa_exception_handler_t
;
2624 /* Execute insn stream from current PC until hitting RFWU or RFWO.
2625 Return type of Xtensa Window Interrupt Handler on success. */
2626 static xtensa_exception_handler_t
2627 execute_code (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
, CORE_ADDR wb
)
2630 xtensa_insnbuf ins
, slot
;
2631 char ibuf
[XTENSA_ISA_BSZ
];
2632 CORE_ADDR ia
, bt
, ba
;
2634 int ilen
, islots
, is
;
2638 void (*func
) (struct gdbarch
*, int, int, int, CORE_ADDR
);
2643 /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
2644 int WindowUnderflow12
= (current_pc
& 0x1ff) >= 0x140;
2646 isa
= xtensa_default_isa
;
2647 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2648 ins
= xtensa_insnbuf_alloc (isa
);
2649 slot
= xtensa_insnbuf_alloc (isa
);
2658 while (insn_num
++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN
)
2660 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2663 bt
= (ba
+ XTENSA_ISA_BSZ
);
2664 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0)
2665 return xtNoExceptionHandler
;
2667 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2668 ifmt
= xtensa_format_decode (isa
, ins
);
2669 if (ifmt
== XTENSA_UNDEFINED
)
2670 return xtNoExceptionHandler
;
2671 ilen
= xtensa_format_length (isa
, ifmt
);
2672 if (ilen
== XTENSA_UNDEFINED
)
2673 return xtNoExceptionHandler
;
2674 islots
= xtensa_format_num_slots (isa
, ifmt
);
2675 if (islots
== XTENSA_UNDEFINED
)
2676 return xtNoExceptionHandler
;
2677 for (is
= 0; is
< islots
; ++is
)
2679 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
2680 return xtNoExceptionHandler
;
2681 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2682 if (opc
== XTENSA_UNDEFINED
)
2683 return xtNoExceptionHandler
;
2684 switch (call0_classify_opcode (isa
, opc
))
2690 /* We expect none of them here. */
2691 return xtNoExceptionHandler
;
2693 func
= execute_l32e
;
2696 func
= execute_s32e
;
2698 case c0opc_rfwo
: /* RFWO. */
2699 /* Here, we return from WindowOverflow handler and,
2700 if we stopped at the very beginning, which means
2701 A0 was saved, we have to restore it now. */
2704 int arreg
= arreg_number (gdbarch
,
2705 gdbarch_tdep (gdbarch
)->a0_base
,
2707 xtensa_write_register (arreg
, a0_saved
);
2709 return xtWindowOverflow
;
2710 case c0opc_rfwu
: /* RFWU. */
2711 /* Here, we return from WindowUnderflow handler.
2712 Let's see if either A7 or A11 has to be restored. */
2713 if (WindowUnderflow12
)
2717 int arreg
= arreg_number (gdbarch
,
2718 gdbarch_tdep (gdbarch
)->a0_base
+ 11,
2720 xtensa_write_register (arreg
, a11_saved
);
2723 else if (a7_was_saved
)
2725 int arreg
= arreg_number (gdbarch
,
2726 gdbarch_tdep (gdbarch
)->a0_base
+ 7,
2728 xtensa_write_register (arreg
, a7_saved
);
2730 return xtWindowUnderflow
;
2731 default: /* Simply skip this insns. */
2735 /* Decode arguments for L32E / S32E and simulate their execution. */
2736 if ( xtensa_opcode_num_operands (isa
, opc
) != 3 )
2737 return xtNoExceptionHandler
;
2738 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
, &at
))
2739 return xtNoExceptionHandler
;
2740 if (xtensa_operand_decode (isa
, opc
, 0, &at
))
2741 return xtNoExceptionHandler
;
2742 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
, is
, slot
, &as
))
2743 return xtNoExceptionHandler
;
2744 if (xtensa_operand_decode (isa
, opc
, 1, &as
))
2745 return xtNoExceptionHandler
;
2746 if (xtensa_operand_get_field (isa
, opc
, 2, ifmt
, is
, slot
, &offset
))
2747 return xtNoExceptionHandler
;
2748 if (xtensa_operand_decode (isa
, opc
, 2, &offset
))
2749 return xtNoExceptionHandler
;
2751 (*func
) (gdbarch
, at
, as
, offset
, wb
);
2756 return xtNoExceptionHandler
;
2759 /* Handle Window Overflow / Underflow exception frames. */
2762 xtensa_window_interrupt_frame_cache (struct frame_info
*this_frame
,
2763 xtensa_frame_cache_t
*cache
,
2766 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2767 CORE_ADDR ps
, wb
, ws
, ra
;
2768 int epc1_regnum
, i
, regnum
;
2769 xtensa_exception_handler_t eh_type
;
2771 /* Read PS, WB, and WS from the hardware. Note that PS register
2772 must be present, if Windowed ABI is supported. */
2773 ps
= xtensa_read_register (gdbarch_ps_regnum (gdbarch
));
2774 wb
= xtensa_read_register (gdbarch_tdep (gdbarch
)->wb_regnum
);
2775 ws
= xtensa_read_register (gdbarch_tdep (gdbarch
)->ws_regnum
);
2777 /* Execute all the remaining instructions from Window Interrupt Handler
2778 by simulating them on the remote protocol level. On return, set the
2779 type of Xtensa Window Interrupt Handler, or report an error. */
2780 eh_type
= execute_code (gdbarch
, pc
, wb
);
2781 if (eh_type
== xtNoExceptionHandler
)
2783 Unable to decode Xtensa Window Interrupt Handler's code."));
2785 cache
->ps
= ps
^ PS_EXC
; /* Clear the exception bit in PS. */
2786 cache
->call0
= 0; /* It's Windowed ABI. */
2788 /* All registers for the cached frame will be alive. */
2789 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
2790 cache
->wd
.aregs
[i
] = -1;
2792 if (eh_type
== xtWindowOverflow
)
2793 cache
->wd
.ws
= ws
^ (1 << wb
);
2794 else /* eh_type == xtWindowUnderflow. */
2795 cache
->wd
.ws
= ws
| (1 << wb
);
2797 cache
->wd
.wb
= (ps
& 0xf00) >> 8; /* Set WB to OWB. */
2798 regnum
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
,
2800 ra
= xtensa_read_register (regnum
);
2801 cache
->wd
.callsize
= WINSIZE (ra
);
2802 cache
->prev_sp
= xtensa_read_register (regnum
+ 1);
2803 /* Set regnum to a frame pointer of the frame being cached. */
2804 regnum
= xtensa_scan_prologue (gdbarch
, pc
);
2805 regnum
= arreg_number (gdbarch
,
2806 gdbarch_tdep (gdbarch
)->a0_base
+ regnum
,
2808 cache
->base
= get_frame_register_unsigned (this_frame
, regnum
);
2810 /* Read PC of interrupted function from EPC1 register. */
2811 epc1_regnum
= xtensa_find_register_by_name (gdbarch
,"epc1");
2812 if (epc1_regnum
< 0)
2813 error(_("Unable to read Xtensa register EPC1"));
2814 cache
->ra
= xtensa_read_register (epc1_regnum
);
2815 cache
->pc
= get_frame_func (this_frame
);
2819 /* Skip function prologue.
2821 Return the pc of the first instruction after prologue. GDB calls this to
2822 find the address of the first line of the function or (if there is no line
2823 number information) to skip the prologue for planting breakpoints on
2824 function entries. Use debug info (if present) or prologue analysis to skip
2825 the prologue to achieve reliable debugging behavior. For windowed ABI,
2826 only the 'entry' instruction is skipped. It is not strictly necessary to
2827 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2828 backtrace at any point in the prologue, however certain potential hazards
2829 are avoided and a more "normal" debugging experience is ensured by
2830 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2831 For example, if we don't skip the prologue:
2832 - Some args may not yet have been saved to the stack where the debug
2833 info expects to find them (true anyway when only 'entry' is skipped);
2834 - Software breakpoints ('break' instrs) may not have been unplanted
2835 when the prologue analysis is done on initializing the frame cache,
2836 and breaks in the prologue will throw off the analysis.
2838 If we have debug info ( line-number info, in particular ) we simply skip
2839 the code associated with the first function line effectively skipping
2840 the prologue code. It works even in cases like
2843 { int local_var = 1;
2847 because, for this source code, both Xtensa compilers will generate two
2848 separate entries ( with the same line number ) in dwarf line-number
2849 section to make sure there is a boundary between the prologue code and
2850 the rest of the function.
2852 If there is no debug info, we need to analyze the code. */
2854 /* #define DONT_SKIP_PROLOGUE */
2857 xtensa_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
2859 struct symtab_and_line prologue_sal
;
2862 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc
);
2864 #if DONT_SKIP_PROLOGUE
2868 /* Try to find first body line from debug info. */
2870 prologue_sal
= find_pc_line (start_pc
, 0);
2871 if (prologue_sal
.line
!= 0) /* Found debug info. */
2873 /* In Call0, it is possible to have a function with only one instruction
2874 ('ret') resulting from a 1-line optimized function that does nothing.
2875 In that case, prologue_sal.end may actually point to the start of the
2876 next function in the text section, causing a breakpoint to be set at
2877 the wrong place. Check if the end address is in a different function,
2878 and if so return the start PC. We know we have symbol info. */
2882 find_pc_partial_function (prologue_sal
.end
, NULL
, &end_func
, NULL
);
2883 if (end_func
!= start_pc
)
2886 return prologue_sal
.end
;
2889 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
2890 body_pc
= call0_analyze_prologue (gdbarch
, start_pc
, 0, 0, 0, NULL
, NULL
);
2891 return body_pc
!= 0 ? body_pc
: start_pc
;
2894 /* Verify the current configuration. */
2896 xtensa_verify_config (struct gdbarch
*gdbarch
)
2898 struct ui_file
*log
;
2899 struct cleanup
*cleanups
;
2900 struct gdbarch_tdep
*tdep
;
2904 tdep
= gdbarch_tdep (gdbarch
);
2905 log
= mem_fileopen ();
2906 cleanups
= make_cleanup_ui_file_delete (log
);
2908 /* Verify that we got a reasonable number of AREGS. */
2909 if ((tdep
->num_aregs
& -tdep
->num_aregs
) != tdep
->num_aregs
)
2910 fprintf_unfiltered (log
, _("\
2911 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
2914 /* Verify that certain registers exist. */
2916 if (tdep
->pc_regnum
== -1)
2917 fprintf_unfiltered (log
, _("\n\tpc_regnum: No PC register"));
2918 if (tdep
->isa_use_exceptions
&& tdep
->ps_regnum
== -1)
2919 fprintf_unfiltered (log
, _("\n\tps_regnum: No PS register"));
2921 if (tdep
->isa_use_windowed_registers
)
2923 if (tdep
->wb_regnum
== -1)
2924 fprintf_unfiltered (log
, _("\n\twb_regnum: No WB register"));
2925 if (tdep
->ws_regnum
== -1)
2926 fprintf_unfiltered (log
, _("\n\tws_regnum: No WS register"));
2927 if (tdep
->ar_base
== -1)
2928 fprintf_unfiltered (log
, _("\n\tar_base: No AR registers"));
2931 if (tdep
->a0_base
== -1)
2932 fprintf_unfiltered (log
, _("\n\ta0_base: No Ax registers"));
2934 buf
= ui_file_xstrdup (log
, &length
);
2935 make_cleanup (xfree
, buf
);
2937 internal_error (__FILE__
, __LINE__
,
2938 _("the following are invalid: %s"), buf
);
2939 do_cleanups (cleanups
);
2943 /* Derive specific register numbers from the array of registers. */
2946 xtensa_derive_tdep (struct gdbarch_tdep
*tdep
)
2948 xtensa_register_t
* rmap
;
2949 int n
, max_size
= 4;
2952 tdep
->num_nopriv_regs
= 0;
2954 /* Special registers 0..255 (core). */
2955 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
2957 for (rmap
= tdep
->regmap
, n
= 0; rmap
->target_number
!= -1; n
++, rmap
++)
2959 if (rmap
->target_number
== 0x0020)
2960 tdep
->pc_regnum
= n
;
2961 else if (rmap
->target_number
== 0x0100)
2963 else if (rmap
->target_number
== 0x0000)
2965 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(72))
2966 tdep
->wb_regnum
= n
;
2967 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(73))
2968 tdep
->ws_regnum
= n
;
2969 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(233))
2970 tdep
->debugcause_regnum
= n
;
2971 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(232))
2972 tdep
->exccause_regnum
= n
;
2973 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(238))
2974 tdep
->excvaddr_regnum
= n
;
2975 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(0))
2976 tdep
->lbeg_regnum
= n
;
2977 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(1))
2978 tdep
->lend_regnum
= n
;
2979 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(2))
2980 tdep
->lcount_regnum
= n
;
2981 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(3))
2982 tdep
->sar_regnum
= n
;
2983 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(5))
2984 tdep
->litbase_regnum
= n
;
2985 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(230))
2986 tdep
->ps_regnum
= n
;
2988 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(226))
2989 tdep
->interrupt_regnum
= n
;
2990 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(227))
2991 tdep
->interrupt2_regnum
= n
;
2992 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(224))
2993 tdep
->cpenable_regnum
= n
;
2996 if (rmap
->byte_size
> max_size
)
2997 max_size
= rmap
->byte_size
;
2998 if (rmap
->mask
!= 0 && tdep
->num_regs
== 0)
3000 /* Find out out how to deal with priveleged registers.
3002 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3003 && tdep->num_nopriv_regs == 0)
3004 tdep->num_nopriv_regs = n;
3006 if ((rmap
->flags
& XTENSA_REGISTER_FLAGS_PRIVILEGED
) != 0
3007 && tdep
->num_regs
== 0)
3011 /* Number of pseudo registers. */
3012 tdep
->num_pseudo_regs
= n
- tdep
->num_regs
;
3014 /* Empirically determined maximum sizes. */
3015 tdep
->max_register_raw_size
= max_size
;
3016 tdep
->max_register_virtual_size
= max_size
;
3019 /* Module "constructor" function. */
3021 extern struct gdbarch_tdep xtensa_tdep
;
3023 static struct gdbarch
*
3024 xtensa_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3026 struct gdbarch_tdep
*tdep
;
3027 struct gdbarch
*gdbarch
;
3028 struct xtensa_abi_handler
*abi_handler
;
3030 DEBUGTRACE ("gdbarch_init()\n");
3032 /* We have to set the byte order before we call gdbarch_alloc. */
3033 info
.byte_order
= XCHAL_HAVE_BE
? BFD_ENDIAN_BIG
: BFD_ENDIAN_LITTLE
;
3035 tdep
= &xtensa_tdep
;
3036 gdbarch
= gdbarch_alloc (&info
, tdep
);
3037 xtensa_derive_tdep (tdep
);
3039 /* Verify our configuration. */
3040 xtensa_verify_config (gdbarch
);
3042 /* Pseudo-Register read/write. */
3043 set_gdbarch_pseudo_register_read (gdbarch
, xtensa_pseudo_register_read
);
3044 set_gdbarch_pseudo_register_write (gdbarch
, xtensa_pseudo_register_write
);
3046 /* Set target information. */
3047 set_gdbarch_num_regs (gdbarch
, tdep
->num_regs
);
3048 set_gdbarch_num_pseudo_regs (gdbarch
, tdep
->num_pseudo_regs
);
3049 set_gdbarch_sp_regnum (gdbarch
, tdep
->a0_base
+ 1);
3050 set_gdbarch_pc_regnum (gdbarch
, tdep
->pc_regnum
);
3051 set_gdbarch_ps_regnum (gdbarch
, tdep
->ps_regnum
);
3053 /* Renumber registers for known formats (stabs and dwarf2). */
3054 set_gdbarch_stab_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
3055 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
3057 /* We provide our own function to get register information. */
3058 set_gdbarch_register_name (gdbarch
, xtensa_register_name
);
3059 set_gdbarch_register_type (gdbarch
, xtensa_register_type
);
3061 /* To call functions from GDB using dummy frame. */
3062 set_gdbarch_push_dummy_call (gdbarch
, xtensa_push_dummy_call
);
3064 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
3066 set_gdbarch_return_value (gdbarch
, xtensa_return_value
);
3068 /* Advance PC across any prologue instructions to reach "real" code. */
3069 set_gdbarch_skip_prologue (gdbarch
, xtensa_skip_prologue
);
3071 /* Stack grows downward. */
3072 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3074 /* Set breakpoints. */
3075 set_gdbarch_breakpoint_from_pc (gdbarch
, xtensa_breakpoint_from_pc
);
3077 /* After breakpoint instruction or illegal instruction, pc still
3078 points at break instruction, so don't decrement. */
3079 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
3081 /* We don't skip args. */
3082 set_gdbarch_frame_args_skip (gdbarch
, 0);
3084 set_gdbarch_unwind_pc (gdbarch
, xtensa_unwind_pc
);
3086 set_gdbarch_frame_align (gdbarch
, xtensa_frame_align
);
3088 set_gdbarch_dummy_id (gdbarch
, xtensa_dummy_id
);
3090 /* Frame handling. */
3091 frame_base_set_default (gdbarch
, &xtensa_frame_base
);
3092 frame_unwind_append_unwinder (gdbarch
, &xtensa_unwind
);
3093 dwarf2_append_unwinders (gdbarch
);
3095 set_gdbarch_print_insn (gdbarch
, print_insn_xtensa
);
3097 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3099 xtensa_add_reggroups (gdbarch
);
3100 set_gdbarch_register_reggroup_p (gdbarch
, xtensa_register_reggroup_p
);
3102 set_gdbarch_regset_from_core_section (gdbarch
,
3103 xtensa_regset_from_core_section
);
3105 set_solib_svr4_fetch_link_map_offsets
3106 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
3112 xtensa_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3114 error (_("xtensa_dump_tdep(): not implemented"));
3117 /* Provide a prototype to silence -Wmissing-prototypes. */
3118 extern initialize_file_ftype _initialize_xtensa_tdep
;
3121 _initialize_xtensa_tdep (void)
3123 struct cmd_list_element
*c
;
3125 gdbarch_register (bfd_arch_xtensa
, xtensa_gdbarch_init
, xtensa_dump_tdep
);
3126 xtensa_init_reggroups ();
3128 add_setshow_zinteger_cmd ("xtensa",
3130 &xtensa_debug_level
,
3131 _("Set Xtensa debugging."),
3132 _("Show Xtensa debugging."), _("\
3133 When non-zero, Xtensa-specific debugging is enabled. \
3134 Can be 1, 2, 3, or 4 indicating the level of debugging."),
3137 &setdebuglist
, &showdebuglist
);