1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005-2012 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "solib-svr4.h"
31 #include "floatformat.h"
33 #include "reggroups.h"
36 #include "dummy-frame.h"
38 #include "dwarf2-frame.h"
39 #include "dwarf2loc.h"
41 #include "frame-base.h"
42 #include "frame-unwind.h"
44 #include "arch-utils.h"
51 #include "gdb_assert.h"
53 #include "xtensa-isa.h"
54 #include "xtensa-tdep.h"
55 #include "xtensa-config.h"
58 static int xtensa_debug_level
= 0;
60 #define DEBUGWARN(args...) \
61 if (xtensa_debug_level > 0) \
62 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
64 #define DEBUGINFO(args...) \
65 if (xtensa_debug_level > 1) \
66 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
68 #define DEBUGTRACE(args...) \
69 if (xtensa_debug_level > 2) \
70 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
72 #define DEBUGVERB(args...) \
73 if (xtensa_debug_level > 3) \
74 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
77 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
78 #define SP_ALIGNMENT 16
81 /* On Windowed ABI, we use a6 through a11 for passing arguments
82 to a function called by GDB because CALL4 is used. */
83 #define ARGS_NUM_REGS 6
84 #define REGISTER_SIZE 4
87 /* Extract the call size from the return address or PS register. */
88 #define PS_CALLINC_SHIFT 16
89 #define PS_CALLINC_MASK 0x00030000
90 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
91 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
93 /* On TX, hardware can be configured without Exception Option.
94 There is no PS register in this case. Inside XT-GDB, let us treat
95 it as a virtual read-only register always holding the same value. */
98 /* ABI-independent macros. */
99 #define ARG_NOF(gdbarch) \
100 (gdbarch_tdep (gdbarch)->call_abi \
101 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
102 #define ARG_1ST(gdbarch) \
103 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
104 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
105 : (gdbarch_tdep (gdbarch)->a0_base + 6))
107 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
108 indicates that the instruction is an ENTRY instruction. */
110 #define XTENSA_IS_ENTRY(gdbarch, op1) \
111 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
112 ? ((op1) == 0x6c) : ((op1) == 0x36))
114 #define XTENSA_ENTRY_LENGTH 3
116 /* windowing_enabled() returns true, if windowing is enabled.
117 WOE must be set to 1; EXCM to 0.
118 Note: We assume that EXCM is always 0 for XEA1. */
120 #define PS_WOE (1<<18)
121 #define PS_EXC (1<<4)
124 windowing_enabled (struct gdbarch
*gdbarch
, unsigned int ps
)
126 /* If we know CALL0 ABI is set explicitly, say it is Call0. */
127 if (gdbarch_tdep (gdbarch
)->call_abi
== CallAbiCall0Only
)
130 return ((ps
& PS_EXC
) == 0 && (ps
& PS_WOE
) != 0);
133 /* Convert a live A-register number to the corresponding AR-register
136 arreg_number (struct gdbarch
*gdbarch
, int a_regnum
, ULONGEST wb
)
138 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
141 arreg
= a_regnum
- tdep
->a0_base
;
142 arreg
+= (wb
& ((tdep
->num_aregs
- 1) >> 2)) << WB_SHIFT
;
143 arreg
&= tdep
->num_aregs
- 1;
145 return arreg
+ tdep
->ar_base
;
148 /* Convert a live AR-register number to the corresponding A-register order
149 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
151 areg_number (struct gdbarch
*gdbarch
, int ar_regnum
, unsigned int wb
)
153 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
156 areg
= ar_regnum
- tdep
->ar_base
;
157 if (areg
< 0 || areg
>= tdep
->num_aregs
)
159 areg
= (areg
- wb
* 4) & (tdep
->num_aregs
- 1);
160 return (areg
> 15) ? -1 : areg
;
163 /* Read Xtensa register directly from the hardware. */
165 xtensa_read_register (int regnum
)
169 regcache_raw_read_unsigned (get_current_regcache (), regnum
, &value
);
170 return (unsigned long) value
;
173 /* Write Xtensa register directly to the hardware. */
175 xtensa_write_register (int regnum
, ULONGEST value
)
177 regcache_raw_write_unsigned (get_current_regcache (), regnum
, value
);
180 /* Return the window size of the previous call to the function from which we
183 This function is used to extract the return value after a called function
184 has returned to the caller. On Xtensa, the register that holds the return
185 value (from the perspective of the caller) depends on what call
186 instruction was used. For now, we are assuming that the call instruction
187 precedes the current address, so we simply analyze the call instruction.
188 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
189 method to call the inferior function. */
192 extract_call_winsize (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
194 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
199 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc
);
201 /* Read the previous instruction (should be a call[x]{4|8|12}. */
202 read_memory (pc
-3, buf
, 3);
203 insn
= extract_unsigned_integer (buf
, 3, byte_order
);
205 /* Decode call instruction:
207 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
208 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
210 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
211 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
213 if (byte_order
== BFD_ENDIAN_LITTLE
)
215 if (((insn
& 0xf) == 0x5) || ((insn
& 0xcf) == 0xc0))
216 winsize
= (insn
& 0x30) >> 2; /* 0, 4, 8, 12. */
220 if (((insn
>> 20) == 0x5) || (((insn
>> 16) & 0xf3) == 0x03))
221 winsize
= (insn
>> 16) & 0xc; /* 0, 4, 8, 12. */
227 /* REGISTER INFORMATION */
229 /* Find register by name. */
231 xtensa_find_register_by_name (struct gdbarch
*gdbarch
, char *name
)
235 for (i
= 0; i
< gdbarch_num_regs (gdbarch
)
236 + gdbarch_num_pseudo_regs (gdbarch
);
239 if (strcasecmp (gdbarch_tdep (gdbarch
)->regmap
[i
].name
, name
) == 0)
245 /* Returns the name of a register. */
247 xtensa_register_name (struct gdbarch
*gdbarch
, int regnum
)
249 /* Return the name stored in the register map. */
250 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
)
251 + gdbarch_num_pseudo_regs (gdbarch
))
252 return gdbarch_tdep (gdbarch
)->regmap
[regnum
].name
;
254 internal_error (__FILE__
, __LINE__
, _("invalid register %d"), regnum
);
258 /* Return the type of a register. Create a new type, if necessary. */
261 xtensa_register_type (struct gdbarch
*gdbarch
, int regnum
)
263 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
265 /* Return signed integer for ARx and Ax registers. */
266 if ((regnum
>= tdep
->ar_base
267 && regnum
< tdep
->ar_base
+ tdep
->num_aregs
)
268 || (regnum
>= tdep
->a0_base
269 && regnum
< tdep
->a0_base
+ 16))
270 return builtin_type (gdbarch
)->builtin_int
;
272 if (regnum
== gdbarch_pc_regnum (gdbarch
)
273 || regnum
== tdep
->a0_base
+ 1)
274 return builtin_type (gdbarch
)->builtin_data_ptr
;
276 /* Return the stored type for all other registers. */
277 else if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
)
278 + gdbarch_num_pseudo_regs (gdbarch
))
280 xtensa_register_t
* reg
= &tdep
->regmap
[regnum
];
282 /* Set ctype for this register (only the first time). */
286 struct ctype_cache
*tp
;
287 int size
= reg
->byte_size
;
289 /* We always use the memory representation,
290 even if the register width is smaller. */
294 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint8
;
298 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint16
;
302 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint32
;
306 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint64
;
310 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint128
;
314 for (tp
= tdep
->type_entries
; tp
!= NULL
; tp
= tp
->next
)
315 if (tp
->size
== size
)
320 char *name
= xstrprintf ("int%d", size
* 8);
321 tp
= xmalloc (sizeof (struct ctype_cache
));
322 tp
->next
= tdep
->type_entries
;
323 tdep
->type_entries
= tp
;
326 = arch_integer_type (gdbarch
, size
* 8, 1, name
);
330 reg
->ctype
= tp
->virtual_type
;
336 internal_error (__FILE__
, __LINE__
, _("invalid register number %d"), regnum
);
341 /* Return the 'local' register number for stubs, dwarf2, etc.
342 The debugging information enumerates registers starting from 0 for A0
343 to n for An. So, we only have to add the base number for A0. */
346 xtensa_reg_to_regnum (struct gdbarch
*gdbarch
, int regnum
)
350 if (regnum
>= 0 && regnum
< 16)
351 return gdbarch_tdep (gdbarch
)->a0_base
+ regnum
;
354 i
< gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
356 if (regnum
== gdbarch_tdep (gdbarch
)->regmap
[i
].target_number
)
359 internal_error (__FILE__
, __LINE__
,
360 _("invalid dwarf/stabs register number %d"), regnum
);
365 /* Write the bits of a masked register to the various registers.
366 Only the masked areas of these registers are modified; the other
367 fields are untouched. The size of masked registers is always less
368 than or equal to 32 bits. */
371 xtensa_register_write_masked (struct regcache
*regcache
,
372 xtensa_register_t
*reg
, const gdb_byte
*buffer
)
374 unsigned int value
[(MAX_REGISTER_SIZE
+ 3) / 4];
375 const xtensa_mask_t
*mask
= reg
->mask
;
377 int shift
= 0; /* Shift for next mask (mod 32). */
378 int start
, size
; /* Start bit and size of current mask. */
380 unsigned int *ptr
= value
;
381 unsigned int regval
, m
, mem
= 0;
383 int bytesize
= reg
->byte_size
;
384 int bitsize
= bytesize
* 8;
387 DEBUGTRACE ("xtensa_register_write_masked ()\n");
389 /* Copy the masked register to host byte-order. */
390 if (gdbarch_byte_order (get_regcache_arch (regcache
)) == BFD_ENDIAN_BIG
)
391 for (i
= 0; i
< bytesize
; i
++)
394 mem
|= (buffer
[bytesize
- i
- 1] << 24);
399 for (i
= 0; i
< bytesize
; i
++)
402 mem
|= (buffer
[i
] << 24);
407 /* We might have to shift the final value:
408 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
409 bytesize & 3 == x -> shift (4-x) * 8. */
411 *ptr
= mem
>> (((0 - bytesize
) & 3) * 8);
415 /* Write the bits to the masked areas of the other registers. */
416 for (i
= 0; i
< mask
->count
; i
++)
418 start
= mask
->mask
[i
].bit_start
;
419 size
= mask
->mask
[i
].bit_size
;
420 regval
= mem
>> shift
;
422 if ((shift
+= size
) > bitsize
)
423 error (_("size of all masks is larger than the register"));
432 regval
|= mem
<< (size
- shift
);
435 /* Make sure we have a valid register. */
436 r
= mask
->mask
[i
].reg_num
;
437 if (r
>= 0 && size
> 0)
439 /* Don't overwrite the unmasked areas. */
441 regcache_cooked_read_unsigned (regcache
, r
, &old_val
);
442 m
= 0xffffffff >> (32 - size
) << start
;
444 regval
= (regval
& m
) | (old_val
& ~m
);
445 regcache_cooked_write_unsigned (regcache
, r
, regval
);
451 /* Read a tie state or mapped registers. Read the masked areas
452 of the registers and assemble them into a single value. */
454 static enum register_status
455 xtensa_register_read_masked (struct regcache
*regcache
,
456 xtensa_register_t
*reg
, gdb_byte
*buffer
)
458 unsigned int value
[(MAX_REGISTER_SIZE
+ 3) / 4];
459 const xtensa_mask_t
*mask
= reg
->mask
;
464 unsigned int *ptr
= value
;
465 unsigned int regval
, mem
= 0;
467 int bytesize
= reg
->byte_size
;
468 int bitsize
= bytesize
* 8;
471 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
472 reg
->name
== 0 ? "" : reg
->name
);
474 /* Assemble the register from the masked areas of other registers. */
475 for (i
= 0; i
< mask
->count
; i
++)
477 int r
= mask
->mask
[i
].reg_num
;
480 enum register_status status
;
483 status
= regcache_cooked_read_unsigned (regcache
, r
, &val
);
484 if (status
!= REG_VALID
)
486 regval
= (unsigned int) val
;
491 start
= mask
->mask
[i
].bit_start
;
492 size
= mask
->mask
[i
].bit_size
;
497 regval
&= (0xffffffff >> (32 - size
));
499 mem
|= regval
<< shift
;
501 if ((shift
+= size
) > bitsize
)
502 error (_("size of all masks is larger than the register"));
513 mem
= regval
>> (size
- shift
);
520 /* Copy value to target byte order. */
524 if (gdbarch_byte_order (get_regcache_arch (regcache
)) == BFD_ENDIAN_BIG
)
525 for (i
= 0; i
< bytesize
; i
++)
529 buffer
[bytesize
- i
- 1] = mem
& 0xff;
533 for (i
= 0; i
< bytesize
; i
++)
537 buffer
[i
] = mem
& 0xff;
545 /* Read pseudo registers. */
547 static enum register_status
548 xtensa_pseudo_register_read (struct gdbarch
*gdbarch
,
549 struct regcache
*regcache
,
553 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
555 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
556 regnum
, xtensa_register_name (gdbarch
, regnum
));
558 if (regnum
== gdbarch_num_regs (gdbarch
)
559 + gdbarch_num_pseudo_regs (gdbarch
) - 1)
560 regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ 1;
562 /* Read aliases a0..a15, if this is a Windowed ABI. */
563 if (gdbarch_tdep (gdbarch
)->isa_use_windowed_registers
564 && (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
)
565 && (regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15))
567 gdb_byte
*buf
= (gdb_byte
*) alloca (MAX_REGISTER_SIZE
);
568 enum register_status status
;
570 status
= regcache_raw_read (regcache
,
571 gdbarch_tdep (gdbarch
)->wb_regnum
,
573 if (status
!= REG_VALID
)
575 regnum
= arreg_number (gdbarch
, regnum
,
576 extract_unsigned_integer (buf
, 4, byte_order
));
579 /* We can always read non-pseudo registers. */
580 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
581 return regcache_raw_read (regcache
, regnum
, buffer
);
583 /* We have to find out how to deal with priveleged registers.
584 Let's treat them as pseudo-registers, but we cannot read/write them. */
586 else if (regnum
< gdbarch_tdep (gdbarch
)->a0_base
)
588 buffer
[0] = (gdb_byte
)0;
589 buffer
[1] = (gdb_byte
)0;
590 buffer
[2] = (gdb_byte
)0;
591 buffer
[3] = (gdb_byte
)0;
594 /* Pseudo registers. */
596 && regnum
< gdbarch_num_regs (gdbarch
)
597 + gdbarch_num_pseudo_regs (gdbarch
))
599 xtensa_register_t
*reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
600 xtensa_register_type_t type
= reg
->type
;
601 int flags
= gdbarch_tdep (gdbarch
)->target_flags
;
603 /* We cannot read Unknown or Unmapped registers. */
604 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
606 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
608 warning (_("cannot read register %s"),
609 xtensa_register_name (gdbarch
, regnum
));
614 /* Some targets cannot read TIE register files. */
615 else if (type
== xtRegisterTypeTieRegfile
)
617 /* Use 'fetch' to get register? */
618 if (flags
& xtTargetFlagsUseFetchStore
)
620 warning (_("cannot read register"));
624 /* On some targets (esp. simulators), we can always read the reg. */
625 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
627 warning (_("cannot read register"));
632 /* We can always read mapped registers. */
633 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
634 return xtensa_register_read_masked (regcache
, reg
, buffer
);
636 /* Assume that we can read the register. */
637 return regcache_raw_read (regcache
, regnum
, buffer
);
640 internal_error (__FILE__
, __LINE__
,
641 _("invalid register number %d"), regnum
);
645 /* Write pseudo registers. */
648 xtensa_pseudo_register_write (struct gdbarch
*gdbarch
,
649 struct regcache
*regcache
,
651 const gdb_byte
*buffer
)
653 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
655 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
656 regnum
, xtensa_register_name (gdbarch
, regnum
));
658 if (regnum
== gdbarch_num_regs (gdbarch
)
659 + gdbarch_num_pseudo_regs (gdbarch
) -1)
660 regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ 1;
662 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
663 if (gdbarch_tdep (gdbarch
)->isa_use_windowed_registers
664 && (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
)
665 && (regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15))
667 gdb_byte
*buf
= (gdb_byte
*) alloca (MAX_REGISTER_SIZE
);
670 regcache_raw_read (regcache
,
671 gdbarch_tdep (gdbarch
)->wb_regnum
, buf
);
672 regnum
= arreg_number (gdbarch
, regnum
,
673 extract_unsigned_integer (buf
, 4, byte_order
));
676 /* We can always write 'core' registers.
677 Note: We might have converted Ax->ARy. */
678 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
679 regcache_raw_write (regcache
, regnum
, buffer
);
681 /* We have to find out how to deal with priveleged registers.
682 Let's treat them as pseudo-registers, but we cannot read/write them. */
684 else if (regnum
< gdbarch_tdep (gdbarch
)->a0_base
)
688 /* Pseudo registers. */
690 && regnum
< gdbarch_num_regs (gdbarch
)
691 + gdbarch_num_pseudo_regs (gdbarch
))
693 xtensa_register_t
*reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
694 xtensa_register_type_t type
= reg
->type
;
695 int flags
= gdbarch_tdep (gdbarch
)->target_flags
;
697 /* On most targets, we cannot write registers
698 of type "Unknown" or "Unmapped". */
699 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
701 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
703 warning (_("cannot write register %s"),
704 xtensa_register_name (gdbarch
, regnum
));
709 /* Some targets cannot read TIE register files. */
710 else if (type
== xtRegisterTypeTieRegfile
)
712 /* Use 'store' to get register? */
713 if (flags
& xtTargetFlagsUseFetchStore
)
715 warning (_("cannot write register"));
719 /* On some targets (esp. simulators), we can always write
721 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
723 warning (_("cannot write register"));
728 /* We can always write mapped registers. */
729 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
731 xtensa_register_write_masked (regcache
, reg
, buffer
);
735 /* Assume that we can write the register. */
736 regcache_raw_write (regcache
, regnum
, buffer
);
739 internal_error (__FILE__
, __LINE__
,
740 _("invalid register number %d"), regnum
);
743 static struct reggroup
*xtensa_ar_reggroup
;
744 static struct reggroup
*xtensa_user_reggroup
;
745 static struct reggroup
*xtensa_vectra_reggroup
;
746 static struct reggroup
*xtensa_cp
[XTENSA_MAX_COPROCESSOR
];
749 xtensa_init_reggroups (void)
752 char cpname
[] = "cp0";
754 xtensa_ar_reggroup
= reggroup_new ("ar", USER_REGGROUP
);
755 xtensa_user_reggroup
= reggroup_new ("user", USER_REGGROUP
);
756 xtensa_vectra_reggroup
= reggroup_new ("vectra", USER_REGGROUP
);
758 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
761 xtensa_cp
[i
] = reggroup_new (cpname
, USER_REGGROUP
);
766 xtensa_add_reggroups (struct gdbarch
*gdbarch
)
770 /* Predefined groups. */
771 reggroup_add (gdbarch
, all_reggroup
);
772 reggroup_add (gdbarch
, save_reggroup
);
773 reggroup_add (gdbarch
, restore_reggroup
);
774 reggroup_add (gdbarch
, system_reggroup
);
775 reggroup_add (gdbarch
, vector_reggroup
);
776 reggroup_add (gdbarch
, general_reggroup
);
777 reggroup_add (gdbarch
, float_reggroup
);
779 /* Xtensa-specific groups. */
780 reggroup_add (gdbarch
, xtensa_ar_reggroup
);
781 reggroup_add (gdbarch
, xtensa_user_reggroup
);
782 reggroup_add (gdbarch
, xtensa_vectra_reggroup
);
784 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
785 reggroup_add (gdbarch
, xtensa_cp
[i
]);
789 xtensa_coprocessor_register_group (struct reggroup
*group
)
793 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
794 if (group
== xtensa_cp
[i
])
800 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
801 | XTENSA_REGISTER_FLAGS_WRITABLE \
802 | XTENSA_REGISTER_FLAGS_VOLATILE)
804 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
805 | XTENSA_REGISTER_FLAGS_WRITABLE)
808 xtensa_register_reggroup_p (struct gdbarch
*gdbarch
,
810 struct reggroup
*group
)
812 xtensa_register_t
* reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
813 xtensa_register_type_t type
= reg
->type
;
814 xtensa_register_group_t rg
= reg
->group
;
817 if (group
== save_reggroup
)
818 /* Every single register should be included into the list of registers
819 to be watched for changes while using -data-list-changed-registers. */
822 /* First, skip registers that are not visible to this target
823 (unknown and unmapped registers when not using ISS). */
825 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
827 if (group
== all_reggroup
)
829 if (group
== xtensa_ar_reggroup
)
830 return rg
& xtRegisterGroupAddrReg
;
831 if (group
== xtensa_user_reggroup
)
832 return rg
& xtRegisterGroupUser
;
833 if (group
== float_reggroup
)
834 return rg
& xtRegisterGroupFloat
;
835 if (group
== general_reggroup
)
836 return rg
& xtRegisterGroupGeneral
;
837 if (group
== system_reggroup
)
838 return rg
& xtRegisterGroupState
;
839 if (group
== vector_reggroup
|| group
== xtensa_vectra_reggroup
)
840 return rg
& xtRegisterGroupVectra
;
841 if (group
== restore_reggroup
)
842 return (regnum
< gdbarch_num_regs (gdbarch
)
843 && (reg
->flags
& SAVE_REST_FLAGS
) == SAVE_REST_VALID
);
844 cp_number
= xtensa_coprocessor_register_group (group
);
846 return rg
& (xtRegisterGroupCP0
<< cp_number
);
852 /* Supply register REGNUM from the buffer specified by GREGS and LEN
853 in the general-purpose register set REGSET to register cache
854 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
857 xtensa_supply_gregset (const struct regset
*regset
,
863 const xtensa_elf_gregset_t
*regs
= gregs
;
864 struct gdbarch
*gdbarch
= get_regcache_arch (rc
);
867 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum
);
869 if (regnum
== gdbarch_pc_regnum (gdbarch
) || regnum
== -1)
870 regcache_raw_supply (rc
, gdbarch_pc_regnum (gdbarch
), (char *) ®s
->pc
);
871 if (regnum
== gdbarch_ps_regnum (gdbarch
) || regnum
== -1)
872 regcache_raw_supply (rc
, gdbarch_ps_regnum (gdbarch
), (char *) ®s
->ps
);
873 if (regnum
== gdbarch_tdep (gdbarch
)->wb_regnum
|| regnum
== -1)
874 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->wb_regnum
,
875 (char *) ®s
->windowbase
);
876 if (regnum
== gdbarch_tdep (gdbarch
)->ws_regnum
|| regnum
== -1)
877 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->ws_regnum
,
878 (char *) ®s
->windowstart
);
879 if (regnum
== gdbarch_tdep (gdbarch
)->lbeg_regnum
|| regnum
== -1)
880 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lbeg_regnum
,
881 (char *) ®s
->lbeg
);
882 if (regnum
== gdbarch_tdep (gdbarch
)->lend_regnum
|| regnum
== -1)
883 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lend_regnum
,
884 (char *) ®s
->lend
);
885 if (regnum
== gdbarch_tdep (gdbarch
)->lcount_regnum
|| regnum
== -1)
886 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lcount_regnum
,
887 (char *) ®s
->lcount
);
888 if (regnum
== gdbarch_tdep (gdbarch
)->sar_regnum
|| regnum
== -1)
889 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->sar_regnum
,
890 (char *) ®s
->sar
);
891 if (regnum
>=gdbarch_tdep (gdbarch
)->ar_base
892 && regnum
< gdbarch_tdep (gdbarch
)->ar_base
893 + gdbarch_tdep (gdbarch
)->num_aregs
)
894 regcache_raw_supply (rc
, regnum
,
895 (char *) ®s
->ar
[regnum
- gdbarch_tdep
896 (gdbarch
)->ar_base
]);
897 else if (regnum
== -1)
899 for (i
= 0; i
< gdbarch_tdep (gdbarch
)->num_aregs
; ++i
)
900 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->ar_base
+ i
,
901 (char *) ®s
->ar
[i
]);
906 /* Xtensa register set. */
912 xtensa_supply_gregset
916 /* Return the appropriate register set for the core
917 section identified by SECT_NAME and SECT_SIZE. */
919 static const struct regset
*
920 xtensa_regset_from_core_section (struct gdbarch
*core_arch
,
921 const char *sect_name
,
924 DEBUGTRACE ("xtensa_regset_from_core_section "
925 "(..., sect_name==\"%s\", sect_size==%x)\n",
926 sect_name
, (unsigned int) sect_size
);
928 if (strcmp (sect_name
, ".reg") == 0
929 && sect_size
>= sizeof(xtensa_elf_gregset_t
))
930 return &xtensa_gregset
;
936 /* Handling frames. */
938 /* Number of registers to save in case of Windowed ABI. */
939 #define XTENSA_NUM_SAVED_AREGS 12
941 /* Frame cache part for Windowed ABI. */
942 typedef struct xtensa_windowed_frame_cache
944 int wb
; /* WINDOWBASE of the previous frame. */
945 int callsize
; /* Call size of this frame. */
946 int ws
; /* WINDOWSTART of the previous frame. It keeps track of
947 life windows only. If there is no bit set for the
948 window, that means it had been already spilled
949 because of window overflow. */
951 /* Addresses of spilled A-registers.
952 AREGS[i] == -1, if corresponding AR is alive. */
953 CORE_ADDR aregs
[XTENSA_NUM_SAVED_AREGS
];
954 } xtensa_windowed_frame_cache_t
;
956 /* Call0 ABI Definitions. */
958 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue
960 #define C0_NREGS 16 /* Number of A-registers to track. */
961 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
962 #define C0_SP 1 /* Register used as SP. */
963 #define C0_FP 15 /* Register used as FP. */
964 #define C0_RA 0 /* Register used as return address. */
965 #define C0_ARGS 2 /* Register used as first arg/retval. */
966 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
968 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
969 A-register where the current content of the reg came from (in terms
970 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
971 mean that the orignal content of the register was saved to the stack.
972 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
973 know where SP will end up until the entire prologue has been analyzed. */
975 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
976 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
977 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
979 extern xtensa_isa xtensa_default_isa
;
981 typedef struct xtensa_c0reg
983 int fr_reg
; /* original register from which register content
984 is derived, or C0_CONST, or C0_INEXP. */
985 int fr_ofs
; /* constant offset from reg, or immediate value. */
986 int to_stk
; /* offset from original SP to register (4-byte aligned),
987 or C0_NOSTK if register has not been saved. */
990 /* Frame cache part for Call0 ABI. */
991 typedef struct xtensa_call0_frame_cache
993 int c0_frmsz
; /* Stack frame size. */
994 int c0_hasfp
; /* Current frame uses frame pointer. */
995 int fp_regnum
; /* A-register used as FP. */
996 int c0_fp
; /* Actual value of frame pointer. */
997 int c0_fpalign
; /* Dinamic adjustment for the stack
998 pointer. It's an AND mask. Zero,
999 if alignment was not adjusted. */
1000 int c0_old_sp
; /* In case of dynamic adjustment, it is
1001 a register holding unaligned sp.
1002 C0_INEXP, when undefined. */
1003 int c0_sp_ofs
; /* If "c0_old_sp" was spilled it's a
1004 stack offset. C0_NOSTK otherwise. */
1006 xtensa_c0reg_t c0_rt
[C0_NREGS
]; /* Register tracking information. */
1007 } xtensa_call0_frame_cache_t
;
1009 typedef struct xtensa_frame_cache
1011 CORE_ADDR base
; /* Stack pointer of this frame. */
1012 CORE_ADDR pc
; /* PC of this frame at the function entry point. */
1013 CORE_ADDR ra
; /* The raw return address of this frame. */
1014 CORE_ADDR ps
; /* The PS register of the previous (older) frame. */
1015 CORE_ADDR prev_sp
; /* Stack Pointer of the previous (older) frame. */
1016 int call0
; /* It's a call0 framework (else windowed). */
1019 xtensa_windowed_frame_cache_t wd
; /* call0 == false. */
1020 xtensa_call0_frame_cache_t c0
; /* call0 == true. */
1022 } xtensa_frame_cache_t
;
1025 static struct xtensa_frame_cache
*
1026 xtensa_alloc_frame_cache (int windowed
)
1028 xtensa_frame_cache_t
*cache
;
1031 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
1033 cache
= FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t
);
1040 cache
->call0
= !windowed
;
1043 cache
->c0
.c0_frmsz
= -1;
1044 cache
->c0
.c0_hasfp
= 0;
1045 cache
->c0
.fp_regnum
= -1;
1046 cache
->c0
.c0_fp
= -1;
1047 cache
->c0
.c0_fpalign
= 0;
1048 cache
->c0
.c0_old_sp
= C0_INEXP
;
1049 cache
->c0
.c0_sp_ofs
= C0_NOSTK
;
1051 for (i
= 0; i
< C0_NREGS
; i
++)
1053 cache
->c0
.c0_rt
[i
].fr_reg
= i
;
1054 cache
->c0
.c0_rt
[i
].fr_ofs
= 0;
1055 cache
->c0
.c0_rt
[i
].to_stk
= C0_NOSTK
;
1062 cache
->wd
.callsize
= -1;
1064 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
1065 cache
->wd
.aregs
[i
] = -1;
1072 xtensa_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
1074 return address
& ~15;
1079 xtensa_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1084 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1085 host_address_to_string (next_frame
));
1087 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1088 pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1090 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc
);
1096 static struct frame_id
1097 xtensa_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1101 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1103 pc
= get_frame_pc (this_frame
);
1104 fp
= get_frame_register_unsigned
1105 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1107 /* Make dummy frame ID unique by adding a constant. */
1108 return frame_id_build (fp
+ SP_ALIGNMENT
, pc
);
1111 /* Returns true, if instruction to execute next is unique to Xtensa Window
1112 Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
1115 xtensa_window_interrupt_insn (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1117 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1118 unsigned int insn
= read_memory_integer (pc
, 4, byte_order
);
1121 if (byte_order
== BFD_ENDIAN_BIG
)
1123 /* Check, if this is L32E or S32E. */
1124 code
= insn
& 0xf000ff00;
1125 if ((code
== 0x00009000) || (code
== 0x00009400))
1127 /* Check, if this is RFWU or RFWO. */
1128 code
= insn
& 0xffffff00;
1129 return ((code
== 0x00430000) || (code
== 0x00530000));
1133 /* Check, if this is L32E or S32E. */
1134 code
= insn
& 0x00ff000f;
1135 if ((code
== 0x090000) || (code
== 0x490000))
1137 /* Check, if this is RFWU or RFWO. */
1138 code
= insn
& 0x00ffffff;
1139 return ((code
== 0x00003400) || (code
== 0x00003500));
1143 /* Returns the best guess about which register is a frame pointer
1144 for the function containing CURRENT_PC. */
1146 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1147 #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1150 xtensa_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
)
1152 #define RETURN_FP goto done
1154 unsigned int fp_regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ 1;
1155 CORE_ADDR start_addr
;
1157 xtensa_insnbuf ins
, slot
;
1158 char ibuf
[XTENSA_ISA_BSZ
];
1159 CORE_ADDR ia
, bt
, ba
;
1161 int ilen
, islots
, is
;
1163 const char *opcname
;
1165 find_pc_partial_function (current_pc
, NULL
, &start_addr
, NULL
);
1166 if (start_addr
== 0)
1169 if (!xtensa_default_isa
)
1170 xtensa_default_isa
= xtensa_isa_init (0, 0);
1171 isa
= xtensa_default_isa
;
1172 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
1173 ins
= xtensa_insnbuf_alloc (isa
);
1174 slot
= xtensa_insnbuf_alloc (isa
);
1177 for (ia
= start_addr
, bt
= ia
; ia
< current_pc
; ia
+= ilen
)
1179 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
1182 bt
= (ba
+ XTENSA_ISA_BSZ
) < current_pc
1183 ? ba
+ XTENSA_ISA_BSZ
: current_pc
;
1184 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0)
1188 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
1189 ifmt
= xtensa_format_decode (isa
, ins
);
1190 if (ifmt
== XTENSA_UNDEFINED
)
1192 ilen
= xtensa_format_length (isa
, ifmt
);
1193 if (ilen
== XTENSA_UNDEFINED
)
1195 islots
= xtensa_format_num_slots (isa
, ifmt
);
1196 if (islots
== XTENSA_UNDEFINED
)
1199 for (is
= 0; is
< islots
; ++is
)
1201 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
1204 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
1205 if (opc
== XTENSA_UNDEFINED
)
1208 opcname
= xtensa_opcode_name (isa
, opc
);
1210 if (strcasecmp (opcname
, "mov.n") == 0
1211 || strcasecmp (opcname
, "or") == 0)
1213 unsigned int register_operand
;
1215 /* Possible candidate for setting frame pointer
1216 from A1. This is what we are looking for. */
1218 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
,
1219 is
, slot
, ®ister_operand
) != 0)
1221 if (xtensa_operand_decode (isa
, opc
, 1, ®ister_operand
) != 0)
1223 if (register_operand
== 1) /* Mov{.n} FP A1. */
1225 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
,
1226 ®ister_operand
) != 0)
1228 if (xtensa_operand_decode (isa
, opc
, 0,
1229 ®ister_operand
) != 0)
1233 = gdbarch_tdep (gdbarch
)->a0_base
+ register_operand
;
1239 /* We have problems decoding the memory. */
1241 || strcasecmp (opcname
, "ill") == 0
1242 || strcasecmp (opcname
, "ill.n") == 0
1243 /* Hit planted breakpoint. */
1244 || strcasecmp (opcname
, "break") == 0
1245 || strcasecmp (opcname
, "break.n") == 0
1246 /* Flow control instructions finish prologue. */
1247 || xtensa_opcode_is_branch (isa
, opc
) > 0
1248 || xtensa_opcode_is_jump (isa
, opc
) > 0
1249 || xtensa_opcode_is_loop (isa
, opc
) > 0
1250 || xtensa_opcode_is_call (isa
, opc
) > 0
1251 || strcasecmp (opcname
, "simcall") == 0
1252 || strcasecmp (opcname
, "syscall") == 0)
1253 /* Can not continue analysis. */
1258 xtensa_insnbuf_free(isa
, slot
);
1259 xtensa_insnbuf_free(isa
, ins
);
1263 /* The key values to identify the frame using "cache" are
1265 cache->base = SP (or best guess about FP) of this frame;
1266 cache->pc = entry-PC (entry point of the frame function);
1267 cache->prev_sp = SP of the previous frame. */
1270 call0_frame_cache (struct frame_info
*this_frame
,
1271 xtensa_frame_cache_t
*cache
, CORE_ADDR pc
);
1274 xtensa_window_interrupt_frame_cache (struct frame_info
*this_frame
,
1275 xtensa_frame_cache_t
*cache
,
1278 static struct xtensa_frame_cache
*
1279 xtensa_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1281 xtensa_frame_cache_t
*cache
;
1282 CORE_ADDR ra
, wb
, ws
, pc
, sp
, ps
;
1283 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1284 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1285 unsigned int fp_regnum
;
1286 int windowed
, ps_regnum
;
1291 pc
= get_frame_register_unsigned (this_frame
, gdbarch_pc_regnum (gdbarch
));
1292 ps_regnum
= gdbarch_ps_regnum (gdbarch
);
1293 ps
= (ps_regnum
>= 0
1294 ? get_frame_register_unsigned (this_frame
, ps_regnum
) : TX_PS
);
1296 windowed
= windowing_enabled (gdbarch
, ps
);
1298 /* Get pristine xtensa-frame. */
1299 cache
= xtensa_alloc_frame_cache (windowed
);
1300 *this_cache
= cache
;
1306 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1307 wb
= get_frame_register_unsigned (this_frame
,
1308 gdbarch_tdep (gdbarch
)->wb_regnum
);
1309 ws
= get_frame_register_unsigned (this_frame
,
1310 gdbarch_tdep (gdbarch
)->ws_regnum
);
1312 op1
= read_memory_integer (pc
, 1, byte_order
);
1313 if (XTENSA_IS_ENTRY (gdbarch
, op1
))
1315 int callinc
= CALLINC (ps
);
1316 ra
= get_frame_register_unsigned
1317 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ callinc
* 4);
1319 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1320 cache
->wd
.callsize
= 0;
1323 cache
->prev_sp
= get_frame_register_unsigned
1324 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1326 /* This only can be the outermost frame since we are
1327 just about to execute ENTRY. SP hasn't been set yet.
1328 We can assume any frame size, because it does not
1329 matter, and, let's fake frame base in cache. */
1330 cache
->base
= cache
->prev_sp
- 16;
1333 cache
->ra
= (cache
->pc
& 0xc0000000) | (ra
& 0x3fffffff);
1334 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1335 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1341 fp_regnum
= xtensa_scan_prologue (gdbarch
, pc
);
1342 ra
= get_frame_register_unsigned (this_frame
,
1343 gdbarch_tdep (gdbarch
)->a0_base
);
1344 cache
->wd
.callsize
= WINSIZE (ra
);
1345 cache
->wd
.wb
= (wb
- cache
->wd
.callsize
/ 4)
1346 & (gdbarch_tdep (gdbarch
)->num_aregs
/ 4 - 1);
1347 cache
->wd
.ws
= ws
& ~(1 << wb
);
1349 cache
->pc
= get_frame_func (this_frame
);
1350 cache
->ra
= (pc
& 0xc0000000) | (ra
& 0x3fffffff);
1351 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1352 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1355 if (cache
->wd
.ws
== 0)
1360 sp
= get_frame_register_unsigned
1361 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1) - 16;
1363 for (i
= 0; i
< 4; i
++, sp
+= 4)
1365 cache
->wd
.aregs
[i
] = sp
;
1368 if (cache
->wd
.callsize
> 4)
1370 /* Set A4...A7/A11. */
1371 /* Get the SP of the frame previous to the previous one.
1372 To achieve this, we have to dereference SP twice. */
1373 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4, byte_order
);
1374 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4, byte_order
);
1375 sp
-= cache
->wd
.callsize
* 4;
1377 for ( i
= 4; i
< cache
->wd
.callsize
; i
++, sp
+= 4)
1379 cache
->wd
.aregs
[i
] = sp
;
1384 if ((cache
->prev_sp
== 0) && ( ra
!= 0 ))
1385 /* If RA is equal to 0 this frame is an outermost frame. Leave
1386 cache->prev_sp unchanged marking the boundary of the frame stack. */
1388 if ((cache
->wd
.ws
& (1 << cache
->wd
.wb
)) == 0)
1390 /* Register window overflow already happened.
1391 We can read caller's SP from the proper spill loction. */
1392 sp
= get_frame_register_unsigned
1393 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1394 cache
->prev_sp
= read_memory_integer (sp
- 12, 4, byte_order
);
1398 /* Read caller's frame SP directly from the previous window. */
1399 int regnum
= arreg_number
1400 (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ 1,
1403 cache
->prev_sp
= xtensa_read_register (regnum
);
1407 else if (xtensa_window_interrupt_insn (gdbarch
, pc
))
1409 /* Execution stopped inside Xtensa Window Interrupt Handler. */
1411 xtensa_window_interrupt_frame_cache (this_frame
, cache
, pc
);
1412 /* Everything was set already, including cache->base. */
1415 else /* Call0 framework. */
1417 call0_frame_cache (this_frame
, cache
, pc
);
1418 fp_regnum
= cache
->c0
.fp_regnum
;
1421 cache
->base
= get_frame_register_unsigned (this_frame
, fp_regnum
);
1426 static int xtensa_session_once_reported
= 1;
1428 /* Report a problem with prologue analysis while doing backtracing.
1429 But, do it only once to avoid annoyng repeated messages. */
1434 if (xtensa_session_once_reported
== 0)
1436 \nUnrecognised function prologue. Stack trace cannot be resolved. \
1437 This message will not be repeated in this session.\n"));
1439 xtensa_session_once_reported
= 1;
1444 xtensa_frame_this_id (struct frame_info
*this_frame
,
1446 struct frame_id
*this_id
)
1448 struct xtensa_frame_cache
*cache
=
1449 xtensa_frame_cache (this_frame
, this_cache
);
1451 if (cache
->prev_sp
== 0)
1454 (*this_id
) = frame_id_build (cache
->prev_sp
, cache
->pc
);
1457 static struct value
*
1458 xtensa_frame_prev_register (struct frame_info
*this_frame
,
1462 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1463 struct xtensa_frame_cache
*cache
;
1464 ULONGEST saved_reg
= 0;
1467 if (*this_cache
== NULL
)
1468 *this_cache
= xtensa_frame_cache (this_frame
, this_cache
);
1469 cache
= *this_cache
;
1471 if (regnum
==gdbarch_pc_regnum (gdbarch
))
1472 saved_reg
= cache
->ra
;
1473 else if (regnum
== gdbarch_tdep (gdbarch
)->a0_base
+ 1)
1474 saved_reg
= cache
->prev_sp
;
1475 else if (!cache
->call0
)
1477 if (regnum
== gdbarch_tdep (gdbarch
)->ws_regnum
)
1478 saved_reg
= cache
->wd
.ws
;
1479 else if (regnum
== gdbarch_tdep (gdbarch
)->wb_regnum
)
1480 saved_reg
= cache
->wd
.wb
;
1481 else if (regnum
== gdbarch_ps_regnum (gdbarch
))
1482 saved_reg
= cache
->ps
;
1490 return frame_unwind_got_constant (this_frame
, regnum
, saved_reg
);
1492 if (!cache
->call0
) /* Windowed ABI. */
1494 /* Convert A-register numbers to AR-register numbers,
1495 if we deal with A-register. */
1496 if (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
1497 && regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15)
1498 regnum
= arreg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1500 /* Check, if we deal with AR-register saved on stack. */
1501 if (regnum
>= gdbarch_tdep (gdbarch
)->ar_base
1502 && regnum
<= (gdbarch_tdep (gdbarch
)->ar_base
1503 + gdbarch_tdep (gdbarch
)->num_aregs
))
1505 int areg
= areg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1508 && areg
< XTENSA_NUM_SAVED_AREGS
1509 && cache
->wd
.aregs
[areg
] != -1)
1510 return frame_unwind_got_memory (this_frame
, regnum
,
1511 cache
->wd
.aregs
[areg
]);
1514 else /* Call0 ABI. */
1516 int reg
= (regnum
>= gdbarch_tdep (gdbarch
)->ar_base
1517 && regnum
<= (gdbarch_tdep (gdbarch
)->ar_base
1519 ? regnum
- gdbarch_tdep (gdbarch
)->ar_base
: regnum
;
1526 /* If register was saved in the prologue, retrieve it. */
1527 stkofs
= cache
->c0
.c0_rt
[reg
].to_stk
;
1528 if (stkofs
!= C0_NOSTK
)
1530 /* Determine SP on entry based on FP. */
1531 spe
= cache
->c0
.c0_fp
1532 - cache
->c0
.c0_rt
[cache
->c0
.fp_regnum
].fr_ofs
;
1534 return frame_unwind_got_memory (this_frame
, regnum
,
1540 /* All other registers have been either saved to
1541 the stack or are still alive in the processor. */
1543 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1547 static const struct frame_unwind
1551 default_frame_unwind_stop_reason
,
1552 xtensa_frame_this_id
,
1553 xtensa_frame_prev_register
,
1555 default_frame_sniffer
1559 xtensa_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1561 struct xtensa_frame_cache
*cache
=
1562 xtensa_frame_cache (this_frame
, this_cache
);
1567 static const struct frame_base
1571 xtensa_frame_base_address
,
1572 xtensa_frame_base_address
,
1573 xtensa_frame_base_address
1578 xtensa_extract_return_value (struct type
*type
,
1579 struct regcache
*regcache
,
1582 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1583 bfd_byte
*valbuf
= dst
;
1584 int len
= TYPE_LENGTH (type
);
1589 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1591 gdb_assert(len
> 0);
1593 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1595 /* First, we have to find the caller window in the register file. */
1596 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1597 callsize
= extract_call_winsize (gdbarch
, pc
);
1599 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1600 if (len
> (callsize
> 8 ? 8 : 16))
1601 internal_error (__FILE__
, __LINE__
,
1602 _("cannot extract return value of %d bytes long"),
1605 /* Get the register offset of the return
1606 register (A2) in the caller window. */
1607 regcache_raw_read_unsigned
1608 (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, &wb
);
1609 areg
= arreg_number (gdbarch
,
1610 gdbarch_tdep (gdbarch
)->a0_base
+ 2 + callsize
, wb
);
1614 /* No windowing hardware - Call0 ABI. */
1615 areg
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_ARGS
;
1618 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg
, len
);
1620 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1623 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1626 regcache_raw_read_part (regcache
, areg
, offset
, len
, valbuf
);
1628 regcache_raw_read (regcache
, areg
, valbuf
);
1634 xtensa_store_return_value (struct type
*type
,
1635 struct regcache
*regcache
,
1638 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1639 const bfd_byte
*valbuf
= dst
;
1643 int len
= TYPE_LENGTH (type
);
1646 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1648 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1650 regcache_raw_read_unsigned
1651 (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, &wb
);
1652 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1653 callsize
= extract_call_winsize (gdbarch
, pc
);
1655 if (len
> (callsize
> 8 ? 8 : 16))
1656 internal_error (__FILE__
, __LINE__
,
1657 _("unimplemented for this length: %d"),
1658 TYPE_LENGTH (type
));
1659 areg
= arreg_number (gdbarch
,
1660 gdbarch_tdep (gdbarch
)->a0_base
+ 2 + callsize
, wb
);
1662 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1663 callsize
, (int) wb
);
1667 areg
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_ARGS
;
1670 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1673 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1676 regcache_raw_write_part (regcache
, areg
, offset
, len
, valbuf
);
1678 regcache_raw_write (regcache
, areg
, valbuf
);
1683 static enum return_value_convention
1684 xtensa_return_value (struct gdbarch
*gdbarch
,
1685 struct type
*func_type
,
1686 struct type
*valtype
,
1687 struct regcache
*regcache
,
1689 const gdb_byte
*writebuf
)
1691 /* Structures up to 16 bytes are returned in registers. */
1693 int struct_return
= ((TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
1694 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
1695 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
1696 && TYPE_LENGTH (valtype
) > 16);
1699 return RETURN_VALUE_STRUCT_CONVENTION
;
1701 DEBUGTRACE ("xtensa_return_value(...)\n");
1703 if (writebuf
!= NULL
)
1705 xtensa_store_return_value (valtype
, regcache
, writebuf
);
1708 if (readbuf
!= NULL
)
1710 gdb_assert (!struct_return
);
1711 xtensa_extract_return_value (valtype
, regcache
, readbuf
);
1713 return RETURN_VALUE_REGISTER_CONVENTION
;
1720 xtensa_push_dummy_call (struct gdbarch
*gdbarch
,
1721 struct value
*function
,
1722 struct regcache
*regcache
,
1725 struct value
**args
,
1728 CORE_ADDR struct_addr
)
1730 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1732 int size
, onstack_size
;
1733 gdb_byte
*buf
= (gdb_byte
*) alloca (16);
1735 struct argument_info
1737 const bfd_byte
*contents
;
1739 int onstack
; /* onstack == 0 => in reg */
1740 int align
; /* alignment */
1743 int offset
; /* stack offset if on stack. */
1744 int regno
; /* regno if in register. */
1748 struct argument_info
*arg_info
=
1749 (struct argument_info
*) alloca (nargs
* sizeof (struct argument_info
));
1753 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1755 if (xtensa_debug_level
> 3)
1758 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs
);
1759 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1760 "struct_addr=0x%x\n",
1761 (int) sp
, (int) struct_return
, (int) struct_addr
);
1763 for (i
= 0; i
< nargs
; i
++)
1765 struct value
*arg
= args
[i
];
1766 struct type
*arg_type
= check_typedef (value_type (arg
));
1767 fprintf_unfiltered (gdb_stdlog
, "%2d: %s %3d ", i
,
1768 host_address_to_string (arg
),
1769 TYPE_LENGTH (arg_type
));
1770 switch (TYPE_CODE (arg_type
))
1773 fprintf_unfiltered (gdb_stdlog
, "int");
1775 case TYPE_CODE_STRUCT
:
1776 fprintf_unfiltered (gdb_stdlog
, "struct");
1779 fprintf_unfiltered (gdb_stdlog
, "%3d", TYPE_CODE (arg_type
));
1782 fprintf_unfiltered (gdb_stdlog
, " %s\n",
1783 host_address_to_string (value_contents (arg
)));
1787 /* First loop: collect information.
1788 Cast into type_long. (This shouldn't happen often for C because
1789 GDB already does this earlier.) It's possible that GDB could
1790 do it all the time but it's harmless to leave this code here. */
1797 size
= REGISTER_SIZE
;
1799 for (i
= 0; i
< nargs
; i
++)
1801 struct argument_info
*info
= &arg_info
[i
];
1802 struct value
*arg
= args
[i
];
1803 struct type
*arg_type
= check_typedef (value_type (arg
));
1805 switch (TYPE_CODE (arg_type
))
1808 case TYPE_CODE_BOOL
:
1809 case TYPE_CODE_CHAR
:
1810 case TYPE_CODE_RANGE
:
1811 case TYPE_CODE_ENUM
:
1813 /* Cast argument to long if necessary as the mask does it too. */
1814 if (TYPE_LENGTH (arg_type
)
1815 < TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
))
1817 arg_type
= builtin_type (gdbarch
)->builtin_long
;
1818 arg
= value_cast (arg_type
, arg
);
1820 /* Aligment is equal to the type length for the basic types. */
1821 info
->align
= TYPE_LENGTH (arg_type
);
1826 /* Align doubles correctly. */
1827 if (TYPE_LENGTH (arg_type
)
1828 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
))
1829 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
);
1831 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
);
1834 case TYPE_CODE_STRUCT
:
1836 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
);
1839 info
->length
= TYPE_LENGTH (arg_type
);
1840 info
->contents
= value_contents (arg
);
1842 /* Align size and onstack_size. */
1843 size
= (size
+ info
->align
- 1) & ~(info
->align
- 1);
1844 onstack_size
= (onstack_size
+ info
->align
- 1) & ~(info
->align
- 1);
1846 if (size
+ info
->length
> REGISTER_SIZE
* ARG_NOF (gdbarch
))
1849 info
->u
.offset
= onstack_size
;
1850 onstack_size
+= info
->length
;
1855 info
->u
.regno
= ARG_1ST (gdbarch
) + size
/ REGISTER_SIZE
;
1857 size
+= info
->length
;
1860 /* Adjust the stack pointer and align it. */
1861 sp
= align_down (sp
- onstack_size
, SP_ALIGNMENT
);
1863 /* Simulate MOVSP, if Windowed ABI. */
1864 if ((gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1867 read_memory (osp
- 16, buf
, 16);
1868 write_memory (sp
- 16, buf
, 16);
1871 /* Second Loop: Load arguments. */
1875 store_unsigned_integer (buf
, REGISTER_SIZE
, byte_order
, struct_addr
);
1876 regcache_cooked_write (regcache
, ARG_1ST (gdbarch
), buf
);
1879 for (i
= 0; i
< nargs
; i
++)
1881 struct argument_info
*info
= &arg_info
[i
];
1885 int n
= info
->length
;
1886 CORE_ADDR offset
= sp
+ info
->u
.offset
;
1888 /* Odd-sized structs are aligned to the lower side of a memory
1889 word in big-endian mode and require a shift. This only
1890 applies for structures smaller than one word. */
1892 if (n
< REGISTER_SIZE
1893 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1894 offset
+= (REGISTER_SIZE
- n
);
1896 write_memory (offset
, info
->contents
, info
->length
);
1901 int n
= info
->length
;
1902 const bfd_byte
*cp
= info
->contents
;
1903 int r
= info
->u
.regno
;
1905 /* Odd-sized structs are aligned to the lower side of registers in
1906 big-endian mode and require a shift. The odd-sized leftover will
1907 be at the end. Note that this is only true for structures smaller
1908 than REGISTER_SIZE; for larger odd-sized structures the excess
1909 will be left-aligned in the register on both endiannesses. */
1911 if (n
< REGISTER_SIZE
&& byte_order
== BFD_ENDIAN_BIG
)
1914 v
= extract_unsigned_integer (cp
, REGISTER_SIZE
, byte_order
);
1915 v
= v
>> ((REGISTER_SIZE
- n
) * TARGET_CHAR_BIT
);
1917 store_unsigned_integer (buf
, REGISTER_SIZE
, byte_order
, v
);
1918 regcache_cooked_write (regcache
, r
, buf
);
1920 cp
+= REGISTER_SIZE
;
1927 regcache_cooked_write (regcache
, r
, cp
);
1929 cp
+= REGISTER_SIZE
;
1936 /* Set the return address of dummy frame to the dummy address.
1937 The return address for the current function (in A0) is
1938 saved in the dummy frame, so we can savely overwrite A0 here. */
1940 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1944 ra
= (bp_addr
& 0x3fffffff) | 0x40000000;
1945 regcache_raw_read_unsigned (regcache
, gdbarch_ps_regnum (gdbarch
), &val
);
1946 ps
= (unsigned long) val
& ~0x00030000;
1947 regcache_cooked_write_unsigned
1948 (regcache
, gdbarch_tdep (gdbarch
)->a0_base
+ 4, ra
);
1949 regcache_cooked_write_unsigned (regcache
,
1950 gdbarch_ps_regnum (gdbarch
),
1953 /* All the registers have been saved. After executing
1954 dummy call, they all will be restored. So it's safe
1955 to modify WINDOWSTART register to make it look like there
1956 is only one register window corresponding to WINDOWEBASE. */
1958 regcache_raw_read (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, buf
);
1959 regcache_cooked_write_unsigned
1960 (regcache
, gdbarch_tdep (gdbarch
)->ws_regnum
,
1961 1 << extract_unsigned_integer (buf
, 4, byte_order
));
1965 /* Simulate CALL0: write RA into A0 register. */
1966 regcache_cooked_write_unsigned
1967 (regcache
, gdbarch_tdep (gdbarch
)->a0_base
, bp_addr
);
1970 /* Set new stack pointer and return it. */
1971 regcache_cooked_write_unsigned (regcache
,
1972 gdbarch_tdep (gdbarch
)->a0_base
+ 1, sp
);
1973 /* Make dummy frame ID unique by adding a constant. */
1974 return sp
+ SP_ALIGNMENT
;
1978 /* Return a breakpoint for the current location of PC. We always use
1979 the density version if we have density instructions (regardless of the
1980 current instruction at PC), and use regular instructions otherwise. */
1982 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1983 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1984 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1985 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1987 static const unsigned char *
1988 xtensa_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
1991 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
1992 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
1993 static unsigned char density_big_breakpoint
[] = DENSITY_BIG_BREAKPOINT
;
1994 static unsigned char density_little_breakpoint
[] = DENSITY_LITTLE_BREAKPOINT
;
1996 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr
);
1998 if (gdbarch_tdep (gdbarch
)->isa_use_density_instructions
)
2000 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2002 *lenptr
= sizeof (density_big_breakpoint
);
2003 return density_big_breakpoint
;
2007 *lenptr
= sizeof (density_little_breakpoint
);
2008 return density_little_breakpoint
;
2013 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2015 *lenptr
= sizeof (big_breakpoint
);
2016 return big_breakpoint
;
2020 *lenptr
= sizeof (little_breakpoint
);
2021 return little_breakpoint
;
2026 /* Call0 ABI support routines. */
2028 /* Return true, if PC points to "ret" or "ret.n". */
2031 call0_ret (CORE_ADDR start_pc
, CORE_ADDR finish_pc
)
2033 #define RETURN_RET goto done
2035 xtensa_insnbuf ins
, slot
;
2036 char ibuf
[XTENSA_ISA_BSZ
];
2037 CORE_ADDR ia
, bt
, ba
;
2039 int ilen
, islots
, is
;
2041 const char *opcname
;
2044 isa
= xtensa_default_isa
;
2045 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2046 ins
= xtensa_insnbuf_alloc (isa
);
2047 slot
= xtensa_insnbuf_alloc (isa
);
2050 for (ia
= start_pc
, bt
= ia
; ia
< finish_pc
; ia
+= ilen
)
2052 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2055 bt
= (ba
+ XTENSA_ISA_BSZ
) < finish_pc
2056 ? ba
+ XTENSA_ISA_BSZ
: finish_pc
;
2057 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0 )
2061 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2062 ifmt
= xtensa_format_decode (isa
, ins
);
2063 if (ifmt
== XTENSA_UNDEFINED
)
2065 ilen
= xtensa_format_length (isa
, ifmt
);
2066 if (ilen
== XTENSA_UNDEFINED
)
2068 islots
= xtensa_format_num_slots (isa
, ifmt
);
2069 if (islots
== XTENSA_UNDEFINED
)
2072 for (is
= 0; is
< islots
; ++is
)
2074 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
2077 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2078 if (opc
== XTENSA_UNDEFINED
)
2081 opcname
= xtensa_opcode_name (isa
, opc
);
2083 if ((strcasecmp (opcname
, "ret.n") == 0)
2084 || (strcasecmp (opcname
, "ret") == 0))
2092 xtensa_insnbuf_free(isa
, slot
);
2093 xtensa_insnbuf_free(isa
, ins
);
2097 /* Call0 opcode class. Opcodes are preclassified according to what they
2098 mean for Call0 prologue analysis, and their number of significant operands.
2099 The purpose of this is to simplify prologue analysis by separating
2100 instruction decoding (libisa) from the semantics of prologue analysis. */
2104 c0opc_illegal
, /* Unknown to libisa (invalid) or 'ill' opcode. */
2105 c0opc_uninteresting
, /* Not interesting for Call0 prologue analysis. */
2106 c0opc_flow
, /* Flow control insn. */
2107 c0opc_entry
, /* ENTRY indicates non-Call0 prologue. */
2108 c0opc_break
, /* Debugger software breakpoints. */
2109 c0opc_add
, /* Adding two registers. */
2110 c0opc_addi
, /* Adding a register and an immediate. */
2111 c0opc_and
, /* Bitwise "and"-ing two registers. */
2112 c0opc_sub
, /* Subtracting a register from a register. */
2113 c0opc_mov
, /* Moving a register to a register. */
2114 c0opc_movi
, /* Moving an immediate to a register. */
2115 c0opc_l32r
, /* Loading a literal. */
2116 c0opc_s32i
, /* Storing word at fixed offset from a base register. */
2117 c0opc_rwxsr
, /* RSR, WRS, or XSR instructions. */
2118 c0opc_l32e
, /* L32E instruction. */
2119 c0opc_s32e
, /* S32E instruction. */
2120 c0opc_rfwo
, /* RFWO instruction. */
2121 c0opc_rfwu
, /* RFWU instruction. */
2122 c0opc_NrOf
/* Number of opcode classifications. */
2125 /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
2128 rwx_special_register (const char *opcname
)
2130 char ch
= *opcname
++;
2132 if ((ch
!= 'r') && (ch
!= 'w') && (ch
!= 'x'))
2134 if (*opcname
++ != 's')
2136 if (*opcname
++ != 'r')
2138 if (*opcname
++ != '.')
2144 /* Classify an opcode based on what it means for Call0 prologue analysis. */
2146 static xtensa_insn_kind
2147 call0_classify_opcode (xtensa_isa isa
, xtensa_opcode opc
)
2149 const char *opcname
;
2150 xtensa_insn_kind opclass
= c0opc_uninteresting
;
2152 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc
);
2154 /* Get opcode name and handle special classifications. */
2156 opcname
= xtensa_opcode_name (isa
, opc
);
2159 || strcasecmp (opcname
, "ill") == 0
2160 || strcasecmp (opcname
, "ill.n") == 0)
2161 opclass
= c0opc_illegal
;
2162 else if (strcasecmp (opcname
, "break") == 0
2163 || strcasecmp (opcname
, "break.n") == 0)
2164 opclass
= c0opc_break
;
2165 else if (strcasecmp (opcname
, "entry") == 0)
2166 opclass
= c0opc_entry
;
2167 else if (strcasecmp (opcname
, "rfwo") == 0)
2168 opclass
= c0opc_rfwo
;
2169 else if (strcasecmp (opcname
, "rfwu") == 0)
2170 opclass
= c0opc_rfwu
;
2171 else if (xtensa_opcode_is_branch (isa
, opc
) > 0
2172 || xtensa_opcode_is_jump (isa
, opc
) > 0
2173 || xtensa_opcode_is_loop (isa
, opc
) > 0
2174 || xtensa_opcode_is_call (isa
, opc
) > 0
2175 || strcasecmp (opcname
, "simcall") == 0
2176 || strcasecmp (opcname
, "syscall") == 0)
2177 opclass
= c0opc_flow
;
2179 /* Also, classify specific opcodes that need to be tracked. */
2180 else if (strcasecmp (opcname
, "add") == 0
2181 || strcasecmp (opcname
, "add.n") == 0)
2182 opclass
= c0opc_add
;
2183 else if (strcasecmp (opcname
, "and") == 0)
2184 opclass
= c0opc_and
;
2185 else if (strcasecmp (opcname
, "addi") == 0
2186 || strcasecmp (opcname
, "addi.n") == 0
2187 || strcasecmp (opcname
, "addmi") == 0)
2188 opclass
= c0opc_addi
;
2189 else if (strcasecmp (opcname
, "sub") == 0)
2190 opclass
= c0opc_sub
;
2191 else if (strcasecmp (opcname
, "mov.n") == 0
2192 || strcasecmp (opcname
, "or") == 0) /* Could be 'mov' asm macro. */
2193 opclass
= c0opc_mov
;
2194 else if (strcasecmp (opcname
, "movi") == 0
2195 || strcasecmp (opcname
, "movi.n") == 0)
2196 opclass
= c0opc_movi
;
2197 else if (strcasecmp (opcname
, "l32r") == 0)
2198 opclass
= c0opc_l32r
;
2199 else if (strcasecmp (opcname
, "s32i") == 0
2200 || strcasecmp (opcname
, "s32i.n") == 0)
2201 opclass
= c0opc_s32i
;
2202 else if (strcasecmp (opcname
, "l32e") == 0)
2203 opclass
= c0opc_l32e
;
2204 else if (strcasecmp (opcname
, "s32e") == 0)
2205 opclass
= c0opc_s32e
;
2206 else if (rwx_special_register (opcname
))
2207 opclass
= c0opc_rwxsr
;
2212 /* Tracks register movement/mutation for a given operation, which may
2213 be within a bundle. Updates the destination register tracking info
2214 accordingly. The pc is needed only for pc-relative load instructions
2215 (eg. l32r). The SP register number is needed to identify stores to
2216 the stack frame. Returns 0, if analysis was succesfull, non-zero
2220 call0_track_op (struct gdbarch
*gdbarch
, xtensa_c0reg_t dst
[], xtensa_c0reg_t src
[],
2221 xtensa_insn_kind opclass
, int nods
, unsigned odv
[],
2222 CORE_ADDR pc
, int spreg
, xtensa_frame_cache_t
*cache
)
2224 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2225 unsigned litbase
, litaddr
, litval
;
2230 /* 3 operands: dst, src, imm. */
2231 gdb_assert (nods
== 3);
2232 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2233 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ odv
[2];
2236 /* 3 operands: dst, src1, src2. */
2237 gdb_assert (nods
== 3);
2238 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2240 dst
[odv
[0]].fr_reg
= src
[odv
[2]].fr_reg
;
2241 dst
[odv
[0]].fr_ofs
= src
[odv
[2]].fr_ofs
+ src
[odv
[1]].fr_ofs
;
2243 else if (src
[odv
[2]].fr_reg
== C0_CONST
)
2245 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2246 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ src
[odv
[2]].fr_ofs
;
2248 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2251 /* 3 operands: dst, src1, src2. */
2252 gdb_assert (nods
== 3);
2253 if (cache
->c0
.c0_fpalign
== 0)
2255 /* Handle dynamic stack alignment. */
2256 if ((src
[odv
[0]].fr_reg
== spreg
) && (src
[odv
[1]].fr_reg
== spreg
))
2258 if (src
[odv
[2]].fr_reg
== C0_CONST
)
2259 cache
->c0
.c0_fpalign
= src
[odv
[2]].fr_ofs
;
2262 else if ((src
[odv
[0]].fr_reg
== spreg
)
2263 && (src
[odv
[2]].fr_reg
== spreg
))
2265 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2266 cache
->c0
.c0_fpalign
= src
[odv
[1]].fr_ofs
;
2269 /* else fall through. */
2271 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2273 dst
[odv
[0]].fr_reg
= src
[odv
[2]].fr_reg
;
2274 dst
[odv
[0]].fr_ofs
= src
[odv
[2]].fr_ofs
& src
[odv
[1]].fr_ofs
;
2276 else if (src
[odv
[2]].fr_reg
== C0_CONST
)
2278 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2279 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
& src
[odv
[2]].fr_ofs
;
2281 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2284 /* 3 operands: dst, src1, src2. */
2285 gdb_assert (nods
== 3);
2286 if (src
[odv
[2]].fr_reg
== C0_CONST
)
2288 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2289 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
- src
[odv
[2]].fr_ofs
;
2291 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2294 /* 2 operands: dst, src [, src]. */
2295 gdb_assert (nods
== 2);
2296 /* First, check if it's a special case of saving unaligned SP
2297 to a spare register in case of dynamic stack adjustment.
2298 But, only do it one time. The second time could be initializing
2299 frame pointer. We don't want to overwrite the first one. */
2300 if ((odv
[1] == spreg
) && (cache
->c0
.c0_old_sp
== C0_INEXP
))
2301 cache
->c0
.c0_old_sp
= odv
[0];
2303 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2304 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
;
2307 /* 2 operands: dst, imm. */
2308 gdb_assert (nods
== 2);
2309 dst
[odv
[0]].fr_reg
= C0_CONST
;
2310 dst
[odv
[0]].fr_ofs
= odv
[1];
2313 /* 2 operands: dst, literal offset. */
2314 gdb_assert (nods
== 2);
2315 /* litbase = xtensa_get_litbase (pc); can be also used. */
2316 litbase
= (gdbarch_tdep (gdbarch
)->litbase_regnum
== -1)
2317 ? 0 : xtensa_read_register
2318 (gdbarch_tdep (gdbarch
)->litbase_regnum
);
2319 litaddr
= litbase
& 1
2320 ? (litbase
& ~1) + (signed)odv
[1]
2321 : (pc
+ 3 + (signed)odv
[1]) & ~3;
2322 litval
= read_memory_integer (litaddr
, 4, byte_order
);
2323 dst
[odv
[0]].fr_reg
= C0_CONST
;
2324 dst
[odv
[0]].fr_ofs
= litval
;
2327 /* 3 operands: value, base, offset. */
2328 gdb_assert (nods
== 3 && spreg
>= 0 && spreg
< C0_NREGS
);
2329 /* First, check if it's a spill for saved unaligned SP,
2330 when dynamic stack adjustment was applied to this frame. */
2331 if ((cache
->c0
.c0_fpalign
!= 0) /* Dynamic stack adjustment. */
2332 && (odv
[1] == spreg
) /* SP usage indicates spill. */
2333 && (odv
[0] == cache
->c0
.c0_old_sp
)) /* Old SP register spilled. */
2334 cache
->c0
.c0_sp_ofs
= odv
[2];
2336 if (src
[odv
[1]].fr_reg
== spreg
/* Store to stack frame. */
2337 && (src
[odv
[1]].fr_ofs
& 3) == 0 /* Alignment preserved. */
2338 && src
[odv
[0]].fr_reg
>= 0 /* Value is from a register. */
2339 && src
[odv
[0]].fr_ofs
== 0 /* Value hasn't been modified. */
2340 && src
[src
[odv
[0]].fr_reg
].to_stk
== C0_NOSTK
) /* First time. */
2342 /* ISA encoding guarantees alignment. But, check it anyway. */
2343 gdb_assert ((odv
[2] & 3) == 0);
2344 dst
[src
[odv
[0]].fr_reg
].to_stk
= src
[odv
[1]].fr_ofs
+ odv
[2];
2347 /* If we end up inside Window Overflow / Underflow interrupt handler
2348 report an error because these handlers should have been handled
2349 already in a different way. */
2361 /* Analyze prologue of the function at start address to determine if it uses
2362 the Call0 ABI, and if so track register moves and linear modifications
2363 in the prologue up to the PC or just beyond the prologue, whichever is
2364 first. An 'entry' instruction indicates non-Call0 ABI and the end of the
2365 prologue. The prologue may overlap non-prologue instructions but is
2366 guaranteed to end by the first flow-control instruction (jump, branch,
2367 call or return). Since an optimized function may move information around
2368 and change the stack frame arbitrarily during the prologue, the information
2369 is guaranteed valid only at the point in the function indicated by the PC.
2370 May be used to skip the prologue or identify the ABI, w/o tracking.
2372 Returns: Address of first instruction after prologue, or PC (whichever
2373 is first), or 0, if decoding failed (in libisa).
2375 start Start address of function/prologue.
2376 pc Program counter to stop at. Use 0 to continue to end of prologue.
2377 If 0, avoids infinite run-on in corrupt code memory by bounding
2378 the scan to the end of the function if that can be determined.
2379 nregs Number of general registers to track.
2381 cache Xtensa frame cache.
2383 Note that these may produce useful results even if decoding fails
2384 because they begin with default assumptions that analysis may change. */
2387 call0_analyze_prologue (struct gdbarch
*gdbarch
,
2388 CORE_ADDR start
, CORE_ADDR pc
,
2389 int nregs
, xtensa_frame_cache_t
*cache
)
2391 CORE_ADDR ia
; /* Current insn address in prologue. */
2392 CORE_ADDR ba
= 0; /* Current address at base of insn buffer. */
2393 CORE_ADDR bt
; /* Current address at top+1 of insn buffer. */
2394 char ibuf
[XTENSA_ISA_BSZ
];/* Instruction buffer for decoding prologue. */
2395 xtensa_isa isa
; /* libisa ISA handle. */
2396 xtensa_insnbuf ins
, slot
; /* libisa handle to decoded insn, slot. */
2397 xtensa_format ifmt
; /* libisa instruction format. */
2398 int ilen
, islots
, is
; /* Instruction length, nbr slots, current slot. */
2399 xtensa_opcode opc
; /* Opcode in current slot. */
2400 xtensa_insn_kind opclass
; /* Opcode class for Call0 prologue analysis. */
2401 int nods
; /* Opcode number of operands. */
2402 unsigned odv
[C0_MAXOPDS
]; /* Operand values in order provided by libisa. */
2403 xtensa_c0reg_t
*rtmp
; /* Register tracking info snapshot. */
2404 int j
; /* General loop counter. */
2405 int fail
= 0; /* Set non-zero and exit, if decoding fails. */
2406 CORE_ADDR body_pc
; /* The PC for the first non-prologue insn. */
2407 CORE_ADDR end_pc
; /* The PC for the lust function insn. */
2409 struct symtab_and_line prologue_sal
;
2411 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2412 (int)start
, (int)pc
);
2414 /* Try to limit the scan to the end of the function if a non-zero pc
2415 arg was not supplied to avoid probing beyond the end of valid memory.
2416 If memory is full of garbage that classifies as c0opc_uninteresting.
2417 If this fails (eg. if no symbols) pc ends up 0 as it was.
2418 Intialize the Call0 frame and register tracking info.
2419 Assume it's Call0 until an 'entry' instruction is encountered.
2420 Assume we may be in the prologue until we hit a flow control instr. */
2426 /* Find out, if we have an information about the prologue from DWARF. */
2427 prologue_sal
= find_pc_line (start
, 0);
2428 if (prologue_sal
.line
!= 0) /* Found debug info. */
2429 body_pc
= prologue_sal
.end
;
2431 /* If we are going to analyze the prologue in general without knowing about
2432 the current PC, make the best assumtion for the end of the prologue. */
2435 find_pc_partial_function (start
, 0, NULL
, &end_pc
);
2436 body_pc
= min (end_pc
, body_pc
);
2439 body_pc
= min (pc
, body_pc
);
2442 rtmp
= (xtensa_c0reg_t
*) alloca(nregs
* sizeof(xtensa_c0reg_t
));
2444 if (!xtensa_default_isa
)
2445 xtensa_default_isa
= xtensa_isa_init (0, 0);
2446 isa
= xtensa_default_isa
;
2447 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2448 ins
= xtensa_insnbuf_alloc (isa
);
2449 slot
= xtensa_insnbuf_alloc (isa
);
2451 for (ia
= start
, bt
= ia
; ia
< body_pc
; ia
+= ilen
)
2453 /* (Re)fill instruction buffer from memory if necessary, but do not
2454 read memory beyond PC to be sure we stay within text section
2455 (this protection only works if a non-zero pc is supplied). */
2457 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2460 bt
= (ba
+ XTENSA_ISA_BSZ
) < body_pc
? ba
+ XTENSA_ISA_BSZ
: body_pc
;
2461 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0 )
2462 error (_("Unable to read target memory ..."));
2465 /* Decode format information. */
2467 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2468 ifmt
= xtensa_format_decode (isa
, ins
);
2469 if (ifmt
== XTENSA_UNDEFINED
)
2474 ilen
= xtensa_format_length (isa
, ifmt
);
2475 if (ilen
== XTENSA_UNDEFINED
)
2480 islots
= xtensa_format_num_slots (isa
, ifmt
);
2481 if (islots
== XTENSA_UNDEFINED
)
2487 /* Analyze a bundle or a single instruction, using a snapshot of
2488 the register tracking info as input for the entire bundle so that
2489 register changes do not take effect within this bundle. */
2491 for (j
= 0; j
< nregs
; ++j
)
2492 rtmp
[j
] = cache
->c0
.c0_rt
[j
];
2494 for (is
= 0; is
< islots
; ++is
)
2496 /* Decode a slot and classify the opcode. */
2498 fail
= xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
);
2502 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2503 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2505 if (opc
== XTENSA_UNDEFINED
)
2506 opclass
= c0opc_illegal
;
2508 opclass
= call0_classify_opcode (isa
, opc
);
2510 /* Decide whether to track this opcode, ignore it, or bail out. */
2519 case c0opc_uninteresting
:
2522 case c0opc_flow
: /* Flow control instructions stop analysis. */
2523 case c0opc_rwxsr
: /* RSR, WSR, XSR instructions stop analysis. */
2528 ia
+= ilen
; /* Skip over 'entry' insn. */
2535 /* Only expected opcodes should get this far. */
2537 /* Extract and decode the operands. */
2538 nods
= xtensa_opcode_num_operands (isa
, opc
);
2539 if (nods
== XTENSA_UNDEFINED
)
2545 for (j
= 0; j
< nods
&& j
< C0_MAXOPDS
; ++j
)
2547 fail
= xtensa_operand_get_field (isa
, opc
, j
, ifmt
,
2552 fail
= xtensa_operand_decode (isa
, opc
, j
, &odv
[j
]);
2557 /* Check operands to verify use of 'mov' assembler macro. */
2558 if (opclass
== c0opc_mov
&& nods
== 3)
2560 if (odv
[2] == odv
[1])
2563 if ((odv
[0] == 1) && (odv
[1] != 1))
2564 /* OR A1, An, An , where n != 1.
2565 This means we are inside epilogue already. */
2570 opclass
= c0opc_uninteresting
;
2575 /* Track register movement and modification for this operation. */
2576 fail
= call0_track_op (gdbarch
, cache
->c0
.c0_rt
, rtmp
,
2577 opclass
, nods
, odv
, ia
, 1, cache
);
2583 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2584 (unsigned)ia
, fail
? "failed" : "succeeded");
2585 xtensa_insnbuf_free(isa
, slot
);
2586 xtensa_insnbuf_free(isa
, ins
);
2587 return fail
? XTENSA_ISA_BADPC
: ia
;
2590 /* Initialize frame cache for the current frame in CALL0 ABI. */
2593 call0_frame_cache (struct frame_info
*this_frame
,
2594 xtensa_frame_cache_t
*cache
, CORE_ADDR pc
)
2596 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2597 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2598 CORE_ADDR start_pc
; /* The beginning of the function. */
2599 CORE_ADDR body_pc
=UINT_MAX
; /* PC, where prologue analysis stopped. */
2600 CORE_ADDR sp
, fp
, ra
;
2601 int fp_regnum
= C0_SP
, c0_hasfp
= 0, c0_frmsz
= 0, prev_sp
= 0, to_stk
;
2603 sp
= get_frame_register_unsigned
2604 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
2605 fp
= sp
; /* Assume FP == SP until proven otherwise. */
2607 /* Find the beginning of the prologue of the function containing the PC
2608 and analyze it up to the PC or the end of the prologue. */
2610 if (find_pc_partial_function (pc
, NULL
, &start_pc
, NULL
))
2612 body_pc
= call0_analyze_prologue (gdbarch
, start_pc
, pc
, C0_NREGS
, cache
);
2614 if (body_pc
== XTENSA_ISA_BADPC
)
2618 goto finish_frame_analysis
;
2622 /* Get the frame information and FP (if used) at the current PC.
2623 If PC is in the prologue, the prologue analysis is more reliable
2624 than DWARF info. We don't not know for sure, if PC is in the prologue,
2625 but we do know no calls have yet taken place, so we can almost
2626 certainly rely on the prologue analysis. */
2630 /* Prologue analysis was successful up to the PC.
2631 It includes the cases when PC == START_PC. */
2632 c0_hasfp
= cache
->c0
.c0_rt
[C0_FP
].fr_reg
== C0_SP
;
2633 /* c0_hasfp == true means there is a frame pointer because
2634 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2635 was derived from SP. Otherwise, it would be C0_FP. */
2636 fp_regnum
= c0_hasfp
? C0_FP
: C0_SP
;
2637 c0_frmsz
= - cache
->c0
.c0_rt
[fp_regnum
].fr_ofs
;
2638 fp_regnum
+= gdbarch_tdep (gdbarch
)->a0_base
;
2640 else /* No data from the prologue analysis. */
2643 fp_regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_SP
;
2648 if (cache
->c0
.c0_fpalign
)
2650 /* This frame has a special prologue with a dynamic stack adjustment
2651 to force an alignment, which is bigger than standard 16 bytes. */
2653 CORE_ADDR unaligned_sp
;
2655 if (cache
->c0
.c0_old_sp
== C0_INEXP
)
2656 /* This can't be. Prologue code should be consistent.
2657 Unaligned stack pointer should be saved in a spare register. */
2661 goto finish_frame_analysis
;
2664 if (cache
->c0
.c0_sp_ofs
== C0_NOSTK
)
2665 /* Saved unaligned value of SP is kept in a register. */
2666 unaligned_sp
= get_frame_register_unsigned
2667 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ cache
->c0
.c0_old_sp
);
2669 /* Get the value from stack. */
2670 unaligned_sp
= (CORE_ADDR
)
2671 read_memory_integer (fp
+ cache
->c0
.c0_sp_ofs
, 4, byte_order
);
2673 prev_sp
= unaligned_sp
+ c0_frmsz
;
2676 prev_sp
= fp
+ c0_frmsz
;
2678 /* Frame size from debug info or prologue tracking does not account for
2679 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2682 fp
= get_frame_register_unsigned (this_frame
, fp_regnum
);
2684 /* Update the stack frame size. */
2685 c0_frmsz
+= fp
- sp
;
2688 /* Get the return address (RA) from the stack if saved,
2689 or try to get it from a register. */
2691 to_stk
= cache
->c0
.c0_rt
[C0_RA
].to_stk
;
2692 if (to_stk
!= C0_NOSTK
)
2694 read_memory_integer (sp
+ c0_frmsz
+ cache
->c0
.c0_rt
[C0_RA
].to_stk
,
2697 else if (cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_CONST
2698 && cache
->c0
.c0_rt
[C0_RA
].fr_ofs
== 0)
2700 /* Special case for terminating backtrace at a function that wants to
2701 be seen as the outermost one. Such a function will clear it's RA (A0)
2702 register to 0 in the prologue instead of saving its original value. */
2707 /* RA was copied to another register or (before any function call) may
2708 still be in the original RA register. This is not always reliable:
2709 even in a leaf function, register tracking stops after prologue, and
2710 even in prologue, non-prologue instructions (not tracked) may overwrite
2711 RA or any register it was copied to. If likely in prologue or before
2712 any call, use retracking info and hope for the best (compiler should
2713 have saved RA in stack if not in a leaf function). If not in prologue,
2719 && (i
== C0_RA
|| cache
->c0
.c0_rt
[i
].fr_reg
!= C0_RA
);
2721 if (i
>= C0_NREGS
&& cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_RA
)
2725 ra
= get_frame_register_unsigned
2727 gdbarch_tdep (gdbarch
)->a0_base
+ cache
->c0
.c0_rt
[i
].fr_reg
);
2732 finish_frame_analysis
:
2733 cache
->pc
= start_pc
;
2735 /* RA == 0 marks the outermost frame. Do not go past it. */
2736 cache
->prev_sp
= (ra
!= 0) ? prev_sp
: 0;
2737 cache
->c0
.fp_regnum
= fp_regnum
;
2738 cache
->c0
.c0_frmsz
= c0_frmsz
;
2739 cache
->c0
.c0_hasfp
= c0_hasfp
;
2740 cache
->c0
.c0_fp
= fp
;
2743 static CORE_ADDR a0_saved
;
2744 static CORE_ADDR a7_saved
;
2745 static CORE_ADDR a11_saved
;
2746 static int a0_was_saved
;
2747 static int a7_was_saved
;
2748 static int a11_was_saved
;
2750 /* Simulate L32E instruction: AT <-- ref (AS + offset). */
2752 execute_l32e (struct gdbarch
*gdbarch
, int at
, int as
, int offset
, CORE_ADDR wb
)
2754 int atreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ at
, wb
);
2755 int asreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ as
, wb
);
2756 CORE_ADDR addr
= xtensa_read_register (asreg
) + offset
;
2757 unsigned int spilled_value
2758 = read_memory_unsigned_integer (addr
, 4, gdbarch_byte_order (gdbarch
));
2760 if ((at
== 0) && !a0_was_saved
)
2762 a0_saved
= xtensa_read_register (atreg
);
2765 else if ((at
== 7) && !a7_was_saved
)
2767 a7_saved
= xtensa_read_register (atreg
);
2770 else if ((at
== 11) && !a11_was_saved
)
2772 a11_saved
= xtensa_read_register (atreg
);
2776 xtensa_write_register (atreg
, spilled_value
);
2779 /* Simulate S32E instruction: AT --> ref (AS + offset). */
2781 execute_s32e (struct gdbarch
*gdbarch
, int at
, int as
, int offset
, CORE_ADDR wb
)
2783 int atreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ at
, wb
);
2784 int asreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ as
, wb
);
2785 CORE_ADDR addr
= xtensa_read_register (asreg
) + offset
;
2786 ULONGEST spilled_value
= xtensa_read_register (atreg
);
2788 write_memory_unsigned_integer (addr
, 4,
2789 gdbarch_byte_order (gdbarch
),
2793 #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2799 xtNoExceptionHandler
2800 } xtensa_exception_handler_t
;
2802 /* Execute instruction stream from current PC until hitting RFWU or RFWO.
2803 Return type of Xtensa Window Interrupt Handler on success. */
2804 static xtensa_exception_handler_t
2805 execute_code (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
, CORE_ADDR wb
)
2808 xtensa_insnbuf ins
, slot
;
2809 char ibuf
[XTENSA_ISA_BSZ
];
2810 CORE_ADDR ia
, bt
, ba
;
2812 int ilen
, islots
, is
;
2816 void (*func
) (struct gdbarch
*, int, int, int, CORE_ADDR
);
2821 /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
2822 int WindowUnderflow12
= (current_pc
& 0x1ff) >= 0x140;
2824 isa
= xtensa_default_isa
;
2825 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2826 ins
= xtensa_insnbuf_alloc (isa
);
2827 slot
= xtensa_insnbuf_alloc (isa
);
2836 while (insn_num
++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN
)
2838 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2841 bt
= (ba
+ XTENSA_ISA_BSZ
);
2842 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0)
2843 return xtNoExceptionHandler
;
2845 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2846 ifmt
= xtensa_format_decode (isa
, ins
);
2847 if (ifmt
== XTENSA_UNDEFINED
)
2848 return xtNoExceptionHandler
;
2849 ilen
= xtensa_format_length (isa
, ifmt
);
2850 if (ilen
== XTENSA_UNDEFINED
)
2851 return xtNoExceptionHandler
;
2852 islots
= xtensa_format_num_slots (isa
, ifmt
);
2853 if (islots
== XTENSA_UNDEFINED
)
2854 return xtNoExceptionHandler
;
2855 for (is
= 0; is
< islots
; ++is
)
2857 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
2858 return xtNoExceptionHandler
;
2859 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2860 if (opc
== XTENSA_UNDEFINED
)
2861 return xtNoExceptionHandler
;
2862 switch (call0_classify_opcode (isa
, opc
))
2868 /* We expect none of them here. */
2869 return xtNoExceptionHandler
;
2871 func
= execute_l32e
;
2874 func
= execute_s32e
;
2876 case c0opc_rfwo
: /* RFWO. */
2877 /* Here, we return from WindowOverflow handler and,
2878 if we stopped at the very beginning, which means
2879 A0 was saved, we have to restore it now. */
2882 int arreg
= arreg_number (gdbarch
,
2883 gdbarch_tdep (gdbarch
)->a0_base
,
2885 xtensa_write_register (arreg
, a0_saved
);
2887 return xtWindowOverflow
;
2888 case c0opc_rfwu
: /* RFWU. */
2889 /* Here, we return from WindowUnderflow handler.
2890 Let's see if either A7 or A11 has to be restored. */
2891 if (WindowUnderflow12
)
2895 int arreg
= arreg_number (gdbarch
,
2896 gdbarch_tdep (gdbarch
)->a0_base
+ 11,
2898 xtensa_write_register (arreg
, a11_saved
);
2901 else if (a7_was_saved
)
2903 int arreg
= arreg_number (gdbarch
,
2904 gdbarch_tdep (gdbarch
)->a0_base
+ 7,
2906 xtensa_write_register (arreg
, a7_saved
);
2908 return xtWindowUnderflow
;
2909 default: /* Simply skip this insns. */
2913 /* Decode arguments for L32E / S32E and simulate their execution. */
2914 if ( xtensa_opcode_num_operands (isa
, opc
) != 3 )
2915 return xtNoExceptionHandler
;
2916 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
, &at
))
2917 return xtNoExceptionHandler
;
2918 if (xtensa_operand_decode (isa
, opc
, 0, &at
))
2919 return xtNoExceptionHandler
;
2920 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
, is
, slot
, &as
))
2921 return xtNoExceptionHandler
;
2922 if (xtensa_operand_decode (isa
, opc
, 1, &as
))
2923 return xtNoExceptionHandler
;
2924 if (xtensa_operand_get_field (isa
, opc
, 2, ifmt
, is
, slot
, &offset
))
2925 return xtNoExceptionHandler
;
2926 if (xtensa_operand_decode (isa
, opc
, 2, &offset
))
2927 return xtNoExceptionHandler
;
2929 (*func
) (gdbarch
, at
, as
, offset
, wb
);
2934 return xtNoExceptionHandler
;
2937 /* Handle Window Overflow / Underflow exception frames. */
2940 xtensa_window_interrupt_frame_cache (struct frame_info
*this_frame
,
2941 xtensa_frame_cache_t
*cache
,
2944 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2945 CORE_ADDR ps
, wb
, ws
, ra
;
2946 int epc1_regnum
, i
, regnum
;
2947 xtensa_exception_handler_t eh_type
;
2949 /* Read PS, WB, and WS from the hardware. Note that PS register
2950 must be present, if Windowed ABI is supported. */
2951 ps
= xtensa_read_register (gdbarch_ps_regnum (gdbarch
));
2952 wb
= xtensa_read_register (gdbarch_tdep (gdbarch
)->wb_regnum
);
2953 ws
= xtensa_read_register (gdbarch_tdep (gdbarch
)->ws_regnum
);
2955 /* Execute all the remaining instructions from Window Interrupt Handler
2956 by simulating them on the remote protocol level. On return, set the
2957 type of Xtensa Window Interrupt Handler, or report an error. */
2958 eh_type
= execute_code (gdbarch
, pc
, wb
);
2959 if (eh_type
== xtNoExceptionHandler
)
2961 Unable to decode Xtensa Window Interrupt Handler's code."));
2963 cache
->ps
= ps
^ PS_EXC
; /* Clear the exception bit in PS. */
2964 cache
->call0
= 0; /* It's Windowed ABI. */
2966 /* All registers for the cached frame will be alive. */
2967 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
2968 cache
->wd
.aregs
[i
] = -1;
2970 if (eh_type
== xtWindowOverflow
)
2971 cache
->wd
.ws
= ws
^ (1 << wb
);
2972 else /* eh_type == xtWindowUnderflow. */
2973 cache
->wd
.ws
= ws
| (1 << wb
);
2975 cache
->wd
.wb
= (ps
& 0xf00) >> 8; /* Set WB to OWB. */
2976 regnum
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
,
2978 ra
= xtensa_read_register (regnum
);
2979 cache
->wd
.callsize
= WINSIZE (ra
);
2980 cache
->prev_sp
= xtensa_read_register (regnum
+ 1);
2981 /* Set regnum to a frame pointer of the frame being cached. */
2982 regnum
= xtensa_scan_prologue (gdbarch
, pc
);
2983 regnum
= arreg_number (gdbarch
,
2984 gdbarch_tdep (gdbarch
)->a0_base
+ regnum
,
2986 cache
->base
= get_frame_register_unsigned (this_frame
, regnum
);
2988 /* Read PC of interrupted function from EPC1 register. */
2989 epc1_regnum
= xtensa_find_register_by_name (gdbarch
,"epc1");
2990 if (epc1_regnum
< 0)
2991 error(_("Unable to read Xtensa register EPC1"));
2992 cache
->ra
= xtensa_read_register (epc1_regnum
);
2993 cache
->pc
= get_frame_func (this_frame
);
2997 /* Skip function prologue.
2999 Return the pc of the first instruction after prologue. GDB calls this to
3000 find the address of the first line of the function or (if there is no line
3001 number information) to skip the prologue for planting breakpoints on
3002 function entries. Use debug info (if present) or prologue analysis to skip
3003 the prologue to achieve reliable debugging behavior. For windowed ABI,
3004 only the 'entry' instruction is skipped. It is not strictly necessary to
3005 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
3006 backtrace at any point in the prologue, however certain potential hazards
3007 are avoided and a more "normal" debugging experience is ensured by
3008 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
3009 For example, if we don't skip the prologue:
3010 - Some args may not yet have been saved to the stack where the debug
3011 info expects to find them (true anyway when only 'entry' is skipped);
3012 - Software breakpoints ('break' instrs) may not have been unplanted
3013 when the prologue analysis is done on initializing the frame cache,
3014 and breaks in the prologue will throw off the analysis.
3016 If we have debug info ( line-number info, in particular ) we simply skip
3017 the code associated with the first function line effectively skipping
3018 the prologue code. It works even in cases like
3021 { int local_var = 1;
3025 because, for this source code, both Xtensa compilers will generate two
3026 separate entries ( with the same line number ) in dwarf line-number
3027 section to make sure there is a boundary between the prologue code and
3028 the rest of the function.
3030 If there is no debug info, we need to analyze the code. */
3032 /* #define DONT_SKIP_PROLOGUE */
3035 xtensa_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
3037 struct symtab_and_line prologue_sal
;
3040 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc
);
3042 #if DONT_SKIP_PROLOGUE
3046 /* Try to find first body line from debug info. */
3048 prologue_sal
= find_pc_line (start_pc
, 0);
3049 if (prologue_sal
.line
!= 0) /* Found debug info. */
3051 /* In Call0, it is possible to have a function with only one instruction
3052 ('ret') resulting from a one-line optimized function that does nothing.
3053 In that case, prologue_sal.end may actually point to the start of the
3054 next function in the text section, causing a breakpoint to be set at
3055 the wrong place. Check, if the end address is within a different
3056 function, and if so return the start PC. We know we have symbol
3061 if ((gdbarch_tdep (gdbarch
)->call_abi
== CallAbiCall0Only
)
3062 && call0_ret (start_pc
, prologue_sal
.end
))
3065 find_pc_partial_function (prologue_sal
.end
, NULL
, &end_func
, NULL
);
3066 if (end_func
!= start_pc
)
3069 return prologue_sal
.end
;
3072 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
3073 body_pc
= call0_analyze_prologue (gdbarch
, start_pc
, 0, 0,
3074 xtensa_alloc_frame_cache (0));
3075 return body_pc
!= 0 ? body_pc
: start_pc
;
3078 /* Verify the current configuration. */
3080 xtensa_verify_config (struct gdbarch
*gdbarch
)
3082 struct ui_file
*log
;
3083 struct cleanup
*cleanups
;
3084 struct gdbarch_tdep
*tdep
;
3088 tdep
= gdbarch_tdep (gdbarch
);
3089 log
= mem_fileopen ();
3090 cleanups
= make_cleanup_ui_file_delete (log
);
3092 /* Verify that we got a reasonable number of AREGS. */
3093 if ((tdep
->num_aregs
& -tdep
->num_aregs
) != tdep
->num_aregs
)
3094 fprintf_unfiltered (log
, _("\
3095 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
3098 /* Verify that certain registers exist. */
3100 if (tdep
->pc_regnum
== -1)
3101 fprintf_unfiltered (log
, _("\n\tpc_regnum: No PC register"));
3102 if (tdep
->isa_use_exceptions
&& tdep
->ps_regnum
== -1)
3103 fprintf_unfiltered (log
, _("\n\tps_regnum: No PS register"));
3105 if (tdep
->isa_use_windowed_registers
)
3107 if (tdep
->wb_regnum
== -1)
3108 fprintf_unfiltered (log
, _("\n\twb_regnum: No WB register"));
3109 if (tdep
->ws_regnum
== -1)
3110 fprintf_unfiltered (log
, _("\n\tws_regnum: No WS register"));
3111 if (tdep
->ar_base
== -1)
3112 fprintf_unfiltered (log
, _("\n\tar_base: No AR registers"));
3115 if (tdep
->a0_base
== -1)
3116 fprintf_unfiltered (log
, _("\n\ta0_base: No Ax registers"));
3118 buf
= ui_file_xstrdup (log
, &length
);
3119 make_cleanup (xfree
, buf
);
3121 internal_error (__FILE__
, __LINE__
,
3122 _("the following are invalid: %s"), buf
);
3123 do_cleanups (cleanups
);
3127 /* Derive specific register numbers from the array of registers. */
3130 xtensa_derive_tdep (struct gdbarch_tdep
*tdep
)
3132 xtensa_register_t
* rmap
;
3133 int n
, max_size
= 4;
3136 tdep
->num_nopriv_regs
= 0;
3138 /* Special registers 0..255 (core). */
3139 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
3141 for (rmap
= tdep
->regmap
, n
= 0; rmap
->target_number
!= -1; n
++, rmap
++)
3143 if (rmap
->target_number
== 0x0020)
3144 tdep
->pc_regnum
= n
;
3145 else if (rmap
->target_number
== 0x0100)
3147 else if (rmap
->target_number
== 0x0000)
3149 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(72))
3150 tdep
->wb_regnum
= n
;
3151 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(73))
3152 tdep
->ws_regnum
= n
;
3153 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(233))
3154 tdep
->debugcause_regnum
= n
;
3155 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(232))
3156 tdep
->exccause_regnum
= n
;
3157 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(238))
3158 tdep
->excvaddr_regnum
= n
;
3159 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(0))
3160 tdep
->lbeg_regnum
= n
;
3161 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(1))
3162 tdep
->lend_regnum
= n
;
3163 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(2))
3164 tdep
->lcount_regnum
= n
;
3165 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(3))
3166 tdep
->sar_regnum
= n
;
3167 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(5))
3168 tdep
->litbase_regnum
= n
;
3169 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(230))
3170 tdep
->ps_regnum
= n
;
3172 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(226))
3173 tdep
->interrupt_regnum
= n
;
3174 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(227))
3175 tdep
->interrupt2_regnum
= n
;
3176 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(224))
3177 tdep
->cpenable_regnum
= n
;
3180 if (rmap
->byte_size
> max_size
)
3181 max_size
= rmap
->byte_size
;
3182 if (rmap
->mask
!= 0 && tdep
->num_regs
== 0)
3184 /* Find out out how to deal with priveleged registers.
3186 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3187 && tdep->num_nopriv_regs == 0)
3188 tdep->num_nopriv_regs = n;
3190 if ((rmap
->flags
& XTENSA_REGISTER_FLAGS_PRIVILEGED
) != 0
3191 && tdep
->num_regs
== 0)
3195 /* Number of pseudo registers. */
3196 tdep
->num_pseudo_regs
= n
- tdep
->num_regs
;
3198 /* Empirically determined maximum sizes. */
3199 tdep
->max_register_raw_size
= max_size
;
3200 tdep
->max_register_virtual_size
= max_size
;
3203 /* Module "constructor" function. */
3205 extern struct gdbarch_tdep xtensa_tdep
;
3207 static struct gdbarch
*
3208 xtensa_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3210 struct gdbarch_tdep
*tdep
;
3211 struct gdbarch
*gdbarch
;
3212 struct xtensa_abi_handler
*abi_handler
;
3214 DEBUGTRACE ("gdbarch_init()\n");
3216 /* We have to set the byte order before we call gdbarch_alloc. */
3217 info
.byte_order
= XCHAL_HAVE_BE
? BFD_ENDIAN_BIG
: BFD_ENDIAN_LITTLE
;
3219 tdep
= &xtensa_tdep
;
3220 gdbarch
= gdbarch_alloc (&info
, tdep
);
3221 xtensa_derive_tdep (tdep
);
3223 /* Verify our configuration. */
3224 xtensa_verify_config (gdbarch
);
3225 xtensa_session_once_reported
= 0;
3227 /* Pseudo-Register read/write. */
3228 set_gdbarch_pseudo_register_read (gdbarch
, xtensa_pseudo_register_read
);
3229 set_gdbarch_pseudo_register_write (gdbarch
, xtensa_pseudo_register_write
);
3231 /* Set target information. */
3232 set_gdbarch_num_regs (gdbarch
, tdep
->num_regs
);
3233 set_gdbarch_num_pseudo_regs (gdbarch
, tdep
->num_pseudo_regs
);
3234 set_gdbarch_sp_regnum (gdbarch
, tdep
->a0_base
+ 1);
3235 set_gdbarch_pc_regnum (gdbarch
, tdep
->pc_regnum
);
3236 set_gdbarch_ps_regnum (gdbarch
, tdep
->ps_regnum
);
3238 /* Renumber registers for known formats (stabs and dwarf2). */
3239 set_gdbarch_stab_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
3240 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
3242 /* We provide our own function to get register information. */
3243 set_gdbarch_register_name (gdbarch
, xtensa_register_name
);
3244 set_gdbarch_register_type (gdbarch
, xtensa_register_type
);
3246 /* To call functions from GDB using dummy frame. */
3247 set_gdbarch_push_dummy_call (gdbarch
, xtensa_push_dummy_call
);
3249 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
3251 set_gdbarch_return_value (gdbarch
, xtensa_return_value
);
3253 /* Advance PC across any prologue instructions to reach "real" code. */
3254 set_gdbarch_skip_prologue (gdbarch
, xtensa_skip_prologue
);
3256 /* Stack grows downward. */
3257 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3259 /* Set breakpoints. */
3260 set_gdbarch_breakpoint_from_pc (gdbarch
, xtensa_breakpoint_from_pc
);
3262 /* After breakpoint instruction or illegal instruction, pc still
3263 points at break instruction, so don't decrement. */
3264 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
3266 /* We don't skip args. */
3267 set_gdbarch_frame_args_skip (gdbarch
, 0);
3269 set_gdbarch_unwind_pc (gdbarch
, xtensa_unwind_pc
);
3271 set_gdbarch_frame_align (gdbarch
, xtensa_frame_align
);
3273 set_gdbarch_dummy_id (gdbarch
, xtensa_dummy_id
);
3275 /* Frame handling. */
3276 frame_base_set_default (gdbarch
, &xtensa_frame_base
);
3277 frame_unwind_append_unwinder (gdbarch
, &xtensa_unwind
);
3278 dwarf2_append_unwinders (gdbarch
);
3280 set_gdbarch_print_insn (gdbarch
, print_insn_xtensa
);
3282 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3284 xtensa_add_reggroups (gdbarch
);
3285 set_gdbarch_register_reggroup_p (gdbarch
, xtensa_register_reggroup_p
);
3287 set_gdbarch_regset_from_core_section (gdbarch
,
3288 xtensa_regset_from_core_section
);
3290 set_solib_svr4_fetch_link_map_offsets
3291 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
3297 xtensa_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3299 error (_("xtensa_dump_tdep(): not implemented"));
3302 /* Provide a prototype to silence -Wmissing-prototypes. */
3303 extern initialize_file_ftype _initialize_xtensa_tdep
;
3306 _initialize_xtensa_tdep (void)
3308 struct cmd_list_element
*c
;
3310 gdbarch_register (bfd_arch_xtensa
, xtensa_gdbarch_init
, xtensa_dump_tdep
);
3311 xtensa_init_reggroups ();
3313 add_setshow_zinteger_cmd ("xtensa",
3315 &xtensa_debug_level
,
3316 _("Set Xtensa debugging."),
3317 _("Show Xtensa debugging."), _("\
3318 When non-zero, Xtensa-specific debugging is enabled. \
3319 Can be 1, 2, 3, or 4 indicating the level of debugging."),
3322 &setdebuglist
, &showdebuglist
);