1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "solib-svr4.h"
31 #include "floatformat.h"
33 #include "reggroups.h"
36 #include "dummy-frame.h"
37 #include "elf/dwarf2.h"
38 #include "dwarf2-frame.h"
39 #include "dwarf2loc.h"
41 #include "frame-base.h"
42 #include "frame-unwind.h"
44 #include "arch-utils.h"
51 #include "gdb_assert.h"
53 #include "xtensa-isa.h"
54 #include "xtensa-tdep.h"
55 #include "xtensa-config.h"
58 static int xtensa_debug_level
= 0;
60 #define DEBUGWARN(args...) \
61 if (xtensa_debug_level > 0) \
62 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
64 #define DEBUGINFO(args...) \
65 if (xtensa_debug_level > 1) \
66 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
68 #define DEBUGTRACE(args...) \
69 if (xtensa_debug_level > 2) \
70 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
72 #define DEBUGVERB(args...) \
73 if (xtensa_debug_level > 3) \
74 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
77 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
78 #define SP_ALIGNMENT 16
81 /* On Windowed ABI, we use a6 through a11 for passing arguments
82 to a function called by GDB because CALL4 is used. */
83 #define ARGS_NUM_REGS 6
84 #define REGISTER_SIZE 4
87 /* Extract the call size from the return address or PS register. */
88 #define PS_CALLINC_SHIFT 16
89 #define PS_CALLINC_MASK 0x00030000
90 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
91 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
93 /* ABI-independent macros. */
94 #define ARG_NOF(gdbarch) \
95 (gdbarch_tdep (gdbarch)->call_abi \
96 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
97 #define ARG_1ST(gdbarch) \
98 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
99 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
100 : (gdbarch_tdep (gdbarch)->a0_base + 6))
102 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
103 indicates that the instruction is an ENTRY instruction. */
105 #define XTENSA_IS_ENTRY(gdbarch, op1) \
106 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
107 ? ((op1) == 0x6c) : ((op1) == 0x36))
109 #define XTENSA_ENTRY_LENGTH 3
111 /* windowing_enabled() returns true, if windowing is enabled.
112 WOE must be set to 1; EXCM to 0.
113 Note: We assume that EXCM is always 0 for XEA1. */
115 #define PS_WOE (1<<18)
116 #define PS_EXC (1<<4)
118 /* Convert a live A-register number to the corresponding AR-register number. */
120 arreg_number (struct gdbarch
*gdbarch
, int a_regnum
, ULONGEST wb
)
122 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
125 arreg
= a_regnum
- tdep
->a0_base
;
126 arreg
+= (wb
& ((tdep
->num_aregs
- 1) >> 2)) << WB_SHIFT
;
127 arreg
&= tdep
->num_aregs
- 1;
129 return arreg
+ tdep
->ar_base
;
132 /* Convert a live AR-register number to the corresponding A-register order
133 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
135 areg_number (struct gdbarch
*gdbarch
, int ar_regnum
, unsigned int wb
)
137 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
140 areg
= ar_regnum
- tdep
->ar_base
;
141 if (areg
< 0 || areg
>= tdep
->num_aregs
)
143 areg
= (areg
- wb
* 4) & (tdep
->num_aregs
- 1);
144 return (areg
> 15) ? -1 : areg
;
148 windowing_enabled (CORE_ADDR ps
)
150 return ((ps
& PS_EXC
) == 0 && (ps
& PS_WOE
) != 0);
153 /* Return the window size of the previous call to the function from which we
156 This function is used to extract the return value after a called function
157 has returned to the caller. On Xtensa, the register that holds the return
158 value (from the perspective of the caller) depends on what call
159 instruction was used. For now, we are assuming that the call instruction
160 precedes the current address, so we simply analyze the call instruction.
161 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
162 method to call the inferior function. */
165 extract_call_winsize (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
171 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc
);
173 /* Read the previous instruction (should be a call[x]{4|8|12}. */
174 read_memory (pc
-3, buf
, 3);
175 insn
= extract_unsigned_integer (buf
, 3);
177 /* Decode call instruction:
179 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
180 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
182 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
183 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
185 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
187 if (((insn
& 0xf) == 0x5) || ((insn
& 0xcf) == 0xc0))
188 winsize
= (insn
& 0x30) >> 2; /* 0, 4, 8, 12. */
192 if (((insn
>> 20) == 0x5) || (((insn
>> 16) & 0xf3) == 0x03))
193 winsize
= (insn
>> 16) & 0xc; /* 0, 4, 8, 12. */
199 /* REGISTER INFORMATION */
201 /* Returns the name of a register. */
203 xtensa_register_name (struct gdbarch
*gdbarch
, int regnum
)
205 /* Return the name stored in the register map. */
206 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
)
207 + gdbarch_num_pseudo_regs (gdbarch
))
208 return gdbarch_tdep (gdbarch
)->regmap
[regnum
].name
;
210 internal_error (__FILE__
, __LINE__
, _("invalid register %d"), regnum
);
215 xtensa_read_register (int regnum
)
219 regcache_raw_read_unsigned (get_current_regcache (), regnum
, &value
);
220 return (unsigned long) value
;
223 /* Return the type of a register. Create a new type, if necessary. */
225 static struct ctype_cache
227 struct ctype_cache
*next
;
229 struct type
*virtual_type
;
230 } *type_entries
= NULL
;
233 xtensa_register_type (struct gdbarch
*gdbarch
, int regnum
)
235 /* Return signed integer for ARx and Ax registers. */
236 if ((regnum
>= gdbarch_tdep (gdbarch
)->ar_base
237 && regnum
< gdbarch_tdep (gdbarch
)->ar_base
238 + gdbarch_tdep (gdbarch
)->num_aregs
)
239 || (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
240 && regnum
< gdbarch_tdep (gdbarch
)->a0_base
+ 16))
241 return builtin_type_int
;
243 if (regnum
== gdbarch_pc_regnum (gdbarch
)
244 || regnum
== gdbarch_tdep (gdbarch
)->a0_base
+ 1)
245 return lookup_pointer_type (builtin_type_void
);
247 /* Return the stored type for all other registers. */
248 else if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
)
249 + gdbarch_num_pseudo_regs (gdbarch
))
251 xtensa_register_t
* reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
253 /* Set ctype for this register (only the first time). */
257 struct ctype_cache
*tp
;
258 int size
= reg
->byte_size
;
260 /* We always use the memory representation,
261 even if the register width is smaller. */
265 reg
->ctype
= builtin_type_uint8
;
269 reg
->ctype
= builtin_type_uint16
;
273 reg
->ctype
= builtin_type_uint32
;
277 reg
->ctype
= builtin_type_uint64
;
281 reg
->ctype
= builtin_type_uint128
;
285 for (tp
= type_entries
; tp
!= NULL
; tp
= tp
->next
)
286 if (tp
->size
== size
)
291 char *name
= xmalloc (16);
292 tp
= xmalloc (sizeof (struct ctype_cache
));
293 tp
->next
= type_entries
;
297 sprintf (name
, "int%d", size
* 8);
298 tp
->virtual_type
= init_type (TYPE_CODE_INT
, size
,
299 TYPE_FLAG_UNSIGNED
, name
,
303 reg
->ctype
= tp
->virtual_type
;
309 internal_error (__FILE__
, __LINE__
, _("invalid register number %d"), regnum
);
314 /* Return the 'local' register number for stubs, dwarf2, etc.
315 The debugging information enumerates registers starting from 0 for A0
316 to n for An. So, we only have to add the base number for A0. */
319 xtensa_reg_to_regnum (struct gdbarch
*gdbarch
, int regnum
)
323 if (regnum
>= 0 && regnum
< 16)
324 return gdbarch_tdep (gdbarch
)->a0_base
+ regnum
;
327 i
< gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
329 if (regnum
== gdbarch_tdep (gdbarch
)->regmap
[i
].target_number
)
332 internal_error (__FILE__
, __LINE__
,
333 _("invalid dwarf/stabs register number %d"), regnum
);
338 /* Write the bits of a masked register to the various registers.
339 Only the masked areas of these registers are modified; the other
340 fields are untouched. The size of masked registers is always less
341 than or equal to 32 bits. */
344 xtensa_register_write_masked (struct regcache
*regcache
,
345 xtensa_register_t
*reg
, const gdb_byte
*buffer
)
347 unsigned int value
[(MAX_REGISTER_SIZE
+ 3) / 4];
348 const xtensa_mask_t
*mask
= reg
->mask
;
350 int shift
= 0; /* Shift for next mask (mod 32). */
351 int start
, size
; /* Start bit and size of current mask. */
353 unsigned int *ptr
= value
;
354 unsigned int regval
, m
, mem
= 0;
356 int bytesize
= reg
->byte_size
;
357 int bitsize
= bytesize
* 8;
360 DEBUGTRACE ("xtensa_register_write_masked ()\n");
362 /* Copy the masked register to host byte-order. */
363 if (gdbarch_byte_order (get_regcache_arch (regcache
)) == BFD_ENDIAN_BIG
)
364 for (i
= 0; i
< bytesize
; i
++)
367 mem
|= (buffer
[bytesize
- i
- 1] << 24);
372 for (i
= 0; i
< bytesize
; i
++)
375 mem
|= (buffer
[i
] << 24);
380 /* We might have to shift the final value:
381 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
382 bytesize & 3 == x -> shift (4-x) * 8. */
384 *ptr
= mem
>> (((0 - bytesize
) & 3) * 8);
388 /* Write the bits to the masked areas of the other registers. */
389 for (i
= 0; i
< mask
->count
; i
++)
391 start
= mask
->mask
[i
].bit_start
;
392 size
= mask
->mask
[i
].bit_size
;
393 regval
= mem
>> shift
;
395 if ((shift
+= size
) > bitsize
)
396 error (_("size of all masks is larger than the register"));
405 regval
|= mem
<< (size
- shift
);
408 /* Make sure we have a valid register. */
409 r
= mask
->mask
[i
].reg_num
;
410 if (r
>= 0 && size
> 0)
412 /* Don't overwrite the unmasked areas. */
414 regcache_cooked_read_unsigned (regcache
, r
, &old_val
);
415 m
= 0xffffffff >> (32 - size
) << start
;
417 regval
= (regval
& m
) | (old_val
& ~m
);
418 regcache_cooked_write_unsigned (regcache
, r
, regval
);
424 /* Read a tie state or mapped registers. Read the masked areas
425 of the registers and assemble them into a single value. */
428 xtensa_register_read_masked (struct regcache
*regcache
,
429 xtensa_register_t
*reg
, gdb_byte
*buffer
)
431 unsigned int value
[(MAX_REGISTER_SIZE
+ 3) / 4];
432 const xtensa_mask_t
*mask
= reg
->mask
;
437 unsigned int *ptr
= value
;
438 unsigned int regval
, mem
= 0;
440 int bytesize
= reg
->byte_size
;
441 int bitsize
= bytesize
* 8;
444 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
445 reg
->name
== 0 ? "" : reg
->name
);
447 /* Assemble the register from the masked areas of other registers. */
448 for (i
= 0; i
< mask
->count
; i
++)
450 int r
= mask
->mask
[i
].reg_num
;
454 regcache_cooked_read_unsigned (regcache
, r
, &val
);
455 regval
= (unsigned int) val
;
460 start
= mask
->mask
[i
].bit_start
;
461 size
= mask
->mask
[i
].bit_size
;
466 regval
&= (0xffffffff >> (32 - size
));
468 mem
|= regval
<< shift
;
470 if ((shift
+= size
) > bitsize
)
471 error (_("size of all masks is larger than the register"));
482 mem
= regval
>> (size
- shift
);
489 /* Copy value to target byte order. */
493 if (gdbarch_byte_order (get_regcache_arch (regcache
)) == BFD_ENDIAN_BIG
)
494 for (i
= 0; i
< bytesize
; i
++)
498 buffer
[bytesize
- i
- 1] = mem
& 0xff;
502 for (i
= 0; i
< bytesize
; i
++)
506 buffer
[i
] = mem
& 0xff;
512 /* Read pseudo registers. */
515 xtensa_pseudo_register_read (struct gdbarch
*gdbarch
,
516 struct regcache
*regcache
,
520 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
521 regnum
, xtensa_register_name (gdbarch
, regnum
));
523 if (regnum
== gdbarch_num_regs (gdbarch
)
524 + gdbarch_num_pseudo_regs (gdbarch
) - 1)
525 regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ 1;
527 /* Read aliases a0..a15, if this is a Windowed ABI. */
528 if (gdbarch_tdep (gdbarch
)->isa_use_windowed_registers
529 && (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
)
530 && (regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15))
532 gdb_byte
*buf
= (gdb_byte
*) alloca (MAX_REGISTER_SIZE
);
534 regcache_raw_read (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, buf
);
535 regnum
= arreg_number (gdbarch
, regnum
,
536 extract_unsigned_integer (buf
, 4));
539 /* We can always read non-pseudo registers. */
540 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
541 regcache_raw_read (regcache
, regnum
, buffer
);
544 /* We have to find out how to deal with priveleged registers.
545 Let's treat them as pseudo-registers, but we cannot read/write them. */
547 else if (regnum
< gdbarch_tdep (gdbarch
)->a0_base
)
549 buffer
[0] = (gdb_byte
)0;
550 buffer
[1] = (gdb_byte
)0;
551 buffer
[2] = (gdb_byte
)0;
552 buffer
[3] = (gdb_byte
)0;
554 /* Pseudo registers. */
556 && regnum
< gdbarch_num_regs (gdbarch
)
557 + gdbarch_num_pseudo_regs (gdbarch
))
559 xtensa_register_t
*reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
560 xtensa_register_type_t type
= reg
->type
;
561 int flags
= gdbarch_tdep (gdbarch
)->target_flags
;
563 /* We cannot read Unknown or Unmapped registers. */
564 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
566 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
568 warning (_("cannot read register %s"),
569 xtensa_register_name (gdbarch
, regnum
));
574 /* Some targets cannot read TIE register files. */
575 else if (type
== xtRegisterTypeTieRegfile
)
577 /* Use 'fetch' to get register? */
578 if (flags
& xtTargetFlagsUseFetchStore
)
580 warning (_("cannot read register"));
584 /* On some targets (esp. simulators), we can always read the reg. */
585 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
587 warning (_("cannot read register"));
592 /* We can always read mapped registers. */
593 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
595 xtensa_register_read_masked (regcache
, reg
, buffer
);
599 /* Assume that we can read the register. */
600 regcache_raw_read (regcache
, regnum
, buffer
);
603 internal_error (__FILE__
, __LINE__
,
604 _("invalid register number %d"), regnum
);
608 /* Write pseudo registers. */
611 xtensa_pseudo_register_write (struct gdbarch
*gdbarch
,
612 struct regcache
*regcache
,
614 const gdb_byte
*buffer
)
616 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
617 regnum
, xtensa_register_name (gdbarch
, regnum
));
619 if (regnum
== gdbarch_num_regs (gdbarch
)
620 + gdbarch_num_pseudo_regs (gdbarch
) -1)
621 regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ 1;
623 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
624 if (gdbarch_tdep (gdbarch
)->isa_use_windowed_registers
625 && (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
)
626 && (regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15))
628 gdb_byte
*buf
= (gdb_byte
*) alloca (MAX_REGISTER_SIZE
);
631 regcache_raw_read (regcache
,
632 gdbarch_tdep (gdbarch
)->wb_regnum
, buf
);
633 regnum
= arreg_number (gdbarch
, regnum
,
634 extract_unsigned_integer (buf
, 4));
637 /* We can always write 'core' registers.
638 Note: We might have converted Ax->ARy. */
639 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
640 regcache_raw_write (regcache
, regnum
, buffer
);
642 /* We have to find out how to deal with priveleged registers.
643 Let's treat them as pseudo-registers, but we cannot read/write them. */
645 else if (regnum
< gdbarch_tdep (gdbarch
)->a0_base
)
649 /* Pseudo registers. */
651 && regnum
< gdbarch_num_regs (gdbarch
)
652 + gdbarch_num_pseudo_regs (gdbarch
))
654 xtensa_register_t
*reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
655 xtensa_register_type_t type
= reg
->type
;
656 int flags
= gdbarch_tdep (gdbarch
)->target_flags
;
658 /* On most targets, we cannot write registers
659 of type "Unknown" or "Unmapped". */
660 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
662 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
664 warning (_("cannot write register %s"),
665 xtensa_register_name (gdbarch
, regnum
));
670 /* Some targets cannot read TIE register files. */
671 else if (type
== xtRegisterTypeTieRegfile
)
673 /* Use 'store' to get register? */
674 if (flags
& xtTargetFlagsUseFetchStore
)
676 warning (_("cannot write register"));
680 /* On some targets (esp. simulators), we can always write
682 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
684 warning (_("cannot write register"));
689 /* We can always write mapped registers. */
690 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
692 xtensa_register_write_masked (regcache
, reg
, buffer
);
696 /* Assume that we can write the register. */
697 regcache_raw_write (regcache
, regnum
, buffer
);
700 internal_error (__FILE__
, __LINE__
,
701 _("invalid register number %d"), regnum
);
704 static struct reggroup
*xtensa_ar_reggroup
;
705 static struct reggroup
*xtensa_user_reggroup
;
706 static struct reggroup
*xtensa_vectra_reggroup
;
707 static struct reggroup
*xtensa_cp
[XTENSA_MAX_COPROCESSOR
];
710 xtensa_init_reggroups (void)
712 xtensa_ar_reggroup
= reggroup_new ("ar", USER_REGGROUP
);
713 xtensa_user_reggroup
= reggroup_new ("user", USER_REGGROUP
);
714 xtensa_vectra_reggroup
= reggroup_new ("vectra", USER_REGGROUP
);
716 xtensa_cp
[0] = reggroup_new ("cp0", USER_REGGROUP
);
717 xtensa_cp
[1] = reggroup_new ("cp1", USER_REGGROUP
);
718 xtensa_cp
[2] = reggroup_new ("cp2", USER_REGGROUP
);
719 xtensa_cp
[3] = reggroup_new ("cp3", USER_REGGROUP
);
720 xtensa_cp
[4] = reggroup_new ("cp4", USER_REGGROUP
);
721 xtensa_cp
[5] = reggroup_new ("cp5", USER_REGGROUP
);
722 xtensa_cp
[6] = reggroup_new ("cp6", USER_REGGROUP
);
723 xtensa_cp
[7] = reggroup_new ("cp7", USER_REGGROUP
);
727 xtensa_add_reggroups (struct gdbarch
*gdbarch
)
731 /* Predefined groups. */
732 reggroup_add (gdbarch
, all_reggroup
);
733 reggroup_add (gdbarch
, save_reggroup
);
734 reggroup_add (gdbarch
, restore_reggroup
);
735 reggroup_add (gdbarch
, system_reggroup
);
736 reggroup_add (gdbarch
, vector_reggroup
);
737 reggroup_add (gdbarch
, general_reggroup
);
738 reggroup_add (gdbarch
, float_reggroup
);
740 /* Xtensa-specific groups. */
741 reggroup_add (gdbarch
, xtensa_ar_reggroup
);
742 reggroup_add (gdbarch
, xtensa_user_reggroup
);
743 reggroup_add (gdbarch
, xtensa_vectra_reggroup
);
745 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
746 reggroup_add (gdbarch
, xtensa_cp
[i
]);
750 xtensa_coprocessor_register_group (struct reggroup
*group
)
754 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
755 if (group
== xtensa_cp
[i
])
761 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
762 | XTENSA_REGISTER_FLAGS_WRITABLE \
763 | XTENSA_REGISTER_FLAGS_VOLATILE)
765 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
766 | XTENSA_REGISTER_FLAGS_WRITABLE)
769 xtensa_register_reggroup_p (struct gdbarch
*gdbarch
,
771 struct reggroup
*group
)
773 xtensa_register_t
* reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
774 xtensa_register_type_t type
= reg
->type
;
775 xtensa_register_group_t rg
= reg
->group
;
778 /* First, skip registers that are not visible to this target
779 (unknown and unmapped registers when not using ISS). */
781 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
783 if (group
== all_reggroup
)
785 if (group
== xtensa_ar_reggroup
)
786 return rg
& xtRegisterGroupAddrReg
;
787 if (group
== xtensa_user_reggroup
)
788 return rg
& xtRegisterGroupUser
;
789 if (group
== float_reggroup
)
790 return rg
& xtRegisterGroupFloat
;
791 if (group
== general_reggroup
)
792 return rg
& xtRegisterGroupGeneral
;
793 if (group
== float_reggroup
)
794 return rg
& xtRegisterGroupFloat
;
795 if (group
== system_reggroup
)
796 return rg
& xtRegisterGroupState
;
797 if (group
== vector_reggroup
|| group
== xtensa_vectra_reggroup
)
798 return rg
& xtRegisterGroupVectra
;
799 if (group
== save_reggroup
|| group
== restore_reggroup
)
800 return (regnum
< gdbarch_num_regs (gdbarch
)
801 && (reg
->flags
& SAVE_REST_FLAGS
) == SAVE_REST_VALID
);
802 if ((cp_number
= xtensa_coprocessor_register_group (group
)) >= 0)
803 return rg
& (xtRegisterGroupCP0
<< cp_number
);
809 /* Supply register REGNUM from the buffer specified by GREGS and LEN
810 in the general-purpose register set REGSET to register cache
811 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
814 xtensa_supply_gregset (const struct regset
*regset
,
820 const xtensa_elf_gregset_t
*regs
= gregs
;
821 struct gdbarch
*gdbarch
= get_regcache_arch (rc
);
824 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...) \n", regnum
);
826 if (regnum
== gdbarch_pc_regnum (gdbarch
) || regnum
== -1)
827 regcache_raw_supply (rc
, gdbarch_pc_regnum (gdbarch
), (char *) ®s
->pc
);
828 if (regnum
== gdbarch_ps_regnum (gdbarch
) || regnum
== -1)
829 regcache_raw_supply (rc
, gdbarch_ps_regnum (gdbarch
), (char *) ®s
->ps
);
830 if (regnum
== gdbarch_tdep (gdbarch
)->wb_regnum
|| regnum
== -1)
831 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->wb_regnum
,
832 (char *) ®s
->windowbase
);
833 if (regnum
== gdbarch_tdep (gdbarch
)->ws_regnum
|| regnum
== -1)
834 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->ws_regnum
,
835 (char *) ®s
->windowstart
);
836 if (regnum
== gdbarch_tdep (gdbarch
)->lbeg_regnum
|| regnum
== -1)
837 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lbeg_regnum
,
838 (char *) ®s
->lbeg
);
839 if (regnum
== gdbarch_tdep (gdbarch
)->lend_regnum
|| regnum
== -1)
840 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lend_regnum
,
841 (char *) ®s
->lend
);
842 if (regnum
== gdbarch_tdep (gdbarch
)->lcount_regnum
|| regnum
== -1)
843 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lcount_regnum
,
844 (char *) ®s
->lcount
);
845 if (regnum
== gdbarch_tdep (gdbarch
)->sar_regnum
|| regnum
== -1)
846 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->sar_regnum
,
847 (char *) ®s
->sar
);
848 if (regnum
>=gdbarch_tdep (gdbarch
)->ar_base
849 && regnum
< gdbarch_tdep (gdbarch
)->ar_base
850 + gdbarch_tdep (gdbarch
)->num_aregs
)
851 regcache_raw_supply (rc
, regnum
,
852 (char *) ®s
->ar
[regnum
- gdbarch_tdep
853 (gdbarch
)->ar_base
]);
854 else if (regnum
== -1)
856 for (i
= 0; i
< gdbarch_tdep (gdbarch
)->num_aregs
; ++i
)
857 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->ar_base
+ i
,
858 (char *) ®s
->ar
[i
]);
863 /* Xtensa register set. */
869 xtensa_supply_gregset
873 /* Return the appropriate register set for the core
874 section identified by SECT_NAME and SECT_SIZE. */
876 static const struct regset
*
877 xtensa_regset_from_core_section (struct gdbarch
*core_arch
,
878 const char *sect_name
,
881 DEBUGTRACE ("xtensa_regset_from_core_section "
882 "(..., sect_name==\"%s\", sect_size==%x) \n",
883 sect_name
, (unsigned int) sect_size
);
885 if (strcmp (sect_name
, ".reg") == 0
886 && sect_size
>= sizeof(xtensa_elf_gregset_t
))
887 return &xtensa_gregset
;
893 /* Handling frames. */
895 /* Number of registers to save in case of Windowed ABI. */
896 #define XTENSA_NUM_SAVED_AREGS 12
898 /* Frame cache part for Windowed ABI. */
899 typedef struct xtensa_windowed_frame_cache
901 int wb
; /* WINDOWBASE of the previous frame. */
902 int callsize
; /* Call size of this frame. */
903 int ws
; /* WINDOWSTART of the previous frame. It keeps track of
904 life windows only. If there is no bit set for the
905 window, that means it had been already spilled
906 because of window overflow. */
908 /* Spilled A-registers from the previous frame.
909 AREGS[i] == -1, if corresponding AR is alive. */
910 CORE_ADDR aregs
[XTENSA_NUM_SAVED_AREGS
];
911 } xtensa_windowed_frame_cache_t
;
913 /* Call0 ABI Definitions. */
915 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue analysis. */
916 #define C0_NREGS 16 /* Number of A-registers to track. */
917 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
918 #define C0_SP 1 /* Register used as SP. */
919 #define C0_FP 15 /* Register used as FP. */
920 #define C0_RA 0 /* Register used as return address. */
921 #define C0_ARGS 2 /* Register used as first arg/retval. */
922 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
924 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
925 A-register where the current content of the reg came from (in terms
926 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
927 mean that the orignal content of the register was saved to the stack.
928 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
929 know where SP will end up until the entire prologue has been analyzed. */
931 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
932 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
933 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
935 extern xtensa_isa xtensa_default_isa
;
937 typedef struct xtensa_c0reg
939 int fr_reg
; /* original register from which register content
940 is derived, or C0_CONST, or C0_INEXP. */
941 int fr_ofs
; /* constant offset from reg, or immediate value. */
942 int to_stk
; /* offset from original SP to register (4-byte aligned),
943 or C0_NOSTK if register has not been saved. */
947 /* Frame cache part for Call0 ABI. */
948 typedef struct xtensa_call0_frame_cache
950 int c0_frmsz
; /* Stack frame size. */
951 int c0_hasfp
; /* Current frame uses frame pointer. */
952 int fp_regnum
; /* A-register used as FP. */
953 int c0_fp
; /* Actual value of frame pointer. */
954 xtensa_c0reg_t c0_rt
[C0_NREGS
]; /* Register tracking information. */
955 } xtensa_call0_frame_cache_t
;
957 typedef struct xtensa_frame_cache
959 CORE_ADDR base
; /* Stack pointer of this frame. */
960 CORE_ADDR pc
; /* PC at the entry point to the function. */
961 CORE_ADDR ra
; /* The raw return address (without CALLINC). */
962 CORE_ADDR ps
; /* The PS register of the previous frame. */
963 CORE_ADDR prev_sp
; /* Stack Pointer of the previous frame. */
964 int call0
; /* It's a call0 framework (else windowed). */
967 xtensa_windowed_frame_cache_t wd
; /* call0 == false. */
968 xtensa_call0_frame_cache_t c0
; /* call0 == true. */
970 } xtensa_frame_cache_t
;
973 static struct xtensa_frame_cache
*
974 xtensa_alloc_frame_cache (int windowed
)
976 xtensa_frame_cache_t
*cache
;
979 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
981 cache
= FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t
);
988 cache
->call0
= !windowed
;
991 cache
->c0
.c0_frmsz
= -1;
992 cache
->c0
.c0_hasfp
= 0;
993 cache
->c0
.fp_regnum
= -1;
994 cache
->c0
.c0_fp
= -1;
996 for (i
= 0; i
< C0_NREGS
; i
++)
998 cache
->c0
.c0_rt
[i
].fr_reg
= i
;
999 cache
->c0
.c0_rt
[i
].fr_ofs
= 0;
1000 cache
->c0
.c0_rt
[i
].to_stk
= C0_NOSTK
;
1007 cache
->wd
.callsize
= -1;
1009 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
1010 cache
->wd
.aregs
[i
] = -1;
1017 xtensa_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
1019 return address
& ~15;
1024 xtensa_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1028 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %p)\n", next_frame
);
1030 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1032 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int)
1033 extract_typed_address (buf
, builtin_type_void_func_ptr
));
1035 return extract_typed_address (buf
, builtin_type_void_func_ptr
);
1039 static struct frame_id
1040 xtensa_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1044 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1046 pc
= get_frame_pc (this_frame
);
1047 fp
= get_frame_register_unsigned
1048 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1050 /* Make dummy frame ID unique by adding a constant. */
1051 return frame_id_build (fp
+ SP_ALIGNMENT
, pc
);
1054 /* Returns the best guess about which register is a frame pointer
1055 for the function containing CURRENT_PC. */
1057 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1060 xtensa_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
)
1062 #define RETURN_FP goto done
1064 unsigned int fp_regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ 1;
1065 CORE_ADDR start_addr
;
1067 xtensa_insnbuf ins
, slot
;
1068 char ibuf
[XTENSA_ISA_BSZ
];
1069 CORE_ADDR ia
, bt
, ba
;
1071 int ilen
, islots
, is
;
1073 const char *opcname
;
1075 find_pc_partial_function (current_pc
, NULL
, &start_addr
, NULL
);
1076 if (start_addr
== 0)
1079 if (!xtensa_default_isa
)
1080 xtensa_default_isa
= xtensa_isa_init (0, 0);
1081 isa
= xtensa_default_isa
;
1082 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
1083 ins
= xtensa_insnbuf_alloc (isa
);
1084 slot
= xtensa_insnbuf_alloc (isa
);
1087 for (ia
= start_addr
, bt
= ia
; ia
< current_pc
; ia
+= ilen
)
1089 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
1092 bt
= (ba
+ XTENSA_ISA_BSZ
) < current_pc
1093 ? ba
+ XTENSA_ISA_BSZ
: current_pc
;
1094 read_memory (ba
, ibuf
, bt
- ba
);
1097 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
1098 ifmt
= xtensa_format_decode (isa
, ins
);
1099 if (ifmt
== XTENSA_UNDEFINED
)
1101 ilen
= xtensa_format_length (isa
, ifmt
);
1102 if (ilen
== XTENSA_UNDEFINED
)
1104 islots
= xtensa_format_num_slots (isa
, ifmt
);
1105 if (islots
== XTENSA_UNDEFINED
)
1108 for (is
= 0; is
< islots
; ++is
)
1110 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
1113 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
1114 if (opc
== XTENSA_UNDEFINED
)
1117 opcname
= xtensa_opcode_name (isa
, opc
);
1119 if (strcasecmp (opcname
, "mov.n") == 0
1120 || strcasecmp (opcname
, "or") == 0)
1122 unsigned int register_operand
;
1124 /* Possible candidate for setting frame pointer
1125 from A1. This is what we are looking for. */
1127 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
,
1128 is
, slot
, ®ister_operand
) != 0)
1130 if (xtensa_operand_decode (isa
, opc
, 1, ®ister_operand
) != 0)
1132 if (register_operand
== 1) /* Mov{.n} FP A1. */
1134 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
,
1135 ®ister_operand
) != 0)
1137 if (xtensa_operand_decode (isa
, opc
, 0,
1138 ®ister_operand
) != 0)
1141 fp_regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ register_operand
;
1147 /* We have problems decoding the memory. */
1149 || strcasecmp (opcname
, "ill") == 0
1150 || strcasecmp (opcname
, "ill.n") == 0
1151 /* Hit planted breakpoint. */
1152 || strcasecmp (opcname
, "break") == 0
1153 || strcasecmp (opcname
, "break.n") == 0
1154 /* Flow control instructions finish prologue. */
1155 || xtensa_opcode_is_branch (isa
, opc
) > 0
1156 || xtensa_opcode_is_jump (isa
, opc
) > 0
1157 || xtensa_opcode_is_loop (isa
, opc
) > 0
1158 || xtensa_opcode_is_call (isa
, opc
) > 0
1159 || strcasecmp (opcname
, "simcall") == 0
1160 || strcasecmp (opcname
, "syscall") == 0)
1161 /* Can not continue analysis. */
1166 xtensa_insnbuf_free(isa
, slot
);
1167 xtensa_insnbuf_free(isa
, ins
);
1171 /* The key values to identify the frame using "cache" are
1173 cache->base = SP (or best guess about FP) of this frame;
1174 cache->pc = entry-PC (entry point of the frame function);
1175 cache->prev_sp = SP of the previous frame.
1179 call0_frame_cache (struct frame_info
*this_frame
,
1180 xtensa_frame_cache_t
*cache
,
1183 static struct xtensa_frame_cache
*
1184 xtensa_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1186 xtensa_frame_cache_t
*cache
;
1187 CORE_ADDR ra
, wb
, ws
, pc
, sp
, ps
;
1188 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1189 unsigned int ps_regnum
= gdbarch_ps_regnum (gdbarch
);
1190 unsigned int fp_regnum
;
1197 windowed
= windowing_enabled (xtensa_read_register (ps_regnum
));
1199 /* Get pristine xtensa-frame. */
1200 cache
= xtensa_alloc_frame_cache (windowed
);
1201 *this_cache
= cache
;
1203 pc
= get_frame_register_unsigned (this_frame
,
1204 gdbarch_pc_regnum (gdbarch
));
1208 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1209 wb
= get_frame_register_unsigned (this_frame
,
1210 gdbarch_tdep (gdbarch
)->wb_regnum
);
1211 ws
= get_frame_register_unsigned (this_frame
,
1212 gdbarch_tdep (gdbarch
)->ws_regnum
);
1213 ps
= get_frame_register_unsigned (this_frame
, ps_regnum
);
1215 op1
= read_memory_integer (pc
, 1);
1216 if (XTENSA_IS_ENTRY (gdbarch
, op1
))
1218 int callinc
= CALLINC (ps
);
1219 ra
= get_frame_register_unsigned
1220 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ callinc
* 4);
1222 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1223 cache
->wd
.callsize
= 0;
1226 cache
->prev_sp
= get_frame_register_unsigned
1227 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1229 /* This only can be the outermost frame since we are
1230 just about to execute ENTRY. SP hasn't been set yet.
1231 We can assume any frame size, because it does not
1232 matter, and, let's fake frame base in cache. */
1233 cache
->base
= cache
->prev_sp
+ 16;
1236 cache
->ra
= (cache
->pc
& 0xc0000000) | (ra
& 0x3fffffff);
1237 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1238 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1244 fp_regnum
= xtensa_scan_prologue (gdbarch
, pc
);
1245 ra
= get_frame_register_unsigned (this_frame
,
1246 gdbarch_tdep (gdbarch
)->a0_base
);
1247 cache
->wd
.callsize
= WINSIZE (ra
);
1248 cache
->wd
.wb
= (wb
- cache
->wd
.callsize
/ 4)
1249 & (gdbarch_tdep (gdbarch
)->num_aregs
/ 4 - 1);
1250 cache
->wd
.ws
= ws
& ~(1 << wb
);
1252 cache
->pc
= get_frame_func (this_frame
);
1253 cache
->ra
= (cache
->pc
& 0xc0000000) | (ra
& 0x3fffffff);
1254 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1255 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1258 if (cache
->wd
.ws
== 0)
1263 sp
= get_frame_register_unsigned
1264 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1) - 16;
1266 for (i
= 0; i
< 4; i
++, sp
+= 4)
1268 cache
->wd
.aregs
[i
] = sp
;
1271 if (cache
->wd
.callsize
> 4)
1273 /* Set A4...A7/A11. */
1274 /* Get the SP of the frame previous to the previous one.
1275 To achieve this, we have to dereference SP twice. */
1276 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4);
1277 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4);
1278 sp
-= cache
->wd
.callsize
* 4;
1280 for ( i
= 4; i
< cache
->wd
.callsize
; i
++, sp
+= 4)
1282 cache
->wd
.aregs
[i
] = sp
;
1287 if ((cache
->prev_sp
== 0) && ( ra
!= 0 ))
1288 /* If RA is equal to 0 this frame is an outermost frame. Leave
1289 cache->prev_sp unchanged marking the boundary of the frame stack. */
1291 if ((cache
->wd
.ws
& (1 << cache
->wd
.wb
)) == 0)
1293 /* Register window overflow already happened.
1294 We can read caller's SP from the proper spill loction. */
1295 sp
= get_frame_register_unsigned
1296 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1297 cache
->prev_sp
= read_memory_integer (sp
- 12, 4);
1301 /* Read caller's frame SP directly from the previous window. */
1302 int regnum
= arreg_number
1303 (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ 1,
1306 cache
->prev_sp
= xtensa_read_register (regnum
);
1310 else /* Call0 framework. */
1312 call0_frame_cache (this_frame
, cache
, pc
);
1313 fp_regnum
= cache
->c0
.fp_regnum
;
1316 cache
->base
= get_frame_register_unsigned (this_frame
, fp_regnum
);
1322 xtensa_frame_this_id (struct frame_info
*this_frame
,
1324 struct frame_id
*this_id
)
1326 struct xtensa_frame_cache
*cache
=
1327 xtensa_frame_cache (this_frame
, this_cache
);
1329 if (cache
->prev_sp
== 0)
1332 (*this_id
) = frame_id_build (cache
->prev_sp
, cache
->pc
);
1335 static struct value
*
1336 xtensa_frame_prev_register (struct frame_info
*this_frame
,
1340 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1341 struct xtensa_frame_cache
*cache
;
1342 ULONGEST saved_reg
= 0;
1345 if (*this_cache
== NULL
)
1346 *this_cache
= xtensa_frame_cache (this_frame
, this_cache
);
1347 cache
= *this_cache
;
1349 if (regnum
==gdbarch_pc_regnum (gdbarch
))
1350 saved_reg
= cache
->ra
;
1351 else if (regnum
== gdbarch_tdep (gdbarch
)->a0_base
+ 1)
1352 saved_reg
= cache
->prev_sp
;
1353 else if (!cache
->call0
)
1355 if (regnum
== gdbarch_tdep (gdbarch
)->ws_regnum
)
1356 saved_reg
= cache
->wd
.ws
;
1357 else if (regnum
== gdbarch_tdep (gdbarch
)->wb_regnum
)
1358 saved_reg
= cache
->wd
.wb
;
1359 else if (regnum
== gdbarch_ps_regnum (gdbarch
))
1360 saved_reg
= cache
->ps
;
1368 return frame_unwind_got_constant (this_frame
, regnum
, saved_reg
);
1370 if (!cache
->call0
) /* Windowed ABI. */
1372 /* Convert A-register numbers to AR-register numbers,
1373 if we deal with A-register. */
1374 if (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
1375 && regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15)
1376 regnum
= arreg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1378 /* Check, if we deal with AR-register saved on stack. */
1379 if (regnum
>= gdbarch_tdep (gdbarch
)->ar_base
1380 && regnum
<= (gdbarch_tdep (gdbarch
)->ar_base
1381 + gdbarch_tdep (gdbarch
)->num_aregs
))
1383 int areg
= areg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1386 && areg
< XTENSA_NUM_SAVED_AREGS
1387 && cache
->wd
.aregs
[areg
] != -1)
1388 return frame_unwind_got_memory (this_frame
, regnum
,
1389 cache
->wd
.aregs
[areg
]);
1392 else /* Call0 ABI. */
1394 int reg
= (regnum
>= gdbarch_tdep (gdbarch
)->ar_base
1395 && regnum
<= (gdbarch_tdep (gdbarch
)->ar_base
1397 ? regnum
- gdbarch_tdep (gdbarch
)->ar_base
: regnum
;
1404 /* If register was saved in the prologue, retrieve it. */
1405 stkofs
= cache
->c0
.c0_rt
[reg
].to_stk
;
1406 if (stkofs
!= C0_NOSTK
)
1408 /* Determine SP on entry based on FP. */
1409 spe
= cache
->c0
.c0_fp
1410 - cache
->c0
.c0_rt
[cache
->c0
.fp_regnum
].fr_ofs
;
1412 return frame_unwind_got_memory (this_frame
, regnum
, spe
+ stkofs
);
1417 /* All other registers have been either saved to
1418 the stack or are still alive in the processor. */
1420 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1424 static const struct frame_unwind
1428 xtensa_frame_this_id
,
1429 xtensa_frame_prev_register
,
1431 default_frame_sniffer
1435 xtensa_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1437 struct xtensa_frame_cache
*cache
=
1438 xtensa_frame_cache (this_frame
, this_cache
);
1443 static const struct frame_base
1447 xtensa_frame_base_address
,
1448 xtensa_frame_base_address
,
1449 xtensa_frame_base_address
1454 xtensa_extract_return_value (struct type
*type
,
1455 struct regcache
*regcache
,
1458 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1459 bfd_byte
*valbuf
= dst
;
1460 int len
= TYPE_LENGTH (type
);
1465 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1467 gdb_assert(len
> 0);
1469 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1471 /* First, we have to find the caller window in the register file. */
1472 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1473 callsize
= extract_call_winsize (gdbarch
, pc
);
1475 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1476 if (len
> (callsize
> 8 ? 8 : 16))
1477 internal_error (__FILE__
, __LINE__
,
1478 _("cannot extract return value of %d bytes long"), len
);
1480 /* Get the register offset of the return
1481 register (A2) in the caller window. */
1482 regcache_raw_read_unsigned
1483 (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, &wb
);
1484 areg
= arreg_number (gdbarch
,
1485 gdbarch_tdep (gdbarch
)->a0_base
+ 2 + callsize
, wb
);
1489 /* No windowing hardware - Call0 ABI. */
1490 areg
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_ARGS
;
1493 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg
, len
);
1495 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1498 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1501 regcache_raw_read_part (regcache
, areg
, offset
, len
, valbuf
);
1503 regcache_raw_read (regcache
, areg
, valbuf
);
1509 xtensa_store_return_value (struct type
*type
,
1510 struct regcache
*regcache
,
1513 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1514 const bfd_byte
*valbuf
= dst
;
1518 int len
= TYPE_LENGTH (type
);
1521 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1523 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1525 regcache_raw_read_unsigned
1526 (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, &wb
);
1527 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1528 callsize
= extract_call_winsize (gdbarch
, pc
);
1530 if (len
> (callsize
> 8 ? 8 : 16))
1531 internal_error (__FILE__
, __LINE__
,
1532 _("unimplemented for this length: %d"),
1533 TYPE_LENGTH (type
));
1534 areg
= arreg_number (gdbarch
,
1535 gdbarch_tdep (gdbarch
)->a0_base
+ 2 + callsize
, wb
);
1537 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1538 callsize
, (int) wb
);
1542 areg
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_ARGS
;
1545 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1548 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1551 regcache_raw_write_part (regcache
, areg
, offset
, len
, valbuf
);
1553 regcache_raw_write (regcache
, areg
, valbuf
);
1558 static enum return_value_convention
1559 xtensa_return_value (struct gdbarch
*gdbarch
,
1560 struct type
*func_type
,
1561 struct type
*valtype
,
1562 struct regcache
*regcache
,
1564 const gdb_byte
*writebuf
)
1566 /* Structures up to 16 bytes are returned in registers. */
1568 int struct_return
= ((TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
1569 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
1570 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
1571 && TYPE_LENGTH (valtype
) > 16);
1574 return RETURN_VALUE_STRUCT_CONVENTION
;
1576 DEBUGTRACE ("xtensa_return_value(...)\n");
1578 if (writebuf
!= NULL
)
1580 xtensa_store_return_value (valtype
, regcache
, writebuf
);
1583 if (readbuf
!= NULL
)
1585 gdb_assert (!struct_return
);
1586 xtensa_extract_return_value (valtype
, regcache
, readbuf
);
1588 return RETURN_VALUE_REGISTER_CONVENTION
;
1595 xtensa_push_dummy_call (struct gdbarch
*gdbarch
,
1596 struct value
*function
,
1597 struct regcache
*regcache
,
1600 struct value
**args
,
1603 CORE_ADDR struct_addr
)
1606 int size
, onstack_size
;
1607 gdb_byte
*buf
= (gdb_byte
*) alloca (16);
1609 struct argument_info
1611 const bfd_byte
*contents
;
1613 int onstack
; /* onstack == 0 => in reg */
1614 int align
; /* alignment */
1617 int offset
; /* stack offset if on stack */
1618 int regno
; /* regno if in register */
1622 struct argument_info
*arg_info
=
1623 (struct argument_info
*) alloca (nargs
* sizeof (struct argument_info
));
1627 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1629 if (xtensa_debug_level
> 3)
1632 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs
);
1633 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1634 "struct_addr=0x%x\n",
1635 (int) sp
, (int) struct_return
, (int) struct_addr
);
1637 for (i
= 0; i
< nargs
; i
++)
1639 struct value
*arg
= args
[i
];
1640 struct type
*arg_type
= check_typedef (value_type (arg
));
1641 fprintf_unfiltered (gdb_stdlog
, "%2d: 0x%lx %3d ",
1642 i
, (unsigned long) arg
, TYPE_LENGTH (arg_type
));
1643 switch (TYPE_CODE (arg_type
))
1646 fprintf_unfiltered (gdb_stdlog
, "int");
1648 case TYPE_CODE_STRUCT
:
1649 fprintf_unfiltered (gdb_stdlog
, "struct");
1652 fprintf_unfiltered (gdb_stdlog
, "%3d", TYPE_CODE (arg_type
));
1655 fprintf_unfiltered (gdb_stdlog
, " 0x%lx\n",
1656 (unsigned long) value_contents (arg
));
1660 /* First loop: collect information.
1661 Cast into type_long. (This shouldn't happen often for C because
1662 GDB already does this earlier.) It's possible that GDB could
1663 do it all the time but it's harmless to leave this code here. */
1670 size
= REGISTER_SIZE
;
1672 for (i
= 0; i
< nargs
; i
++)
1674 struct argument_info
*info
= &arg_info
[i
];
1675 struct value
*arg
= args
[i
];
1676 struct type
*arg_type
= check_typedef (value_type (arg
));
1678 switch (TYPE_CODE (arg_type
))
1681 case TYPE_CODE_BOOL
:
1682 case TYPE_CODE_CHAR
:
1683 case TYPE_CODE_RANGE
:
1684 case TYPE_CODE_ENUM
:
1686 /* Cast argument to long if necessary as the mask does it too. */
1687 if (TYPE_LENGTH (arg_type
) < TYPE_LENGTH (builtin_type_long
))
1689 arg_type
= builtin_type_long
;
1690 arg
= value_cast (arg_type
, arg
);
1692 /* Aligment is equal to the type length for the basic types. */
1693 info
->align
= TYPE_LENGTH (arg_type
);
1698 /* Align doubles correctly. */
1699 if (TYPE_LENGTH (arg_type
) == TYPE_LENGTH (builtin_type_double
))
1700 info
->align
= TYPE_LENGTH (builtin_type_double
);
1702 info
->align
= TYPE_LENGTH (builtin_type_long
);
1705 case TYPE_CODE_STRUCT
:
1707 info
->align
= TYPE_LENGTH (builtin_type_long
);
1710 info
->length
= TYPE_LENGTH (arg_type
);
1711 info
->contents
= value_contents (arg
);
1713 /* Align size and onstack_size. */
1714 size
= (size
+ info
->align
- 1) & ~(info
->align
- 1);
1715 onstack_size
= (onstack_size
+ info
->align
- 1) & ~(info
->align
- 1);
1717 if (size
+ info
->length
> REGISTER_SIZE
* ARG_NOF (gdbarch
))
1720 info
->u
.offset
= onstack_size
;
1721 onstack_size
+= info
->length
;
1726 info
->u
.regno
= ARG_1ST (gdbarch
) + size
/ REGISTER_SIZE
;
1728 size
+= info
->length
;
1731 /* Adjust the stack pointer and align it. */
1732 sp
= align_down (sp
- onstack_size
, SP_ALIGNMENT
);
1734 /* Simulate MOVSP, if Windowed ABI. */
1735 if ((gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1738 read_memory (osp
- 16, buf
, 16);
1739 write_memory (sp
- 16, buf
, 16);
1742 /* Second Loop: Load arguments. */
1746 store_unsigned_integer (buf
, REGISTER_SIZE
, struct_addr
);
1747 regcache_cooked_write (regcache
, ARG_1ST (gdbarch
), buf
);
1750 for (i
= 0; i
< nargs
; i
++)
1752 struct argument_info
*info
= &arg_info
[i
];
1756 int n
= info
->length
;
1757 CORE_ADDR offset
= sp
+ info
->u
.offset
;
1759 /* Odd-sized structs are aligned to the lower side of a memory
1760 word in big-endian mode and require a shift. This only
1761 applies for structures smaller than one word. */
1763 if (n
< REGISTER_SIZE
1764 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1765 offset
+= (REGISTER_SIZE
- n
);
1767 write_memory (offset
, info
->contents
, info
->length
);
1772 int n
= info
->length
;
1773 const bfd_byte
*cp
= info
->contents
;
1774 int r
= info
->u
.regno
;
1776 /* Odd-sized structs are aligned to the lower side of registers in
1777 big-endian mode and require a shift. The odd-sized leftover will
1778 be at the end. Note that this is only true for structures smaller
1779 than REGISTER_SIZE; for larger odd-sized structures the excess
1780 will be left-aligned in the register on both endiannesses. */
1782 if (n
< REGISTER_SIZE
1783 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1785 ULONGEST v
= extract_unsigned_integer (cp
, REGISTER_SIZE
);
1786 v
= v
>> ((REGISTER_SIZE
- n
) * TARGET_CHAR_BIT
);
1788 store_unsigned_integer (buf
, REGISTER_SIZE
, v
);
1789 regcache_cooked_write (regcache
, r
, buf
);
1791 cp
+= REGISTER_SIZE
;
1798 regcache_cooked_write (regcache
, r
, cp
);
1800 cp
+= REGISTER_SIZE
;
1807 /* Set the return address of dummy frame to the dummy address.
1808 The return address for the current function (in A0) is
1809 saved in the dummy frame, so we can savely overwrite A0 here. */
1811 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1813 ra
= (bp_addr
& 0x3fffffff) | 0x40000000;
1814 regcache_raw_read (regcache
, gdbarch_ps_regnum (gdbarch
), buf
);
1815 ps
= extract_unsigned_integer (buf
, 4) & ~0x00030000;
1816 regcache_cooked_write_unsigned
1817 (regcache
, gdbarch_tdep (gdbarch
)->a0_base
+ 4, ra
);
1818 regcache_cooked_write_unsigned (regcache
,
1819 gdbarch_ps_regnum (gdbarch
),
1822 /* All the registers have been saved. After executing
1823 dummy call, they all will be restored. So it's safe
1824 to modify WINDOWSTART register to make it look like there
1825 is only one register window corresponding to WINDOWEBASE. */
1827 regcache_raw_read (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, buf
);
1828 regcache_cooked_write_unsigned (regcache
,
1829 gdbarch_tdep (gdbarch
)->ws_regnum
,
1830 1 << extract_unsigned_integer (buf
, 4));
1834 /* Simulate CALL0: write RA into A0 register. */
1835 regcache_cooked_write_unsigned
1836 (regcache
, gdbarch_tdep (gdbarch
)->a0_base
, bp_addr
);
1839 /* Set new stack pointer and return it. */
1840 regcache_cooked_write_unsigned (regcache
,
1841 gdbarch_tdep (gdbarch
)->a0_base
+ 1, sp
);
1842 /* Make dummy frame ID unique by adding a constant. */
1843 return sp
+ SP_ALIGNMENT
;
1847 /* Return a breakpoint for the current location of PC. We always use
1848 the density version if we have density instructions (regardless of the
1849 current instruction at PC), and use regular instructions otherwise. */
1851 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1852 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1853 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1854 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1856 static const unsigned char *
1857 xtensa_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
1860 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
1861 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
1862 static unsigned char density_big_breakpoint
[] = DENSITY_BIG_BREAKPOINT
;
1863 static unsigned char density_little_breakpoint
[] = DENSITY_LITTLE_BREAKPOINT
;
1865 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr
);
1867 if (gdbarch_tdep (gdbarch
)->isa_use_density_instructions
)
1869 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1871 *lenptr
= sizeof (density_big_breakpoint
);
1872 return density_big_breakpoint
;
1876 *lenptr
= sizeof (density_little_breakpoint
);
1877 return density_little_breakpoint
;
1882 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1884 *lenptr
= sizeof (big_breakpoint
);
1885 return big_breakpoint
;
1889 *lenptr
= sizeof (little_breakpoint
);
1890 return little_breakpoint
;
1895 /* Call0 ABI support routines. */
1897 /* Call0 opcode class. Opcodes are preclassified according to what they
1898 mean for Call0 prologue analysis, and their number of significant operands.
1899 The purpose of this is to simplify prologue analysis by separating
1900 instruction decoding (libisa) from the semantics of prologue analysis. */
1903 c0opc_illegal
, /* Unknown to libisa (invalid) or 'ill' opcode. */
1904 c0opc_uninteresting
, /* Not interesting for Call0 prologue analysis. */
1905 c0opc_flow
, /* Flow control insn. */
1906 c0opc_entry
, /* ENTRY indicates non-Call0 prologue. */
1907 c0opc_break
, /* Debugger software breakpoints. */
1908 c0opc_add
, /* Adding two registers. */
1909 c0opc_addi
, /* Adding a register and an immediate. */
1910 c0opc_sub
, /* Subtracting a register from a register. */
1911 c0opc_mov
, /* Moving a register to a register. */
1912 c0opc_movi
, /* Moving an immediate to a register. */
1913 c0opc_l32r
, /* Loading a literal. */
1914 c0opc_s32i
, /* Storing word at fixed offset from a base register. */
1915 c0opc_NrOf
/* Number of opcode classifications. */
1919 /* Classify an opcode based on what it means for Call0 prologue analysis. */
1921 static xtensa_insn_kind
1922 call0_classify_opcode (xtensa_isa isa
, xtensa_opcode opc
)
1924 const char *opcname
;
1925 xtensa_insn_kind opclass
= c0opc_uninteresting
;
1927 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc
);
1929 /* Get opcode name and handle special classifications. */
1931 opcname
= xtensa_opcode_name (isa
, opc
);
1934 || strcasecmp (opcname
, "ill") == 0
1935 || strcasecmp (opcname
, "ill.n") == 0)
1936 opclass
= c0opc_illegal
;
1937 else if (strcasecmp (opcname
, "break") == 0
1938 || strcasecmp (opcname
, "break.n") == 0)
1939 opclass
= c0opc_break
;
1940 else if (strcasecmp (opcname
, "entry") == 0)
1941 opclass
= c0opc_entry
;
1942 else if (xtensa_opcode_is_branch (isa
, opc
) > 0
1943 || xtensa_opcode_is_jump (isa
, opc
) > 0
1944 || xtensa_opcode_is_loop (isa
, opc
) > 0
1945 || xtensa_opcode_is_call (isa
, opc
) > 0
1946 || strcasecmp (opcname
, "simcall") == 0
1947 || strcasecmp (opcname
, "syscall") == 0)
1948 opclass
= c0opc_flow
;
1950 /* Also, classify specific opcodes that need to be tracked. */
1951 else if (strcasecmp (opcname
, "add") == 0
1952 || strcasecmp (opcname
, "add.n") == 0)
1953 opclass
= c0opc_add
;
1954 else if (strcasecmp (opcname
, "addi") == 0
1955 || strcasecmp (opcname
, "addi.n") == 0
1956 || strcasecmp (opcname
, "addmi") == 0)
1957 opclass
= c0opc_addi
;
1958 else if (strcasecmp (opcname
, "sub") == 0)
1959 opclass
= c0opc_sub
;
1960 else if (strcasecmp (opcname
, "mov.n") == 0
1961 || strcasecmp (opcname
, "or") == 0) /* Could be 'mov' asm macro. */
1962 opclass
= c0opc_mov
;
1963 else if (strcasecmp (opcname
, "movi") == 0
1964 || strcasecmp (opcname
, "movi.n") == 0)
1965 opclass
= c0opc_movi
;
1966 else if (strcasecmp (opcname
, "l32r") == 0)
1967 opclass
= c0opc_l32r
;
1968 else if (strcasecmp (opcname
, "s32i") == 0
1969 || strcasecmp (opcname
, "s32i.n") == 0)
1970 opclass
= c0opc_s32i
;
1975 /* Tracks register movement/mutation for a given operation, which may
1976 be within a bundle. Updates the destination register tracking info
1977 accordingly. The pc is needed only for pc-relative load instructions
1978 (eg. l32r). The SP register number is needed to identify stores to
1982 call0_track_op (xtensa_c0reg_t dst
[], xtensa_c0reg_t src
[],
1983 xtensa_insn_kind opclass
, int nods
, unsigned odv
[],
1984 CORE_ADDR pc
, int spreg
)
1986 unsigned litbase
, litaddr
, litval
;
1991 /* 3 operands: dst, src, imm. */
1992 gdb_assert (nods
== 3);
1993 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
1994 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ odv
[2];
1997 /* 3 operands: dst, src1, src2. */
1998 gdb_assert (nods
== 3);
1999 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2001 dst
[odv
[0]].fr_reg
= src
[odv
[2]].fr_reg
;
2002 dst
[odv
[0]].fr_ofs
= src
[odv
[2]].fr_ofs
+ src
[odv
[1]].fr_ofs
;
2004 else if (src
[odv
[2]].fr_reg
== C0_CONST
)
2006 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2007 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ src
[odv
[2]].fr_ofs
;
2009 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2012 /* 3 operands: dst, src1, src2. */
2013 gdb_assert (nods
== 3);
2014 if (src
[odv
[2]].fr_reg
== C0_CONST
)
2016 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2017 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
- src
[odv
[2]].fr_ofs
;
2019 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2022 /* 2 operands: dst, src [, src]. */
2023 gdb_assert (nods
== 2);
2024 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2025 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
;
2028 /* 2 operands: dst, imm. */
2029 gdb_assert (nods
== 2);
2030 dst
[odv
[0]].fr_reg
= C0_CONST
;
2031 dst
[odv
[0]].fr_ofs
= odv
[1];
2034 /* 2 operands: dst, literal offset. */
2035 gdb_assert (nods
== 2);
2036 /* litbase = xtensa_get_litbase (pc); can be also used. */
2037 litbase
= (gdbarch_tdep (current_gdbarch
)->litbase_regnum
== -1)
2038 ? 0 : xtensa_read_register
2039 (gdbarch_tdep (current_gdbarch
)->litbase_regnum
);
2040 litaddr
= litbase
& 1
2041 ? (litbase
& ~1) + (signed)odv
[1]
2042 : (pc
+ 3 + (signed)odv
[1]) & ~3;
2043 litval
= read_memory_integer(litaddr
, 4);
2044 dst
[odv
[0]].fr_reg
= C0_CONST
;
2045 dst
[odv
[0]].fr_ofs
= litval
;
2048 /* 3 operands: value, base, offset. */
2049 gdb_assert (nods
== 3 && spreg
>= 0 && spreg
< C0_NREGS
);
2050 if (src
[odv
[1]].fr_reg
== spreg
/* Store to stack frame. */
2051 && (src
[odv
[1]].fr_ofs
& 3) == 0 /* Alignment preserved. */
2052 && src
[odv
[0]].fr_reg
>= 0 /* Value is from a register. */
2053 && src
[odv
[0]].fr_ofs
== 0 /* Value hasn't been modified. */
2054 && src
[src
[odv
[0]].fr_reg
].to_stk
== C0_NOSTK
) /* First time. */
2056 /* ISA encoding guarantees alignment. But, check it anyway. */
2057 gdb_assert ((odv
[2] & 3) == 0);
2058 dst
[src
[odv
[0]].fr_reg
].to_stk
= src
[odv
[1]].fr_ofs
+ odv
[2];
2066 /* Analyze prologue of the function at start address to determine if it uses
2067 the Call0 ABI, and if so track register moves and linear modifications
2068 in the prologue up to the PC or just beyond the prologue, whichever is first.
2069 An 'entry' instruction indicates non-Call0 ABI and the end of the prologue.
2070 The prologue may overlap non-prologue instructions but is guaranteed to end
2071 by the first flow-control instruction (jump, branch, call or return).
2072 Since an optimized function may move information around and change the
2073 stack frame arbitrarily during the prologue, the information is guaranteed
2074 valid only at the point in the function indicated by the PC.
2075 May be used to skip the prologue or identify the ABI, w/o tracking.
2077 Returns: Address of first instruction after prologue, or PC (whichever
2078 is first), or 0, if decoding failed (in libisa).
2080 start Start address of function/prologue.
2081 pc Program counter to stop at. Use 0 to continue to end of prologue.
2082 If 0, avoids infinite run-on in corrupt code memory by bounding
2083 the scan to the end of the function if that can be determined.
2084 nregs Number of general registers to track (size of rt[] array).
2086 rt[] Array[nregs] of xtensa_c0reg structures for register tracking info.
2087 If NULL, registers are not tracked.
2089 call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0
2090 (more accurately, non-zero until 'entry' insn is encountered).
2092 Note that these may produce useful results even if decoding fails
2093 because they begin with default assumptions that analysis may change. */
2096 call0_analyze_prologue (CORE_ADDR start
, CORE_ADDR pc
,
2097 int nregs
, xtensa_c0reg_t rt
[], int *call0
)
2099 CORE_ADDR ia
; /* Current insn address in prologue. */
2100 CORE_ADDR ba
= 0; /* Current address at base of insn buffer. */
2101 CORE_ADDR bt
; /* Current address at top+1 of insn buffer. */
2102 #define BSZ 32 /* Instruction buffer size. */
2103 char ibuf
[BSZ
]; /* Instruction buffer for decoding prologue. */
2104 xtensa_isa isa
; /* libisa ISA handle. */
2105 xtensa_insnbuf ins
, slot
; /* libisa handle to decoded insn, slot. */
2106 xtensa_format ifmt
; /* libisa instruction format. */
2107 int ilen
, islots
, is
; /* Instruction length, nbr slots, current slot. */
2108 xtensa_opcode opc
; /* Opcode in current slot. */
2109 xtensa_insn_kind opclass
; /* Opcode class for Call0 prologue analysis. */
2110 int nods
; /* Opcode number of operands. */
2111 unsigned odv
[C0_MAXOPDS
]; /* Operand values in order provided by libisa. */
2112 xtensa_c0reg_t
*rtmp
; /* Register tracking info snapshot. */
2113 int j
; /* General loop counter. */
2114 int fail
= 0; /* Set non-zero and exit, if decoding fails. */
2115 CORE_ADDR body_pc
; /* The PC for the first non-prologue insn. */
2116 CORE_ADDR end_pc
; /* The PC for the lust function insn. */
2118 struct symtab_and_line prologue_sal
;
2120 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2121 (int)start
, (int)pc
);
2123 /* Try to limit the scan to the end of the function if a non-zero pc
2124 arg was not supplied to avoid probing beyond the end of valid memory.
2125 If memory is full of garbage that classifies as c0opc_uninteresting.
2126 If this fails (eg. if no symbols) pc ends up 0 as it was.
2127 Intialize the Call0 frame and register tracking info.
2128 Assume it's Call0 until an 'entry' instruction is encountered.
2129 Assume we may be in the prologue until we hit a flow control instr. */
2135 /* Find out, if we have an information about the prologue from DWARF. */
2136 prologue_sal
= find_pc_line (start
, 0);
2137 if (prologue_sal
.line
!= 0) /* Found debug info. */
2138 body_pc
= prologue_sal
.end
;
2140 /* If we are going to analyze the prologue in general without knowing about
2141 the current PC, make the best assumtion for the end of the prologue. */
2144 find_pc_partial_function (start
, 0, NULL
, &end_pc
);
2145 body_pc
= min (end_pc
, body_pc
);
2148 body_pc
= min (pc
, body_pc
);
2155 rtmp
= (xtensa_c0reg_t
*) alloca(nregs
* sizeof(xtensa_c0reg_t
));
2156 /* rt is already initialized in xtensa_alloc_frame_cache(). */
2160 if (!xtensa_default_isa
)
2161 xtensa_default_isa
= xtensa_isa_init (0, 0);
2162 isa
= xtensa_default_isa
;
2163 gdb_assert (BSZ
>= xtensa_isa_maxlength (isa
));
2164 ins
= xtensa_insnbuf_alloc (isa
);
2165 slot
= xtensa_insnbuf_alloc (isa
);
2167 for (ia
= start
, bt
= ia
; ia
< body_pc
; ia
+= ilen
)
2169 /* (Re)fill instruction buffer from memory if necessary, but do not
2170 read memory beyond PC to be sure we stay within text section
2171 (this protection only works if a non-zero pc is supplied). */
2173 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2176 bt
= (ba
+ BSZ
) < body_pc
? ba
+ BSZ
: body_pc
;
2177 read_memory (ba
, ibuf
, bt
- ba
);
2180 /* Decode format information. */
2182 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2183 ifmt
= xtensa_format_decode (isa
, ins
);
2184 if (ifmt
== XTENSA_UNDEFINED
)
2189 ilen
= xtensa_format_length (isa
, ifmt
);
2190 if (ilen
== XTENSA_UNDEFINED
)
2195 islots
= xtensa_format_num_slots (isa
, ifmt
);
2196 if (islots
== XTENSA_UNDEFINED
)
2202 /* Analyze a bundle or a single instruction, using a snapshot of
2203 the register tracking info as input for the entire bundle so that
2204 register changes do not take effect within this bundle. */
2206 for (j
= 0; j
< nregs
; ++j
)
2209 for (is
= 0; is
< islots
; ++is
)
2211 /* Decode a slot and classify the opcode. */
2213 fail
= xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
);
2217 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2218 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2220 if (opc
== XTENSA_UNDEFINED
)
2221 opclass
= c0opc_illegal
;
2223 opclass
= call0_classify_opcode (isa
, opc
);
2225 /* Decide whether to track this opcode, ignore it, or bail out. */
2234 case c0opc_uninteresting
:
2243 ia
+= ilen
; /* Skip over 'entry' insn. */
2251 /* Only expected opcodes should get this far. */
2255 /* Extract and decode the operands. */
2256 nods
= xtensa_opcode_num_operands (isa
, opc
);
2257 if (nods
== XTENSA_UNDEFINED
)
2263 for (j
= 0; j
< nods
&& j
< C0_MAXOPDS
; ++j
)
2265 fail
= xtensa_operand_get_field (isa
, opc
, j
, ifmt
,
2270 fail
= xtensa_operand_decode (isa
, opc
, j
, &odv
[j
]);
2275 /* Check operands to verify use of 'mov' assembler macro. */
2276 if (opclass
== c0opc_mov
&& nods
== 3)
2278 if (odv
[2] == odv
[1])
2282 opclass
= c0opc_uninteresting
;
2287 /* Track register movement and modification for this operation. */
2288 call0_track_op (rt
, rtmp
, opclass
, nods
, odv
, ia
, 1);
2292 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2293 (unsigned)ia
, fail
? "failed" : "succeeded");
2294 xtensa_insnbuf_free(isa
, slot
);
2295 xtensa_insnbuf_free(isa
, ins
);
2296 return fail
? 0 : ia
;
2299 /* Initialize frame cache for the current frame in CALL0 ABI. */
2302 call0_frame_cache (struct frame_info
*this_frame
,
2303 xtensa_frame_cache_t
*cache
, CORE_ADDR pc
)
2305 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2306 CORE_ADDR start_pc
; /* The beginning of the function. */
2307 CORE_ADDR body_pc
=UINT_MAX
; /* PC, where prologue analysis stopped. */
2308 CORE_ADDR sp
, fp
, ra
;
2309 int fp_regnum
, c0_hasfp
, c0_frmsz
, prev_sp
, to_stk
;
2311 /* Find the beginning of the prologue of the function containing the PC
2312 and analyze it up to the PC or the end of the prologue. */
2314 if (find_pc_partial_function (pc
, NULL
, &start_pc
, NULL
))
2316 body_pc
= call0_analyze_prologue (start_pc
, pc
, C0_NREGS
,
2317 &cache
->c0
.c0_rt
[0],
2321 sp
= get_frame_register_unsigned
2322 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
2323 fp
= sp
; /* Assume FP == SP until proven otherwise. */
2325 /* Get the frame information and FP (if used) at the current PC.
2326 If PC is in the prologue, the prologue analysis is more reliable
2327 than DWARF info. We don't not know for sure if PC is in the prologue,
2328 but we know no calls have yet taken place, so we can almost
2329 certainly rely on the prologue analysis. */
2333 /* Prologue analysis was successful up to the PC.
2334 It includes the cases when PC == START_PC. */
2335 c0_hasfp
= cache
->c0
.c0_rt
[C0_FP
].fr_reg
== C0_SP
;
2336 /* c0_hasfp == true means there is a frame pointer because
2337 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2338 was derived from SP. Otherwise, it would be C0_FP. */
2339 fp_regnum
= c0_hasfp
? C0_FP
: C0_SP
;
2340 c0_frmsz
= - cache
->c0
.c0_rt
[fp_regnum
].fr_ofs
;
2341 fp_regnum
+= gdbarch_tdep (gdbarch
)->a0_base
;
2343 else /* No data from the prologue analysis. */
2346 fp_regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_SP
;
2351 prev_sp
= fp
+ c0_frmsz
;
2353 /* Frame size from debug info or prologue tracking does not account for
2354 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2357 fp
= get_frame_register_unsigned (this_frame
, fp_regnum
);
2359 /* Recalculate previous SP. */
2360 prev_sp
= fp
+ c0_frmsz
;
2361 /* Update the stack frame size. */
2362 c0_frmsz
+= fp
- sp
;
2365 /* Get the return address (RA) from the stack if saved,
2366 or try to get it from a register. */
2368 to_stk
= cache
->c0
.c0_rt
[C0_RA
].to_stk
;
2369 if (to_stk
!= C0_NOSTK
)
2371 read_memory_integer (sp
+ c0_frmsz
+ cache
->c0
.c0_rt
[C0_RA
].to_stk
, 4);
2373 else if (cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_CONST
2374 && cache
->c0
.c0_rt
[C0_RA
].fr_ofs
== 0)
2376 /* Special case for terminating backtrace at a function that wants to
2377 be seen as the outermost. Such a function will clear it's RA (A0)
2378 register to 0 in the prologue instead of saving its original value. */
2383 /* RA was copied to another register or (before any function call) may
2384 still be in the original RA register. This is not always reliable:
2385 even in a leaf function, register tracking stops after prologue, and
2386 even in prologue, non-prologue instructions (not tracked) may overwrite
2387 RA or any register it was copied to. If likely in prologue or before
2388 any call, use retracking info and hope for the best (compiler should
2389 have saved RA in stack if not in a leaf function). If not in prologue,
2395 (i
== C0_RA
|| cache
->c0
.c0_rt
[i
].fr_reg
!= C0_RA
);
2397 if (i
>= C0_NREGS
&& cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_RA
)
2401 ra
= get_frame_register_unsigned
2403 gdbarch_tdep (gdbarch
)->a0_base
+ cache
->c0
.c0_rt
[i
].fr_reg
);
2408 cache
->pc
= start_pc
;
2410 /* RA == 0 marks the outermost frame. Do not go past it. */
2411 cache
->prev_sp
= (ra
!= 0) ? prev_sp
: 0;
2412 cache
->c0
.fp_regnum
= fp_regnum
;
2413 cache
->c0
.c0_frmsz
= c0_frmsz
;
2414 cache
->c0
.c0_hasfp
= c0_hasfp
;
2415 cache
->c0
.c0_fp
= fp
;
2419 /* Skip function prologue.
2421 Return the pc of the first instruction after prologue. GDB calls this to
2422 find the address of the first line of the function or (if there is no line
2423 number information) to skip the prologue for planting breakpoints on
2424 function entries. Use debug info (if present) or prologue analysis to skip
2425 the prologue to achieve reliable debugging behavior. For windowed ABI,
2426 only the 'entry' instruction is skipped. It is not strictly necessary to
2427 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2428 backtrace at any point in the prologue, however certain potential hazards
2429 are avoided and a more "normal" debugging experience is ensured by
2430 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2431 For example, if we don't skip the prologue:
2432 - Some args may not yet have been saved to the stack where the debug
2433 info expects to find them (true anyway when only 'entry' is skipped);
2434 - Software breakpoints ('break' instrs) may not have been unplanted
2435 when the prologue analysis is done on initializing the frame cache,
2436 and breaks in the prologue will throw off the analysis.
2438 If we have debug info ( line-number info, in particular ) we simply skip
2439 the code associated with the first function line effectively skipping
2440 the prologue code. It works even in cases like
2443 { int local_var = 1;
2447 because, for this source code, both Xtensa compilers will generate two
2448 separate entries ( with the same line number ) in dwarf line-number
2449 section to make sure there is a boundary between the prologue code and
2450 the rest of the function.
2452 If there is no debug info, we need to analyze the code. */
2454 /* #define DONT_SKIP_PROLOGUE */
2457 xtensa_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
2459 struct symtab_and_line prologue_sal
;
2462 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc
);
2464 #if DONT_SKIP_PROLOGUE
2468 /* Try to find first body line from debug info. */
2470 prologue_sal
= find_pc_line (start_pc
, 0);
2471 if (prologue_sal
.line
!= 0) /* Found debug info. */
2473 /* In Call0, it is possible to have a function with only one instruction
2474 ('ret') resulting from a 1-line optimized function that does nothing.
2475 In that case, prologue_sal.end may actually point to the start of the
2476 next function in the text section, causing a breakpoint to be set at
2477 the wrong place. Check if the end address is in a different function,
2478 and if so return the start PC. We know we have symbol info. */
2482 find_pc_partial_function (prologue_sal
.end
, NULL
, &end_func
, NULL
);
2483 if (end_func
!= start_pc
)
2486 return prologue_sal
.end
;
2489 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
2490 body_pc
= call0_analyze_prologue(start_pc
, 0, 0, NULL
, NULL
);
2491 return body_pc
!= 0 ? body_pc
: start_pc
;
2494 /* Verify the current configuration. */
2496 xtensa_verify_config (struct gdbarch
*gdbarch
)
2498 struct ui_file
*log
;
2499 struct cleanup
*cleanups
;
2500 struct gdbarch_tdep
*tdep
;
2504 tdep
= gdbarch_tdep (gdbarch
);
2505 log
= mem_fileopen ();
2506 cleanups
= make_cleanup_ui_file_delete (log
);
2508 /* Verify that we got a reasonable number of AREGS. */
2509 if ((tdep
->num_aregs
& -tdep
->num_aregs
) != tdep
->num_aregs
)
2510 fprintf_unfiltered (log
, _("\
2511 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
2514 /* Verify that certain registers exist. */
2516 if (tdep
->pc_regnum
== -1)
2517 fprintf_unfiltered (log
, _("\n\tpc_regnum: No PC register"));
2518 if (tdep
->isa_use_exceptions
&& tdep
->ps_regnum
== -1)
2519 fprintf_unfiltered (log
, _("\n\tps_regnum: No PS register"));
2521 if (tdep
->isa_use_windowed_registers
)
2523 if (tdep
->wb_regnum
== -1)
2524 fprintf_unfiltered (log
, _("\n\twb_regnum: No WB register"));
2525 if (tdep
->ws_regnum
== -1)
2526 fprintf_unfiltered (log
, _("\n\tws_regnum: No WS register"));
2527 if (tdep
->ar_base
== -1)
2528 fprintf_unfiltered (log
, _("\n\tar_base: No AR registers"));
2531 if (tdep
->a0_base
== -1)
2532 fprintf_unfiltered (log
, _("\n\ta0_base: No Ax registers"));
2534 buf
= ui_file_xstrdup (log
, &dummy
);
2535 make_cleanup (xfree
, buf
);
2536 if (strlen (buf
) > 0)
2537 internal_error (__FILE__
, __LINE__
,
2538 _("the following are invalid: %s"), buf
);
2539 do_cleanups (cleanups
);
2543 /* Derive specific register numbers from the array of registers. */
2546 xtensa_derive_tdep (struct gdbarch_tdep
*tdep
)
2548 xtensa_register_t
* rmap
;
2549 int n
, max_size
= 4;
2552 tdep
->num_nopriv_regs
= 0;
2554 /* Special registers 0..255 (core). */
2555 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
2557 for (rmap
= tdep
->regmap
, n
= 0; rmap
->target_number
!= -1; n
++, rmap
++)
2559 if (rmap
->target_number
== 0x0020)
2560 tdep
->pc_regnum
= n
;
2561 else if (rmap
->target_number
== 0x0100)
2563 else if (rmap
->target_number
== 0x0000)
2565 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(72))
2566 tdep
->wb_regnum
= n
;
2567 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(73))
2568 tdep
->ws_regnum
= n
;
2569 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(233))
2570 tdep
->debugcause_regnum
= n
;
2571 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(232))
2572 tdep
->exccause_regnum
= n
;
2573 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(238))
2574 tdep
->excvaddr_regnum
= n
;
2575 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(0))
2576 tdep
->lbeg_regnum
= n
;
2577 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(1))
2578 tdep
->lend_regnum
= n
;
2579 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(2))
2580 tdep
->lcount_regnum
= n
;
2581 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(3))
2582 tdep
->sar_regnum
= n
;
2583 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(5))
2584 tdep
->litbase_regnum
= n
;
2585 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(230))
2586 tdep
->ps_regnum
= n
;
2588 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(226))
2589 tdep
->interrupt_regnum
= n
;
2590 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(227))
2591 tdep
->interrupt2_regnum
= n
;
2592 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(224))
2593 tdep
->cpenable_regnum
= n
;
2596 if (rmap
->byte_size
> max_size
)
2597 max_size
= rmap
->byte_size
;
2598 if (rmap
->mask
!= 0 && tdep
->num_regs
== 0)
2600 /* Find out out how to deal with priveleged registers.
2602 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
2603 && tdep->num_nopriv_regs == 0)
2604 tdep->num_nopriv_regs = n;
2606 if ((rmap
->flags
& XTENSA_REGISTER_FLAGS_PRIVILEGED
) != 0
2607 && tdep
->num_regs
== 0)
2611 /* Number of pseudo registers. */
2612 tdep
->num_pseudo_regs
= n
- tdep
->num_regs
;
2614 /* Empirically determined maximum sizes. */
2615 tdep
->max_register_raw_size
= max_size
;
2616 tdep
->max_register_virtual_size
= max_size
;
2619 /* Module "constructor" function. */
2621 extern struct gdbarch_tdep xtensa_tdep
;
2623 static struct gdbarch
*
2624 xtensa_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2626 struct gdbarch_tdep
*tdep
;
2627 struct gdbarch
*gdbarch
;
2628 struct xtensa_abi_handler
*abi_handler
;
2630 DEBUGTRACE ("gdbarch_init()\n");
2632 /* We have to set the byte order before we call gdbarch_alloc. */
2633 info
.byte_order
= XCHAL_HAVE_BE
? BFD_ENDIAN_BIG
: BFD_ENDIAN_LITTLE
;
2635 tdep
= &xtensa_tdep
;
2636 gdbarch
= gdbarch_alloc (&info
, tdep
);
2637 xtensa_derive_tdep (tdep
);
2639 /* Verify our configuration. */
2640 xtensa_verify_config (gdbarch
);
2642 /* Pseudo-Register read/write. */
2643 set_gdbarch_pseudo_register_read (gdbarch
, xtensa_pseudo_register_read
);
2644 set_gdbarch_pseudo_register_write (gdbarch
, xtensa_pseudo_register_write
);
2646 /* Set target information. */
2647 set_gdbarch_num_regs (gdbarch
, tdep
->num_regs
);
2648 set_gdbarch_num_pseudo_regs (gdbarch
, tdep
->num_pseudo_regs
);
2649 set_gdbarch_sp_regnum (gdbarch
, tdep
->a0_base
+ 1);
2650 set_gdbarch_pc_regnum (gdbarch
, tdep
->pc_regnum
);
2651 set_gdbarch_ps_regnum (gdbarch
, tdep
->ps_regnum
);
2653 /* Renumber registers for known formats (stab, dwarf, and dwarf2). */
2654 set_gdbarch_stab_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
2655 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
2656 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
2658 /* We provide our own function to get register information. */
2659 set_gdbarch_register_name (gdbarch
, xtensa_register_name
);
2660 set_gdbarch_register_type (gdbarch
, xtensa_register_type
);
2662 /* To call functions from GDB using dummy frame */
2663 set_gdbarch_push_dummy_call (gdbarch
, xtensa_push_dummy_call
);
2665 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2667 set_gdbarch_return_value (gdbarch
, xtensa_return_value
);
2669 /* Advance PC across any prologue instructions to reach "real" code. */
2670 set_gdbarch_skip_prologue (gdbarch
, xtensa_skip_prologue
);
2672 /* Stack grows downward. */
2673 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2675 /* Set breakpoints. */
2676 set_gdbarch_breakpoint_from_pc (gdbarch
, xtensa_breakpoint_from_pc
);
2678 /* After breakpoint instruction or illegal instruction, pc still
2679 points at break instruction, so don't decrement. */
2680 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
2682 /* We don't skip args. */
2683 set_gdbarch_frame_args_skip (gdbarch
, 0);
2685 set_gdbarch_unwind_pc (gdbarch
, xtensa_unwind_pc
);
2687 set_gdbarch_frame_align (gdbarch
, xtensa_frame_align
);
2689 set_gdbarch_dummy_id (gdbarch
, xtensa_dummy_id
);
2691 /* Frame handling. */
2692 frame_base_set_default (gdbarch
, &xtensa_frame_base
);
2693 frame_unwind_append_unwinder (gdbarch
, &xtensa_unwind
);
2694 dwarf2_append_unwinders (gdbarch
);
2696 set_gdbarch_print_insn (gdbarch
, print_insn_xtensa
);
2698 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
2700 xtensa_add_reggroups (gdbarch
);
2701 set_gdbarch_register_reggroup_p (gdbarch
, xtensa_register_reggroup_p
);
2703 set_gdbarch_regset_from_core_section (gdbarch
,
2704 xtensa_regset_from_core_section
);
2706 set_solib_svr4_fetch_link_map_offsets
2707 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
2713 xtensa_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
2715 error (_("xtensa_dump_tdep(): not implemented"));
2719 _initialize_xtensa_tdep (void)
2721 struct cmd_list_element
*c
;
2723 gdbarch_register (bfd_arch_xtensa
, xtensa_gdbarch_init
, xtensa_dump_tdep
);
2724 xtensa_init_reggroups ();
2726 add_setshow_zinteger_cmd ("xtensa",
2728 &xtensa_debug_level
, _("\
2729 Set Xtensa debugging."), _("\
2730 Show Xtensa debugging."), _("\
2731 When non-zero, Xtensa-specific debugging is enabled. \
2732 Can be 1, 2, 3, or 4 indicating the level of debugging."),
2735 &setdebuglist
, &showdebuglist
);