1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "solib-svr4.h"
32 #include "floatformat.h"
34 #include "reggroups.h"
37 #include "dummy-frame.h"
39 #include "dwarf2-frame.h"
40 #include "dwarf2loc.h"
42 #include "frame-base.h"
43 #include "frame-unwind.h"
45 #include "arch-utils.h"
52 #include "gdb_assert.h"
54 #include "xtensa-isa.h"
55 #include "xtensa-tdep.h"
56 #include "xtensa-config.h"
59 static int xtensa_debug_level
= 0;
61 #define DEBUGWARN(args...) \
62 if (xtensa_debug_level > 0) \
63 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
65 #define DEBUGINFO(args...) \
66 if (xtensa_debug_level > 1) \
67 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
69 #define DEBUGTRACE(args...) \
70 if (xtensa_debug_level > 2) \
71 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
73 #define DEBUGVERB(args...) \
74 if (xtensa_debug_level > 3) \
75 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
78 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
79 #define SP_ALIGNMENT 16
82 /* On Windowed ABI, we use a6 through a11 for passing arguments
83 to a function called by GDB because CALL4 is used. */
84 #define ARGS_NUM_REGS 6
85 #define REGISTER_SIZE 4
88 /* Extract the call size from the return address or PS register. */
89 #define PS_CALLINC_SHIFT 16
90 #define PS_CALLINC_MASK 0x00030000
91 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
92 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
94 /* ABI-independent macros. */
95 #define ARG_NOF(gdbarch) \
96 (gdbarch_tdep (gdbarch)->call_abi \
97 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
98 #define ARG_1ST(gdbarch) \
99 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
100 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
101 : (gdbarch_tdep (gdbarch)->a0_base + 6))
103 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
104 indicates that the instruction is an ENTRY instruction. */
106 #define XTENSA_IS_ENTRY(gdbarch, op1) \
107 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
108 ? ((op1) == 0x6c) : ((op1) == 0x36))
110 #define XTENSA_ENTRY_LENGTH 3
112 /* windowing_enabled() returns true, if windowing is enabled.
113 WOE must be set to 1; EXCM to 0.
114 Note: We assume that EXCM is always 0 for XEA1. */
116 #define PS_WOE (1<<18)
117 #define PS_EXC (1<<4)
119 /* Convert a live A-register number to the corresponding AR-register
122 arreg_number (struct gdbarch
*gdbarch
, int a_regnum
, ULONGEST wb
)
124 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
127 arreg
= a_regnum
- tdep
->a0_base
;
128 arreg
+= (wb
& ((tdep
->num_aregs
- 1) >> 2)) << WB_SHIFT
;
129 arreg
&= tdep
->num_aregs
- 1;
131 return arreg
+ tdep
->ar_base
;
134 /* Convert a live AR-register number to the corresponding A-register order
135 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
137 areg_number (struct gdbarch
*gdbarch
, int ar_regnum
, unsigned int wb
)
139 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
142 areg
= ar_regnum
- tdep
->ar_base
;
143 if (areg
< 0 || areg
>= tdep
->num_aregs
)
145 areg
= (areg
- wb
* 4) & (tdep
->num_aregs
- 1);
146 return (areg
> 15) ? -1 : areg
;
150 windowing_enabled (CORE_ADDR ps
)
152 return ((ps
& PS_EXC
) == 0 && (ps
& PS_WOE
) != 0);
155 /* Return the window size of the previous call to the function from which we
158 This function is used to extract the return value after a called function
159 has returned to the caller. On Xtensa, the register that holds the return
160 value (from the perspective of the caller) depends on what call
161 instruction was used. For now, we are assuming that the call instruction
162 precedes the current address, so we simply analyze the call instruction.
163 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
164 method to call the inferior function. */
167 extract_call_winsize (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
169 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
174 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc
);
176 /* Read the previous instruction (should be a call[x]{4|8|12}. */
177 read_memory (pc
-3, buf
, 3);
178 insn
= extract_unsigned_integer (buf
, 3, byte_order
);
180 /* Decode call instruction:
182 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
183 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
185 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
186 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
188 if (byte_order
== BFD_ENDIAN_LITTLE
)
190 if (((insn
& 0xf) == 0x5) || ((insn
& 0xcf) == 0xc0))
191 winsize
= (insn
& 0x30) >> 2; /* 0, 4, 8, 12. */
195 if (((insn
>> 20) == 0x5) || (((insn
>> 16) & 0xf3) == 0x03))
196 winsize
= (insn
>> 16) & 0xc; /* 0, 4, 8, 12. */
202 /* REGISTER INFORMATION */
204 /* Returns the name of a register. */
206 xtensa_register_name (struct gdbarch
*gdbarch
, int regnum
)
208 /* Return the name stored in the register map. */
209 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
)
210 + gdbarch_num_pseudo_regs (gdbarch
))
211 return gdbarch_tdep (gdbarch
)->regmap
[regnum
].name
;
213 internal_error (__FILE__
, __LINE__
, _("invalid register %d"), regnum
);
217 /* Return the type of a register. Create a new type, if necessary. */
220 xtensa_register_type (struct gdbarch
*gdbarch
, int regnum
)
222 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
224 /* Return signed integer for ARx and Ax registers. */
225 if ((regnum
>= tdep
->ar_base
226 && regnum
< tdep
->ar_base
+ tdep
->num_aregs
)
227 || (regnum
>= tdep
->a0_base
228 && regnum
< tdep
->a0_base
+ 16))
229 return builtin_type (gdbarch
)->builtin_int
;
231 if (regnum
== gdbarch_pc_regnum (gdbarch
)
232 || regnum
== tdep
->a0_base
+ 1)
233 return builtin_type (gdbarch
)->builtin_data_ptr
;
235 /* Return the stored type for all other registers. */
236 else if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
)
237 + gdbarch_num_pseudo_regs (gdbarch
))
239 xtensa_register_t
* reg
= &tdep
->regmap
[regnum
];
241 /* Set ctype for this register (only the first time). */
245 struct ctype_cache
*tp
;
246 int size
= reg
->byte_size
;
248 /* We always use the memory representation,
249 even if the register width is smaller. */
253 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint8
;
257 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint16
;
261 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint32
;
265 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint64
;
269 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint128
;
273 for (tp
= tdep
->type_entries
; tp
!= NULL
; tp
= tp
->next
)
274 if (tp
->size
== size
)
279 char *name
= xmalloc (16);
280 tp
= xmalloc (sizeof (struct ctype_cache
));
281 tp
->next
= tdep
->type_entries
;
282 tdep
->type_entries
= tp
;
285 sprintf (name
, "int%d", size
* 8);
287 = arch_integer_type (gdbarch
, size
* 8, 1, xstrdup (name
));
290 reg
->ctype
= tp
->virtual_type
;
296 internal_error (__FILE__
, __LINE__
, _("invalid register number %d"), regnum
);
301 /* Return the 'local' register number for stubs, dwarf2, etc.
302 The debugging information enumerates registers starting from 0 for A0
303 to n for An. So, we only have to add the base number for A0. */
306 xtensa_reg_to_regnum (struct gdbarch
*gdbarch
, int regnum
)
310 if (regnum
>= 0 && regnum
< 16)
311 return gdbarch_tdep (gdbarch
)->a0_base
+ regnum
;
314 i
< gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
316 if (regnum
== gdbarch_tdep (gdbarch
)->regmap
[i
].target_number
)
319 internal_error (__FILE__
, __LINE__
,
320 _("invalid dwarf/stabs register number %d"), regnum
);
325 /* Write the bits of a masked register to the various registers.
326 Only the masked areas of these registers are modified; the other
327 fields are untouched. The size of masked registers is always less
328 than or equal to 32 bits. */
331 xtensa_register_write_masked (struct regcache
*regcache
,
332 xtensa_register_t
*reg
, const gdb_byte
*buffer
)
334 unsigned int value
[(MAX_REGISTER_SIZE
+ 3) / 4];
335 const xtensa_mask_t
*mask
= reg
->mask
;
337 int shift
= 0; /* Shift for next mask (mod 32). */
338 int start
, size
; /* Start bit and size of current mask. */
340 unsigned int *ptr
= value
;
341 unsigned int regval
, m
, mem
= 0;
343 int bytesize
= reg
->byte_size
;
344 int bitsize
= bytesize
* 8;
347 DEBUGTRACE ("xtensa_register_write_masked ()\n");
349 /* Copy the masked register to host byte-order. */
350 if (gdbarch_byte_order (get_regcache_arch (regcache
)) == BFD_ENDIAN_BIG
)
351 for (i
= 0; i
< bytesize
; i
++)
354 mem
|= (buffer
[bytesize
- i
- 1] << 24);
359 for (i
= 0; i
< bytesize
; i
++)
362 mem
|= (buffer
[i
] << 24);
367 /* We might have to shift the final value:
368 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
369 bytesize & 3 == x -> shift (4-x) * 8. */
371 *ptr
= mem
>> (((0 - bytesize
) & 3) * 8);
375 /* Write the bits to the masked areas of the other registers. */
376 for (i
= 0; i
< mask
->count
; i
++)
378 start
= mask
->mask
[i
].bit_start
;
379 size
= mask
->mask
[i
].bit_size
;
380 regval
= mem
>> shift
;
382 if ((shift
+= size
) > bitsize
)
383 error (_("size of all masks is larger than the register"));
392 regval
|= mem
<< (size
- shift
);
395 /* Make sure we have a valid register. */
396 r
= mask
->mask
[i
].reg_num
;
397 if (r
>= 0 && size
> 0)
399 /* Don't overwrite the unmasked areas. */
401 regcache_cooked_read_unsigned (regcache
, r
, &old_val
);
402 m
= 0xffffffff >> (32 - size
) << start
;
404 regval
= (regval
& m
) | (old_val
& ~m
);
405 regcache_cooked_write_unsigned (regcache
, r
, regval
);
411 /* Read a tie state or mapped registers. Read the masked areas
412 of the registers and assemble them into a single value. */
415 xtensa_register_read_masked (struct regcache
*regcache
,
416 xtensa_register_t
*reg
, gdb_byte
*buffer
)
418 unsigned int value
[(MAX_REGISTER_SIZE
+ 3) / 4];
419 const xtensa_mask_t
*mask
= reg
->mask
;
424 unsigned int *ptr
= value
;
425 unsigned int regval
, mem
= 0;
427 int bytesize
= reg
->byte_size
;
428 int bitsize
= bytesize
* 8;
431 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
432 reg
->name
== 0 ? "" : reg
->name
);
434 /* Assemble the register from the masked areas of other registers. */
435 for (i
= 0; i
< mask
->count
; i
++)
437 int r
= mask
->mask
[i
].reg_num
;
441 regcache_cooked_read_unsigned (regcache
, r
, &val
);
442 regval
= (unsigned int) val
;
447 start
= mask
->mask
[i
].bit_start
;
448 size
= mask
->mask
[i
].bit_size
;
453 regval
&= (0xffffffff >> (32 - size
));
455 mem
|= regval
<< shift
;
457 if ((shift
+= size
) > bitsize
)
458 error (_("size of all masks is larger than the register"));
469 mem
= regval
>> (size
- shift
);
476 /* Copy value to target byte order. */
480 if (gdbarch_byte_order (get_regcache_arch (regcache
)) == BFD_ENDIAN_BIG
)
481 for (i
= 0; i
< bytesize
; i
++)
485 buffer
[bytesize
- i
- 1] = mem
& 0xff;
489 for (i
= 0; i
< bytesize
; i
++)
493 buffer
[i
] = mem
& 0xff;
499 /* Read pseudo registers. */
502 xtensa_pseudo_register_read (struct gdbarch
*gdbarch
,
503 struct regcache
*regcache
,
507 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
509 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
510 regnum
, xtensa_register_name (gdbarch
, regnum
));
512 if (regnum
== gdbarch_num_regs (gdbarch
)
513 + gdbarch_num_pseudo_regs (gdbarch
) - 1)
514 regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ 1;
516 /* Read aliases a0..a15, if this is a Windowed ABI. */
517 if (gdbarch_tdep (gdbarch
)->isa_use_windowed_registers
518 && (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
)
519 && (regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15))
521 gdb_byte
*buf
= (gdb_byte
*) alloca (MAX_REGISTER_SIZE
);
523 regcache_raw_read (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, buf
);
524 regnum
= arreg_number (gdbarch
, regnum
,
525 extract_unsigned_integer (buf
, 4, byte_order
));
528 /* We can always read non-pseudo registers. */
529 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
530 regcache_raw_read (regcache
, regnum
, buffer
);
533 /* We have to find out how to deal with priveleged registers.
534 Let's treat them as pseudo-registers, but we cannot read/write them. */
536 else if (regnum
< gdbarch_tdep (gdbarch
)->a0_base
)
538 buffer
[0] = (gdb_byte
)0;
539 buffer
[1] = (gdb_byte
)0;
540 buffer
[2] = (gdb_byte
)0;
541 buffer
[3] = (gdb_byte
)0;
543 /* Pseudo registers. */
545 && regnum
< gdbarch_num_regs (gdbarch
)
546 + gdbarch_num_pseudo_regs (gdbarch
))
548 xtensa_register_t
*reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
549 xtensa_register_type_t type
= reg
->type
;
550 int flags
= gdbarch_tdep (gdbarch
)->target_flags
;
552 /* We cannot read Unknown or Unmapped registers. */
553 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
555 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
557 warning (_("cannot read register %s"),
558 xtensa_register_name (gdbarch
, regnum
));
563 /* Some targets cannot read TIE register files. */
564 else if (type
== xtRegisterTypeTieRegfile
)
566 /* Use 'fetch' to get register? */
567 if (flags
& xtTargetFlagsUseFetchStore
)
569 warning (_("cannot read register"));
573 /* On some targets (esp. simulators), we can always read the reg. */
574 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
576 warning (_("cannot read register"));
581 /* We can always read mapped registers. */
582 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
584 xtensa_register_read_masked (regcache
, reg
, buffer
);
588 /* Assume that we can read the register. */
589 regcache_raw_read (regcache
, regnum
, buffer
);
592 internal_error (__FILE__
, __LINE__
,
593 _("invalid register number %d"), regnum
);
597 /* Write pseudo registers. */
600 xtensa_pseudo_register_write (struct gdbarch
*gdbarch
,
601 struct regcache
*regcache
,
603 const gdb_byte
*buffer
)
605 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
607 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
608 regnum
, xtensa_register_name (gdbarch
, regnum
));
610 if (regnum
== gdbarch_num_regs (gdbarch
)
611 + gdbarch_num_pseudo_regs (gdbarch
) -1)
612 regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ 1;
614 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
615 if (gdbarch_tdep (gdbarch
)->isa_use_windowed_registers
616 && (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
)
617 && (regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15))
619 gdb_byte
*buf
= (gdb_byte
*) alloca (MAX_REGISTER_SIZE
);
622 regcache_raw_read (regcache
,
623 gdbarch_tdep (gdbarch
)->wb_regnum
, buf
);
624 regnum
= arreg_number (gdbarch
, regnum
,
625 extract_unsigned_integer (buf
, 4, byte_order
));
628 /* We can always write 'core' registers.
629 Note: We might have converted Ax->ARy. */
630 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
631 regcache_raw_write (regcache
, regnum
, buffer
);
633 /* We have to find out how to deal with priveleged registers.
634 Let's treat them as pseudo-registers, but we cannot read/write them. */
636 else if (regnum
< gdbarch_tdep (gdbarch
)->a0_base
)
640 /* Pseudo registers. */
642 && regnum
< gdbarch_num_regs (gdbarch
)
643 + gdbarch_num_pseudo_regs (gdbarch
))
645 xtensa_register_t
*reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
646 xtensa_register_type_t type
= reg
->type
;
647 int flags
= gdbarch_tdep (gdbarch
)->target_flags
;
649 /* On most targets, we cannot write registers
650 of type "Unknown" or "Unmapped". */
651 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
653 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
655 warning (_("cannot write register %s"),
656 xtensa_register_name (gdbarch
, regnum
));
661 /* Some targets cannot read TIE register files. */
662 else if (type
== xtRegisterTypeTieRegfile
)
664 /* Use 'store' to get register? */
665 if (flags
& xtTargetFlagsUseFetchStore
)
667 warning (_("cannot write register"));
671 /* On some targets (esp. simulators), we can always write
673 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
675 warning (_("cannot write register"));
680 /* We can always write mapped registers. */
681 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
683 xtensa_register_write_masked (regcache
, reg
, buffer
);
687 /* Assume that we can write the register. */
688 regcache_raw_write (regcache
, regnum
, buffer
);
691 internal_error (__FILE__
, __LINE__
,
692 _("invalid register number %d"), regnum
);
695 static struct reggroup
*xtensa_ar_reggroup
;
696 static struct reggroup
*xtensa_user_reggroup
;
697 static struct reggroup
*xtensa_vectra_reggroup
;
698 static struct reggroup
*xtensa_cp
[XTENSA_MAX_COPROCESSOR
];
701 xtensa_init_reggroups (void)
703 xtensa_ar_reggroup
= reggroup_new ("ar", USER_REGGROUP
);
704 xtensa_user_reggroup
= reggroup_new ("user", USER_REGGROUP
);
705 xtensa_vectra_reggroup
= reggroup_new ("vectra", USER_REGGROUP
);
707 xtensa_cp
[0] = reggroup_new ("cp0", USER_REGGROUP
);
708 xtensa_cp
[1] = reggroup_new ("cp1", USER_REGGROUP
);
709 xtensa_cp
[2] = reggroup_new ("cp2", USER_REGGROUP
);
710 xtensa_cp
[3] = reggroup_new ("cp3", USER_REGGROUP
);
711 xtensa_cp
[4] = reggroup_new ("cp4", USER_REGGROUP
);
712 xtensa_cp
[5] = reggroup_new ("cp5", USER_REGGROUP
);
713 xtensa_cp
[6] = reggroup_new ("cp6", USER_REGGROUP
);
714 xtensa_cp
[7] = reggroup_new ("cp7", USER_REGGROUP
);
718 xtensa_add_reggroups (struct gdbarch
*gdbarch
)
722 /* Predefined groups. */
723 reggroup_add (gdbarch
, all_reggroup
);
724 reggroup_add (gdbarch
, save_reggroup
);
725 reggroup_add (gdbarch
, restore_reggroup
);
726 reggroup_add (gdbarch
, system_reggroup
);
727 reggroup_add (gdbarch
, vector_reggroup
);
728 reggroup_add (gdbarch
, general_reggroup
);
729 reggroup_add (gdbarch
, float_reggroup
);
731 /* Xtensa-specific groups. */
732 reggroup_add (gdbarch
, xtensa_ar_reggroup
);
733 reggroup_add (gdbarch
, xtensa_user_reggroup
);
734 reggroup_add (gdbarch
, xtensa_vectra_reggroup
);
736 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
737 reggroup_add (gdbarch
, xtensa_cp
[i
]);
741 xtensa_coprocessor_register_group (struct reggroup
*group
)
745 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
746 if (group
== xtensa_cp
[i
])
752 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
753 | XTENSA_REGISTER_FLAGS_WRITABLE \
754 | XTENSA_REGISTER_FLAGS_VOLATILE)
756 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
757 | XTENSA_REGISTER_FLAGS_WRITABLE)
760 xtensa_register_reggroup_p (struct gdbarch
*gdbarch
,
762 struct reggroup
*group
)
764 xtensa_register_t
* reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
765 xtensa_register_type_t type
= reg
->type
;
766 xtensa_register_group_t rg
= reg
->group
;
769 /* First, skip registers that are not visible to this target
770 (unknown and unmapped registers when not using ISS). */
772 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
774 if (group
== all_reggroup
)
776 if (group
== xtensa_ar_reggroup
)
777 return rg
& xtRegisterGroupAddrReg
;
778 if (group
== xtensa_user_reggroup
)
779 return rg
& xtRegisterGroupUser
;
780 if (group
== float_reggroup
)
781 return rg
& xtRegisterGroupFloat
;
782 if (group
== general_reggroup
)
783 return rg
& xtRegisterGroupGeneral
;
784 if (group
== float_reggroup
)
785 return rg
& xtRegisterGroupFloat
;
786 if (group
== system_reggroup
)
787 return rg
& xtRegisterGroupState
;
788 if (group
== vector_reggroup
|| group
== xtensa_vectra_reggroup
)
789 return rg
& xtRegisterGroupVectra
;
790 if (group
== save_reggroup
|| group
== restore_reggroup
)
791 return (regnum
< gdbarch_num_regs (gdbarch
)
792 && (reg
->flags
& SAVE_REST_FLAGS
) == SAVE_REST_VALID
);
793 if ((cp_number
= xtensa_coprocessor_register_group (group
)) >= 0)
794 return rg
& (xtRegisterGroupCP0
<< cp_number
);
800 /* Supply register REGNUM from the buffer specified by GREGS and LEN
801 in the general-purpose register set REGSET to register cache
802 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
805 xtensa_supply_gregset (const struct regset
*regset
,
811 const xtensa_elf_gregset_t
*regs
= gregs
;
812 struct gdbarch
*gdbarch
= get_regcache_arch (rc
);
815 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum
);
817 if (regnum
== gdbarch_pc_regnum (gdbarch
) || regnum
== -1)
818 regcache_raw_supply (rc
, gdbarch_pc_regnum (gdbarch
), (char *) ®s
->pc
);
819 if (regnum
== gdbarch_ps_regnum (gdbarch
) || regnum
== -1)
820 regcache_raw_supply (rc
, gdbarch_ps_regnum (gdbarch
), (char *) ®s
->ps
);
821 if (regnum
== gdbarch_tdep (gdbarch
)->wb_regnum
|| regnum
== -1)
822 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->wb_regnum
,
823 (char *) ®s
->windowbase
);
824 if (regnum
== gdbarch_tdep (gdbarch
)->ws_regnum
|| regnum
== -1)
825 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->ws_regnum
,
826 (char *) ®s
->windowstart
);
827 if (regnum
== gdbarch_tdep (gdbarch
)->lbeg_regnum
|| regnum
== -1)
828 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lbeg_regnum
,
829 (char *) ®s
->lbeg
);
830 if (regnum
== gdbarch_tdep (gdbarch
)->lend_regnum
|| regnum
== -1)
831 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lend_regnum
,
832 (char *) ®s
->lend
);
833 if (regnum
== gdbarch_tdep (gdbarch
)->lcount_regnum
|| regnum
== -1)
834 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lcount_regnum
,
835 (char *) ®s
->lcount
);
836 if (regnum
== gdbarch_tdep (gdbarch
)->sar_regnum
|| regnum
== -1)
837 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->sar_regnum
,
838 (char *) ®s
->sar
);
839 if (regnum
>=gdbarch_tdep (gdbarch
)->ar_base
840 && regnum
< gdbarch_tdep (gdbarch
)->ar_base
841 + gdbarch_tdep (gdbarch
)->num_aregs
)
842 regcache_raw_supply (rc
, regnum
,
843 (char *) ®s
->ar
[regnum
- gdbarch_tdep
844 (gdbarch
)->ar_base
]);
845 else if (regnum
== -1)
847 for (i
= 0; i
< gdbarch_tdep (gdbarch
)->num_aregs
; ++i
)
848 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->ar_base
+ i
,
849 (char *) ®s
->ar
[i
]);
854 /* Xtensa register set. */
860 xtensa_supply_gregset
864 /* Return the appropriate register set for the core
865 section identified by SECT_NAME and SECT_SIZE. */
867 static const struct regset
*
868 xtensa_regset_from_core_section (struct gdbarch
*core_arch
,
869 const char *sect_name
,
872 DEBUGTRACE ("xtensa_regset_from_core_section "
873 "(..., sect_name==\"%s\", sect_size==%x)\n",
874 sect_name
, (unsigned int) sect_size
);
876 if (strcmp (sect_name
, ".reg") == 0
877 && sect_size
>= sizeof(xtensa_elf_gregset_t
))
878 return &xtensa_gregset
;
884 /* Handling frames. */
886 /* Number of registers to save in case of Windowed ABI. */
887 #define XTENSA_NUM_SAVED_AREGS 12
889 /* Frame cache part for Windowed ABI. */
890 typedef struct xtensa_windowed_frame_cache
892 int wb
; /* WINDOWBASE of the previous frame. */
893 int callsize
; /* Call size of this frame. */
894 int ws
; /* WINDOWSTART of the previous frame. It
895 keeps track of life windows only. If there
896 is no bit set for the window, that means it
897 had been already spilled because of window
900 /* Spilled A-registers from the previous frame.
901 AREGS[i] == -1, if corresponding AR is alive. */
902 CORE_ADDR aregs
[XTENSA_NUM_SAVED_AREGS
];
903 } xtensa_windowed_frame_cache_t
;
905 /* Call0 ABI Definitions. */
907 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue
909 #define C0_NREGS 16 /* Number of A-registers to track. */
910 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
911 #define C0_SP 1 /* Register used as SP. */
912 #define C0_FP 15 /* Register used as FP. */
913 #define C0_RA 0 /* Register used as return address. */
914 #define C0_ARGS 2 /* Register used as first arg/retval. */
915 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
917 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
918 A-register where the current content of the reg came from (in terms
919 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
920 mean that the orignal content of the register was saved to the stack.
921 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
922 know where SP will end up until the entire prologue has been analyzed. */
924 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
925 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
926 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
928 extern xtensa_isa xtensa_default_isa
;
930 typedef struct xtensa_c0reg
932 int fr_reg
; /* original register from which register content
933 is derived, or C0_CONST, or C0_INEXP. */
934 int fr_ofs
; /* constant offset from reg, or immediate value. */
935 int to_stk
; /* offset from original SP to register (4-byte
936 aligned), or C0_NOSTK if register has not
941 /* Frame cache part for Call0 ABI. */
942 typedef struct xtensa_call0_frame_cache
944 int c0_frmsz
; /* Stack frame size. */
945 int c0_hasfp
; /* Current frame uses frame
947 int fp_regnum
; /* A-register used as FP. */
948 int c0_fp
; /* Actual value of frame pointer. */
949 xtensa_c0reg_t c0_rt
[C0_NREGS
]; /* Register tracking information. */
950 } xtensa_call0_frame_cache_t
;
952 typedef struct xtensa_frame_cache
954 CORE_ADDR base
; /* Stack pointer of this frame. */
955 CORE_ADDR pc
; /* PC at the entry point to the function. */
956 CORE_ADDR ra
; /* The raw return address (without CALLINC). */
957 CORE_ADDR ps
; /* The PS register of this frame. */
958 CORE_ADDR prev_sp
; /* Stack Pointer of the previous frame. */
959 int call0
; /* It's a call0 framework (else windowed). */
962 xtensa_windowed_frame_cache_t wd
; /* call0 == false. */
963 xtensa_call0_frame_cache_t c0
; /* call0 == true. */
965 } xtensa_frame_cache_t
;
968 static struct xtensa_frame_cache
*
969 xtensa_alloc_frame_cache (int windowed
)
971 xtensa_frame_cache_t
*cache
;
974 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
976 cache
= FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t
);
983 cache
->call0
= !windowed
;
986 cache
->c0
.c0_frmsz
= -1;
987 cache
->c0
.c0_hasfp
= 0;
988 cache
->c0
.fp_regnum
= -1;
989 cache
->c0
.c0_fp
= -1;
991 for (i
= 0; i
< C0_NREGS
; i
++)
993 cache
->c0
.c0_rt
[i
].fr_reg
= i
;
994 cache
->c0
.c0_rt
[i
].fr_ofs
= 0;
995 cache
->c0
.c0_rt
[i
].to_stk
= C0_NOSTK
;
1002 cache
->wd
.callsize
= -1;
1004 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
1005 cache
->wd
.aregs
[i
] = -1;
1012 xtensa_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
1014 return address
& ~15;
1019 xtensa_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1024 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1025 host_address_to_string (next_frame
));
1027 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1028 pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1030 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc
);
1036 static struct frame_id
1037 xtensa_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1041 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1043 pc
= get_frame_pc (this_frame
);
1044 fp
= get_frame_register_unsigned
1045 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1047 /* Make dummy frame ID unique by adding a constant. */
1048 return frame_id_build (fp
+ SP_ALIGNMENT
, pc
);
1051 /* Returns the best guess about which register is a frame pointer
1052 for the function containing CURRENT_PC. */
1054 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1055 #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1058 xtensa_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
)
1060 #define RETURN_FP goto done
1062 unsigned int fp_regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ 1;
1063 CORE_ADDR start_addr
;
1065 xtensa_insnbuf ins
, slot
;
1066 char ibuf
[XTENSA_ISA_BSZ
];
1067 CORE_ADDR ia
, bt
, ba
;
1069 int ilen
, islots
, is
;
1071 const char *opcname
;
1073 find_pc_partial_function (current_pc
, NULL
, &start_addr
, NULL
);
1074 if (start_addr
== 0)
1077 if (!xtensa_default_isa
)
1078 xtensa_default_isa
= xtensa_isa_init (0, 0);
1079 isa
= xtensa_default_isa
;
1080 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
1081 ins
= xtensa_insnbuf_alloc (isa
);
1082 slot
= xtensa_insnbuf_alloc (isa
);
1085 for (ia
= start_addr
, bt
= ia
; ia
< current_pc
; ia
+= ilen
)
1087 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
1090 bt
= (ba
+ XTENSA_ISA_BSZ
) < current_pc
1091 ? ba
+ XTENSA_ISA_BSZ
: current_pc
;
1092 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0)
1096 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
1097 ifmt
= xtensa_format_decode (isa
, ins
);
1098 if (ifmt
== XTENSA_UNDEFINED
)
1100 ilen
= xtensa_format_length (isa
, ifmt
);
1101 if (ilen
== XTENSA_UNDEFINED
)
1103 islots
= xtensa_format_num_slots (isa
, ifmt
);
1104 if (islots
== XTENSA_UNDEFINED
)
1107 for (is
= 0; is
< islots
; ++is
)
1109 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
1112 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
1113 if (opc
== XTENSA_UNDEFINED
)
1116 opcname
= xtensa_opcode_name (isa
, opc
);
1118 if (strcasecmp (opcname
, "mov.n") == 0
1119 || strcasecmp (opcname
, "or") == 0)
1121 unsigned int register_operand
;
1123 /* Possible candidate for setting frame pointer
1124 from A1. This is what we are looking for. */
1126 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
,
1127 is
, slot
, ®ister_operand
) != 0)
1129 if (xtensa_operand_decode (isa
, opc
, 1, ®ister_operand
) != 0)
1131 if (register_operand
== 1) /* Mov{.n} FP A1. */
1133 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
,
1134 ®ister_operand
) != 0)
1136 if (xtensa_operand_decode (isa
, opc
, 0,
1137 ®ister_operand
) != 0)
1141 = gdbarch_tdep (gdbarch
)->a0_base
+ register_operand
;
1147 /* We have problems decoding the memory. */
1149 || strcasecmp (opcname
, "ill") == 0
1150 || strcasecmp (opcname
, "ill.n") == 0
1151 /* Hit planted breakpoint. */
1152 || strcasecmp (opcname
, "break") == 0
1153 || strcasecmp (opcname
, "break.n") == 0
1154 /* Flow control instructions finish prologue. */
1155 || xtensa_opcode_is_branch (isa
, opc
) > 0
1156 || xtensa_opcode_is_jump (isa
, opc
) > 0
1157 || xtensa_opcode_is_loop (isa
, opc
) > 0
1158 || xtensa_opcode_is_call (isa
, opc
) > 0
1159 || strcasecmp (opcname
, "simcall") == 0
1160 || strcasecmp (opcname
, "syscall") == 0)
1161 /* Can not continue analysis. */
1166 xtensa_insnbuf_free(isa
, slot
);
1167 xtensa_insnbuf_free(isa
, ins
);
1171 /* The key values to identify the frame using "cache" are
1173 cache->base = SP (or best guess about FP) of this frame;
1174 cache->pc = entry-PC (entry point of the frame function);
1175 cache->prev_sp = SP of the previous frame. */
1178 call0_frame_cache (struct frame_info
*this_frame
,
1179 xtensa_frame_cache_t
*cache
,
1180 CORE_ADDR pc
, CORE_ADDR litbase
);
1182 static struct xtensa_frame_cache
*
1183 xtensa_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1185 xtensa_frame_cache_t
*cache
;
1186 CORE_ADDR ra
, wb
, ws
, pc
, sp
, ps
;
1187 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1188 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1189 unsigned int fp_regnum
;
1196 ps
= get_frame_register_unsigned (this_frame
, gdbarch_ps_regnum (gdbarch
));
1197 windowed
= windowing_enabled (ps
);
1199 /* Get pristine xtensa-frame. */
1200 cache
= xtensa_alloc_frame_cache (windowed
);
1201 *this_cache
= cache
;
1203 pc
= get_frame_register_unsigned (this_frame
, gdbarch_pc_regnum (gdbarch
));
1207 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1208 wb
= get_frame_register_unsigned (this_frame
,
1209 gdbarch_tdep (gdbarch
)->wb_regnum
);
1210 ws
= get_frame_register_unsigned (this_frame
,
1211 gdbarch_tdep (gdbarch
)->ws_regnum
);
1213 op1
= read_memory_integer (pc
, 1, byte_order
);
1214 if (XTENSA_IS_ENTRY (gdbarch
, op1
))
1216 int callinc
= CALLINC (ps
);
1217 ra
= get_frame_register_unsigned
1218 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ callinc
* 4);
1220 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1221 cache
->wd
.callsize
= 0;
1224 cache
->prev_sp
= get_frame_register_unsigned
1225 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1227 /* This only can be the outermost frame since we are
1228 just about to execute ENTRY. SP hasn't been set yet.
1229 We can assume any frame size, because it does not
1230 matter, and, let's fake frame base in cache. */
1231 cache
->base
= cache
->prev_sp
+ 16;
1234 cache
->ra
= (cache
->pc
& 0xc0000000) | (ra
& 0x3fffffff);
1235 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1236 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1242 fp_regnum
= xtensa_scan_prologue (gdbarch
, pc
);
1243 ra
= get_frame_register_unsigned (this_frame
,
1244 gdbarch_tdep (gdbarch
)->a0_base
);
1245 cache
->wd
.callsize
= WINSIZE (ra
);
1246 cache
->wd
.wb
= (wb
- cache
->wd
.callsize
/ 4)
1247 & (gdbarch_tdep (gdbarch
)->num_aregs
/ 4 - 1);
1248 cache
->wd
.ws
= ws
& ~(1 << wb
);
1250 cache
->pc
= get_frame_func (this_frame
);
1251 cache
->ra
= (pc
& 0xc0000000) | (ra
& 0x3fffffff);
1252 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1253 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1256 if (cache
->wd
.ws
== 0)
1261 sp
= get_frame_register_unsigned
1262 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1) - 16;
1264 for (i
= 0; i
< 4; i
++, sp
+= 4)
1266 cache
->wd
.aregs
[i
] = sp
;
1269 if (cache
->wd
.callsize
> 4)
1271 /* Set A4...A7/A11. */
1272 /* Get the SP of the frame previous to the previous one.
1273 To achieve this, we have to dereference SP twice. */
1274 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4, byte_order
);
1275 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4, byte_order
);
1276 sp
-= cache
->wd
.callsize
* 4;
1278 for ( i
= 4; i
< cache
->wd
.callsize
; i
++, sp
+= 4)
1280 cache
->wd
.aregs
[i
] = sp
;
1285 if ((cache
->prev_sp
== 0) && ( ra
!= 0 ))
1286 /* If RA is equal to 0 this frame is an outermost frame.
1287 Leave cache->prev_sp unchanged marking the boundary of the
1290 if ((cache
->wd
.ws
& (1 << cache
->wd
.wb
)) == 0)
1292 /* Register window overflow already happened.
1293 We can read caller's SP from the proper spill loction. */
1294 sp
= get_frame_register_unsigned
1295 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1296 cache
->prev_sp
= read_memory_integer (sp
- 12, 4, byte_order
);
1300 /* Read caller's frame SP directly from the previous window. */
1301 int regnum
= arreg_number
1302 (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ 1,
1305 cache
->prev_sp
= get_frame_register_unsigned (this_frame
,
1310 else /* Call0 framework. */
1312 unsigned int litbase_regnum
= gdbarch_tdep (gdbarch
)->litbase_regnum
;
1313 CORE_ADDR litbase
= (litbase_regnum
== -1)
1314 ? 0 : get_frame_register_unsigned (this_frame
, litbase_regnum
);
1316 call0_frame_cache (this_frame
, cache
, pc
, litbase
);
1317 fp_regnum
= cache
->c0
.fp_regnum
;
1320 cache
->base
= get_frame_register_unsigned (this_frame
, fp_regnum
);
1326 xtensa_frame_this_id (struct frame_info
*this_frame
,
1328 struct frame_id
*this_id
)
1330 struct xtensa_frame_cache
*cache
=
1331 xtensa_frame_cache (this_frame
, this_cache
);
1333 if (cache
->prev_sp
== 0)
1336 (*this_id
) = frame_id_build (cache
->prev_sp
, cache
->pc
);
1339 static struct value
*
1340 xtensa_frame_prev_register (struct frame_info
*this_frame
,
1344 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1345 struct xtensa_frame_cache
*cache
;
1346 ULONGEST saved_reg
= 0;
1349 if (*this_cache
== NULL
)
1350 *this_cache
= xtensa_frame_cache (this_frame
, this_cache
);
1351 cache
= *this_cache
;
1353 if (regnum
==gdbarch_pc_regnum (gdbarch
))
1354 saved_reg
= cache
->ra
;
1355 else if (regnum
== gdbarch_tdep (gdbarch
)->a0_base
+ 1)
1356 saved_reg
= cache
->prev_sp
;
1357 else if (!cache
->call0
)
1359 if (regnum
== gdbarch_tdep (gdbarch
)->ws_regnum
)
1360 saved_reg
= cache
->wd
.ws
;
1361 else if (regnum
== gdbarch_tdep (gdbarch
)->wb_regnum
)
1362 saved_reg
= cache
->wd
.wb
;
1363 else if (regnum
== gdbarch_ps_regnum (gdbarch
))
1364 saved_reg
= cache
->ps
;
1372 return frame_unwind_got_constant (this_frame
, regnum
, saved_reg
);
1374 if (!cache
->call0
) /* Windowed ABI. */
1376 /* Convert A-register numbers to AR-register numbers,
1377 if we deal with A-register. */
1378 if (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
1379 && regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15)
1380 regnum
= arreg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1382 /* Check, if we deal with AR-register saved on stack. */
1383 if (regnum
>= gdbarch_tdep (gdbarch
)->ar_base
1384 && regnum
<= (gdbarch_tdep (gdbarch
)->ar_base
1385 + gdbarch_tdep (gdbarch
)->num_aregs
))
1387 int areg
= areg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1390 && areg
< XTENSA_NUM_SAVED_AREGS
1391 && cache
->wd
.aregs
[areg
] != -1)
1392 return frame_unwind_got_memory (this_frame
, regnum
,
1393 cache
->wd
.aregs
[areg
]);
1396 else /* Call0 ABI. */
1398 int reg
= (regnum
>= gdbarch_tdep (gdbarch
)->ar_base
1399 && regnum
<= (gdbarch_tdep (gdbarch
)->ar_base
1401 ? regnum
- gdbarch_tdep (gdbarch
)->ar_base
: regnum
;
1408 /* If register was saved in the prologue, retrieve it. */
1409 stkofs
= cache
->c0
.c0_rt
[reg
].to_stk
;
1410 if (stkofs
!= C0_NOSTK
)
1412 /* Determine SP on entry based on FP. */
1413 spe
= cache
->c0
.c0_fp
1414 - cache
->c0
.c0_rt
[cache
->c0
.fp_regnum
].fr_ofs
;
1416 return frame_unwind_got_memory (this_frame
, regnum
,
1422 /* All other registers have been either saved to
1423 the stack or are still alive in the processor. */
1425 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1429 static const struct frame_unwind
1433 xtensa_frame_this_id
,
1434 xtensa_frame_prev_register
,
1436 default_frame_sniffer
1440 xtensa_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1442 struct xtensa_frame_cache
*cache
=
1443 xtensa_frame_cache (this_frame
, this_cache
);
1448 static const struct frame_base
1452 xtensa_frame_base_address
,
1453 xtensa_frame_base_address
,
1454 xtensa_frame_base_address
1459 xtensa_extract_return_value (struct type
*type
,
1460 struct regcache
*regcache
,
1463 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1464 bfd_byte
*valbuf
= dst
;
1465 int len
= TYPE_LENGTH (type
);
1470 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1472 gdb_assert(len
> 0);
1474 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1476 /* First, we have to find the caller window in the register file. */
1477 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1478 callsize
= extract_call_winsize (gdbarch
, pc
);
1480 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1481 if (len
> (callsize
> 8 ? 8 : 16))
1482 internal_error (__FILE__
, __LINE__
,
1483 _("cannot extract return value of %d bytes long"),
1486 /* Get the register offset of the return
1487 register (A2) in the caller window. */
1488 regcache_raw_read_unsigned
1489 (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, &wb
);
1490 areg
= arreg_number (gdbarch
,
1491 gdbarch_tdep (gdbarch
)->a0_base
+ 2 + callsize
, wb
);
1495 /* No windowing hardware - Call0 ABI. */
1496 areg
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_ARGS
;
1499 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg
, len
);
1501 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1504 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1507 regcache_raw_read_part (regcache
, areg
, offset
, len
, valbuf
);
1509 regcache_raw_read (regcache
, areg
, valbuf
);
1515 xtensa_store_return_value (struct type
*type
,
1516 struct regcache
*regcache
,
1519 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1520 const bfd_byte
*valbuf
= dst
;
1524 int len
= TYPE_LENGTH (type
);
1527 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1529 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1531 regcache_raw_read_unsigned
1532 (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, &wb
);
1533 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1534 callsize
= extract_call_winsize (gdbarch
, pc
);
1536 if (len
> (callsize
> 8 ? 8 : 16))
1537 internal_error (__FILE__
, __LINE__
,
1538 _("unimplemented for this length: %d"),
1539 TYPE_LENGTH (type
));
1540 areg
= arreg_number (gdbarch
,
1541 gdbarch_tdep (gdbarch
)->a0_base
+ 2 + callsize
, wb
);
1543 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1544 callsize
, (int) wb
);
1548 areg
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_ARGS
;
1551 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1554 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1557 regcache_raw_write_part (regcache
, areg
, offset
, len
, valbuf
);
1559 regcache_raw_write (regcache
, areg
, valbuf
);
1564 static enum return_value_convention
1565 xtensa_return_value (struct gdbarch
*gdbarch
,
1566 struct type
*func_type
,
1567 struct type
*valtype
,
1568 struct regcache
*regcache
,
1570 const gdb_byte
*writebuf
)
1572 /* Structures up to 16 bytes are returned in registers. */
1574 int struct_return
= ((TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
1575 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
1576 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
1577 && TYPE_LENGTH (valtype
) > 16);
1580 return RETURN_VALUE_STRUCT_CONVENTION
;
1582 DEBUGTRACE ("xtensa_return_value(...)\n");
1584 if (writebuf
!= NULL
)
1586 xtensa_store_return_value (valtype
, regcache
, writebuf
);
1589 if (readbuf
!= NULL
)
1591 gdb_assert (!struct_return
);
1592 xtensa_extract_return_value (valtype
, regcache
, readbuf
);
1594 return RETURN_VALUE_REGISTER_CONVENTION
;
1601 xtensa_push_dummy_call (struct gdbarch
*gdbarch
,
1602 struct value
*function
,
1603 struct regcache
*regcache
,
1606 struct value
**args
,
1609 CORE_ADDR struct_addr
)
1611 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1613 int size
, onstack_size
;
1614 gdb_byte
*buf
= (gdb_byte
*) alloca (16);
1616 struct argument_info
1618 const bfd_byte
*contents
;
1620 int onstack
; /* onstack == 0 => in reg */
1621 int align
; /* alignment */
1624 int offset
; /* stack offset if on stack. */
1625 int regno
; /* regno if in register. */
1629 struct argument_info
*arg_info
=
1630 (struct argument_info
*) alloca (nargs
* sizeof (struct argument_info
));
1634 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1636 if (xtensa_debug_level
> 3)
1639 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs
);
1640 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1641 "struct_addr=0x%x\n",
1642 (int) sp
, (int) struct_return
, (int) struct_addr
);
1644 for (i
= 0; i
< nargs
; i
++)
1646 struct value
*arg
= args
[i
];
1647 struct type
*arg_type
= check_typedef (value_type (arg
));
1648 fprintf_unfiltered (gdb_stdlog
, "%2d: %s %3d ", i
,
1649 host_address_to_string (arg
),
1650 TYPE_LENGTH (arg_type
));
1651 switch (TYPE_CODE (arg_type
))
1654 fprintf_unfiltered (gdb_stdlog
, "int");
1656 case TYPE_CODE_STRUCT
:
1657 fprintf_unfiltered (gdb_stdlog
, "struct");
1660 fprintf_unfiltered (gdb_stdlog
, "%3d", TYPE_CODE (arg_type
));
1663 fprintf_unfiltered (gdb_stdlog
, " %s\n",
1664 host_address_to_string (value_contents (arg
)));
1668 /* First loop: collect information.
1669 Cast into type_long. (This shouldn't happen often for C because
1670 GDB already does this earlier.) It's possible that GDB could
1671 do it all the time but it's harmless to leave this code here. */
1678 size
= REGISTER_SIZE
;
1680 for (i
= 0; i
< nargs
; i
++)
1682 struct argument_info
*info
= &arg_info
[i
];
1683 struct value
*arg
= args
[i
];
1684 struct type
*arg_type
= check_typedef (value_type (arg
));
1686 switch (TYPE_CODE (arg_type
))
1689 case TYPE_CODE_BOOL
:
1690 case TYPE_CODE_CHAR
:
1691 case TYPE_CODE_RANGE
:
1692 case TYPE_CODE_ENUM
:
1694 /* Cast argument to long if necessary as the mask does it too. */
1695 if (TYPE_LENGTH (arg_type
)
1696 < TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
))
1698 arg_type
= builtin_type (gdbarch
)->builtin_long
;
1699 arg
= value_cast (arg_type
, arg
);
1701 /* Aligment is equal to the type length for the basic types. */
1702 info
->align
= TYPE_LENGTH (arg_type
);
1707 /* Align doubles correctly. */
1708 if (TYPE_LENGTH (arg_type
)
1709 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
))
1710 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
);
1712 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
);
1715 case TYPE_CODE_STRUCT
:
1717 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
);
1720 info
->length
= TYPE_LENGTH (arg_type
);
1721 info
->contents
= value_contents (arg
);
1723 /* Align size and onstack_size. */
1724 size
= (size
+ info
->align
- 1) & ~(info
->align
- 1);
1725 onstack_size
= (onstack_size
+ info
->align
- 1) & ~(info
->align
- 1);
1727 if (size
+ info
->length
> REGISTER_SIZE
* ARG_NOF (gdbarch
))
1730 info
->u
.offset
= onstack_size
;
1731 onstack_size
+= info
->length
;
1736 info
->u
.regno
= ARG_1ST (gdbarch
) + size
/ REGISTER_SIZE
;
1738 size
+= info
->length
;
1741 /* Adjust the stack pointer and align it. */
1742 sp
= align_down (sp
- onstack_size
, SP_ALIGNMENT
);
1744 /* Simulate MOVSP, if Windowed ABI. */
1745 if ((gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1748 read_memory (osp
- 16, buf
, 16);
1749 write_memory (sp
- 16, buf
, 16);
1752 /* Second Loop: Load arguments. */
1756 store_unsigned_integer (buf
, REGISTER_SIZE
, byte_order
, struct_addr
);
1757 regcache_cooked_write (regcache
, ARG_1ST (gdbarch
), buf
);
1760 for (i
= 0; i
< nargs
; i
++)
1762 struct argument_info
*info
= &arg_info
[i
];
1766 int n
= info
->length
;
1767 CORE_ADDR offset
= sp
+ info
->u
.offset
;
1769 /* Odd-sized structs are aligned to the lower side of a memory
1770 word in big-endian mode and require a shift. This only
1771 applies for structures smaller than one word. */
1773 if (n
< REGISTER_SIZE
1774 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1775 offset
+= (REGISTER_SIZE
- n
);
1777 write_memory (offset
, info
->contents
, info
->length
);
1782 int n
= info
->length
;
1783 const bfd_byte
*cp
= info
->contents
;
1784 int r
= info
->u
.regno
;
1786 /* Odd-sized structs are aligned to the lower side of registers in
1787 big-endian mode and require a shift. The odd-sized leftover will
1788 be at the end. Note that this is only true for structures smaller
1789 than REGISTER_SIZE; for larger odd-sized structures the excess
1790 will be left-aligned in the register on both endiannesses. */
1792 if (n
< REGISTER_SIZE
&& byte_order
== BFD_ENDIAN_BIG
)
1795 v
= extract_unsigned_integer (cp
, REGISTER_SIZE
, byte_order
);
1796 v
= v
>> ((REGISTER_SIZE
- n
) * TARGET_CHAR_BIT
);
1798 store_unsigned_integer (buf
, REGISTER_SIZE
, byte_order
, v
);
1799 regcache_cooked_write (regcache
, r
, buf
);
1801 cp
+= REGISTER_SIZE
;
1808 regcache_cooked_write (regcache
, r
, cp
);
1810 cp
+= REGISTER_SIZE
;
1817 /* Set the return address of dummy frame to the dummy address.
1818 The return address for the current function (in A0) is
1819 saved in the dummy frame, so we can savely overwrite A0 here. */
1821 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1823 ra
= (bp_addr
& 0x3fffffff) | 0x40000000;
1824 regcache_raw_read (regcache
, gdbarch_ps_regnum (gdbarch
), buf
);
1825 ps
= extract_unsigned_integer (buf
, 4, byte_order
) & ~0x00030000;
1826 regcache_cooked_write_unsigned
1827 (regcache
, gdbarch_tdep (gdbarch
)->a0_base
+ 4, ra
);
1828 regcache_cooked_write_unsigned (regcache
,
1829 gdbarch_ps_regnum (gdbarch
),
1832 /* All the registers have been saved. After executing
1833 dummy call, they all will be restored. So it's safe
1834 to modify WINDOWSTART register to make it look like there
1835 is only one register window corresponding to WINDOWEBASE. */
1837 regcache_raw_read (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, buf
);
1838 regcache_cooked_write_unsigned
1839 (regcache
, gdbarch_tdep (gdbarch
)->ws_regnum
,
1840 1 << extract_unsigned_integer (buf
, 4, byte_order
));
1844 /* Simulate CALL0: write RA into A0 register. */
1845 regcache_cooked_write_unsigned
1846 (regcache
, gdbarch_tdep (gdbarch
)->a0_base
, bp_addr
);
1849 /* Set new stack pointer and return it. */
1850 regcache_cooked_write_unsigned (regcache
,
1851 gdbarch_tdep (gdbarch
)->a0_base
+ 1, sp
);
1852 /* Make dummy frame ID unique by adding a constant. */
1853 return sp
+ SP_ALIGNMENT
;
1857 /* Return a breakpoint for the current location of PC. We always use
1858 the density version if we have density instructions (regardless of the
1859 current instruction at PC), and use regular instructions otherwise. */
1861 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1862 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1863 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1864 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1866 static const unsigned char *
1867 xtensa_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
1870 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
1871 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
1872 static unsigned char density_big_breakpoint
[] = DENSITY_BIG_BREAKPOINT
;
1873 static unsigned char density_little_breakpoint
[] = DENSITY_LITTLE_BREAKPOINT
;
1875 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr
);
1877 if (gdbarch_tdep (gdbarch
)->isa_use_density_instructions
)
1879 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1881 *lenptr
= sizeof (density_big_breakpoint
);
1882 return density_big_breakpoint
;
1886 *lenptr
= sizeof (density_little_breakpoint
);
1887 return density_little_breakpoint
;
1892 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1894 *lenptr
= sizeof (big_breakpoint
);
1895 return big_breakpoint
;
1899 *lenptr
= sizeof (little_breakpoint
);
1900 return little_breakpoint
;
1905 /* Call0 ABI support routines. */
1907 /* Call0 opcode class. Opcodes are preclassified according to what they
1908 mean for Call0 prologue analysis, and their number of significant operands.
1909 The purpose of this is to simplify prologue analysis by separating
1910 instruction decoding (libisa) from the semantics of prologue analysis. */
1913 c0opc_illegal
, /* Unknown to libisa (invalid) or 'ill' opcode. */
1914 c0opc_uninteresting
, /* Not interesting for Call0 prologue analysis. */
1915 c0opc_flow
, /* Flow control insn. */
1916 c0opc_entry
, /* ENTRY indicates non-Call0 prologue. */
1917 c0opc_break
, /* Debugger software breakpoints. */
1918 c0opc_add
, /* Adding two registers. */
1919 c0opc_addi
, /* Adding a register and an immediate. */
1920 c0opc_sub
, /* Subtracting a register from a register. */
1921 c0opc_mov
, /* Moving a register to a register. */
1922 c0opc_movi
, /* Moving an immediate to a register. */
1923 c0opc_l32r
, /* Loading a literal. */
1924 c0opc_s32i
, /* Storing word at fixed offset from a base
1926 c0opc_NrOf
/* Number of opcode classifications. */
1930 /* Classify an opcode based on what it means for Call0 prologue analysis. */
1932 static xtensa_insn_kind
1933 call0_classify_opcode (xtensa_isa isa
, xtensa_opcode opc
)
1935 const char *opcname
;
1936 xtensa_insn_kind opclass
= c0opc_uninteresting
;
1938 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc
);
1940 /* Get opcode name and handle special classifications. */
1942 opcname
= xtensa_opcode_name (isa
, opc
);
1945 || strcasecmp (opcname
, "ill") == 0
1946 || strcasecmp (opcname
, "ill.n") == 0)
1947 opclass
= c0opc_illegal
;
1948 else if (strcasecmp (opcname
, "break") == 0
1949 || strcasecmp (opcname
, "break.n") == 0)
1950 opclass
= c0opc_break
;
1951 else if (strcasecmp (opcname
, "entry") == 0)
1952 opclass
= c0opc_entry
;
1953 else if (xtensa_opcode_is_branch (isa
, opc
) > 0
1954 || xtensa_opcode_is_jump (isa
, opc
) > 0
1955 || xtensa_opcode_is_loop (isa
, opc
) > 0
1956 || xtensa_opcode_is_call (isa
, opc
) > 0
1957 || strcasecmp (opcname
, "simcall") == 0
1958 || strcasecmp (opcname
, "syscall") == 0)
1959 opclass
= c0opc_flow
;
1961 /* Also, classify specific opcodes that need to be tracked. */
1962 else if (strcasecmp (opcname
, "add") == 0
1963 || strcasecmp (opcname
, "add.n") == 0)
1964 opclass
= c0opc_add
;
1965 else if (strcasecmp (opcname
, "addi") == 0
1966 || strcasecmp (opcname
, "addi.n") == 0
1967 || strcasecmp (opcname
, "addmi") == 0)
1968 opclass
= c0opc_addi
;
1969 else if (strcasecmp (opcname
, "sub") == 0)
1970 opclass
= c0opc_sub
;
1971 else if (strcasecmp (opcname
, "mov.n") == 0
1972 || strcasecmp (opcname
, "or") == 0) /* Could be 'mov' asm macro. */
1973 opclass
= c0opc_mov
;
1974 else if (strcasecmp (opcname
, "movi") == 0
1975 || strcasecmp (opcname
, "movi.n") == 0)
1976 opclass
= c0opc_movi
;
1977 else if (strcasecmp (opcname
, "l32r") == 0)
1978 opclass
= c0opc_l32r
;
1979 else if (strcasecmp (opcname
, "s32i") == 0
1980 || strcasecmp (opcname
, "s32i.n") == 0)
1981 opclass
= c0opc_s32i
;
1986 /* Tracks register movement/mutation for a given operation, which may
1987 be within a bundle. Updates the destination register tracking info
1988 accordingly. The pc is needed only for pc-relative load instructions
1989 (eg. l32r). The SP register number is needed to identify stores to
1993 call0_track_op (struct gdbarch
*gdbarch
,
1994 xtensa_c0reg_t dst
[], xtensa_c0reg_t src
[],
1995 xtensa_insn_kind opclass
, int nods
, unsigned odv
[],
1996 CORE_ADDR pc
, CORE_ADDR litbase
, int spreg
)
1998 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1999 unsigned litaddr
, litval
;
2004 /* 3 operands: dst, src, imm. */
2005 gdb_assert (nods
== 3);
2006 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2007 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ odv
[2];
2010 /* 3 operands: dst, src1, src2. */
2011 gdb_assert (nods
== 3);
2012 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2014 dst
[odv
[0]].fr_reg
= src
[odv
[2]].fr_reg
;
2015 dst
[odv
[0]].fr_ofs
= src
[odv
[2]].fr_ofs
+ src
[odv
[1]].fr_ofs
;
2017 else if (src
[odv
[2]].fr_reg
== C0_CONST
)
2019 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2020 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ src
[odv
[2]].fr_ofs
;
2022 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2025 /* 3 operands: dst, src1, src2. */
2026 gdb_assert (nods
== 3);
2027 if (src
[odv
[2]].fr_reg
== C0_CONST
)
2029 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2030 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
- src
[odv
[2]].fr_ofs
;
2032 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2035 /* 2 operands: dst, src [, src]. */
2036 gdb_assert (nods
== 2);
2037 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2038 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
;
2041 /* 2 operands: dst, imm. */
2042 gdb_assert (nods
== 2);
2043 dst
[odv
[0]].fr_reg
= C0_CONST
;
2044 dst
[odv
[0]].fr_ofs
= odv
[1];
2047 /* 2 operands: dst, literal offset. */
2048 gdb_assert (nods
== 2);
2049 litaddr
= litbase
& 1
2050 ? (litbase
& ~1) + (signed)odv
[1]
2051 : (pc
+ 3 + (signed)odv
[1]) & ~3;
2052 litval
= read_memory_integer (litaddr
, 4, byte_order
);
2053 dst
[odv
[0]].fr_reg
= C0_CONST
;
2054 dst
[odv
[0]].fr_ofs
= litval
;
2057 /* 3 operands: value, base, offset. */
2058 gdb_assert (nods
== 3 && spreg
>= 0 && spreg
< C0_NREGS
);
2059 if (src
[odv
[1]].fr_reg
== spreg
/* Store to stack frame. */
2060 && (src
[odv
[1]].fr_ofs
& 3) == 0 /* Alignment preserved. */
2061 && src
[odv
[0]].fr_reg
>= 0 /* Value is from a register. */
2062 && src
[odv
[0]].fr_ofs
== 0 /* Value hasn't been modified. */
2063 && src
[src
[odv
[0]].fr_reg
].to_stk
== C0_NOSTK
) /* First time. */
2065 /* ISA encoding guarantees alignment. But, check it anyway. */
2066 gdb_assert ((odv
[2] & 3) == 0);
2067 dst
[src
[odv
[0]].fr_reg
].to_stk
= src
[odv
[1]].fr_ofs
+ odv
[2];
2071 gdb_assert_not_reached ("unexpected instruction kind");
2075 /* Analyze prologue of the function at start address to determine if it uses
2076 the Call0 ABI, and if so track register moves and linear modifications
2077 in the prologue up to the PC or just beyond the prologue, whichever is first.
2078 An 'entry' instruction indicates non-Call0 ABI and the end of the prologue.
2079 The prologue may overlap non-prologue instructions but is guaranteed to end
2080 by the first flow-control instruction (jump, branch, call or return).
2081 Since an optimized function may move information around and change the
2082 stack frame arbitrarily during the prologue, the information is guaranteed
2083 valid only at the point in the function indicated by the PC.
2084 May be used to skip the prologue or identify the ABI, w/o tracking.
2086 Returns: Address of first instruction after prologue, or PC (whichever
2087 is first), or 0, if decoding failed (in libisa).
2089 start Start address of function/prologue.
2090 pc Program counter to stop at. Use 0 to continue to end of prologue.
2091 If 0, avoids infinite run-on in corrupt code memory by bounding
2092 the scan to the end of the function if that can be determined.
2093 nregs Number of general registers to track (size of rt[] array).
2095 rt[] Array[nregs] of xtensa_c0reg structures for register tracking info.
2096 If NULL, registers are not tracked.
2098 call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0
2099 (more accurately, non-zero until 'entry' insn is encountered).
2101 Note that these may produce useful results even if decoding fails
2102 because they begin with default assumptions that analysis may change. */
2105 call0_analyze_prologue (struct gdbarch
*gdbarch
,
2106 CORE_ADDR start
, CORE_ADDR pc
, CORE_ADDR litbase
,
2107 int nregs
, xtensa_c0reg_t rt
[], int *call0
)
2109 CORE_ADDR ia
; /* Current insn address in prologue. */
2110 CORE_ADDR ba
= 0; /* Current address at base of insn buffer. */
2111 CORE_ADDR bt
; /* Current address at top+1 of insn buffer. */
2112 char ibuf
[XTENSA_ISA_BSZ
];/* Instruction buffer for decoding prologue. */
2113 xtensa_isa isa
; /* libisa ISA handle. */
2114 xtensa_insnbuf ins
, slot
; /* libisa handle to decoded insn, slot. */
2115 xtensa_format ifmt
; /* libisa instruction format. */
2116 int ilen
, islots
, is
; /* Instruction length, nbr slots, current slot. */
2117 xtensa_opcode opc
; /* Opcode in current slot. */
2118 xtensa_insn_kind opclass
; /* Opcode class for Call0 prologue analysis. */
2119 int nods
; /* Opcode number of operands. */
2120 unsigned odv
[C0_MAXOPDS
]; /* Operand values in order provided by libisa. */
2121 xtensa_c0reg_t
*rtmp
; /* Register tracking info snapshot. */
2122 int j
; /* General loop counter. */
2123 int fail
= 0; /* Set non-zero and exit, if decoding fails. */
2124 CORE_ADDR body_pc
; /* The PC for the first non-prologue insn. */
2125 CORE_ADDR end_pc
; /* The PC for the lust function insn. */
2127 struct symtab_and_line prologue_sal
;
2129 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2130 (int)start
, (int)pc
);
2132 /* Try to limit the scan to the end of the function if a non-zero pc
2133 arg was not supplied to avoid probing beyond the end of valid memory.
2134 If memory is full of garbage that classifies as c0opc_uninteresting.
2135 If this fails (eg. if no symbols) pc ends up 0 as it was.
2136 Intialize the Call0 frame and register tracking info.
2137 Assume it's Call0 until an 'entry' instruction is encountered.
2138 Assume we may be in the prologue until we hit a flow control instr. */
2144 /* Find out, if we have an information about the prologue from DWARF. */
2145 prologue_sal
= find_pc_line (start
, 0);
2146 if (prologue_sal
.line
!= 0) /* Found debug info. */
2147 body_pc
= prologue_sal
.end
;
2149 /* If we are going to analyze the prologue in general without knowing about
2150 the current PC, make the best assumtion for the end of the prologue. */
2153 find_pc_partial_function (start
, 0, NULL
, &end_pc
);
2154 body_pc
= min (end_pc
, body_pc
);
2157 body_pc
= min (pc
, body_pc
);
2164 rtmp
= (xtensa_c0reg_t
*) alloca(nregs
* sizeof(xtensa_c0reg_t
));
2165 /* rt is already initialized in xtensa_alloc_frame_cache(). */
2169 if (!xtensa_default_isa
)
2170 xtensa_default_isa
= xtensa_isa_init (0, 0);
2171 isa
= xtensa_default_isa
;
2172 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2173 ins
= xtensa_insnbuf_alloc (isa
);
2174 slot
= xtensa_insnbuf_alloc (isa
);
2176 for (ia
= start
, bt
= ia
; ia
< body_pc
; ia
+= ilen
)
2178 /* (Re)fill instruction buffer from memory if necessary, but do not
2179 read memory beyond PC to be sure we stay within text section
2180 (this protection only works if a non-zero pc is supplied). */
2182 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2185 bt
= (ba
+ XTENSA_ISA_BSZ
) < body_pc
? ba
+ XTENSA_ISA_BSZ
: body_pc
;
2186 read_memory (ba
, ibuf
, bt
- ba
);
2187 /* If there is a memory reading error read_memory () will report it
2188 and then throw an exception, stopping command execution. */
2191 /* Decode format information. */
2193 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2194 ifmt
= xtensa_format_decode (isa
, ins
);
2195 if (ifmt
== XTENSA_UNDEFINED
)
2200 ilen
= xtensa_format_length (isa
, ifmt
);
2201 if (ilen
== XTENSA_UNDEFINED
)
2206 islots
= xtensa_format_num_slots (isa
, ifmt
);
2207 if (islots
== XTENSA_UNDEFINED
)
2213 /* Analyze a bundle or a single instruction, using a snapshot of
2214 the register tracking info as input for the entire bundle so that
2215 register changes do not take effect within this bundle. */
2217 for (j
= 0; j
< nregs
; ++j
)
2220 for (is
= 0; is
< islots
; ++is
)
2222 /* Decode a slot and classify the opcode. */
2224 fail
= xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
);
2228 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2229 DEBUGVERB ("[call0_analyze_prologue] instr "
2230 "addr = 0x%08x, opc = %d\n",
2232 if (opc
== XTENSA_UNDEFINED
)
2233 opclass
= c0opc_illegal
;
2235 opclass
= call0_classify_opcode (isa
, opc
);
2237 /* Decide whether to track this opcode, ignore it, or bail out. */
2246 case c0opc_uninteresting
:
2255 ia
+= ilen
; /* Skip over 'entry' insn. */
2263 /* Only expected opcodes should get this far. */
2267 /* Extract and decode the operands. */
2268 nods
= xtensa_opcode_num_operands (isa
, opc
);
2269 if (nods
== XTENSA_UNDEFINED
)
2275 for (j
= 0; j
< nods
&& j
< C0_MAXOPDS
; ++j
)
2277 fail
= xtensa_operand_get_field (isa
, opc
, j
, ifmt
,
2282 fail
= xtensa_operand_decode (isa
, opc
, j
, &odv
[j
]);
2287 /* Check operands to verify use of 'mov' assembler macro. */
2288 if (opclass
== c0opc_mov
&& nods
== 3)
2290 if (odv
[2] == odv
[1])
2294 opclass
= c0opc_uninteresting
;
2299 /* Track register movement and modification for this operation. */
2300 call0_track_op (gdbarch
, rt
, rtmp
, opclass
,
2301 nods
, odv
, ia
, litbase
, 1);
2305 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2306 (unsigned)ia
, fail
? "failed" : "succeeded");
2307 xtensa_insnbuf_free(isa
, slot
);
2308 xtensa_insnbuf_free(isa
, ins
);
2309 return fail
? XTENSA_ISA_BADPC
: ia
;
2312 /* Initialize frame cache for the current frame in CALL0 ABI. */
2315 call0_frame_cache (struct frame_info
*this_frame
,
2316 xtensa_frame_cache_t
*cache
,
2317 CORE_ADDR pc
, CORE_ADDR litbase
)
2319 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2320 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2321 CORE_ADDR start_pc
; /* The beginning of the function. */
2322 CORE_ADDR body_pc
=UINT_MAX
; /* PC, where prologue analysis stopped. */
2323 CORE_ADDR sp
, fp
, ra
;
2324 int fp_regnum
, c0_hasfp
, c0_frmsz
, prev_sp
, to_stk
;
2326 /* Find the beginning of the prologue of the function containing the PC
2327 and analyze it up to the PC or the end of the prologue. */
2329 if (find_pc_partial_function (pc
, NULL
, &start_pc
, NULL
))
2331 body_pc
= call0_analyze_prologue (gdbarch
, start_pc
, pc
, litbase
,
2333 &cache
->c0
.c0_rt
[0],
2336 if (body_pc
== XTENSA_ISA_BADPC
)
2337 error (_("Xtensa-specific internal error: CALL0 prologue \
2338 analysis failed in this frame. GDB command execution stopped."));
2341 sp
= get_frame_register_unsigned
2342 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
2343 fp
= sp
; /* Assume FP == SP until proven otherwise. */
2345 /* Get the frame information and FP (if used) at the current PC.
2346 If PC is in the prologue, the prologue analysis is more reliable
2347 than DWARF info. We don't not know for sure if PC is in the prologue,
2348 but we know no calls have yet taken place, so we can almost
2349 certainly rely on the prologue analysis. */
2353 /* Prologue analysis was successful up to the PC.
2354 It includes the cases when PC == START_PC. */
2355 c0_hasfp
= cache
->c0
.c0_rt
[C0_FP
].fr_reg
== C0_SP
;
2356 /* c0_hasfp == true means there is a frame pointer because
2357 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2358 was derived from SP. Otherwise, it would be C0_FP. */
2359 fp_regnum
= c0_hasfp
? C0_FP
: C0_SP
;
2360 c0_frmsz
= - cache
->c0
.c0_rt
[fp_regnum
].fr_ofs
;
2361 fp_regnum
+= gdbarch_tdep (gdbarch
)->a0_base
;
2363 else /* No data from the prologue analysis. */
2366 fp_regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_SP
;
2371 prev_sp
= fp
+ c0_frmsz
;
2373 /* Frame size from debug info or prologue tracking does not account for
2374 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2377 fp
= get_frame_register_unsigned (this_frame
, fp_regnum
);
2379 /* Recalculate previous SP. */
2380 prev_sp
= fp
+ c0_frmsz
;
2381 /* Update the stack frame size. */
2382 c0_frmsz
+= fp
- sp
;
2385 /* Get the return address (RA) from the stack if saved,
2386 or try to get it from a register. */
2388 to_stk
= cache
->c0
.c0_rt
[C0_RA
].to_stk
;
2389 if (to_stk
!= C0_NOSTK
)
2391 read_memory_integer (sp
+ c0_frmsz
+ cache
->c0
.c0_rt
[C0_RA
].to_stk
,
2394 else if (cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_CONST
2395 && cache
->c0
.c0_rt
[C0_RA
].fr_ofs
== 0)
2397 /* Special case for terminating backtrace at a function that
2398 wants to be seen as the outermost. Such a function will
2399 clear it's RA (A0) register to 0 in the prologue instead of
2400 saving its original value. */
2405 /* RA was copied to another register or (before any function
2406 call) may still be in the original RA register. This is not
2407 always reliable: even in a leaf function, register tracking
2408 stops after prologue, and even in prologue, non-prologue
2409 instructions (not tracked) may overwrite RA or any register
2410 it was copied to. If likely in prologue or before any call,
2411 use retracking info and hope for the best (compiler should
2412 have saved RA in stack if not in a leaf function). If not in
2413 prologue, too bad. */
2418 (i
== C0_RA
|| cache
->c0
.c0_rt
[i
].fr_reg
!= C0_RA
);
2420 if (i
>= C0_NREGS
&& cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_RA
)
2424 ra
= get_frame_register_unsigned
2426 gdbarch_tdep (gdbarch
)->a0_base
+ cache
->c0
.c0_rt
[i
].fr_reg
);
2431 cache
->pc
= start_pc
;
2433 /* RA == 0 marks the outermost frame. Do not go past it. */
2434 cache
->prev_sp
= (ra
!= 0) ? prev_sp
: 0;
2435 cache
->c0
.fp_regnum
= fp_regnum
;
2436 cache
->c0
.c0_frmsz
= c0_frmsz
;
2437 cache
->c0
.c0_hasfp
= c0_hasfp
;
2438 cache
->c0
.c0_fp
= fp
;
2442 /* Skip function prologue.
2444 Return the pc of the first instruction after prologue. GDB calls this to
2445 find the address of the first line of the function or (if there is no line
2446 number information) to skip the prologue for planting breakpoints on
2447 function entries. Use debug info (if present) or prologue analysis to skip
2448 the prologue to achieve reliable debugging behavior. For windowed ABI,
2449 only the 'entry' instruction is skipped. It is not strictly necessary to
2450 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2451 backtrace at any point in the prologue, however certain potential hazards
2452 are avoided and a more "normal" debugging experience is ensured by
2453 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2454 For example, if we don't skip the prologue:
2455 - Some args may not yet have been saved to the stack where the debug
2456 info expects to find them (true anyway when only 'entry' is skipped);
2457 - Software breakpoints ('break' instrs) may not have been unplanted
2458 when the prologue analysis is done on initializing the frame cache,
2459 and breaks in the prologue will throw off the analysis.
2461 If we have debug info ( line-number info, in particular ) we simply skip
2462 the code associated with the first function line effectively skipping
2463 the prologue code. It works even in cases like
2466 { int local_var = 1;
2470 because, for this source code, both Xtensa compilers will generate two
2471 separate entries ( with the same line number ) in dwarf line-number
2472 section to make sure there is a boundary between the prologue code and
2473 the rest of the function.
2475 If there is no debug info, we need to analyze the code. */
2477 /* #define DONT_SKIP_PROLOGUE */
2480 xtensa_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
2482 struct symtab_and_line prologue_sal
;
2485 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc
);
2487 #if DONT_SKIP_PROLOGUE
2491 /* Try to find first body line from debug info. */
2493 prologue_sal
= find_pc_line (start_pc
, 0);
2494 if (prologue_sal
.line
!= 0) /* Found debug info. */
2496 /* In Call0, it is possible to have a function with only one instruction
2497 ('ret') resulting from a 1-line optimized function that does nothing.
2498 In that case, prologue_sal.end may actually point to the start of the
2499 next function in the text section, causing a breakpoint to be set at
2500 the wrong place. Check if the end address is in a different function,
2501 and if so return the start PC. We know we have symbol info. */
2505 find_pc_partial_function (prologue_sal
.end
, NULL
, &end_func
, NULL
);
2506 if (end_func
!= start_pc
)
2509 return prologue_sal
.end
;
2512 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
2513 body_pc
= call0_analyze_prologue (gdbarch
, start_pc
, 0, 0, 0, NULL
, NULL
);
2514 return body_pc
!= 0 ? body_pc
: start_pc
;
2517 /* Verify the current configuration. */
2519 xtensa_verify_config (struct gdbarch
*gdbarch
)
2521 struct ui_file
*log
;
2522 struct cleanup
*cleanups
;
2523 struct gdbarch_tdep
*tdep
;
2527 tdep
= gdbarch_tdep (gdbarch
);
2528 log
= mem_fileopen ();
2529 cleanups
= make_cleanup_ui_file_delete (log
);
2531 /* Verify that we got a reasonable number of AREGS. */
2532 if ((tdep
->num_aregs
& -tdep
->num_aregs
) != tdep
->num_aregs
)
2533 fprintf_unfiltered (log
, _("\
2534 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
2537 /* Verify that certain registers exist. */
2539 if (tdep
->pc_regnum
== -1)
2540 fprintf_unfiltered (log
, _("\n\tpc_regnum: No PC register"));
2541 if (tdep
->isa_use_exceptions
&& tdep
->ps_regnum
== -1)
2542 fprintf_unfiltered (log
, _("\n\tps_regnum: No PS register"));
2544 if (tdep
->isa_use_windowed_registers
)
2546 if (tdep
->wb_regnum
== -1)
2547 fprintf_unfiltered (log
, _("\n\twb_regnum: No WB register"));
2548 if (tdep
->ws_regnum
== -1)
2549 fprintf_unfiltered (log
, _("\n\tws_regnum: No WS register"));
2550 if (tdep
->ar_base
== -1)
2551 fprintf_unfiltered (log
, _("\n\tar_base: No AR registers"));
2554 if (tdep
->a0_base
== -1)
2555 fprintf_unfiltered (log
, _("\n\ta0_base: No Ax registers"));
2557 buf
= ui_file_xstrdup (log
, &length
);
2558 make_cleanup (xfree
, buf
);
2560 internal_error (__FILE__
, __LINE__
,
2561 _("the following are invalid: %s"), buf
);
2562 do_cleanups (cleanups
);
2566 /* Derive specific register numbers from the array of registers. */
2569 xtensa_derive_tdep (struct gdbarch_tdep
*tdep
)
2571 xtensa_register_t
* rmap
;
2572 int n
, max_size
= 4;
2575 tdep
->num_nopriv_regs
= 0;
2577 /* Special registers 0..255 (core). */
2578 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
2580 for (rmap
= tdep
->regmap
, n
= 0; rmap
->target_number
!= -1; n
++, rmap
++)
2582 if (rmap
->target_number
== 0x0020)
2583 tdep
->pc_regnum
= n
;
2584 else if (rmap
->target_number
== 0x0100)
2586 else if (rmap
->target_number
== 0x0000)
2588 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(72))
2589 tdep
->wb_regnum
= n
;
2590 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(73))
2591 tdep
->ws_regnum
= n
;
2592 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(233))
2593 tdep
->debugcause_regnum
= n
;
2594 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(232))
2595 tdep
->exccause_regnum
= n
;
2596 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(238))
2597 tdep
->excvaddr_regnum
= n
;
2598 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(0))
2599 tdep
->lbeg_regnum
= n
;
2600 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(1))
2601 tdep
->lend_regnum
= n
;
2602 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(2))
2603 tdep
->lcount_regnum
= n
;
2604 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(3))
2605 tdep
->sar_regnum
= n
;
2606 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(5))
2607 tdep
->litbase_regnum
= n
;
2608 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(230))
2609 tdep
->ps_regnum
= n
;
2611 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(226))
2612 tdep
->interrupt_regnum
= n
;
2613 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(227))
2614 tdep
->interrupt2_regnum
= n
;
2615 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(224))
2616 tdep
->cpenable_regnum
= n
;
2619 if (rmap
->byte_size
> max_size
)
2620 max_size
= rmap
->byte_size
;
2621 if (rmap
->mask
!= 0 && tdep
->num_regs
== 0)
2623 /* Find out out how to deal with priveleged registers.
2625 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
2626 && tdep->num_nopriv_regs == 0)
2627 tdep->num_nopriv_regs = n;
2629 if ((rmap
->flags
& XTENSA_REGISTER_FLAGS_PRIVILEGED
) != 0
2630 && tdep
->num_regs
== 0)
2634 /* Number of pseudo registers. */
2635 tdep
->num_pseudo_regs
= n
- tdep
->num_regs
;
2637 /* Empirically determined maximum sizes. */
2638 tdep
->max_register_raw_size
= max_size
;
2639 tdep
->max_register_virtual_size
= max_size
;
2642 /* Module "constructor" function. */
2644 extern struct gdbarch_tdep xtensa_tdep
;
2646 static struct gdbarch
*
2647 xtensa_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2649 struct gdbarch_tdep
*tdep
;
2650 struct gdbarch
*gdbarch
;
2651 struct xtensa_abi_handler
*abi_handler
;
2653 DEBUGTRACE ("gdbarch_init()\n");
2655 /* We have to set the byte order before we call gdbarch_alloc. */
2656 info
.byte_order
= XCHAL_HAVE_BE
? BFD_ENDIAN_BIG
: BFD_ENDIAN_LITTLE
;
2658 tdep
= &xtensa_tdep
;
2659 gdbarch
= gdbarch_alloc (&info
, tdep
);
2660 xtensa_derive_tdep (tdep
);
2662 /* Verify our configuration. */
2663 xtensa_verify_config (gdbarch
);
2665 /* Pseudo-Register read/write. */
2666 set_gdbarch_pseudo_register_read (gdbarch
, xtensa_pseudo_register_read
);
2667 set_gdbarch_pseudo_register_write (gdbarch
, xtensa_pseudo_register_write
);
2669 /* Set target information. */
2670 set_gdbarch_num_regs (gdbarch
, tdep
->num_regs
);
2671 set_gdbarch_num_pseudo_regs (gdbarch
, tdep
->num_pseudo_regs
);
2672 set_gdbarch_sp_regnum (gdbarch
, tdep
->a0_base
+ 1);
2673 set_gdbarch_pc_regnum (gdbarch
, tdep
->pc_regnum
);
2674 set_gdbarch_ps_regnum (gdbarch
, tdep
->ps_regnum
);
2676 /* Renumber registers for known formats (stabs and dwarf2). */
2677 set_gdbarch_stab_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
2678 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
2680 /* We provide our own function to get register information. */
2681 set_gdbarch_register_name (gdbarch
, xtensa_register_name
);
2682 set_gdbarch_register_type (gdbarch
, xtensa_register_type
);
2684 /* To call functions from GDB using dummy frame. */
2685 set_gdbarch_push_dummy_call (gdbarch
, xtensa_push_dummy_call
);
2687 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2689 set_gdbarch_return_value (gdbarch
, xtensa_return_value
);
2691 /* Advance PC across any prologue instructions to reach "real" code. */
2692 set_gdbarch_skip_prologue (gdbarch
, xtensa_skip_prologue
);
2694 /* Stack grows downward. */
2695 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2697 /* Set breakpoints. */
2698 set_gdbarch_breakpoint_from_pc (gdbarch
, xtensa_breakpoint_from_pc
);
2700 /* After breakpoint instruction or illegal instruction, pc still
2701 points at break instruction, so don't decrement. */
2702 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
2704 /* We don't skip args. */
2705 set_gdbarch_frame_args_skip (gdbarch
, 0);
2707 set_gdbarch_unwind_pc (gdbarch
, xtensa_unwind_pc
);
2709 set_gdbarch_frame_align (gdbarch
, xtensa_frame_align
);
2711 set_gdbarch_dummy_id (gdbarch
, xtensa_dummy_id
);
2713 /* Frame handling. */
2714 frame_base_set_default (gdbarch
, &xtensa_frame_base
);
2715 frame_unwind_append_unwinder (gdbarch
, &xtensa_unwind
);
2716 dwarf2_append_unwinders (gdbarch
);
2718 set_gdbarch_print_insn (gdbarch
, print_insn_xtensa
);
2720 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
2722 xtensa_add_reggroups (gdbarch
);
2723 set_gdbarch_register_reggroup_p (gdbarch
, xtensa_register_reggroup_p
);
2725 set_gdbarch_regset_from_core_section (gdbarch
,
2726 xtensa_regset_from_core_section
);
2728 set_solib_svr4_fetch_link_map_offsets
2729 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
2735 xtensa_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
2737 error (_("xtensa_dump_tdep(): not implemented"));
2740 /* Provide a prototype to silence -Wmissing-prototypes. */
2741 extern initialize_file_ftype _initialize_xtensa_tdep
;
2744 _initialize_xtensa_tdep (void)
2746 struct cmd_list_element
*c
;
2748 gdbarch_register (bfd_arch_xtensa
, xtensa_gdbarch_init
, xtensa_dump_tdep
);
2749 xtensa_init_reggroups ();
2751 add_setshow_zinteger_cmd ("xtensa",
2753 &xtensa_debug_level
,
2754 _("Set Xtensa debugging."),
2755 _("Show Xtensa debugging."), _("\
2756 When non-zero, Xtensa-specific debugging is enabled. \
2757 Can be 1, 2, 3, or 4 indicating the level of debugging."),
2760 &setdebuglist
, &showdebuglist
);