1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "solib-svr4.h"
33 #include "reggroups.h"
36 #include "dummy-frame.h"
38 #include "dwarf2-frame.h"
39 #include "dwarf2loc.h"
40 #include "frame-base.h"
41 #include "frame-unwind.h"
43 #include "arch-utils.h"
51 #include "xtensa-isa.h"
52 #include "xtensa-tdep.h"
53 #include "xtensa-config.h"
57 static unsigned int xtensa_debug_level
= 0;
59 #define DEBUGWARN(args...) \
60 if (xtensa_debug_level > 0) \
61 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
63 #define DEBUGINFO(args...) \
64 if (xtensa_debug_level > 1) \
65 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
67 #define DEBUGTRACE(args...) \
68 if (xtensa_debug_level > 2) \
69 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
71 #define DEBUGVERB(args...) \
72 if (xtensa_debug_level > 3) \
73 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
76 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
77 #define SP_ALIGNMENT 16
80 /* On Windowed ABI, we use a6 through a11 for passing arguments
81 to a function called by GDB because CALL4 is used. */
82 #define ARGS_NUM_REGS 6
83 #define REGISTER_SIZE 4
86 /* Extract the call size from the return address or PS register. */
87 #define PS_CALLINC_SHIFT 16
88 #define PS_CALLINC_MASK 0x00030000
89 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
90 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
92 /* On TX, hardware can be configured without Exception Option.
93 There is no PS register in this case. Inside XT-GDB, let us treat
94 it as a virtual read-only register always holding the same value. */
97 /* ABI-independent macros. */
98 #define ARG_NOF(gdbarch) \
99 (gdbarch_tdep (gdbarch)->call_abi \
100 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
101 #define ARG_1ST(gdbarch) \
102 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
103 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
104 : (gdbarch_tdep (gdbarch)->a0_base + 6))
106 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
107 indicates that the instruction is an ENTRY instruction. */
109 #define XTENSA_IS_ENTRY(gdbarch, op1) \
110 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
111 ? ((op1) == 0x6c) : ((op1) == 0x36))
113 #define XTENSA_ENTRY_LENGTH 3
115 /* windowing_enabled() returns true, if windowing is enabled.
116 WOE must be set to 1; EXCM to 0.
117 Note: We assume that EXCM is always 0 for XEA1. */
119 #define PS_WOE (1<<18)
120 #define PS_EXC (1<<4)
122 /* Big enough to hold the size of the largest register in bytes. */
123 #define XTENSA_MAX_REGISTER_SIZE 64
126 windowing_enabled (struct gdbarch
*gdbarch
, unsigned int ps
)
128 /* If we know CALL0 ABI is set explicitly, say it is Call0. */
129 if (gdbarch_tdep (gdbarch
)->call_abi
== CallAbiCall0Only
)
132 return ((ps
& PS_EXC
) == 0 && (ps
& PS_WOE
) != 0);
135 /* Convert a live A-register number to the corresponding AR-register
138 arreg_number (struct gdbarch
*gdbarch
, int a_regnum
, ULONGEST wb
)
140 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
143 arreg
= a_regnum
- tdep
->a0_base
;
144 arreg
+= (wb
& ((tdep
->num_aregs
- 1) >> 2)) << WB_SHIFT
;
145 arreg
&= tdep
->num_aregs
- 1;
147 return arreg
+ tdep
->ar_base
;
150 /* Convert a live AR-register number to the corresponding A-register order
151 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
153 areg_number (struct gdbarch
*gdbarch
, int ar_regnum
, unsigned int wb
)
155 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
158 areg
= ar_regnum
- tdep
->ar_base
;
159 if (areg
< 0 || areg
>= tdep
->num_aregs
)
161 areg
= (areg
- wb
* 4) & (tdep
->num_aregs
- 1);
162 return (areg
> 15) ? -1 : areg
;
165 /* Read Xtensa register directly from the hardware. */
167 xtensa_read_register (int regnum
)
171 regcache_raw_read_unsigned (get_current_regcache (), regnum
, &value
);
172 return (unsigned long) value
;
175 /* Write Xtensa register directly to the hardware. */
177 xtensa_write_register (int regnum
, ULONGEST value
)
179 regcache_raw_write_unsigned (get_current_regcache (), regnum
, value
);
182 /* Return the window size of the previous call to the function from which we
185 This function is used to extract the return value after a called function
186 has returned to the caller. On Xtensa, the register that holds the return
187 value (from the perspective of the caller) depends on what call
188 instruction was used. For now, we are assuming that the call instruction
189 precedes the current address, so we simply analyze the call instruction.
190 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
191 method to call the inferior function. */
194 extract_call_winsize (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
196 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
201 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc
);
203 /* Read the previous instruction (should be a call[x]{4|8|12}. */
204 read_memory (pc
-3, buf
, 3);
205 insn
= extract_unsigned_integer (buf
, 3, byte_order
);
207 /* Decode call instruction:
209 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
210 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
212 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
213 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
215 if (byte_order
== BFD_ENDIAN_LITTLE
)
217 if (((insn
& 0xf) == 0x5) || ((insn
& 0xcf) == 0xc0))
218 winsize
= (insn
& 0x30) >> 2; /* 0, 4, 8, 12. */
222 if (((insn
>> 20) == 0x5) || (((insn
>> 16) & 0xf3) == 0x03))
223 winsize
= (insn
>> 16) & 0xc; /* 0, 4, 8, 12. */
229 /* REGISTER INFORMATION */
231 /* Find register by name. */
233 xtensa_find_register_by_name (struct gdbarch
*gdbarch
, const char *name
)
237 for (i
= 0; i
< gdbarch_num_regs (gdbarch
)
238 + gdbarch_num_pseudo_regs (gdbarch
);
241 if (strcasecmp (gdbarch_tdep (gdbarch
)->regmap
[i
].name
, name
) == 0)
247 /* Returns the name of a register. */
249 xtensa_register_name (struct gdbarch
*gdbarch
, int regnum
)
251 /* Return the name stored in the register map. */
252 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
)
253 + gdbarch_num_pseudo_regs (gdbarch
))
254 return gdbarch_tdep (gdbarch
)->regmap
[regnum
].name
;
256 internal_error (__FILE__
, __LINE__
, _("invalid register %d"), regnum
);
260 /* Return the type of a register. Create a new type, if necessary. */
263 xtensa_register_type (struct gdbarch
*gdbarch
, int regnum
)
265 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
267 /* Return signed integer for ARx and Ax registers. */
268 if ((regnum
>= tdep
->ar_base
269 && regnum
< tdep
->ar_base
+ tdep
->num_aregs
)
270 || (regnum
>= tdep
->a0_base
271 && regnum
< tdep
->a0_base
+ 16))
272 return builtin_type (gdbarch
)->builtin_int
;
274 if (regnum
== gdbarch_pc_regnum (gdbarch
)
275 || regnum
== tdep
->a0_base
+ 1)
276 return builtin_type (gdbarch
)->builtin_data_ptr
;
278 /* Return the stored type for all other registers. */
279 else if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
)
280 + gdbarch_num_pseudo_regs (gdbarch
))
282 xtensa_register_t
* reg
= &tdep
->regmap
[regnum
];
284 /* Set ctype for this register (only the first time). */
288 struct ctype_cache
*tp
;
289 int size
= reg
->byte_size
;
291 /* We always use the memory representation,
292 even if the register width is smaller. */
296 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint8
;
300 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint16
;
304 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint32
;
308 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint64
;
312 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint128
;
316 for (tp
= tdep
->type_entries
; tp
!= NULL
; tp
= tp
->next
)
317 if (tp
->size
== size
)
322 char *name
= xstrprintf ("int%d", size
* 8);
324 tp
= XNEW (struct ctype_cache
);
325 tp
->next
= tdep
->type_entries
;
326 tdep
->type_entries
= tp
;
329 = arch_integer_type (gdbarch
, size
* 8, 1, name
);
333 reg
->ctype
= tp
->virtual_type
;
339 internal_error (__FILE__
, __LINE__
, _("invalid register number %d"), regnum
);
344 /* Return the 'local' register number for stubs, dwarf2, etc.
345 The debugging information enumerates registers starting from 0 for A0
346 to n for An. So, we only have to add the base number for A0. */
349 xtensa_reg_to_regnum (struct gdbarch
*gdbarch
, int regnum
)
353 if (regnum
>= 0 && regnum
< 16)
354 return gdbarch_tdep (gdbarch
)->a0_base
+ regnum
;
357 i
< gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
359 if (regnum
== gdbarch_tdep (gdbarch
)->regmap
[i
].target_number
)
366 /* Write the bits of a masked register to the various registers.
367 Only the masked areas of these registers are modified; the other
368 fields are untouched. The size of masked registers is always less
369 than or equal to 32 bits. */
372 xtensa_register_write_masked (struct regcache
*regcache
,
373 xtensa_register_t
*reg
, const gdb_byte
*buffer
)
375 unsigned int value
[(XTENSA_MAX_REGISTER_SIZE
+ 3) / 4];
376 const xtensa_mask_t
*mask
= reg
->mask
;
378 int shift
= 0; /* Shift for next mask (mod 32). */
379 int start
, size
; /* Start bit and size of current mask. */
381 unsigned int *ptr
= value
;
382 unsigned int regval
, m
, mem
= 0;
384 int bytesize
= reg
->byte_size
;
385 int bitsize
= bytesize
* 8;
388 DEBUGTRACE ("xtensa_register_write_masked ()\n");
390 /* Copy the masked register to host byte-order. */
391 if (gdbarch_byte_order (get_regcache_arch (regcache
)) == BFD_ENDIAN_BIG
)
392 for (i
= 0; i
< bytesize
; i
++)
395 mem
|= (buffer
[bytesize
- i
- 1] << 24);
400 for (i
= 0; i
< bytesize
; i
++)
403 mem
|= (buffer
[i
] << 24);
408 /* We might have to shift the final value:
409 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
410 bytesize & 3 == x -> shift (4-x) * 8. */
412 *ptr
= mem
>> (((0 - bytesize
) & 3) * 8);
416 /* Write the bits to the masked areas of the other registers. */
417 for (i
= 0; i
< mask
->count
; i
++)
419 start
= mask
->mask
[i
].bit_start
;
420 size
= mask
->mask
[i
].bit_size
;
421 regval
= mem
>> shift
;
423 if ((shift
+= size
) > bitsize
)
424 error (_("size of all masks is larger than the register"));
433 regval
|= mem
<< (size
- shift
);
436 /* Make sure we have a valid register. */
437 r
= mask
->mask
[i
].reg_num
;
438 if (r
>= 0 && size
> 0)
440 /* Don't overwrite the unmasked areas. */
442 regcache_cooked_read_unsigned (regcache
, r
, &old_val
);
443 m
= 0xffffffff >> (32 - size
) << start
;
445 regval
= (regval
& m
) | (old_val
& ~m
);
446 regcache_cooked_write_unsigned (regcache
, r
, regval
);
452 /* Read a tie state or mapped registers. Read the masked areas
453 of the registers and assemble them into a single value. */
455 static enum register_status
456 xtensa_register_read_masked (struct regcache
*regcache
,
457 xtensa_register_t
*reg
, gdb_byte
*buffer
)
459 unsigned int value
[(XTENSA_MAX_REGISTER_SIZE
+ 3) / 4];
460 const xtensa_mask_t
*mask
= reg
->mask
;
465 unsigned int *ptr
= value
;
466 unsigned int regval
, mem
= 0;
468 int bytesize
= reg
->byte_size
;
469 int bitsize
= bytesize
* 8;
472 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
473 reg
->name
== 0 ? "" : reg
->name
);
475 /* Assemble the register from the masked areas of other registers. */
476 for (i
= 0; i
< mask
->count
; i
++)
478 int r
= mask
->mask
[i
].reg_num
;
481 enum register_status status
;
484 status
= regcache_cooked_read_unsigned (regcache
, r
, &val
);
485 if (status
!= REG_VALID
)
487 regval
= (unsigned int) val
;
492 start
= mask
->mask
[i
].bit_start
;
493 size
= mask
->mask
[i
].bit_size
;
498 regval
&= (0xffffffff >> (32 - size
));
500 mem
|= regval
<< shift
;
502 if ((shift
+= size
) > bitsize
)
503 error (_("size of all masks is larger than the register"));
514 mem
= regval
>> (size
- shift
);
521 /* Copy value to target byte order. */
525 if (gdbarch_byte_order (get_regcache_arch (regcache
)) == BFD_ENDIAN_BIG
)
526 for (i
= 0; i
< bytesize
; i
++)
530 buffer
[bytesize
- i
- 1] = mem
& 0xff;
534 for (i
= 0; i
< bytesize
; i
++)
538 buffer
[i
] = mem
& 0xff;
546 /* Read pseudo registers. */
548 static enum register_status
549 xtensa_pseudo_register_read (struct gdbarch
*gdbarch
,
550 struct regcache
*regcache
,
554 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
556 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
557 regnum
, xtensa_register_name (gdbarch
, regnum
));
559 /* Read aliases a0..a15, if this is a Windowed ABI. */
560 if (gdbarch_tdep (gdbarch
)->isa_use_windowed_registers
561 && (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
)
562 && (regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15))
565 enum register_status status
;
567 status
= regcache_raw_read_unsigned (regcache
,
568 gdbarch_tdep (gdbarch
)->wb_regnum
,
570 if (status
!= REG_VALID
)
572 regnum
= arreg_number (gdbarch
, regnum
, value
);
575 /* We can always read non-pseudo registers. */
576 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
577 return regcache_raw_read (regcache
, regnum
, buffer
);
579 /* We have to find out how to deal with priveleged registers.
580 Let's treat them as pseudo-registers, but we cannot read/write them. */
582 else if (gdbarch_tdep (gdbarch
)->call_abi
== CallAbiCall0Only
583 || regnum
< gdbarch_tdep (gdbarch
)->a0_base
)
585 buffer
[0] = (gdb_byte
)0;
586 buffer
[1] = (gdb_byte
)0;
587 buffer
[2] = (gdb_byte
)0;
588 buffer
[3] = (gdb_byte
)0;
591 /* Pseudo registers. */
593 && regnum
< gdbarch_num_regs (gdbarch
)
594 + gdbarch_num_pseudo_regs (gdbarch
))
596 xtensa_register_t
*reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
597 xtensa_register_type_t type
= reg
->type
;
598 int flags
= gdbarch_tdep (gdbarch
)->target_flags
;
600 /* We cannot read Unknown or Unmapped registers. */
601 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
603 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
605 warning (_("cannot read register %s"),
606 xtensa_register_name (gdbarch
, regnum
));
611 /* Some targets cannot read TIE register files. */
612 else if (type
== xtRegisterTypeTieRegfile
)
614 /* Use 'fetch' to get register? */
615 if (flags
& xtTargetFlagsUseFetchStore
)
617 warning (_("cannot read register"));
621 /* On some targets (esp. simulators), we can always read the reg. */
622 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
624 warning (_("cannot read register"));
629 /* We can always read mapped registers. */
630 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
631 return xtensa_register_read_masked (regcache
, reg
, buffer
);
633 /* Assume that we can read the register. */
634 return regcache_raw_read (regcache
, regnum
, buffer
);
637 internal_error (__FILE__
, __LINE__
,
638 _("invalid register number %d"), regnum
);
642 /* Write pseudo registers. */
645 xtensa_pseudo_register_write (struct gdbarch
*gdbarch
,
646 struct regcache
*regcache
,
648 const gdb_byte
*buffer
)
650 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
652 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
653 regnum
, xtensa_register_name (gdbarch
, regnum
));
655 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
656 if (gdbarch_tdep (gdbarch
)->isa_use_windowed_registers
657 && (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
)
658 && (regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15))
661 regcache_raw_read_unsigned (regcache
,
662 gdbarch_tdep (gdbarch
)->wb_regnum
, &value
);
663 regnum
= arreg_number (gdbarch
, regnum
, value
);
666 /* We can always write 'core' registers.
667 Note: We might have converted Ax->ARy. */
668 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
669 regcache_raw_write (regcache
, regnum
, buffer
);
671 /* We have to find out how to deal with priveleged registers.
672 Let's treat them as pseudo-registers, but we cannot read/write them. */
674 else if (regnum
< gdbarch_tdep (gdbarch
)->a0_base
)
678 /* Pseudo registers. */
680 && regnum
< gdbarch_num_regs (gdbarch
)
681 + gdbarch_num_pseudo_regs (gdbarch
))
683 xtensa_register_t
*reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
684 xtensa_register_type_t type
= reg
->type
;
685 int flags
= gdbarch_tdep (gdbarch
)->target_flags
;
687 /* On most targets, we cannot write registers
688 of type "Unknown" or "Unmapped". */
689 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
691 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
693 warning (_("cannot write register %s"),
694 xtensa_register_name (gdbarch
, regnum
));
699 /* Some targets cannot read TIE register files. */
700 else if (type
== xtRegisterTypeTieRegfile
)
702 /* Use 'store' to get register? */
703 if (flags
& xtTargetFlagsUseFetchStore
)
705 warning (_("cannot write register"));
709 /* On some targets (esp. simulators), we can always write
711 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
713 warning (_("cannot write register"));
718 /* We can always write mapped registers. */
719 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
721 xtensa_register_write_masked (regcache
, reg
, buffer
);
725 /* Assume that we can write the register. */
726 regcache_raw_write (regcache
, regnum
, buffer
);
729 internal_error (__FILE__
, __LINE__
,
730 _("invalid register number %d"), regnum
);
733 static struct reggroup
*xtensa_ar_reggroup
;
734 static struct reggroup
*xtensa_user_reggroup
;
735 static struct reggroup
*xtensa_vectra_reggroup
;
736 static struct reggroup
*xtensa_cp
[XTENSA_MAX_COPROCESSOR
];
739 xtensa_init_reggroups (void)
743 xtensa_ar_reggroup
= reggroup_new ("ar", USER_REGGROUP
);
744 xtensa_user_reggroup
= reggroup_new ("user", USER_REGGROUP
);
745 xtensa_vectra_reggroup
= reggroup_new ("vectra", USER_REGGROUP
);
747 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
748 xtensa_cp
[i
] = reggroup_new (xstrprintf ("cp%d", i
), USER_REGGROUP
);
752 xtensa_add_reggroups (struct gdbarch
*gdbarch
)
756 /* Predefined groups. */
757 reggroup_add (gdbarch
, all_reggroup
);
758 reggroup_add (gdbarch
, save_reggroup
);
759 reggroup_add (gdbarch
, restore_reggroup
);
760 reggroup_add (gdbarch
, system_reggroup
);
761 reggroup_add (gdbarch
, vector_reggroup
);
762 reggroup_add (gdbarch
, general_reggroup
);
763 reggroup_add (gdbarch
, float_reggroup
);
765 /* Xtensa-specific groups. */
766 reggroup_add (gdbarch
, xtensa_ar_reggroup
);
767 reggroup_add (gdbarch
, xtensa_user_reggroup
);
768 reggroup_add (gdbarch
, xtensa_vectra_reggroup
);
770 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
771 reggroup_add (gdbarch
, xtensa_cp
[i
]);
775 xtensa_coprocessor_register_group (struct reggroup
*group
)
779 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
780 if (group
== xtensa_cp
[i
])
786 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
787 | XTENSA_REGISTER_FLAGS_WRITABLE \
788 | XTENSA_REGISTER_FLAGS_VOLATILE)
790 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
791 | XTENSA_REGISTER_FLAGS_WRITABLE)
794 xtensa_register_reggroup_p (struct gdbarch
*gdbarch
,
796 struct reggroup
*group
)
798 xtensa_register_t
* reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
799 xtensa_register_type_t type
= reg
->type
;
800 xtensa_register_group_t rg
= reg
->group
;
803 if (group
== save_reggroup
)
804 /* Every single register should be included into the list of registers
805 to be watched for changes while using -data-list-changed-registers. */
808 /* First, skip registers that are not visible to this target
809 (unknown and unmapped registers when not using ISS). */
811 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
813 if (group
== all_reggroup
)
815 if (group
== xtensa_ar_reggroup
)
816 return rg
& xtRegisterGroupAddrReg
;
817 if (group
== xtensa_user_reggroup
)
818 return rg
& xtRegisterGroupUser
;
819 if (group
== float_reggroup
)
820 return rg
& xtRegisterGroupFloat
;
821 if (group
== general_reggroup
)
822 return rg
& xtRegisterGroupGeneral
;
823 if (group
== system_reggroup
)
824 return rg
& xtRegisterGroupState
;
825 if (group
== vector_reggroup
|| group
== xtensa_vectra_reggroup
)
826 return rg
& xtRegisterGroupVectra
;
827 if (group
== restore_reggroup
)
828 return (regnum
< gdbarch_num_regs (gdbarch
)
829 && (reg
->flags
& SAVE_REST_FLAGS
) == SAVE_REST_VALID
);
830 cp_number
= xtensa_coprocessor_register_group (group
);
832 return rg
& (xtRegisterGroupCP0
<< cp_number
);
838 /* Supply register REGNUM from the buffer specified by GREGS and LEN
839 in the general-purpose register set REGSET to register cache
840 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
843 xtensa_supply_gregset (const struct regset
*regset
,
849 const xtensa_elf_gregset_t
*regs
= (const xtensa_elf_gregset_t
*) gregs
;
850 struct gdbarch
*gdbarch
= get_regcache_arch (rc
);
853 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum
);
855 if (regnum
== gdbarch_pc_regnum (gdbarch
) || regnum
== -1)
856 regcache_raw_supply (rc
, gdbarch_pc_regnum (gdbarch
), (char *) ®s
->pc
);
857 if (regnum
== gdbarch_ps_regnum (gdbarch
) || regnum
== -1)
858 regcache_raw_supply (rc
, gdbarch_ps_regnum (gdbarch
), (char *) ®s
->ps
);
859 if (regnum
== gdbarch_tdep (gdbarch
)->wb_regnum
|| regnum
== -1)
860 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->wb_regnum
,
861 (char *) ®s
->windowbase
);
862 if (regnum
== gdbarch_tdep (gdbarch
)->ws_regnum
|| regnum
== -1)
863 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->ws_regnum
,
864 (char *) ®s
->windowstart
);
865 if (regnum
== gdbarch_tdep (gdbarch
)->lbeg_regnum
|| regnum
== -1)
866 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lbeg_regnum
,
867 (char *) ®s
->lbeg
);
868 if (regnum
== gdbarch_tdep (gdbarch
)->lend_regnum
|| regnum
== -1)
869 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lend_regnum
,
870 (char *) ®s
->lend
);
871 if (regnum
== gdbarch_tdep (gdbarch
)->lcount_regnum
|| regnum
== -1)
872 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lcount_regnum
,
873 (char *) ®s
->lcount
);
874 if (regnum
== gdbarch_tdep (gdbarch
)->sar_regnum
|| regnum
== -1)
875 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->sar_regnum
,
876 (char *) ®s
->sar
);
877 if (regnum
>=gdbarch_tdep (gdbarch
)->ar_base
878 && regnum
< gdbarch_tdep (gdbarch
)->ar_base
879 + gdbarch_tdep (gdbarch
)->num_aregs
)
880 regcache_raw_supply (rc
, regnum
,
881 (char *) ®s
->ar
[regnum
- gdbarch_tdep
882 (gdbarch
)->ar_base
]);
883 else if (regnum
== -1)
885 for (i
= 0; i
< gdbarch_tdep (gdbarch
)->num_aregs
; ++i
)
886 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->ar_base
+ i
,
887 (char *) ®s
->ar
[i
]);
892 /* Xtensa register set. */
898 xtensa_supply_gregset
902 /* Iterate over supported core file register note sections. */
905 xtensa_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
906 iterate_over_regset_sections_cb
*cb
,
908 const struct regcache
*regcache
)
910 DEBUGTRACE ("xtensa_iterate_over_regset_sections\n");
912 cb (".reg", sizeof (xtensa_elf_gregset_t
), &xtensa_gregset
,
917 /* Handling frames. */
919 /* Number of registers to save in case of Windowed ABI. */
920 #define XTENSA_NUM_SAVED_AREGS 12
922 /* Frame cache part for Windowed ABI. */
923 typedef struct xtensa_windowed_frame_cache
925 int wb
; /* WINDOWBASE of the previous frame. */
926 int callsize
; /* Call size of this frame. */
927 int ws
; /* WINDOWSTART of the previous frame. It keeps track of
928 life windows only. If there is no bit set for the
929 window, that means it had been already spilled
930 because of window overflow. */
932 /* Addresses of spilled A-registers.
933 AREGS[i] == -1, if corresponding AR is alive. */
934 CORE_ADDR aregs
[XTENSA_NUM_SAVED_AREGS
];
935 } xtensa_windowed_frame_cache_t
;
937 /* Call0 ABI Definitions. */
939 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue
941 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
942 #define C0_SP 1 /* Register used as SP. */
943 #define C0_FP 15 /* Register used as FP. */
944 #define C0_RA 0 /* Register used as return address. */
945 #define C0_ARGS 2 /* Register used as first arg/retval. */
946 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
948 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
949 A-register where the current content of the reg came from (in terms
950 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
951 mean that the orignal content of the register was saved to the stack.
952 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
953 know where SP will end up until the entire prologue has been analyzed. */
955 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
956 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
957 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
959 extern xtensa_isa xtensa_default_isa
;
961 typedef struct xtensa_c0reg
963 int fr_reg
; /* original register from which register content
964 is derived, or C0_CONST, or C0_INEXP. */
965 int fr_ofs
; /* constant offset from reg, or immediate value. */
966 int to_stk
; /* offset from original SP to register (4-byte aligned),
967 or C0_NOSTK if register has not been saved. */
970 /* Frame cache part for Call0 ABI. */
971 typedef struct xtensa_call0_frame_cache
973 int c0_frmsz
; /* Stack frame size. */
974 int c0_hasfp
; /* Current frame uses frame pointer. */
975 int fp_regnum
; /* A-register used as FP. */
976 int c0_fp
; /* Actual value of frame pointer. */
977 int c0_fpalign
; /* Dinamic adjustment for the stack
978 pointer. It's an AND mask. Zero,
979 if alignment was not adjusted. */
980 int c0_old_sp
; /* In case of dynamic adjustment, it is
981 a register holding unaligned sp.
982 C0_INEXP, when undefined. */
983 int c0_sp_ofs
; /* If "c0_old_sp" was spilled it's a
984 stack offset. C0_NOSTK otherwise. */
986 xtensa_c0reg_t c0_rt
[C0_NREGS
]; /* Register tracking information. */
987 } xtensa_call0_frame_cache_t
;
989 typedef struct xtensa_frame_cache
991 CORE_ADDR base
; /* Stack pointer of this frame. */
992 CORE_ADDR pc
; /* PC of this frame at the function entry point. */
993 CORE_ADDR ra
; /* The raw return address of this frame. */
994 CORE_ADDR ps
; /* The PS register of the previous (older) frame. */
995 CORE_ADDR prev_sp
; /* Stack Pointer of the previous (older) frame. */
996 int call0
; /* It's a call0 framework (else windowed). */
999 xtensa_windowed_frame_cache_t wd
; /* call0 == false. */
1000 xtensa_call0_frame_cache_t c0
; /* call0 == true. */
1002 } xtensa_frame_cache_t
;
1005 static struct xtensa_frame_cache
*
1006 xtensa_alloc_frame_cache (int windowed
)
1008 xtensa_frame_cache_t
*cache
;
1011 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
1013 cache
= FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t
);
1020 cache
->call0
= !windowed
;
1023 cache
->c0
.c0_frmsz
= -1;
1024 cache
->c0
.c0_hasfp
= 0;
1025 cache
->c0
.fp_regnum
= -1;
1026 cache
->c0
.c0_fp
= -1;
1027 cache
->c0
.c0_fpalign
= 0;
1028 cache
->c0
.c0_old_sp
= C0_INEXP
;
1029 cache
->c0
.c0_sp_ofs
= C0_NOSTK
;
1031 for (i
= 0; i
< C0_NREGS
; i
++)
1033 cache
->c0
.c0_rt
[i
].fr_reg
= i
;
1034 cache
->c0
.c0_rt
[i
].fr_ofs
= 0;
1035 cache
->c0
.c0_rt
[i
].to_stk
= C0_NOSTK
;
1042 cache
->wd
.callsize
= -1;
1044 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
1045 cache
->wd
.aregs
[i
] = -1;
1052 xtensa_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
1054 return address
& ~15;
1059 xtensa_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1064 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1065 host_address_to_string (next_frame
));
1067 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1068 pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1070 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc
);
1076 static struct frame_id
1077 xtensa_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1081 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1083 pc
= get_frame_pc (this_frame
);
1084 fp
= get_frame_register_unsigned
1085 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1087 /* Make dummy frame ID unique by adding a constant. */
1088 return frame_id_build (fp
+ SP_ALIGNMENT
, pc
);
1091 /* Returns true, if instruction to execute next is unique to Xtensa Window
1092 Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
1095 xtensa_window_interrupt_insn (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1097 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1098 unsigned int insn
= read_memory_integer (pc
, 4, byte_order
);
1101 if (byte_order
== BFD_ENDIAN_BIG
)
1103 /* Check, if this is L32E or S32E. */
1104 code
= insn
& 0xf000ff00;
1105 if ((code
== 0x00009000) || (code
== 0x00009400))
1107 /* Check, if this is RFWU or RFWO. */
1108 code
= insn
& 0xffffff00;
1109 return ((code
== 0x00430000) || (code
== 0x00530000));
1113 /* Check, if this is L32E or S32E. */
1114 code
= insn
& 0x00ff000f;
1115 if ((code
== 0x090000) || (code
== 0x490000))
1117 /* Check, if this is RFWU or RFWO. */
1118 code
= insn
& 0x00ffffff;
1119 return ((code
== 0x00003400) || (code
== 0x00003500));
1123 /* Returns the best guess about which register is a frame pointer
1124 for the function containing CURRENT_PC. */
1126 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1127 #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1130 xtensa_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
)
1132 #define RETURN_FP goto done
1134 unsigned int fp_regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ 1;
1135 CORE_ADDR start_addr
;
1137 xtensa_insnbuf ins
, slot
;
1138 gdb_byte ibuf
[XTENSA_ISA_BSZ
];
1139 CORE_ADDR ia
, bt
, ba
;
1141 int ilen
, islots
, is
;
1143 const char *opcname
;
1145 find_pc_partial_function (current_pc
, NULL
, &start_addr
, NULL
);
1146 if (start_addr
== 0)
1149 isa
= xtensa_default_isa
;
1150 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
1151 ins
= xtensa_insnbuf_alloc (isa
);
1152 slot
= xtensa_insnbuf_alloc (isa
);
1155 for (ia
= start_addr
, bt
= ia
; ia
< current_pc
; ia
+= ilen
)
1157 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
1160 bt
= (ba
+ XTENSA_ISA_BSZ
) < current_pc
1161 ? ba
+ XTENSA_ISA_BSZ
: current_pc
;
1162 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0)
1166 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
1167 ifmt
= xtensa_format_decode (isa
, ins
);
1168 if (ifmt
== XTENSA_UNDEFINED
)
1170 ilen
= xtensa_format_length (isa
, ifmt
);
1171 if (ilen
== XTENSA_UNDEFINED
)
1173 islots
= xtensa_format_num_slots (isa
, ifmt
);
1174 if (islots
== XTENSA_UNDEFINED
)
1177 for (is
= 0; is
< islots
; ++is
)
1179 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
1182 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
1183 if (opc
== XTENSA_UNDEFINED
)
1186 opcname
= xtensa_opcode_name (isa
, opc
);
1188 if (strcasecmp (opcname
, "mov.n") == 0
1189 || strcasecmp (opcname
, "or") == 0)
1191 unsigned int register_operand
;
1193 /* Possible candidate for setting frame pointer
1194 from A1. This is what we are looking for. */
1196 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
,
1197 is
, slot
, ®ister_operand
) != 0)
1199 if (xtensa_operand_decode (isa
, opc
, 1, ®ister_operand
) != 0)
1201 if (register_operand
== 1) /* Mov{.n} FP A1. */
1203 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
,
1204 ®ister_operand
) != 0)
1206 if (xtensa_operand_decode (isa
, opc
, 0,
1207 ®ister_operand
) != 0)
1211 = gdbarch_tdep (gdbarch
)->a0_base
+ register_operand
;
1217 /* We have problems decoding the memory. */
1219 || strcasecmp (opcname
, "ill") == 0
1220 || strcasecmp (opcname
, "ill.n") == 0
1221 /* Hit planted breakpoint. */
1222 || strcasecmp (opcname
, "break") == 0
1223 || strcasecmp (opcname
, "break.n") == 0
1224 /* Flow control instructions finish prologue. */
1225 || xtensa_opcode_is_branch (isa
, opc
) > 0
1226 || xtensa_opcode_is_jump (isa
, opc
) > 0
1227 || xtensa_opcode_is_loop (isa
, opc
) > 0
1228 || xtensa_opcode_is_call (isa
, opc
) > 0
1229 || strcasecmp (opcname
, "simcall") == 0
1230 || strcasecmp (opcname
, "syscall") == 0)
1231 /* Can not continue analysis. */
1236 xtensa_insnbuf_free(isa
, slot
);
1237 xtensa_insnbuf_free(isa
, ins
);
1241 /* The key values to identify the frame using "cache" are
1243 cache->base = SP (or best guess about FP) of this frame;
1244 cache->pc = entry-PC (entry point of the frame function);
1245 cache->prev_sp = SP of the previous frame. */
1248 call0_frame_cache (struct frame_info
*this_frame
,
1249 xtensa_frame_cache_t
*cache
, CORE_ADDR pc
);
1252 xtensa_window_interrupt_frame_cache (struct frame_info
*this_frame
,
1253 xtensa_frame_cache_t
*cache
,
1256 static struct xtensa_frame_cache
*
1257 xtensa_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1259 xtensa_frame_cache_t
*cache
;
1260 CORE_ADDR ra
, wb
, ws
, pc
, sp
, ps
;
1261 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1262 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1263 unsigned int fp_regnum
;
1264 int windowed
, ps_regnum
;
1267 return (struct xtensa_frame_cache
*) *this_cache
;
1269 pc
= get_frame_register_unsigned (this_frame
, gdbarch_pc_regnum (gdbarch
));
1270 ps_regnum
= gdbarch_ps_regnum (gdbarch
);
1271 ps
= (ps_regnum
>= 0
1272 ? get_frame_register_unsigned (this_frame
, ps_regnum
) : TX_PS
);
1274 windowed
= windowing_enabled (gdbarch
, ps
);
1276 /* Get pristine xtensa-frame. */
1277 cache
= xtensa_alloc_frame_cache (windowed
);
1278 *this_cache
= cache
;
1284 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1285 wb
= get_frame_register_unsigned (this_frame
,
1286 gdbarch_tdep (gdbarch
)->wb_regnum
);
1287 ws
= get_frame_register_unsigned (this_frame
,
1288 gdbarch_tdep (gdbarch
)->ws_regnum
);
1290 if (safe_read_memory_integer (pc
, 1, byte_order
, &op1
)
1291 && XTENSA_IS_ENTRY (gdbarch
, op1
))
1293 int callinc
= CALLINC (ps
);
1294 ra
= get_frame_register_unsigned
1295 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ callinc
* 4);
1297 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1298 cache
->wd
.callsize
= 0;
1301 cache
->prev_sp
= get_frame_register_unsigned
1302 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1304 /* This only can be the outermost frame since we are
1305 just about to execute ENTRY. SP hasn't been set yet.
1306 We can assume any frame size, because it does not
1307 matter, and, let's fake frame base in cache. */
1308 cache
->base
= cache
->prev_sp
- 16;
1311 cache
->ra
= (cache
->pc
& 0xc0000000) | (ra
& 0x3fffffff);
1312 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1313 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1319 fp_regnum
= xtensa_scan_prologue (gdbarch
, pc
);
1320 ra
= get_frame_register_unsigned (this_frame
,
1321 gdbarch_tdep (gdbarch
)->a0_base
);
1322 cache
->wd
.callsize
= WINSIZE (ra
);
1323 cache
->wd
.wb
= (wb
- cache
->wd
.callsize
/ 4)
1324 & (gdbarch_tdep (gdbarch
)->num_aregs
/ 4 - 1);
1325 cache
->wd
.ws
= ws
& ~(1 << wb
);
1327 cache
->pc
= get_frame_func (this_frame
);
1328 cache
->ra
= (pc
& 0xc0000000) | (ra
& 0x3fffffff);
1329 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1330 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1333 if (cache
->wd
.ws
== 0)
1338 sp
= get_frame_register_unsigned
1339 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1) - 16;
1341 for (i
= 0; i
< 4; i
++, sp
+= 4)
1343 cache
->wd
.aregs
[i
] = sp
;
1346 if (cache
->wd
.callsize
> 4)
1348 /* Set A4...A7/A11. */
1349 /* Get the SP of the frame previous to the previous one.
1350 To achieve this, we have to dereference SP twice. */
1351 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4, byte_order
);
1352 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4, byte_order
);
1353 sp
-= cache
->wd
.callsize
* 4;
1355 for ( i
= 4; i
< cache
->wd
.callsize
; i
++, sp
+= 4)
1357 cache
->wd
.aregs
[i
] = sp
;
1362 if ((cache
->prev_sp
== 0) && ( ra
!= 0 ))
1363 /* If RA is equal to 0 this frame is an outermost frame. Leave
1364 cache->prev_sp unchanged marking the boundary of the frame stack. */
1366 if ((cache
->wd
.ws
& (1 << cache
->wd
.wb
)) == 0)
1368 /* Register window overflow already happened.
1369 We can read caller's SP from the proper spill loction. */
1370 sp
= get_frame_register_unsigned
1371 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1372 cache
->prev_sp
= read_memory_integer (sp
- 12, 4, byte_order
);
1376 /* Read caller's frame SP directly from the previous window. */
1377 int regnum
= arreg_number
1378 (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ 1,
1381 cache
->prev_sp
= xtensa_read_register (regnum
);
1385 else if (xtensa_window_interrupt_insn (gdbarch
, pc
))
1387 /* Execution stopped inside Xtensa Window Interrupt Handler. */
1389 xtensa_window_interrupt_frame_cache (this_frame
, cache
, pc
);
1390 /* Everything was set already, including cache->base. */
1393 else /* Call0 framework. */
1395 call0_frame_cache (this_frame
, cache
, pc
);
1396 fp_regnum
= cache
->c0
.fp_regnum
;
1399 cache
->base
= get_frame_register_unsigned (this_frame
, fp_regnum
);
1404 static int xtensa_session_once_reported
= 1;
1406 /* Report a problem with prologue analysis while doing backtracing.
1407 But, do it only once to avoid annoyng repeated messages. */
1412 if (xtensa_session_once_reported
== 0)
1414 \nUnrecognised function prologue. Stack trace cannot be resolved. \
1415 This message will not be repeated in this session.\n"));
1417 xtensa_session_once_reported
= 1;
1422 xtensa_frame_this_id (struct frame_info
*this_frame
,
1424 struct frame_id
*this_id
)
1426 struct xtensa_frame_cache
*cache
=
1427 xtensa_frame_cache (this_frame
, this_cache
);
1429 if (cache
->prev_sp
== 0)
1432 (*this_id
) = frame_id_build (cache
->prev_sp
, cache
->pc
);
1435 static struct value
*
1436 xtensa_frame_prev_register (struct frame_info
*this_frame
,
1440 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1441 struct xtensa_frame_cache
*cache
;
1442 ULONGEST saved_reg
= 0;
1445 if (*this_cache
== NULL
)
1446 *this_cache
= xtensa_frame_cache (this_frame
, this_cache
);
1447 cache
= (struct xtensa_frame_cache
*) *this_cache
;
1449 if (regnum
==gdbarch_pc_regnum (gdbarch
))
1450 saved_reg
= cache
->ra
;
1451 else if (regnum
== gdbarch_tdep (gdbarch
)->a0_base
+ 1)
1452 saved_reg
= cache
->prev_sp
;
1453 else if (!cache
->call0
)
1455 if (regnum
== gdbarch_tdep (gdbarch
)->ws_regnum
)
1456 saved_reg
= cache
->wd
.ws
;
1457 else if (regnum
== gdbarch_tdep (gdbarch
)->wb_regnum
)
1458 saved_reg
= cache
->wd
.wb
;
1459 else if (regnum
== gdbarch_ps_regnum (gdbarch
))
1460 saved_reg
= cache
->ps
;
1468 return frame_unwind_got_constant (this_frame
, regnum
, saved_reg
);
1470 if (!cache
->call0
) /* Windowed ABI. */
1472 /* Convert A-register numbers to AR-register numbers,
1473 if we deal with A-register. */
1474 if (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
1475 && regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15)
1476 regnum
= arreg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1478 /* Check, if we deal with AR-register saved on stack. */
1479 if (regnum
>= gdbarch_tdep (gdbarch
)->ar_base
1480 && regnum
<= (gdbarch_tdep (gdbarch
)->ar_base
1481 + gdbarch_tdep (gdbarch
)->num_aregs
))
1483 int areg
= areg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1486 && areg
< XTENSA_NUM_SAVED_AREGS
1487 && cache
->wd
.aregs
[areg
] != -1)
1488 return frame_unwind_got_memory (this_frame
, regnum
,
1489 cache
->wd
.aregs
[areg
]);
1492 else /* Call0 ABI. */
1494 int reg
= (regnum
>= gdbarch_tdep (gdbarch
)->ar_base
1495 && regnum
<= (gdbarch_tdep (gdbarch
)->ar_base
1497 ? regnum
- gdbarch_tdep (gdbarch
)->ar_base
: regnum
;
1504 /* If register was saved in the prologue, retrieve it. */
1505 stkofs
= cache
->c0
.c0_rt
[reg
].to_stk
;
1506 if (stkofs
!= C0_NOSTK
)
1508 /* Determine SP on entry based on FP. */
1509 spe
= cache
->c0
.c0_fp
1510 - cache
->c0
.c0_rt
[cache
->c0
.fp_regnum
].fr_ofs
;
1512 return frame_unwind_got_memory (this_frame
, regnum
,
1518 /* All other registers have been either saved to
1519 the stack or are still alive in the processor. */
1521 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1525 static const struct frame_unwind
1529 default_frame_unwind_stop_reason
,
1530 xtensa_frame_this_id
,
1531 xtensa_frame_prev_register
,
1533 default_frame_sniffer
1537 xtensa_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1539 struct xtensa_frame_cache
*cache
=
1540 xtensa_frame_cache (this_frame
, this_cache
);
1545 static const struct frame_base
1549 xtensa_frame_base_address
,
1550 xtensa_frame_base_address
,
1551 xtensa_frame_base_address
1556 xtensa_extract_return_value (struct type
*type
,
1557 struct regcache
*regcache
,
1560 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1561 bfd_byte
*valbuf
= (bfd_byte
*) dst
;
1562 int len
= TYPE_LENGTH (type
);
1567 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1569 gdb_assert(len
> 0);
1571 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1573 /* First, we have to find the caller window in the register file. */
1574 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1575 callsize
= extract_call_winsize (gdbarch
, pc
);
1577 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1578 if (len
> (callsize
> 8 ? 8 : 16))
1579 internal_error (__FILE__
, __LINE__
,
1580 _("cannot extract return value of %d bytes long"),
1583 /* Get the register offset of the return
1584 register (A2) in the caller window. */
1585 regcache_raw_read_unsigned
1586 (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, &wb
);
1587 areg
= arreg_number (gdbarch
,
1588 gdbarch_tdep (gdbarch
)->a0_base
+ 2 + callsize
, wb
);
1592 /* No windowing hardware - Call0 ABI. */
1593 areg
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_ARGS
;
1596 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg
, len
);
1598 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1601 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1604 regcache_raw_read_part (regcache
, areg
, offset
, len
, valbuf
);
1606 regcache_raw_read (regcache
, areg
, valbuf
);
1612 xtensa_store_return_value (struct type
*type
,
1613 struct regcache
*regcache
,
1616 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1617 const bfd_byte
*valbuf
= (const bfd_byte
*) dst
;
1621 int len
= TYPE_LENGTH (type
);
1624 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1626 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1628 regcache_raw_read_unsigned
1629 (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, &wb
);
1630 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1631 callsize
= extract_call_winsize (gdbarch
, pc
);
1633 if (len
> (callsize
> 8 ? 8 : 16))
1634 internal_error (__FILE__
, __LINE__
,
1635 _("unimplemented for this length: %d"),
1636 TYPE_LENGTH (type
));
1637 areg
= arreg_number (gdbarch
,
1638 gdbarch_tdep (gdbarch
)->a0_base
+ 2 + callsize
, wb
);
1640 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1641 callsize
, (int) wb
);
1645 areg
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_ARGS
;
1648 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1651 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1654 regcache_raw_write_part (regcache
, areg
, offset
, len
, valbuf
);
1656 regcache_raw_write (regcache
, areg
, valbuf
);
1661 static enum return_value_convention
1662 xtensa_return_value (struct gdbarch
*gdbarch
,
1663 struct value
*function
,
1664 struct type
*valtype
,
1665 struct regcache
*regcache
,
1667 const gdb_byte
*writebuf
)
1669 /* Structures up to 16 bytes are returned in registers. */
1671 int struct_return
= ((TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
1672 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
1673 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
1674 && TYPE_LENGTH (valtype
) > 16);
1677 return RETURN_VALUE_STRUCT_CONVENTION
;
1679 DEBUGTRACE ("xtensa_return_value(...)\n");
1681 if (writebuf
!= NULL
)
1683 xtensa_store_return_value (valtype
, regcache
, writebuf
);
1686 if (readbuf
!= NULL
)
1688 gdb_assert (!struct_return
);
1689 xtensa_extract_return_value (valtype
, regcache
, readbuf
);
1691 return RETURN_VALUE_REGISTER_CONVENTION
;
1698 xtensa_push_dummy_call (struct gdbarch
*gdbarch
,
1699 struct value
*function
,
1700 struct regcache
*regcache
,
1703 struct value
**args
,
1706 CORE_ADDR struct_addr
)
1708 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1710 int size
, onstack_size
;
1711 gdb_byte
*buf
= (gdb_byte
*) alloca (16);
1713 struct argument_info
1715 const bfd_byte
*contents
;
1717 int onstack
; /* onstack == 0 => in reg */
1718 int align
; /* alignment */
1721 int offset
; /* stack offset if on stack. */
1722 int regno
; /* regno if in register. */
1726 struct argument_info
*arg_info
=
1727 (struct argument_info
*) alloca (nargs
* sizeof (struct argument_info
));
1731 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1733 if (xtensa_debug_level
> 3)
1736 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs
);
1737 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1738 "struct_addr=0x%x\n",
1739 (int) sp
, (int) struct_return
, (int) struct_addr
);
1741 for (i
= 0; i
< nargs
; i
++)
1743 struct value
*arg
= args
[i
];
1744 struct type
*arg_type
= check_typedef (value_type (arg
));
1745 fprintf_unfiltered (gdb_stdlog
, "%2d: %s %3d ", i
,
1746 host_address_to_string (arg
),
1747 TYPE_LENGTH (arg_type
));
1748 switch (TYPE_CODE (arg_type
))
1751 fprintf_unfiltered (gdb_stdlog
, "int");
1753 case TYPE_CODE_STRUCT
:
1754 fprintf_unfiltered (gdb_stdlog
, "struct");
1757 fprintf_unfiltered (gdb_stdlog
, "%3d", TYPE_CODE (arg_type
));
1760 fprintf_unfiltered (gdb_stdlog
, " %s\n",
1761 host_address_to_string (value_contents (arg
)));
1765 /* First loop: collect information.
1766 Cast into type_long. (This shouldn't happen often for C because
1767 GDB already does this earlier.) It's possible that GDB could
1768 do it all the time but it's harmless to leave this code here. */
1775 size
= REGISTER_SIZE
;
1777 for (i
= 0; i
< nargs
; i
++)
1779 struct argument_info
*info
= &arg_info
[i
];
1780 struct value
*arg
= args
[i
];
1781 struct type
*arg_type
= check_typedef (value_type (arg
));
1783 switch (TYPE_CODE (arg_type
))
1786 case TYPE_CODE_BOOL
:
1787 case TYPE_CODE_CHAR
:
1788 case TYPE_CODE_RANGE
:
1789 case TYPE_CODE_ENUM
:
1791 /* Cast argument to long if necessary as the mask does it too. */
1792 if (TYPE_LENGTH (arg_type
)
1793 < TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
))
1795 arg_type
= builtin_type (gdbarch
)->builtin_long
;
1796 arg
= value_cast (arg_type
, arg
);
1798 /* Aligment is equal to the type length for the basic types. */
1799 info
->align
= TYPE_LENGTH (arg_type
);
1804 /* Align doubles correctly. */
1805 if (TYPE_LENGTH (arg_type
)
1806 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
))
1807 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
);
1809 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
);
1812 case TYPE_CODE_STRUCT
:
1814 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
);
1817 info
->length
= TYPE_LENGTH (arg_type
);
1818 info
->contents
= value_contents (arg
);
1820 /* Align size and onstack_size. */
1821 size
= (size
+ info
->align
- 1) & ~(info
->align
- 1);
1822 onstack_size
= (onstack_size
+ info
->align
- 1) & ~(info
->align
- 1);
1824 if (size
+ info
->length
> REGISTER_SIZE
* ARG_NOF (gdbarch
))
1827 info
->u
.offset
= onstack_size
;
1828 onstack_size
+= info
->length
;
1833 info
->u
.regno
= ARG_1ST (gdbarch
) + size
/ REGISTER_SIZE
;
1835 size
+= info
->length
;
1838 /* Adjust the stack pointer and align it. */
1839 sp
= align_down (sp
- onstack_size
, SP_ALIGNMENT
);
1841 /* Simulate MOVSP, if Windowed ABI. */
1842 if ((gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1845 read_memory (osp
- 16, buf
, 16);
1846 write_memory (sp
- 16, buf
, 16);
1849 /* Second Loop: Load arguments. */
1853 store_unsigned_integer (buf
, REGISTER_SIZE
, byte_order
, struct_addr
);
1854 regcache_cooked_write (regcache
, ARG_1ST (gdbarch
), buf
);
1857 for (i
= 0; i
< nargs
; i
++)
1859 struct argument_info
*info
= &arg_info
[i
];
1863 int n
= info
->length
;
1864 CORE_ADDR offset
= sp
+ info
->u
.offset
;
1866 /* Odd-sized structs are aligned to the lower side of a memory
1867 word in big-endian mode and require a shift. This only
1868 applies for structures smaller than one word. */
1870 if (n
< REGISTER_SIZE
1871 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1872 offset
+= (REGISTER_SIZE
- n
);
1874 write_memory (offset
, info
->contents
, info
->length
);
1879 int n
= info
->length
;
1880 const bfd_byte
*cp
= info
->contents
;
1881 int r
= info
->u
.regno
;
1883 /* Odd-sized structs are aligned to the lower side of registers in
1884 big-endian mode and require a shift. The odd-sized leftover will
1885 be at the end. Note that this is only true for structures smaller
1886 than REGISTER_SIZE; for larger odd-sized structures the excess
1887 will be left-aligned in the register on both endiannesses. */
1889 if (n
< REGISTER_SIZE
&& byte_order
== BFD_ENDIAN_BIG
)
1892 v
= extract_unsigned_integer (cp
, REGISTER_SIZE
, byte_order
);
1893 v
= v
>> ((REGISTER_SIZE
- n
) * TARGET_CHAR_BIT
);
1895 store_unsigned_integer (buf
, REGISTER_SIZE
, byte_order
, v
);
1896 regcache_cooked_write (regcache
, r
, buf
);
1898 cp
+= REGISTER_SIZE
;
1905 regcache_cooked_write (regcache
, r
, cp
);
1907 cp
+= REGISTER_SIZE
;
1914 /* Set the return address of dummy frame to the dummy address.
1915 The return address for the current function (in A0) is
1916 saved in the dummy frame, so we can savely overwrite A0 here. */
1918 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1922 ra
= (bp_addr
& 0x3fffffff) | 0x40000000;
1923 regcache_raw_read_unsigned (regcache
, gdbarch_ps_regnum (gdbarch
), &val
);
1924 ps
= (unsigned long) val
& ~0x00030000;
1925 regcache_cooked_write_unsigned
1926 (regcache
, gdbarch_tdep (gdbarch
)->a0_base
+ 4, ra
);
1927 regcache_cooked_write_unsigned (regcache
,
1928 gdbarch_ps_regnum (gdbarch
),
1931 /* All the registers have been saved. After executing
1932 dummy call, they all will be restored. So it's safe
1933 to modify WINDOWSTART register to make it look like there
1934 is only one register window corresponding to WINDOWEBASE. */
1936 regcache_raw_read (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, buf
);
1937 regcache_cooked_write_unsigned
1938 (regcache
, gdbarch_tdep (gdbarch
)->ws_regnum
,
1939 1 << extract_unsigned_integer (buf
, 4, byte_order
));
1943 /* Simulate CALL0: write RA into A0 register. */
1944 regcache_cooked_write_unsigned
1945 (regcache
, gdbarch_tdep (gdbarch
)->a0_base
, bp_addr
);
1948 /* Set new stack pointer and return it. */
1949 regcache_cooked_write_unsigned (regcache
,
1950 gdbarch_tdep (gdbarch
)->a0_base
+ 1, sp
);
1951 /* Make dummy frame ID unique by adding a constant. */
1952 return sp
+ SP_ALIGNMENT
;
1955 /* Implement the breakpoint_kind_from_pc gdbarch method. */
1958 xtensa_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
1960 if (gdbarch_tdep (gdbarch
)->isa_use_density_instructions
)
1966 /* Return a breakpoint for the current location of PC. We always use
1967 the density version if we have density instructions (regardless of the
1968 current instruction at PC), and use regular instructions otherwise. */
1970 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1971 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1972 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1973 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1975 /* Implement the sw_breakpoint_from_kind gdbarch method. */
1977 static const gdb_byte
*
1978 xtensa_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
1984 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
1985 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
1987 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1988 return big_breakpoint
;
1990 return little_breakpoint
;
1994 static unsigned char density_big_breakpoint
[] = DENSITY_BIG_BREAKPOINT
;
1995 static unsigned char density_little_breakpoint
[]
1996 = DENSITY_LITTLE_BREAKPOINT
;
1998 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1999 return density_big_breakpoint
;
2001 return density_little_breakpoint
;
2005 /* Call0 ABI support routines. */
2007 /* Return true, if PC points to "ret" or "ret.n". */
2010 call0_ret (CORE_ADDR start_pc
, CORE_ADDR finish_pc
)
2012 #define RETURN_RET goto done
2014 xtensa_insnbuf ins
, slot
;
2015 gdb_byte ibuf
[XTENSA_ISA_BSZ
];
2016 CORE_ADDR ia
, bt
, ba
;
2018 int ilen
, islots
, is
;
2020 const char *opcname
;
2023 isa
= xtensa_default_isa
;
2024 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2025 ins
= xtensa_insnbuf_alloc (isa
);
2026 slot
= xtensa_insnbuf_alloc (isa
);
2029 for (ia
= start_pc
, bt
= ia
; ia
< finish_pc
; ia
+= ilen
)
2031 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2034 bt
= (ba
+ XTENSA_ISA_BSZ
) < finish_pc
2035 ? ba
+ XTENSA_ISA_BSZ
: finish_pc
;
2036 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0 )
2040 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2041 ifmt
= xtensa_format_decode (isa
, ins
);
2042 if (ifmt
== XTENSA_UNDEFINED
)
2044 ilen
= xtensa_format_length (isa
, ifmt
);
2045 if (ilen
== XTENSA_UNDEFINED
)
2047 islots
= xtensa_format_num_slots (isa
, ifmt
);
2048 if (islots
== XTENSA_UNDEFINED
)
2051 for (is
= 0; is
< islots
; ++is
)
2053 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
2056 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2057 if (opc
== XTENSA_UNDEFINED
)
2060 opcname
= xtensa_opcode_name (isa
, opc
);
2062 if ((strcasecmp (opcname
, "ret.n") == 0)
2063 || (strcasecmp (opcname
, "ret") == 0))
2071 xtensa_insnbuf_free(isa
, slot
);
2072 xtensa_insnbuf_free(isa
, ins
);
2076 /* Call0 opcode class. Opcodes are preclassified according to what they
2077 mean for Call0 prologue analysis, and their number of significant operands.
2078 The purpose of this is to simplify prologue analysis by separating
2079 instruction decoding (libisa) from the semantics of prologue analysis. */
2083 c0opc_illegal
, /* Unknown to libisa (invalid) or 'ill' opcode. */
2084 c0opc_uninteresting
, /* Not interesting for Call0 prologue analysis. */
2085 c0opc_flow
, /* Flow control insn. */
2086 c0opc_entry
, /* ENTRY indicates non-Call0 prologue. */
2087 c0opc_break
, /* Debugger software breakpoints. */
2088 c0opc_add
, /* Adding two registers. */
2089 c0opc_addi
, /* Adding a register and an immediate. */
2090 c0opc_and
, /* Bitwise "and"-ing two registers. */
2091 c0opc_sub
, /* Subtracting a register from a register. */
2092 c0opc_mov
, /* Moving a register to a register. */
2093 c0opc_movi
, /* Moving an immediate to a register. */
2094 c0opc_l32r
, /* Loading a literal. */
2095 c0opc_s32i
, /* Storing word at fixed offset from a base register. */
2096 c0opc_rwxsr
, /* RSR, WRS, or XSR instructions. */
2097 c0opc_l32e
, /* L32E instruction. */
2098 c0opc_s32e
, /* S32E instruction. */
2099 c0opc_rfwo
, /* RFWO instruction. */
2100 c0opc_rfwu
, /* RFWU instruction. */
2101 c0opc_NrOf
/* Number of opcode classifications. */
2104 /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
2107 rwx_special_register (const char *opcname
)
2109 char ch
= *opcname
++;
2111 if ((ch
!= 'r') && (ch
!= 'w') && (ch
!= 'x'))
2113 if (*opcname
++ != 's')
2115 if (*opcname
++ != 'r')
2117 if (*opcname
++ != '.')
2123 /* Classify an opcode based on what it means for Call0 prologue analysis. */
2125 static xtensa_insn_kind
2126 call0_classify_opcode (xtensa_isa isa
, xtensa_opcode opc
)
2128 const char *opcname
;
2129 xtensa_insn_kind opclass
= c0opc_uninteresting
;
2131 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc
);
2133 /* Get opcode name and handle special classifications. */
2135 opcname
= xtensa_opcode_name (isa
, opc
);
2138 || strcasecmp (opcname
, "ill") == 0
2139 || strcasecmp (opcname
, "ill.n") == 0)
2140 opclass
= c0opc_illegal
;
2141 else if (strcasecmp (opcname
, "break") == 0
2142 || strcasecmp (opcname
, "break.n") == 0)
2143 opclass
= c0opc_break
;
2144 else if (strcasecmp (opcname
, "entry") == 0)
2145 opclass
= c0opc_entry
;
2146 else if (strcasecmp (opcname
, "rfwo") == 0)
2147 opclass
= c0opc_rfwo
;
2148 else if (strcasecmp (opcname
, "rfwu") == 0)
2149 opclass
= c0opc_rfwu
;
2150 else if (xtensa_opcode_is_branch (isa
, opc
) > 0
2151 || xtensa_opcode_is_jump (isa
, opc
) > 0
2152 || xtensa_opcode_is_loop (isa
, opc
) > 0
2153 || xtensa_opcode_is_call (isa
, opc
) > 0
2154 || strcasecmp (opcname
, "simcall") == 0
2155 || strcasecmp (opcname
, "syscall") == 0)
2156 opclass
= c0opc_flow
;
2158 /* Also, classify specific opcodes that need to be tracked. */
2159 else if (strcasecmp (opcname
, "add") == 0
2160 || strcasecmp (opcname
, "add.n") == 0)
2161 opclass
= c0opc_add
;
2162 else if (strcasecmp (opcname
, "and") == 0)
2163 opclass
= c0opc_and
;
2164 else if (strcasecmp (opcname
, "addi") == 0
2165 || strcasecmp (opcname
, "addi.n") == 0
2166 || strcasecmp (opcname
, "addmi") == 0)
2167 opclass
= c0opc_addi
;
2168 else if (strcasecmp (opcname
, "sub") == 0)
2169 opclass
= c0opc_sub
;
2170 else if (strcasecmp (opcname
, "mov.n") == 0
2171 || strcasecmp (opcname
, "or") == 0) /* Could be 'mov' asm macro. */
2172 opclass
= c0opc_mov
;
2173 else if (strcasecmp (opcname
, "movi") == 0
2174 || strcasecmp (opcname
, "movi.n") == 0)
2175 opclass
= c0opc_movi
;
2176 else if (strcasecmp (opcname
, "l32r") == 0)
2177 opclass
= c0opc_l32r
;
2178 else if (strcasecmp (opcname
, "s32i") == 0
2179 || strcasecmp (opcname
, "s32i.n") == 0)
2180 opclass
= c0opc_s32i
;
2181 else if (strcasecmp (opcname
, "l32e") == 0)
2182 opclass
= c0opc_l32e
;
2183 else if (strcasecmp (opcname
, "s32e") == 0)
2184 opclass
= c0opc_s32e
;
2185 else if (rwx_special_register (opcname
))
2186 opclass
= c0opc_rwxsr
;
2191 /* Tracks register movement/mutation for a given operation, which may
2192 be within a bundle. Updates the destination register tracking info
2193 accordingly. The pc is needed only for pc-relative load instructions
2194 (eg. l32r). The SP register number is needed to identify stores to
2195 the stack frame. Returns 0, if analysis was succesfull, non-zero
2199 call0_track_op (struct gdbarch
*gdbarch
, xtensa_c0reg_t dst
[], xtensa_c0reg_t src
[],
2200 xtensa_insn_kind opclass
, int nods
, unsigned odv
[],
2201 CORE_ADDR pc
, int spreg
, xtensa_frame_cache_t
*cache
)
2203 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2204 unsigned litbase
, litaddr
, litval
;
2209 /* 3 operands: dst, src, imm. */
2210 gdb_assert (nods
== 3);
2211 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2212 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ odv
[2];
2215 /* 3 operands: dst, src1, src2. */
2216 gdb_assert (nods
== 3);
2217 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2219 dst
[odv
[0]].fr_reg
= src
[odv
[2]].fr_reg
;
2220 dst
[odv
[0]].fr_ofs
= src
[odv
[2]].fr_ofs
+ src
[odv
[1]].fr_ofs
;
2222 else if (src
[odv
[2]].fr_reg
== C0_CONST
)
2224 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2225 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ src
[odv
[2]].fr_ofs
;
2227 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2230 /* 3 operands: dst, src1, src2. */
2231 gdb_assert (nods
== 3);
2232 if (cache
->c0
.c0_fpalign
== 0)
2234 /* Handle dynamic stack alignment. */
2235 if ((src
[odv
[0]].fr_reg
== spreg
) && (src
[odv
[1]].fr_reg
== spreg
))
2237 if (src
[odv
[2]].fr_reg
== C0_CONST
)
2238 cache
->c0
.c0_fpalign
= src
[odv
[2]].fr_ofs
;
2241 else if ((src
[odv
[0]].fr_reg
== spreg
)
2242 && (src
[odv
[2]].fr_reg
== spreg
))
2244 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2245 cache
->c0
.c0_fpalign
= src
[odv
[1]].fr_ofs
;
2248 /* else fall through. */
2250 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2252 dst
[odv
[0]].fr_reg
= src
[odv
[2]].fr_reg
;
2253 dst
[odv
[0]].fr_ofs
= src
[odv
[2]].fr_ofs
& src
[odv
[1]].fr_ofs
;
2255 else if (src
[odv
[2]].fr_reg
== C0_CONST
)
2257 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2258 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
& src
[odv
[2]].fr_ofs
;
2260 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2263 /* 3 operands: dst, src1, src2. */
2264 gdb_assert (nods
== 3);
2265 if (src
[odv
[2]].fr_reg
== C0_CONST
)
2267 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2268 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
- src
[odv
[2]].fr_ofs
;
2270 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2273 /* 2 operands: dst, src [, src]. */
2274 gdb_assert (nods
== 2);
2275 /* First, check if it's a special case of saving unaligned SP
2276 to a spare register in case of dynamic stack adjustment.
2277 But, only do it one time. The second time could be initializing
2278 frame pointer. We don't want to overwrite the first one. */
2279 if ((odv
[1] == spreg
) && (cache
->c0
.c0_old_sp
== C0_INEXP
))
2280 cache
->c0
.c0_old_sp
= odv
[0];
2282 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2283 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
;
2286 /* 2 operands: dst, imm. */
2287 gdb_assert (nods
== 2);
2288 dst
[odv
[0]].fr_reg
= C0_CONST
;
2289 dst
[odv
[0]].fr_ofs
= odv
[1];
2292 /* 2 operands: dst, literal offset. */
2293 gdb_assert (nods
== 2);
2294 /* litbase = xtensa_get_litbase (pc); can be also used. */
2295 litbase
= (gdbarch_tdep (gdbarch
)->litbase_regnum
== -1)
2296 ? 0 : xtensa_read_register
2297 (gdbarch_tdep (gdbarch
)->litbase_regnum
);
2298 litaddr
= litbase
& 1
2299 ? (litbase
& ~1) + (signed)odv
[1]
2300 : (pc
+ 3 + (signed)odv
[1]) & ~3;
2301 litval
= read_memory_integer (litaddr
, 4, byte_order
);
2302 dst
[odv
[0]].fr_reg
= C0_CONST
;
2303 dst
[odv
[0]].fr_ofs
= litval
;
2306 /* 3 operands: value, base, offset. */
2307 gdb_assert (nods
== 3 && spreg
>= 0 && spreg
< C0_NREGS
);
2308 /* First, check if it's a spill for saved unaligned SP,
2309 when dynamic stack adjustment was applied to this frame. */
2310 if ((cache
->c0
.c0_fpalign
!= 0) /* Dynamic stack adjustment. */
2311 && (odv
[1] == spreg
) /* SP usage indicates spill. */
2312 && (odv
[0] == cache
->c0
.c0_old_sp
)) /* Old SP register spilled. */
2313 cache
->c0
.c0_sp_ofs
= odv
[2];
2315 if (src
[odv
[1]].fr_reg
== spreg
/* Store to stack frame. */
2316 && (src
[odv
[1]].fr_ofs
& 3) == 0 /* Alignment preserved. */
2317 && src
[odv
[0]].fr_reg
>= 0 /* Value is from a register. */
2318 && src
[odv
[0]].fr_ofs
== 0 /* Value hasn't been modified. */
2319 && src
[src
[odv
[0]].fr_reg
].to_stk
== C0_NOSTK
) /* First time. */
2321 /* ISA encoding guarantees alignment. But, check it anyway. */
2322 gdb_assert ((odv
[2] & 3) == 0);
2323 dst
[src
[odv
[0]].fr_reg
].to_stk
= src
[odv
[1]].fr_ofs
+ odv
[2];
2326 /* If we end up inside Window Overflow / Underflow interrupt handler
2327 report an error because these handlers should have been handled
2328 already in a different way. */
2340 /* Analyze prologue of the function at start address to determine if it uses
2341 the Call0 ABI, and if so track register moves and linear modifications
2342 in the prologue up to the PC or just beyond the prologue, whichever is
2343 first. An 'entry' instruction indicates non-Call0 ABI and the end of the
2344 prologue. The prologue may overlap non-prologue instructions but is
2345 guaranteed to end by the first flow-control instruction (jump, branch,
2346 call or return). Since an optimized function may move information around
2347 and change the stack frame arbitrarily during the prologue, the information
2348 is guaranteed valid only at the point in the function indicated by the PC.
2349 May be used to skip the prologue or identify the ABI, w/o tracking.
2351 Returns: Address of first instruction after prologue, or PC (whichever
2352 is first), or 0, if decoding failed (in libisa).
2354 start Start address of function/prologue.
2355 pc Program counter to stop at. Use 0 to continue to end of prologue.
2356 If 0, avoids infinite run-on in corrupt code memory by bounding
2357 the scan to the end of the function if that can be determined.
2358 nregs Number of general registers to track.
2360 cache Xtensa frame cache.
2362 Note that these may produce useful results even if decoding fails
2363 because they begin with default assumptions that analysis may change. */
2366 call0_analyze_prologue (struct gdbarch
*gdbarch
,
2367 CORE_ADDR start
, CORE_ADDR pc
,
2368 int nregs
, xtensa_frame_cache_t
*cache
)
2370 CORE_ADDR ia
; /* Current insn address in prologue. */
2371 CORE_ADDR ba
= 0; /* Current address at base of insn buffer. */
2372 CORE_ADDR bt
; /* Current address at top+1 of insn buffer. */
2373 gdb_byte ibuf
[XTENSA_ISA_BSZ
];/* Instruction buffer for decoding prologue. */
2374 xtensa_isa isa
; /* libisa ISA handle. */
2375 xtensa_insnbuf ins
, slot
; /* libisa handle to decoded insn, slot. */
2376 xtensa_format ifmt
; /* libisa instruction format. */
2377 int ilen
, islots
, is
; /* Instruction length, nbr slots, current slot. */
2378 xtensa_opcode opc
; /* Opcode in current slot. */
2379 xtensa_insn_kind opclass
; /* Opcode class for Call0 prologue analysis. */
2380 int nods
; /* Opcode number of operands. */
2381 unsigned odv
[C0_MAXOPDS
]; /* Operand values in order provided by libisa. */
2382 xtensa_c0reg_t
*rtmp
; /* Register tracking info snapshot. */
2383 int j
; /* General loop counter. */
2384 int fail
= 0; /* Set non-zero and exit, if decoding fails. */
2385 CORE_ADDR body_pc
; /* The PC for the first non-prologue insn. */
2386 CORE_ADDR end_pc
; /* The PC for the lust function insn. */
2388 struct symtab_and_line prologue_sal
;
2390 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2391 (int)start
, (int)pc
);
2393 /* Try to limit the scan to the end of the function if a non-zero pc
2394 arg was not supplied to avoid probing beyond the end of valid memory.
2395 If memory is full of garbage that classifies as c0opc_uninteresting.
2396 If this fails (eg. if no symbols) pc ends up 0 as it was.
2397 Initialize the Call0 frame and register tracking info.
2398 Assume it's Call0 until an 'entry' instruction is encountered.
2399 Assume we may be in the prologue until we hit a flow control instr. */
2405 /* Find out, if we have an information about the prologue from DWARF. */
2406 prologue_sal
= find_pc_line (start
, 0);
2407 if (prologue_sal
.line
!= 0) /* Found debug info. */
2408 body_pc
= prologue_sal
.end
;
2410 /* If we are going to analyze the prologue in general without knowing about
2411 the current PC, make the best assumtion for the end of the prologue. */
2414 find_pc_partial_function (start
, 0, NULL
, &end_pc
);
2415 body_pc
= std::min (end_pc
, body_pc
);
2418 body_pc
= std::min (pc
, body_pc
);
2421 rtmp
= (xtensa_c0reg_t
*) alloca(nregs
* sizeof(xtensa_c0reg_t
));
2423 isa
= xtensa_default_isa
;
2424 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2425 ins
= xtensa_insnbuf_alloc (isa
);
2426 slot
= xtensa_insnbuf_alloc (isa
);
2428 for (ia
= start
, bt
= ia
; ia
< body_pc
; ia
+= ilen
)
2430 /* (Re)fill instruction buffer from memory if necessary, but do not
2431 read memory beyond PC to be sure we stay within text section
2432 (this protection only works if a non-zero pc is supplied). */
2434 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2437 bt
= (ba
+ XTENSA_ISA_BSZ
) < body_pc
? ba
+ XTENSA_ISA_BSZ
: body_pc
;
2438 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0 )
2439 error (_("Unable to read target memory ..."));
2442 /* Decode format information. */
2444 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2445 ifmt
= xtensa_format_decode (isa
, ins
);
2446 if (ifmt
== XTENSA_UNDEFINED
)
2451 ilen
= xtensa_format_length (isa
, ifmt
);
2452 if (ilen
== XTENSA_UNDEFINED
)
2457 islots
= xtensa_format_num_slots (isa
, ifmt
);
2458 if (islots
== XTENSA_UNDEFINED
)
2464 /* Analyze a bundle or a single instruction, using a snapshot of
2465 the register tracking info as input for the entire bundle so that
2466 register changes do not take effect within this bundle. */
2468 for (j
= 0; j
< nregs
; ++j
)
2469 rtmp
[j
] = cache
->c0
.c0_rt
[j
];
2471 for (is
= 0; is
< islots
; ++is
)
2473 /* Decode a slot and classify the opcode. */
2475 fail
= xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
);
2479 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2480 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2482 if (opc
== XTENSA_UNDEFINED
)
2483 opclass
= c0opc_illegal
;
2485 opclass
= call0_classify_opcode (isa
, opc
);
2487 /* Decide whether to track this opcode, ignore it, or bail out. */
2496 case c0opc_uninteresting
:
2499 case c0opc_flow
: /* Flow control instructions stop analysis. */
2500 case c0opc_rwxsr
: /* RSR, WSR, XSR instructions stop analysis. */
2505 ia
+= ilen
; /* Skip over 'entry' insn. */
2512 /* Only expected opcodes should get this far. */
2514 /* Extract and decode the operands. */
2515 nods
= xtensa_opcode_num_operands (isa
, opc
);
2516 if (nods
== XTENSA_UNDEFINED
)
2522 for (j
= 0; j
< nods
&& j
< C0_MAXOPDS
; ++j
)
2524 fail
= xtensa_operand_get_field (isa
, opc
, j
, ifmt
,
2529 fail
= xtensa_operand_decode (isa
, opc
, j
, &odv
[j
]);
2534 /* Check operands to verify use of 'mov' assembler macro. */
2535 if (opclass
== c0opc_mov
&& nods
== 3)
2537 if (odv
[2] == odv
[1])
2540 if ((odv
[0] == 1) && (odv
[1] != 1))
2541 /* OR A1, An, An , where n != 1.
2542 This means we are inside epilogue already. */
2547 opclass
= c0opc_uninteresting
;
2552 /* Track register movement and modification for this operation. */
2553 fail
= call0_track_op (gdbarch
, cache
->c0
.c0_rt
, rtmp
,
2554 opclass
, nods
, odv
, ia
, 1, cache
);
2560 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2561 (unsigned)ia
, fail
? "failed" : "succeeded");
2562 xtensa_insnbuf_free(isa
, slot
);
2563 xtensa_insnbuf_free(isa
, ins
);
2564 return fail
? XTENSA_ISA_BADPC
: ia
;
2567 /* Initialize frame cache for the current frame in CALL0 ABI. */
2570 call0_frame_cache (struct frame_info
*this_frame
,
2571 xtensa_frame_cache_t
*cache
, CORE_ADDR pc
)
2573 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2574 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2575 CORE_ADDR start_pc
; /* The beginning of the function. */
2576 CORE_ADDR body_pc
=UINT_MAX
; /* PC, where prologue analysis stopped. */
2577 CORE_ADDR sp
, fp
, ra
;
2578 int fp_regnum
= C0_SP
, c0_hasfp
= 0, c0_frmsz
= 0, prev_sp
= 0, to_stk
;
2580 sp
= get_frame_register_unsigned
2581 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
2582 fp
= sp
; /* Assume FP == SP until proven otherwise. */
2584 /* Find the beginning of the prologue of the function containing the PC
2585 and analyze it up to the PC or the end of the prologue. */
2587 if (find_pc_partial_function (pc
, NULL
, &start_pc
, NULL
))
2589 body_pc
= call0_analyze_prologue (gdbarch
, start_pc
, pc
, C0_NREGS
, cache
);
2591 if (body_pc
== XTENSA_ISA_BADPC
)
2595 goto finish_frame_analysis
;
2599 /* Get the frame information and FP (if used) at the current PC.
2600 If PC is in the prologue, the prologue analysis is more reliable
2601 than DWARF info. We don't not know for sure, if PC is in the prologue,
2602 but we do know no calls have yet taken place, so we can almost
2603 certainly rely on the prologue analysis. */
2607 /* Prologue analysis was successful up to the PC.
2608 It includes the cases when PC == START_PC. */
2609 c0_hasfp
= cache
->c0
.c0_rt
[C0_FP
].fr_reg
== C0_SP
;
2610 /* c0_hasfp == true means there is a frame pointer because
2611 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2612 was derived from SP. Otherwise, it would be C0_FP. */
2613 fp_regnum
= c0_hasfp
? C0_FP
: C0_SP
;
2614 c0_frmsz
= - cache
->c0
.c0_rt
[fp_regnum
].fr_ofs
;
2615 fp_regnum
+= gdbarch_tdep (gdbarch
)->a0_base
;
2617 else /* No data from the prologue analysis. */
2620 fp_regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_SP
;
2625 if (cache
->c0
.c0_fpalign
)
2627 /* This frame has a special prologue with a dynamic stack adjustment
2628 to force an alignment, which is bigger than standard 16 bytes. */
2630 CORE_ADDR unaligned_sp
;
2632 if (cache
->c0
.c0_old_sp
== C0_INEXP
)
2633 /* This can't be. Prologue code should be consistent.
2634 Unaligned stack pointer should be saved in a spare register. */
2638 goto finish_frame_analysis
;
2641 if (cache
->c0
.c0_sp_ofs
== C0_NOSTK
)
2642 /* Saved unaligned value of SP is kept in a register. */
2643 unaligned_sp
= get_frame_register_unsigned
2644 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ cache
->c0
.c0_old_sp
);
2646 /* Get the value from stack. */
2647 unaligned_sp
= (CORE_ADDR
)
2648 read_memory_integer (fp
+ cache
->c0
.c0_sp_ofs
, 4, byte_order
);
2650 prev_sp
= unaligned_sp
+ c0_frmsz
;
2653 prev_sp
= fp
+ c0_frmsz
;
2655 /* Frame size from debug info or prologue tracking does not account for
2656 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2659 fp
= get_frame_register_unsigned (this_frame
, fp_regnum
);
2661 /* Update the stack frame size. */
2662 c0_frmsz
+= fp
- sp
;
2665 /* Get the return address (RA) from the stack if saved,
2666 or try to get it from a register. */
2668 to_stk
= cache
->c0
.c0_rt
[C0_RA
].to_stk
;
2669 if (to_stk
!= C0_NOSTK
)
2671 read_memory_integer (sp
+ c0_frmsz
+ cache
->c0
.c0_rt
[C0_RA
].to_stk
,
2674 else if (cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_CONST
2675 && cache
->c0
.c0_rt
[C0_RA
].fr_ofs
== 0)
2677 /* Special case for terminating backtrace at a function that wants to
2678 be seen as the outermost one. Such a function will clear it's RA (A0)
2679 register to 0 in the prologue instead of saving its original value. */
2684 /* RA was copied to another register or (before any function call) may
2685 still be in the original RA register. This is not always reliable:
2686 even in a leaf function, register tracking stops after prologue, and
2687 even in prologue, non-prologue instructions (not tracked) may overwrite
2688 RA or any register it was copied to. If likely in prologue or before
2689 any call, use retracking info and hope for the best (compiler should
2690 have saved RA in stack if not in a leaf function). If not in prologue,
2696 && (i
== C0_RA
|| cache
->c0
.c0_rt
[i
].fr_reg
!= C0_RA
);
2698 if (i
>= C0_NREGS
&& cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_RA
)
2702 ra
= get_frame_register_unsigned
2704 gdbarch_tdep (gdbarch
)->a0_base
+ cache
->c0
.c0_rt
[i
].fr_reg
);
2709 finish_frame_analysis
:
2710 cache
->pc
= start_pc
;
2712 /* RA == 0 marks the outermost frame. Do not go past it. */
2713 cache
->prev_sp
= (ra
!= 0) ? prev_sp
: 0;
2714 cache
->c0
.fp_regnum
= fp_regnum
;
2715 cache
->c0
.c0_frmsz
= c0_frmsz
;
2716 cache
->c0
.c0_hasfp
= c0_hasfp
;
2717 cache
->c0
.c0_fp
= fp
;
2720 static CORE_ADDR a0_saved
;
2721 static CORE_ADDR a7_saved
;
2722 static CORE_ADDR a11_saved
;
2723 static int a0_was_saved
;
2724 static int a7_was_saved
;
2725 static int a11_was_saved
;
2727 /* Simulate L32E instruction: AT <-- ref (AS + offset). */
2729 execute_l32e (struct gdbarch
*gdbarch
, int at
, int as
, int offset
, CORE_ADDR wb
)
2731 int atreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ at
, wb
);
2732 int asreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ as
, wb
);
2733 CORE_ADDR addr
= xtensa_read_register (asreg
) + offset
;
2734 unsigned int spilled_value
2735 = read_memory_unsigned_integer (addr
, 4, gdbarch_byte_order (gdbarch
));
2737 if ((at
== 0) && !a0_was_saved
)
2739 a0_saved
= xtensa_read_register (atreg
);
2742 else if ((at
== 7) && !a7_was_saved
)
2744 a7_saved
= xtensa_read_register (atreg
);
2747 else if ((at
== 11) && !a11_was_saved
)
2749 a11_saved
= xtensa_read_register (atreg
);
2753 xtensa_write_register (atreg
, spilled_value
);
2756 /* Simulate S32E instruction: AT --> ref (AS + offset). */
2758 execute_s32e (struct gdbarch
*gdbarch
, int at
, int as
, int offset
, CORE_ADDR wb
)
2760 int atreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ at
, wb
);
2761 int asreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ as
, wb
);
2762 CORE_ADDR addr
= xtensa_read_register (asreg
) + offset
;
2763 ULONGEST spilled_value
= xtensa_read_register (atreg
);
2765 write_memory_unsigned_integer (addr
, 4,
2766 gdbarch_byte_order (gdbarch
),
2770 #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2776 xtNoExceptionHandler
2777 } xtensa_exception_handler_t
;
2779 /* Execute instruction stream from current PC until hitting RFWU or RFWO.
2780 Return type of Xtensa Window Interrupt Handler on success. */
2781 static xtensa_exception_handler_t
2782 execute_code (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
, CORE_ADDR wb
)
2785 xtensa_insnbuf ins
, slot
;
2786 gdb_byte ibuf
[XTENSA_ISA_BSZ
];
2787 CORE_ADDR ia
, bt
, ba
;
2789 int ilen
, islots
, is
;
2792 void (*func
) (struct gdbarch
*, int, int, int, CORE_ADDR
);
2794 uint32_t at
, as
, offset
;
2796 /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
2797 int WindowUnderflow12
= (current_pc
& 0x1ff) >= 0x140;
2799 isa
= xtensa_default_isa
;
2800 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2801 ins
= xtensa_insnbuf_alloc (isa
);
2802 slot
= xtensa_insnbuf_alloc (isa
);
2811 while (insn_num
++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN
)
2813 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2816 bt
= (ba
+ XTENSA_ISA_BSZ
);
2817 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0)
2818 return xtNoExceptionHandler
;
2820 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2821 ifmt
= xtensa_format_decode (isa
, ins
);
2822 if (ifmt
== XTENSA_UNDEFINED
)
2823 return xtNoExceptionHandler
;
2824 ilen
= xtensa_format_length (isa
, ifmt
);
2825 if (ilen
== XTENSA_UNDEFINED
)
2826 return xtNoExceptionHandler
;
2827 islots
= xtensa_format_num_slots (isa
, ifmt
);
2828 if (islots
== XTENSA_UNDEFINED
)
2829 return xtNoExceptionHandler
;
2830 for (is
= 0; is
< islots
; ++is
)
2832 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
2833 return xtNoExceptionHandler
;
2834 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2835 if (opc
== XTENSA_UNDEFINED
)
2836 return xtNoExceptionHandler
;
2837 switch (call0_classify_opcode (isa
, opc
))
2843 /* We expect none of them here. */
2844 return xtNoExceptionHandler
;
2846 func
= execute_l32e
;
2849 func
= execute_s32e
;
2851 case c0opc_rfwo
: /* RFWO. */
2852 /* Here, we return from WindowOverflow handler and,
2853 if we stopped at the very beginning, which means
2854 A0 was saved, we have to restore it now. */
2857 int arreg
= arreg_number (gdbarch
,
2858 gdbarch_tdep (gdbarch
)->a0_base
,
2860 xtensa_write_register (arreg
, a0_saved
);
2862 return xtWindowOverflow
;
2863 case c0opc_rfwu
: /* RFWU. */
2864 /* Here, we return from WindowUnderflow handler.
2865 Let's see if either A7 or A11 has to be restored. */
2866 if (WindowUnderflow12
)
2870 int arreg
= arreg_number (gdbarch
,
2871 gdbarch_tdep (gdbarch
)->a0_base
+ 11,
2873 xtensa_write_register (arreg
, a11_saved
);
2876 else if (a7_was_saved
)
2878 int arreg
= arreg_number (gdbarch
,
2879 gdbarch_tdep (gdbarch
)->a0_base
+ 7,
2881 xtensa_write_register (arreg
, a7_saved
);
2883 return xtWindowUnderflow
;
2884 default: /* Simply skip this insns. */
2888 /* Decode arguments for L32E / S32E and simulate their execution. */
2889 if ( xtensa_opcode_num_operands (isa
, opc
) != 3 )
2890 return xtNoExceptionHandler
;
2891 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
, &at
))
2892 return xtNoExceptionHandler
;
2893 if (xtensa_operand_decode (isa
, opc
, 0, &at
))
2894 return xtNoExceptionHandler
;
2895 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
, is
, slot
, &as
))
2896 return xtNoExceptionHandler
;
2897 if (xtensa_operand_decode (isa
, opc
, 1, &as
))
2898 return xtNoExceptionHandler
;
2899 if (xtensa_operand_get_field (isa
, opc
, 2, ifmt
, is
, slot
, &offset
))
2900 return xtNoExceptionHandler
;
2901 if (xtensa_operand_decode (isa
, opc
, 2, &offset
))
2902 return xtNoExceptionHandler
;
2904 (*func
) (gdbarch
, at
, as
, offset
, wb
);
2909 return xtNoExceptionHandler
;
2912 /* Handle Window Overflow / Underflow exception frames. */
2915 xtensa_window_interrupt_frame_cache (struct frame_info
*this_frame
,
2916 xtensa_frame_cache_t
*cache
,
2919 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2920 CORE_ADDR ps
, wb
, ws
, ra
;
2921 int epc1_regnum
, i
, regnum
;
2922 xtensa_exception_handler_t eh_type
;
2924 /* Read PS, WB, and WS from the hardware. Note that PS register
2925 must be present, if Windowed ABI is supported. */
2926 ps
= xtensa_read_register (gdbarch_ps_regnum (gdbarch
));
2927 wb
= xtensa_read_register (gdbarch_tdep (gdbarch
)->wb_regnum
);
2928 ws
= xtensa_read_register (gdbarch_tdep (gdbarch
)->ws_regnum
);
2930 /* Execute all the remaining instructions from Window Interrupt Handler
2931 by simulating them on the remote protocol level. On return, set the
2932 type of Xtensa Window Interrupt Handler, or report an error. */
2933 eh_type
= execute_code (gdbarch
, pc
, wb
);
2934 if (eh_type
== xtNoExceptionHandler
)
2936 Unable to decode Xtensa Window Interrupt Handler's code."));
2938 cache
->ps
= ps
^ PS_EXC
; /* Clear the exception bit in PS. */
2939 cache
->call0
= 0; /* It's Windowed ABI. */
2941 /* All registers for the cached frame will be alive. */
2942 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
2943 cache
->wd
.aregs
[i
] = -1;
2945 if (eh_type
== xtWindowOverflow
)
2946 cache
->wd
.ws
= ws
^ (1 << wb
);
2947 else /* eh_type == xtWindowUnderflow. */
2948 cache
->wd
.ws
= ws
| (1 << wb
);
2950 cache
->wd
.wb
= (ps
& 0xf00) >> 8; /* Set WB to OWB. */
2951 regnum
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
,
2953 ra
= xtensa_read_register (regnum
);
2954 cache
->wd
.callsize
= WINSIZE (ra
);
2955 cache
->prev_sp
= xtensa_read_register (regnum
+ 1);
2956 /* Set regnum to a frame pointer of the frame being cached. */
2957 regnum
= xtensa_scan_prologue (gdbarch
, pc
);
2958 regnum
= arreg_number (gdbarch
,
2959 gdbarch_tdep (gdbarch
)->a0_base
+ regnum
,
2961 cache
->base
= get_frame_register_unsigned (this_frame
, regnum
);
2963 /* Read PC of interrupted function from EPC1 register. */
2964 epc1_regnum
= xtensa_find_register_by_name (gdbarch
,"epc1");
2965 if (epc1_regnum
< 0)
2966 error(_("Unable to read Xtensa register EPC1"));
2967 cache
->ra
= xtensa_read_register (epc1_regnum
);
2968 cache
->pc
= get_frame_func (this_frame
);
2972 /* Skip function prologue.
2974 Return the pc of the first instruction after prologue. GDB calls this to
2975 find the address of the first line of the function or (if there is no line
2976 number information) to skip the prologue for planting breakpoints on
2977 function entries. Use debug info (if present) or prologue analysis to skip
2978 the prologue to achieve reliable debugging behavior. For windowed ABI,
2979 only the 'entry' instruction is skipped. It is not strictly necessary to
2980 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2981 backtrace at any point in the prologue, however certain potential hazards
2982 are avoided and a more "normal" debugging experience is ensured by
2983 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2984 For example, if we don't skip the prologue:
2985 - Some args may not yet have been saved to the stack where the debug
2986 info expects to find them (true anyway when only 'entry' is skipped);
2987 - Software breakpoints ('break' instrs) may not have been unplanted
2988 when the prologue analysis is done on initializing the frame cache,
2989 and breaks in the prologue will throw off the analysis.
2991 If we have debug info ( line-number info, in particular ) we simply skip
2992 the code associated with the first function line effectively skipping
2993 the prologue code. It works even in cases like
2996 { int local_var = 1;
3000 because, for this source code, both Xtensa compilers will generate two
3001 separate entries ( with the same line number ) in dwarf line-number
3002 section to make sure there is a boundary between the prologue code and
3003 the rest of the function.
3005 If there is no debug info, we need to analyze the code. */
3007 /* #define DONT_SKIP_PROLOGUE */
3010 xtensa_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
3012 struct symtab_and_line prologue_sal
;
3015 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc
);
3017 #if DONT_SKIP_PROLOGUE
3021 /* Try to find first body line from debug info. */
3023 prologue_sal
= find_pc_line (start_pc
, 0);
3024 if (prologue_sal
.line
!= 0) /* Found debug info. */
3026 /* In Call0, it is possible to have a function with only one instruction
3027 ('ret') resulting from a one-line optimized function that does nothing.
3028 In that case, prologue_sal.end may actually point to the start of the
3029 next function in the text section, causing a breakpoint to be set at
3030 the wrong place. Check, if the end address is within a different
3031 function, and if so return the start PC. We know we have symbol
3036 if ((gdbarch_tdep (gdbarch
)->call_abi
== CallAbiCall0Only
)
3037 && call0_ret (start_pc
, prologue_sal
.end
))
3040 find_pc_partial_function (prologue_sal
.end
, NULL
, &end_func
, NULL
);
3041 if (end_func
!= start_pc
)
3044 return prologue_sal
.end
;
3047 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
3048 body_pc
= call0_analyze_prologue (gdbarch
, start_pc
, 0, 0,
3049 xtensa_alloc_frame_cache (0));
3050 return body_pc
!= 0 ? body_pc
: start_pc
;
3053 /* Verify the current configuration. */
3055 xtensa_verify_config (struct gdbarch
*gdbarch
)
3057 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3060 /* Verify that we got a reasonable number of AREGS. */
3061 if ((tdep
->num_aregs
& -tdep
->num_aregs
) != tdep
->num_aregs
)
3063 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
3066 /* Verify that certain registers exist. */
3068 if (tdep
->pc_regnum
== -1)
3069 log
.printf (_("\n\tpc_regnum: No PC register"));
3070 if (tdep
->isa_use_exceptions
&& tdep
->ps_regnum
== -1)
3071 log
.printf (_("\n\tps_regnum: No PS register"));
3073 if (tdep
->isa_use_windowed_registers
)
3075 if (tdep
->wb_regnum
== -1)
3076 log
.printf (_("\n\twb_regnum: No WB register"));
3077 if (tdep
->ws_regnum
== -1)
3078 log
.printf (_("\n\tws_regnum: No WS register"));
3079 if (tdep
->ar_base
== -1)
3080 log
.printf (_("\n\tar_base: No AR registers"));
3083 if (tdep
->a0_base
== -1)
3084 log
.printf (_("\n\ta0_base: No Ax registers"));
3087 internal_error (__FILE__
, __LINE__
,
3088 _("the following are invalid: %s"), log
.c_str ());
3092 /* Derive specific register numbers from the array of registers. */
3095 xtensa_derive_tdep (struct gdbarch_tdep
*tdep
)
3097 xtensa_register_t
* rmap
;
3098 int n
, max_size
= 4;
3101 tdep
->num_nopriv_regs
= 0;
3103 /* Special registers 0..255 (core). */
3104 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
3105 /* User registers 0..255. */
3106 #define XTENSA_DBREGN_UREG(n) (0x0300+(n))
3108 for (rmap
= tdep
->regmap
, n
= 0; rmap
->target_number
!= -1; n
++, rmap
++)
3110 if (rmap
->target_number
== 0x0020)
3111 tdep
->pc_regnum
= n
;
3112 else if (rmap
->target_number
== 0x0100)
3114 else if (rmap
->target_number
== 0x0000)
3116 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(72))
3117 tdep
->wb_regnum
= n
;
3118 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(73))
3119 tdep
->ws_regnum
= n
;
3120 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(233))
3121 tdep
->debugcause_regnum
= n
;
3122 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(232))
3123 tdep
->exccause_regnum
= n
;
3124 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(238))
3125 tdep
->excvaddr_regnum
= n
;
3126 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(0))
3127 tdep
->lbeg_regnum
= n
;
3128 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(1))
3129 tdep
->lend_regnum
= n
;
3130 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(2))
3131 tdep
->lcount_regnum
= n
;
3132 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(3))
3133 tdep
->sar_regnum
= n
;
3134 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(5))
3135 tdep
->litbase_regnum
= n
;
3136 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(230))
3137 tdep
->ps_regnum
= n
;
3138 else if (rmap
->target_number
== XTENSA_DBREGN_UREG(231))
3139 tdep
->threadptr_regnum
= n
;
3141 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(226))
3142 tdep
->interrupt_regnum
= n
;
3143 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(227))
3144 tdep
->interrupt2_regnum
= n
;
3145 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(224))
3146 tdep
->cpenable_regnum
= n
;
3149 if (rmap
->byte_size
> max_size
)
3150 max_size
= rmap
->byte_size
;
3151 if (rmap
->mask
!= 0 && tdep
->num_regs
== 0)
3153 /* Find out out how to deal with priveleged registers.
3155 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3156 && tdep->num_nopriv_regs == 0)
3157 tdep->num_nopriv_regs = n;
3159 if ((rmap
->flags
& XTENSA_REGISTER_FLAGS_PRIVILEGED
) != 0
3160 && tdep
->num_regs
== 0)
3164 /* Number of pseudo registers. */
3165 tdep
->num_pseudo_regs
= n
- tdep
->num_regs
;
3167 /* Empirically determined maximum sizes. */
3168 tdep
->max_register_raw_size
= max_size
;
3169 tdep
->max_register_virtual_size
= max_size
;
3172 /* Module "constructor" function. */
3174 extern struct gdbarch_tdep xtensa_tdep
;
3176 static struct gdbarch
*
3177 xtensa_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3179 struct gdbarch_tdep
*tdep
;
3180 struct gdbarch
*gdbarch
;
3182 DEBUGTRACE ("gdbarch_init()\n");
3184 if (!xtensa_default_isa
)
3185 xtensa_default_isa
= xtensa_isa_init (0, 0);
3187 /* We have to set the byte order before we call gdbarch_alloc. */
3188 info
.byte_order
= XCHAL_HAVE_BE
? BFD_ENDIAN_BIG
: BFD_ENDIAN_LITTLE
;
3190 tdep
= &xtensa_tdep
;
3191 gdbarch
= gdbarch_alloc (&info
, tdep
);
3192 xtensa_derive_tdep (tdep
);
3194 /* Verify our configuration. */
3195 xtensa_verify_config (gdbarch
);
3196 xtensa_session_once_reported
= 0;
3198 set_gdbarch_wchar_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
3199 set_gdbarch_wchar_signed (gdbarch
, 0);
3201 /* Pseudo-Register read/write. */
3202 set_gdbarch_pseudo_register_read (gdbarch
, xtensa_pseudo_register_read
);
3203 set_gdbarch_pseudo_register_write (gdbarch
, xtensa_pseudo_register_write
);
3205 /* Set target information. */
3206 set_gdbarch_num_regs (gdbarch
, tdep
->num_regs
);
3207 set_gdbarch_num_pseudo_regs (gdbarch
, tdep
->num_pseudo_regs
);
3208 set_gdbarch_sp_regnum (gdbarch
, tdep
->a0_base
+ 1);
3209 set_gdbarch_pc_regnum (gdbarch
, tdep
->pc_regnum
);
3210 set_gdbarch_ps_regnum (gdbarch
, tdep
->ps_regnum
);
3212 /* Renumber registers for known formats (stabs and dwarf2). */
3213 set_gdbarch_stab_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
3214 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
3216 /* We provide our own function to get register information. */
3217 set_gdbarch_register_name (gdbarch
, xtensa_register_name
);
3218 set_gdbarch_register_type (gdbarch
, xtensa_register_type
);
3220 /* To call functions from GDB using dummy frame. */
3221 set_gdbarch_push_dummy_call (gdbarch
, xtensa_push_dummy_call
);
3223 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
3225 set_gdbarch_return_value (gdbarch
, xtensa_return_value
);
3227 /* Advance PC across any prologue instructions to reach "real" code. */
3228 set_gdbarch_skip_prologue (gdbarch
, xtensa_skip_prologue
);
3230 /* Stack grows downward. */
3231 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3233 /* Set breakpoints. */
3234 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
3235 xtensa_breakpoint_kind_from_pc
);
3236 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
3237 xtensa_sw_breakpoint_from_kind
);
3239 /* After breakpoint instruction or illegal instruction, pc still
3240 points at break instruction, so don't decrement. */
3241 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
3243 /* We don't skip args. */
3244 set_gdbarch_frame_args_skip (gdbarch
, 0);
3246 set_gdbarch_unwind_pc (gdbarch
, xtensa_unwind_pc
);
3248 set_gdbarch_frame_align (gdbarch
, xtensa_frame_align
);
3250 set_gdbarch_dummy_id (gdbarch
, xtensa_dummy_id
);
3252 /* Frame handling. */
3253 frame_base_set_default (gdbarch
, &xtensa_frame_base
);
3254 frame_unwind_append_unwinder (gdbarch
, &xtensa_unwind
);
3255 dwarf2_append_unwinders (gdbarch
);
3257 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3259 xtensa_add_reggroups (gdbarch
);
3260 set_gdbarch_register_reggroup_p (gdbarch
, xtensa_register_reggroup_p
);
3262 set_gdbarch_iterate_over_regset_sections
3263 (gdbarch
, xtensa_iterate_over_regset_sections
);
3265 set_solib_svr4_fetch_link_map_offsets
3266 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
3268 /* Hook in the ABI-specific overrides, if they have been registered. */
3269 gdbarch_init_osabi (info
, gdbarch
);
3275 xtensa_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3277 error (_("xtensa_dump_tdep(): not implemented"));
3281 _initialize_xtensa_tdep (void)
3283 gdbarch_register (bfd_arch_xtensa
, xtensa_gdbarch_init
, xtensa_dump_tdep
);
3284 xtensa_init_reggroups ();
3286 add_setshow_zuinteger_cmd ("xtensa",
3288 &xtensa_debug_level
,
3289 _("Set Xtensa debugging."),
3290 _("Show Xtensa debugging."), _("\
3291 When non-zero, Xtensa-specific debugging is enabled. \
3292 Can be 1, 2, 3, or 4 indicating the level of debugging."),
3295 &setdebuglist
, &showdebuglist
);