1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
32 #include "floatformat.h"
34 #include "reggroups.h"
37 #include "dummy-frame.h"
38 #include "elf/dwarf2.h"
39 #include "dwarf2-frame.h"
40 #include "dwarf2loc.h"
42 #include "frame-base.h"
43 #include "frame-unwind.h"
45 #include "arch-utils.h"
52 #include "gdb_assert.h"
54 #include "xtensa-tdep.h"
57 static int xtensa_debug_level
= 0;
59 #define DEBUGWARN(args...) \
60 if (xtensa_debug_level > 0) \
61 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
63 #define DEBUGINFO(args...) \
64 if (xtensa_debug_level > 1) \
65 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
67 #define DEBUGTRACE(args...) \
68 if (xtensa_debug_level > 2) \
69 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
71 #define DEBUGVERB(args...) \
72 if (xtensa_debug_level > 3) \
73 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
76 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
78 #define SP_ALIGNMENT 16
81 /* We use a6 through a11 for passing arguments to a function called by GDB. */
83 #define ARGS_FIRST_REG A6_REGNUM
84 #define ARGS_NUM_REGS 6
85 #define REGISTER_SIZE 4
88 /* Extract the call size from the return address or ps register. */
90 #define PS_CALLINC_SHIFT 16
91 #define PS_CALLINC_MASK 0x00030000
92 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
93 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
96 /* Convert a live Ax register number to the corresponding Areg number. */
98 #define AREG_NUMBER(r, wb) \
99 ((((r) - A0_REGNUM + (((wb) & WB_MASK)<<WB_SHIFT)) & AREGS_MASK) + AR_BASE)
102 /* Define prototypes. */
104 extern struct gdbarch_tdep
*xtensa_config_tdep (struct gdbarch_info
*);
105 extern int xtensa_config_byte_order (struct gdbarch_info
*);
108 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
109 indicates that the instruction is an ENTRY instruction. */
111 #define XTENSA_IS_ENTRY(op1) \
112 ((gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) \
113 ? ((op1) == 0x6c) : ((op1) == 0x36))
115 #define XTENSA_ENTRY_LENGTH 3
118 /* windowing_enabled() returns true, if windowing is enabled.
119 WOE must be set to 1; EXCM to 0.
120 Note: We assume that EXCM is always 0 for XEA1. */
123 windowing_enabled (CORE_ADDR ps
)
125 return ((ps
& (1 << 4)) == 0 && (ps
& (1 << 18)) != 0);
128 /* Return the window size of the previous call to the function from which we
131 This function is used to extract the return value after a called function
132 has returned to the callee. On Xtensa, the register that holds the return
133 value (from the perspective of the caller) depends on what call
134 instruction was used. For now, we are assuming that the call instruction
135 precedes the current address, so we simply analyze the call instruction.
136 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
137 method to call the inferior function. */
140 extract_call_winsize (CORE_ADDR pc
)
142 int winsize
= 4; /* Default: No call, e.g. dummy frame. */
146 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc
);
148 /* Read the previous instruction (should be a call[x]{4|8|12}. */
149 read_memory (pc
-3, buf
, 3);
150 insn
= extract_unsigned_integer (buf
, 3);
152 /* Decode call instruction:
154 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
155 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
157 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
158 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
161 (Return the default value (4) if we can't find a valid call insn. */
163 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_LITTLE
)
165 if (((insn
& 0xf) == 0x5) || ((insn
& 0xcf) == 0xc0))
166 winsize
= (insn
& 0x30) >> 2; /* 0, 4, 8, 12 */
170 if (((insn
>> 20) == 0x5) || (((insn
>> 16) & 0xf3) == 0x03))
171 winsize
= (insn
>> 16) & 0xc; /* 0, 4, 8, 12 */
177 /* REGISTER INFORMATION */
179 /* Returns the name of a register. */
182 xtensa_register_name (int regnum
)
184 /* Return the name stored in the register map. */
185 if (regnum
>= 0 && regnum
< gdbarch_num_regs (current_gdbarch
)
186 + gdbarch_num_pseudo_regs (current_gdbarch
))
187 return REGMAP
[regnum
].name
;
189 /* Invalid register number. */
190 internal_error (__FILE__
, __LINE__
, _("invalid register %d"), regnum
);
195 /* Return the type of a register. Create a new type, if necessary. */
197 static struct ctype_cache
199 struct ctype_cache
*next
;
201 struct type
*virtual_type
;
202 } *type_entries
= NULL
;
205 xtensa_register_type (struct gdbarch
*gdbarch
, int regnum
)
207 /* Return signed integer for ARx and Ax registers. */
208 if ((regnum
>= AR_BASE
&& regnum
< AR_BASE
+ NUM_AREGS
)
209 || (regnum
>= A0_BASE
&& regnum
< A0_BASE
+ 16))
210 return builtin_type_int
;
212 if (regnum
== gdbarch_pc_regnum (current_gdbarch
) || regnum
== A1_REGNUM
)
213 return lookup_pointer_type (builtin_type_void
);
215 /* Return the stored type for all other registers. */
216 else if (regnum
>= 0 && regnum
< gdbarch_num_regs (current_gdbarch
)
217 + gdbarch_num_pseudo_regs (current_gdbarch
))
219 xtensa_register_t
* reg
= ®MAP
[regnum
];
221 /* Set ctype for this register (only the first time we ask for it). */
225 struct ctype_cache
*tp
;
226 int size
= reg
->byte_size
;
228 /* We always use the memory representation, even if the register
233 reg
->ctype
= builtin_type_uint8
;
237 reg
->ctype
= builtin_type_uint16
;
241 reg
->ctype
= builtin_type_uint32
;
245 reg
->ctype
= builtin_type_uint64
;
249 reg
->ctype
= builtin_type_uint128
;
253 for (tp
= type_entries
; tp
!= NULL
; tp
= tp
->next
)
254 if (tp
->size
== size
)
259 char *name
= xmalloc (16);
260 tp
= xmalloc (sizeof (struct ctype_cache
));
261 tp
->next
= type_entries
;
265 sprintf (name
, "int%d", size
* 8);
266 tp
->virtual_type
= init_type (TYPE_CODE_INT
, size
,
267 TYPE_FLAG_UNSIGNED
, name
,
271 reg
->ctype
= tp
->virtual_type
;
277 /* Invalid register number. */
278 internal_error (__FILE__
, __LINE__
, _("invalid register number %d"), regnum
);
283 /* Returns the 'local' register number for stubs, dwarf2, etc.
284 The debugging information enumerates registers starting from 0 for A0
285 to n for An. So, we only have to add the base number for A0. */
288 xtensa_reg_to_regnum (int regnum
)
292 if (regnum
>= 0 && regnum
< 16)
293 return A0_BASE
+ regnum
;
296 i
< gdbarch_num_regs (current_gdbarch
)
297 + gdbarch_num_pseudo_regs (current_gdbarch
);
299 if (regnum
== REGMAP
[i
].target_number
)
302 /* Invalid register number. */
303 internal_error (__FILE__
, __LINE__
,
304 _("invalid dwarf/stabs register number %d"), regnum
);
309 /* Handle the special case of masked registers. */
311 /* Write the bits of a masked register to the various registers that
312 are combined into this register. Only the masked areas of these
313 registers are modified; the other fields are untouched.
314 (Note: The size of masked registers is always less or equal 32 bits.) */
317 xtensa_register_write_masked (struct regcache
*regcache
,
318 xtensa_register_t
*reg
, const gdb_byte
*buffer
)
320 unsigned int value
[(MAX_REGISTER_SIZE
+ 3) / 4];
322 const xtensa_mask_t
*mask
= reg
->mask
;
324 int shift
= 0; /* Shift for next mask (mod 32). */
325 int start
, size
; /* Start bit and size of current mask. */
327 unsigned int *ptr
= value
;
328 unsigned int regval
, m
, mem
= 0;
330 int bytesize
= reg
->byte_size
;
331 int bitsize
= bytesize
* 8;
334 DEBUGTRACE ("xtensa_register_write_masked ()\n");
336 /* Copy the masked register to host byte-order. */
337 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
338 for (i
= 0; i
< bytesize
; i
++)
341 mem
|= (buffer
[bytesize
- i
- 1] << 24);
346 for (i
= 0; i
< bytesize
; i
++)
349 mem
|= (buffer
[i
] << 24);
354 /* We might have to shift the final value:
355 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
356 bytesize & 3 == x -> shift (4-x) * 8. */
358 *ptr
= mem
>> (((0 - bytesize
) & 3) * 8);
362 /* Write the bits to the masked areas of the other registers. */
363 for (i
= 0; i
< mask
->count
; i
++)
365 start
= mask
->mask
[i
].bit_start
;
366 size
= mask
->mask
[i
].bit_size
;
367 regval
= mem
>> shift
;
369 if ((shift
+= size
) > bitsize
)
370 error (_("size of all masks is larger than the register"));
379 regval
|= mem
<< (size
- shift
);
382 /* Make sure we have a valid register. */
383 r
= mask
->mask
[i
].reg_num
;
384 if (r
>= 0 && size
> 0)
386 /* Don't overwrite the unmasked areas. */
388 regcache_cooked_read_unsigned (regcache
, r
, &old_val
);
389 m
= 0xffffffff >> (32 - size
) << start
;
391 regval
= (regval
& m
) | (old_val
& ~m
);
392 regcache_cooked_write_unsigned (regcache
, r
, regval
);
398 /* Read the masked areas of the registers and assemble it into a single
402 xtensa_register_read_masked (struct regcache
*regcache
,
403 xtensa_register_t
*reg
, gdb_byte
*buffer
)
405 unsigned int value
[(MAX_REGISTER_SIZE
+ 3) / 4];
407 const xtensa_mask_t
*mask
= reg
->mask
;
412 unsigned int *ptr
= value
;
413 unsigned int regval
, mem
= 0;
415 int bytesize
= reg
->byte_size
;
416 int bitsize
= bytesize
* 8;
419 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
420 reg
->name
== 0 ? "" : reg
->name
);
422 /* Assemble the register from the masked areas of other registers. */
423 for (i
= 0; i
< mask
->count
; i
++)
425 int r
= mask
->mask
[i
].reg_num
;
429 regcache_cooked_read_unsigned (regcache
, r
, &val
);
430 regval
= (unsigned int) val
;
435 start
= mask
->mask
[i
].bit_start
;
436 size
= mask
->mask
[i
].bit_size
;
441 regval
&= (0xffffffff >> (32 - size
));
443 mem
|= regval
<< shift
;
445 if ((shift
+= size
) > bitsize
)
446 error (_("size of all masks is larger than the register"));
457 mem
= regval
>> (size
- shift
);
464 /* Copy value to target byte order. */
468 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
469 for (i
= 0; i
< bytesize
; i
++)
473 buffer
[bytesize
- i
- 1] = mem
& 0xff;
477 for (i
= 0; i
< bytesize
; i
++)
481 buffer
[i
] = mem
& 0xff;
487 /* Read pseudo registers. */
490 xtensa_pseudo_register_read (struct gdbarch
*gdbarch
,
491 struct regcache
*regcache
,
495 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
496 regnum
, xtensa_register_name (regnum
));
498 /* Check if it is FP (renumber it in this case -> A0...A15). */
499 if (regnum
== FP_ALIAS
)
500 error (_("trying to read FP"));
502 /* Read aliases a0..a15. */
503 if (regnum
>= A0_REGNUM
&& regnum
<= A15_REGNUM
)
505 gdb_byte
*buf
= (gdb_byte
*) alloca (MAX_REGISTER_SIZE
);
507 regcache_raw_read (regcache
, WB_REGNUM
, buf
);
508 regnum
= AREG_NUMBER (regnum
, extract_unsigned_integer (buf
, 4));
511 /* We can always read 'regular' registers. */
512 if (regnum
>= 0 && regnum
< gdbarch_num_regs (current_gdbarch
))
513 regcache_raw_read (regcache
, regnum
, buffer
);
515 /* Pseudo registers. */
517 && regnum
< gdbarch_num_regs (current_gdbarch
)
518 + gdbarch_num_pseudo_regs (current_gdbarch
))
520 xtensa_register_t
*reg
= ®MAP
[regnum
];
521 xtensa_register_type_t type
= reg
->type
;
522 int flags
= XTENSA_TARGET_FLAGS
;
524 /* Can we read Unknown or Unmapped registers? */
525 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
527 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
529 warning (_("cannot read register %s"),
530 xtensa_register_name (regnum
));
535 /* Some targets cannot read TIE register files. */
536 else if (type
== xtRegisterTypeTieRegfile
)
538 /* Use 'fetch' to get register? */
539 if (flags
& xtTargetFlagsUseFetchStore
)
541 warning (_("cannot read register"));
545 /* On some targets (esp. simulators), we can always read the reg. */
546 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
548 warning (_("cannot read register"));
553 /* We can always read mapped registers. */
554 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
556 xtensa_register_read_masked (regcache
, reg
, buffer
);
560 /* Assume that we can read the register. */
561 regcache_raw_read (regcache
, regnum
, buffer
);
565 internal_error (__FILE__
, __LINE__
,
566 _("invalid register number %d"), regnum
);
570 /* Write pseudo registers. */
573 xtensa_pseudo_register_write (struct gdbarch
*gdbarch
,
574 struct regcache
*regcache
,
576 const gdb_byte
*buffer
)
578 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
579 regnum
, xtensa_register_name (regnum
));
581 /* Check if this is FP. */
582 if (regnum
== FP_ALIAS
)
583 error (_("trying to write FP"));
585 /* Renumber register, if aliase a0..a15. */
586 if (regnum
>= A0_REGNUM
&& regnum
<= A15_REGNUM
)
588 gdb_byte
*buf
= (gdb_byte
*) alloca (MAX_REGISTER_SIZE
);
591 regcache_raw_read (regcache
, WB_REGNUM
, buf
);
592 regnum
= AREG_NUMBER (regnum
, extract_unsigned_integer (buf
, 4));
595 /* We can always write 'core' registers.
596 Note: We might have converted Ax->ARy. */
597 if (regnum
>= 0 && regnum
< gdbarch_num_regs (current_gdbarch
))
598 regcache_raw_write (regcache
, regnum
, buffer
);
600 /* Pseudo registers. */
602 && regnum
< gdbarch_num_regs (current_gdbarch
)
603 + gdbarch_num_pseudo_regs (current_gdbarch
))
605 xtensa_register_t
*reg
= ®MAP
[regnum
];
606 xtensa_register_type_t type
= reg
->type
;
607 int flags
= XTENSA_TARGET_FLAGS
;
609 /* On most targets, we can't write registers of type "Unknown"
611 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
613 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
615 warning (_("cannot write register %s"),
616 xtensa_register_name (regnum
));
621 /* Some targets cannot read TIE register files. */
622 else if (type
== xtRegisterTypeTieRegfile
)
624 /* Use 'store' to get register? */
625 if (flags
& xtTargetFlagsUseFetchStore
)
627 warning (_("cannot write register"));
631 /* On some targets (esp. simulators), we can always write
634 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
636 warning (_("cannot write register"));
641 /* We can always write mapped registers. */
642 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
644 xtensa_register_write_masked (regcache
, reg
, buffer
);
648 /* Assume that we can write the register. */
649 regcache_raw_write (regcache
, regnum
, buffer
);
653 internal_error (__FILE__
, __LINE__
,
654 _("invalid register number %d"), regnum
);
658 static struct reggroup
*xtensa_ar_reggroup
;
659 static struct reggroup
*xtensa_user_reggroup
;
660 static struct reggroup
*xtensa_vectra_reggroup
;
663 xtensa_init_reggroups (void)
665 xtensa_ar_reggroup
= reggroup_new ("ar", USER_REGGROUP
);
666 xtensa_user_reggroup
= reggroup_new ("user", USER_REGGROUP
);
667 xtensa_vectra_reggroup
= reggroup_new ("vectra", USER_REGGROUP
);
672 xtensa_add_reggroups (struct gdbarch
*gdbarch
)
674 reggroup_add (gdbarch
, all_reggroup
);
675 reggroup_add (gdbarch
, save_reggroup
);
676 reggroup_add (gdbarch
, restore_reggroup
);
677 reggroup_add (gdbarch
, system_reggroup
);
678 reggroup_add (gdbarch
, vector_reggroup
); /* vectra */
679 reggroup_add (gdbarch
, general_reggroup
); /* core */
680 reggroup_add (gdbarch
, float_reggroup
); /* float */
682 reggroup_add (gdbarch
, xtensa_ar_reggroup
); /* ar */
683 reggroup_add (gdbarch
, xtensa_user_reggroup
); /* user */
684 reggroup_add (gdbarch
, xtensa_vectra_reggroup
); /* vectra */
688 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
689 | XTENSA_REGISTER_FLAGS_WRITABLE \
690 | XTENSA_REGISTER_FLAGS_VOLATILE)
692 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
693 | XTENSA_REGISTER_FLAGS_WRITABLE)
696 xtensa_register_reggroup_p (struct gdbarch
*gdbarch
,
698 struct reggroup
*group
)
700 xtensa_register_t
* reg
= ®MAP
[regnum
];
701 xtensa_register_type_t type
= reg
->type
;
702 xtensa_register_group_t rg
= reg
->group
;
704 /* First, skip registers that are not visible to this target
705 (unknown and unmapped registers when not using ISS). */
707 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
709 if (group
== all_reggroup
)
711 if (group
== xtensa_ar_reggroup
)
712 return rg
& xtRegisterGroupAddrReg
;
713 if (group
== xtensa_user_reggroup
)
714 return rg
& xtRegisterGroupUser
;
715 if (group
== float_reggroup
)
716 return rg
& xtRegisterGroupFloat
;
717 if (group
== general_reggroup
)
718 return rg
& xtRegisterGroupGeneral
;
719 if (group
== float_reggroup
)
720 return rg
& xtRegisterGroupFloat
;
721 if (group
== system_reggroup
)
722 return rg
& xtRegisterGroupState
;
723 if (group
== vector_reggroup
|| group
== xtensa_vectra_reggroup
)
724 return rg
& xtRegisterGroupVectra
;
725 if (group
== save_reggroup
|| group
== restore_reggroup
)
726 return (regnum
< gdbarch_num_regs (current_gdbarch
)
727 && (reg
->flags
& SAVE_REST_FLAGS
) == SAVE_REST_VALID
);
733 /* CORE FILE SUPPORT */
735 /* Supply register REGNUM from the buffer specified by GREGS and LEN
736 in the general-purpose register set REGSET to register cache
737 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
740 xtensa_supply_gregset (const struct regset
*regset
,
746 const xtensa_elf_gregset_t
*regs
= gregs
;
749 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...) \n", regnum
);
751 if (regnum
== gdbarch_pc_regnum (current_gdbarch
) || regnum
== -1)
752 regcache_raw_supply (rc
,
753 gdbarch_pc_regnum (current_gdbarch
),
755 if (regnum
== gdbarch_ps_regnum (current_gdbarch
) || regnum
== -1)
756 regcache_raw_supply (rc
, gdbarch_ps_regnum (current_gdbarch
),
758 if (regnum
== WB_REGNUM
|| regnum
== -1)
759 regcache_raw_supply (rc
, WB_REGNUM
, (char *) ®s
->windowbase
);
760 if (regnum
== WS_REGNUM
|| regnum
== -1)
761 regcache_raw_supply (rc
, WS_REGNUM
, (char *) ®s
->windowstart
);
762 if (regnum
== LBEG_REGNUM
|| regnum
== -1)
763 regcache_raw_supply (rc
, LBEG_REGNUM
, (char *) ®s
->lbeg
);
764 if (regnum
== LEND_REGNUM
|| regnum
== -1)
765 regcache_raw_supply (rc
, LEND_REGNUM
, (char *) ®s
->lend
);
766 if (regnum
== LCOUNT_REGNUM
|| regnum
== -1)
767 regcache_raw_supply (rc
, LCOUNT_REGNUM
, (char *) ®s
->lcount
);
768 if (regnum
== SAR_REGNUM
|| regnum
== -1)
769 regcache_raw_supply (rc
, SAR_REGNUM
, (char *) ®s
->sar
);
770 if (regnum
== EXCCAUSE_REGNUM
|| regnum
== -1)
771 regcache_raw_supply (rc
, EXCCAUSE_REGNUM
, (char *) ®s
->exccause
);
772 if (regnum
== EXCVADDR_REGNUM
|| regnum
== -1)
773 regcache_raw_supply (rc
, EXCVADDR_REGNUM
, (char *) ®s
->excvaddr
);
774 if (regnum
>= AR_BASE
&& regnum
< AR_BASE
+ NUM_AREGS
)
775 regcache_raw_supply (rc
, regnum
, (char *) ®s
->ar
[regnum
- AR_BASE
]);
776 else if (regnum
== -1)
778 for (i
= 0; i
< NUM_AREGS
; ++i
)
779 regcache_raw_supply (rc
, AR_BASE
+ i
, (char *) ®s
->ar
[i
]);
784 /* Xtensa register set. */
790 xtensa_supply_gregset
794 /* Return the appropriate register set for the core section identified
795 by SECT_NAME and SECT_SIZE. */
797 static const struct regset
*
798 xtensa_regset_from_core_section (struct gdbarch
*core_arch
,
799 const char *sect_name
,
802 DEBUGTRACE ("xtensa_regset_from_core_section "
803 "(..., sect_name==\"%s\", sect_size==%x) \n",
804 sect_name
, (int) sect_size
);
806 if (strcmp (sect_name
, ".reg") == 0
807 && sect_size
>= sizeof(xtensa_elf_gregset_t
))
808 return &xtensa_gregset
;
816 /* We currently don't support the call0-abi, so we have at max. 12 registers
817 saved on the stack. */
819 #define XTENSA_NUM_SAVED_AREGS 12
821 typedef struct xtensa_frame_cache
825 CORE_ADDR ra
; /* The raw return address; use to compute call_inc. */
827 int wb
; /* Base for this frame; -1 if not in regfile. */
828 int callsize
; /* Call size to next frame. */
830 CORE_ADDR aregs
[XTENSA_NUM_SAVED_AREGS
];
832 } xtensa_frame_cache_t
;
835 static struct xtensa_frame_cache
*
836 xtensa_alloc_frame_cache (void)
838 xtensa_frame_cache_t
*cache
;
841 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
843 cache
= FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t
);
850 cache
->callsize
= -1;
853 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
854 cache
->aregs
[i
] = -1;
861 xtensa_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
863 return address
& ~15;
868 xtensa_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
872 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %p)\n", next_frame
);
874 frame_unwind_register (next_frame
, gdbarch_pc_regnum (current_gdbarch
), buf
);
876 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int)
877 extract_typed_address (buf
, builtin_type_void_func_ptr
));
879 return extract_typed_address (buf
, builtin_type_void_func_ptr
);
883 static struct frame_id
884 xtensa_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
889 /* next_frame->prev is a dummy frame. Return a frame ID of that frame. */
891 DEBUGTRACE ("xtensa_unwind_dummy_id ()\n");
893 pc
= frame_pc_unwind (next_frame
);
894 frame_unwind_register (next_frame
, A1_REGNUM
, buf
);
895 fp
= extract_unsigned_integer (buf
, 4);
897 /* Make dummy frame ID unique by adding a constant. */
898 return frame_id_build (fp
+SP_ALIGNMENT
, pc
);
902 static struct xtensa_frame_cache
*
903 xtensa_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
905 xtensa_frame_cache_t
*cache
;
907 CORE_ADDR ra
, wb
, ws
, pc
, sp
, ps
;
910 DEBUGTRACE ("xtensa_frame_cache (next_frame %p, *this_cache %p)\n",
911 next_frame
, this_cache
? *this_cache
: (void*)0xdeadbeef);
913 /* Already cached? */
917 /* Get pristine xtensa-frame. */
918 cache
= xtensa_alloc_frame_cache ();
921 /* Get windowbase, windowstart, ps, and pc. */
922 wb
= frame_unwind_register_unsigned (next_frame
, WB_REGNUM
);
923 ws
= frame_unwind_register_unsigned (next_frame
, WS_REGNUM
);
924 ps
= frame_unwind_register_unsigned (next_frame
,
925 gdbarch_ps_regnum (current_gdbarch
));
926 pc
= frame_unwind_register_unsigned (next_frame
,
927 gdbarch_pc_regnum (current_gdbarch
));
929 op1
= read_memory_integer (pc
, 1);
930 if (XTENSA_IS_ENTRY (op1
) || !windowing_enabled (ps
))
932 int callinc
= CALLINC (ps
);
933 ra
= frame_unwind_register_unsigned (next_frame
,
934 A0_REGNUM
+ callinc
* 4);
936 DEBUGINFO("[xtensa_frame_cache] 'entry' at 0x%08x\n (callinc = %d)",
939 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
943 cache
->prev_sp
= frame_unwind_register_unsigned (next_frame
, A1_REGNUM
);
947 ra
= frame_unwind_register_unsigned (next_frame
, A0_REGNUM
);
948 cache
->callsize
= WINSIZE (ra
);
949 cache
->wb
= (wb
- (cache
->callsize
/ 4)) & ((NUM_AREGS
/ 4) - 1);
950 cache
->ws
= ws
& ~(1 << wb
);
953 cache
->pc
= ((frame_func_unwind (next_frame
, NORMAL_FRAME
) & 0xc0000000)
954 | (ra
& 0x3fffffff));
955 cache
->ps
= (ps
& ~PS_CALLINC_MASK
) | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
958 /* Note: We could also calculate the location on stack when we actually
959 access the register. However, this approach, saving the location
960 in the cache frame, is probably easier to support the call0 ABI. */
967 sp
= frame_unwind_register_unsigned (next_frame
, A1_REGNUM
) - 16;
969 for (i
= 0; i
< 4; i
++, sp
+= 4)
971 cache
->aregs
[i
] = sp
;
974 if (cache
->callsize
> 4)
976 /* Set A4...A7/A11. */
978 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4);
979 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4);
980 sp
-= cache
->callsize
* 4;
982 for ( /* i=4 */ ; i
< cache
->callsize
; i
++, sp
+= 4)
984 cache
->aregs
[i
] = sp
;
989 if (cache
->prev_sp
== 0)
993 /* Register window overflow already happened.
994 We can read caller's frame SP from the proper spill loction. */
996 read_memory_integer (cache
->aregs
[1],
997 register_size (current_gdbarch
,
1002 /* Read caller's frame SP directly from the previous window. */
1004 int regnum
= AREG_NUMBER (A1_REGNUM
, cache
->wb
);
1006 cache
->prev_sp
= frame_unwind_register_unsigned (next_frame
, regnum
);
1010 cache
->base
= frame_unwind_register_unsigned (next_frame
,A1_REGNUM
);
1012 DEBUGINFO ("[xtensa_frame_cache] base 0x%08x, wb %d, "
1013 "ws 0x%08x, callsize %d, pc 0x%08x, ps 0x%08x, prev_sp 0x%08x\n",
1014 (unsigned int) cache
->base
, (unsigned int) cache
->wb
,
1015 cache
->ws
, cache
->callsize
, (unsigned int) cache
->pc
,
1016 (unsigned int) cache
->ps
, (unsigned int) cache
->prev_sp
);
1023 xtensa_frame_this_id (struct frame_info
*next_frame
,
1025 struct frame_id
*this_id
)
1027 struct xtensa_frame_cache
*cache
=
1028 xtensa_frame_cache (next_frame
, this_cache
);
1030 DEBUGTRACE ("xtensa_frame_this_id (next %p, *this %p)\n",
1031 next_frame
, *this_cache
);
1033 if (cache
->prev_sp
== 0)
1036 (*this_id
) = frame_id_build (cache
->prev_sp
, cache
->pc
);
1041 xtensa_frame_prev_register (struct frame_info
*next_frame
,
1045 enum lval_type
*lvalp
,
1050 struct xtensa_frame_cache
*cache
=
1051 xtensa_frame_cache (next_frame
, this_cache
);
1052 CORE_ADDR saved_reg
= 0;
1055 DEBUGTRACE ("xtensa_frame_prev_register (next %p, "
1056 "*this %p, regnum %d (%s), ...)\n",
1058 *this_cache
? *this_cache
: 0, regnum
,
1059 xtensa_register_name (regnum
));
1061 if (regnum
== WS_REGNUM
)
1064 saved_reg
= cache
->ws
;
1066 saved_reg
= 1 << cache
->wb
;
1068 else if (regnum
== WB_REGNUM
)
1069 saved_reg
= cache
->wb
;
1070 else if (regnum
== gdbarch_pc_regnum (current_gdbarch
))
1071 saved_reg
= cache
->pc
;
1072 else if (regnum
== gdbarch_ps_regnum (current_gdbarch
))
1073 saved_reg
= cache
->ps
;
1084 store_unsigned_integer (valuep
, 4, saved_reg
);
1089 /* Convert Ax register numbers to ARx register numbers. */
1090 if (regnum
>= A0_REGNUM
&& regnum
<= A15_REGNUM
)
1091 regnum
= AREG_NUMBER (regnum
, cache
->wb
);
1093 /* Check if ARx register has been saved to stack. */
1094 if (regnum
>= AR_BASE
&& regnum
<= (AR_BASE
+ NUM_AREGS
))
1096 int areg
= regnum
- AR_BASE
- (cache
->wb
* 4);
1099 && areg
< XTENSA_NUM_SAVED_AREGS
1100 && cache
->aregs
[areg
] != -1)
1103 *lvalp
= lval_memory
;
1104 *addrp
= cache
->aregs
[areg
];
1108 read_memory (*addrp
, valuep
,
1109 register_size (current_gdbarch
, regnum
));
1111 DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n");
1116 /* Note: All other registers have been either saved to the dummy stack
1117 or are still alive in the processor. */
1120 *lvalp
= lval_register
;
1124 frame_unwind_register (next_frame
, (*realnump
), valuep
);
1128 static const struct frame_unwind
1129 xtensa_frame_unwind
=
1132 xtensa_frame_this_id
,
1133 xtensa_frame_prev_register
1136 static const struct frame_unwind
*
1137 xtensa_frame_sniffer (struct frame_info
*next_frame
)
1139 return &xtensa_frame_unwind
;
1143 xtensa_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1145 struct xtensa_frame_cache
*cache
=
1146 xtensa_frame_cache (next_frame
, this_cache
);
1151 static const struct frame_base
1154 &xtensa_frame_unwind
,
1155 xtensa_frame_base_address
,
1156 xtensa_frame_base_address
,
1157 xtensa_frame_base_address
1162 xtensa_extract_return_value (struct type
*type
,
1163 struct regcache
*regcache
,
1166 bfd_byte
*valbuf
= dst
;
1167 int len
= TYPE_LENGTH (type
);
1172 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1174 gdb_assert(len
> 0);
1176 /* First, we have to find the caller window in the register file. */
1177 regcache_raw_read_unsigned (regcache
,
1178 gdbarch_pc_regnum (current_gdbarch
), &pc
);
1179 callsize
= extract_call_winsize (pc
);
1181 /* On Xtensa, we can return up to 4 words (or 2 when called by call12). */
1182 if (len
> (callsize
> 8 ? 8 : 16))
1183 internal_error (__FILE__
, __LINE__
,
1184 _("cannot extract return value of %d bytes long"), len
);
1186 /* Get the register offset of the return register (A2) in the caller
1188 regcache_raw_read_unsigned (regcache
, WB_REGNUM
, &wb
);
1189 areg
= AREG_NUMBER(A2_REGNUM
+ callsize
, wb
);
1191 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg
, len
);
1193 if (len
< 4 && gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1196 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1199 regcache_raw_read_part (regcache
, areg
, offset
, len
, valbuf
);
1201 regcache_raw_read (regcache
, areg
, valbuf
);
1207 xtensa_store_return_value (struct type
*type
,
1208 struct regcache
*regcache
,
1211 const bfd_byte
*valbuf
= dst
;
1215 int len
= TYPE_LENGTH (type
);
1218 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1220 regcache_raw_read_unsigned (regcache
, WB_REGNUM
, &wb
);
1221 regcache_raw_read_unsigned (regcache
,
1222 gdbarch_pc_regnum (current_gdbarch
), &pc
);
1223 callsize
= extract_call_winsize (pc
);
1225 if (len
> (callsize
> 8 ? 8 : 16))
1226 internal_error (__FILE__
, __LINE__
,
1227 _("unimplemented for this length: %d"),
1228 TYPE_LENGTH (type
));
1230 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1231 callsize
, (int) wb
);
1233 if (len
< 4 && gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1236 areg
= AREG_NUMBER (A2_REGNUM
+ callsize
, wb
);
1238 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1241 regcache_raw_write_part (regcache
, areg
, offset
, len
, valbuf
);
1243 regcache_raw_write (regcache
, areg
, valbuf
);
1248 enum return_value_convention
1249 xtensa_return_value (struct gdbarch
*gdbarch
,
1250 struct type
*valtype
,
1251 struct regcache
*regcache
,
1253 const gdb_byte
*writebuf
)
1255 /* Note: Structures up to 16 bytes are returned in registers. */
1257 int struct_return
= ((TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
1258 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
1259 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
1260 && TYPE_LENGTH (valtype
) > 16);
1263 return RETURN_VALUE_STRUCT_CONVENTION
;
1265 DEBUGTRACE ("xtensa_return_value(...)\n");
1267 if (writebuf
!= NULL
)
1269 xtensa_store_return_value (valtype
, regcache
, writebuf
);
1272 if (readbuf
!= NULL
)
1274 gdb_assert (!struct_return
);
1275 xtensa_extract_return_value (valtype
, regcache
, readbuf
);
1277 return RETURN_VALUE_REGISTER_CONVENTION
;
1284 xtensa_push_dummy_call (struct gdbarch
*gdbarch
,
1285 struct value
*function
,
1286 struct regcache
*regcache
,
1289 struct value
**args
,
1292 CORE_ADDR struct_addr
)
1295 int size
, onstack_size
;
1296 gdb_byte
*buf
= (gdb_byte
*) alloca (16);
1298 struct argument_info
1300 const bfd_byte
*contents
;
1302 int onstack
; /* onstack == 0 => in reg */
1303 int align
; /* alignment */
1306 int offset
; /* stack offset if on stack */
1307 int regno
; /* regno if in register */
1311 struct argument_info
*arg_info
=
1312 (struct argument_info
*) alloca (nargs
* sizeof (struct argument_info
));
1316 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1318 if (xtensa_debug_level
> 3)
1321 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs
);
1322 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1323 "struct_addr=0x%x\n",
1324 (int) sp
, (int) struct_return
, (int) struct_addr
);
1326 for (i
= 0; i
< nargs
; i
++)
1328 struct value
*arg
= args
[i
];
1329 struct type
*arg_type
= check_typedef (value_type (arg
));
1330 fprintf_unfiltered (gdb_stdlog
, "%2d: %p %3d ",
1331 i
, arg
, TYPE_LENGTH (arg_type
));
1332 switch (TYPE_CODE (arg_type
))
1335 fprintf_unfiltered (gdb_stdlog
, "int");
1337 case TYPE_CODE_STRUCT
:
1338 fprintf_unfiltered (gdb_stdlog
, "struct");
1341 fprintf_unfiltered (gdb_stdlog
, "%3d", TYPE_CODE (arg_type
));
1344 fprintf_unfiltered (gdb_stdlog
, " %p\n",
1345 value_contents (arg
));
1349 /* First loop: collect information.
1350 Cast into type_long. (This shouldn't happen often for C because
1351 GDB already does this earlier.) It's possible that GDB could
1352 do it all the time but it's harmless to leave this code here. */
1359 size
= REGISTER_SIZE
;
1361 for (i
= 0; i
< nargs
; i
++)
1363 struct argument_info
*info
= &arg_info
[i
];
1364 struct value
*arg
= args
[i
];
1365 struct type
*arg_type
= check_typedef (value_type (arg
));
1367 switch (TYPE_CODE (arg_type
))
1370 case TYPE_CODE_BOOL
:
1371 case TYPE_CODE_CHAR
:
1372 case TYPE_CODE_RANGE
:
1373 case TYPE_CODE_ENUM
:
1375 /* Cast argument to long if necessary as the mask does it too. */
1376 if (TYPE_LENGTH (arg_type
) < TYPE_LENGTH (builtin_type_long
))
1378 arg_type
= builtin_type_long
;
1379 arg
= value_cast (arg_type
, arg
);
1381 info
->align
= TYPE_LENGTH (builtin_type_long
);
1386 /* Align doubles correctly. */
1387 if (TYPE_LENGTH (arg_type
) == TYPE_LENGTH (builtin_type_double
))
1388 info
->align
= TYPE_LENGTH (builtin_type_double
);
1390 info
->align
= TYPE_LENGTH (builtin_type_long
);
1393 case TYPE_CODE_STRUCT
:
1395 info
->align
= TYPE_LENGTH (builtin_type_long
);
1398 info
->length
= TYPE_LENGTH (arg_type
);
1399 info
->contents
= value_contents (arg
);
1401 /* Align size and onstack_size. */
1402 size
= (size
+ info
->align
- 1) & ~(info
->align
- 1);
1403 onstack_size
= (onstack_size
+ info
->align
- 1) & ~(info
->align
- 1);
1405 if (size
+ info
->length
> REGISTER_SIZE
* ARGS_NUM_REGS
)
1408 info
->u
.offset
= onstack_size
;
1409 onstack_size
+= info
->length
;
1414 info
->u
.regno
= ARGS_FIRST_REG
+ size
/ REGISTER_SIZE
;
1416 size
+= info
->length
;
1419 /* Adjust the stack pointer and align it. */
1420 sp
= align_down (sp
- onstack_size
, SP_ALIGNMENT
);
1422 /* Simulate MOVSP. */
1425 read_memory (osp
- 16, buf
, 16);
1426 write_memory (sp
- 16, buf
, 16);
1429 /* Second Loop: Load arguments. */
1433 store_unsigned_integer (buf
, REGISTER_SIZE
, struct_addr
);
1434 regcache_cooked_write (regcache
, ARGS_FIRST_REG
, buf
);
1437 for (i
= 0; i
< nargs
; i
++)
1439 struct argument_info
*info
= &arg_info
[i
];
1443 int n
= info
->length
;
1444 CORE_ADDR offset
= sp
+ info
->u
.offset
;
1446 /* Odd-sized structs are aligned to the lower side of a memory
1447 word in big-endian mode and require a shift. This only
1448 applies for structures smaller than one word. */
1450 if (n
< REGISTER_SIZE
1451 && gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1452 offset
+= (REGISTER_SIZE
- n
);
1454 write_memory (offset
, info
->contents
, info
->length
);
1459 int n
= info
->length
;
1460 const bfd_byte
*cp
= info
->contents
;
1461 int r
= info
->u
.regno
;
1463 /* Odd-sized structs are aligned to the lower side of registers in
1464 big-endian mode and require a shift. The odd-sized leftover will
1465 be at the end. Note that this is only true for structures smaller
1466 than REGISTER_SIZE; for larger odd-sized structures the excess
1467 will be left-aligned in the register on both endiannesses. */
1469 if (n
< REGISTER_SIZE
1470 && gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1472 ULONGEST v
= extract_unsigned_integer (cp
, REGISTER_SIZE
);
1473 v
= v
>> ((REGISTER_SIZE
- n
) * TARGET_CHAR_BIT
);
1475 store_unsigned_integer (buf
, REGISTER_SIZE
, v
);
1476 regcache_cooked_write (regcache
, r
, buf
);
1478 cp
+= REGISTER_SIZE
;
1485 /* ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE);*/
1486 regcache_cooked_write (regcache
, r
, cp
);
1488 /* regcache_cooked_write_unsigned (regcache, r, v); */
1489 cp
+= REGISTER_SIZE
;
1497 /* Set the return address of dummy frame to the dummy address.
1498 Note: The return address for the current function (in A0) is
1499 saved in the dummy frame, so we can savely overwrite A0 here. */
1501 ra
= (bp_addr
& 0x3fffffff) | 0x40000000;
1502 regcache_raw_read (regcache
, gdbarch_ps_regnum (current_gdbarch
), buf
);
1503 ps
= extract_unsigned_integer (buf
, 4) & ~0x00030000;
1504 regcache_cooked_write_unsigned (regcache
, A4_REGNUM
, ra
);
1505 regcache_cooked_write_unsigned (regcache
,
1506 gdbarch_ps_regnum (current_gdbarch
),
1509 /* Set new stack pointer and return it. */
1510 regcache_cooked_write_unsigned (regcache
, A1_REGNUM
, sp
);
1511 /* Make dummy frame ID unique by adding a constant. */
1512 return sp
+ SP_ALIGNMENT
;
1516 /* Return a breakpoint for the current location of PC. We always use
1517 the density version if we have density instructions (regardless of the
1518 current instruction at PC), and use regular instructions otherwise. */
1520 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1521 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1522 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1523 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1525 const unsigned char *
1526 xtensa_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
1528 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
1529 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
1530 static unsigned char density_big_breakpoint
[] = DENSITY_BIG_BREAKPOINT
;
1531 static unsigned char density_little_breakpoint
[] = DENSITY_LITTLE_BREAKPOINT
;
1533 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr
);
1535 if (ISA_USE_DENSITY_INSTRUCTIONS
)
1537 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1539 *lenptr
= sizeof (density_big_breakpoint
);
1540 return density_big_breakpoint
;
1544 *lenptr
= sizeof (density_little_breakpoint
);
1545 return density_little_breakpoint
;
1550 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1552 *lenptr
= sizeof (big_breakpoint
);
1553 return big_breakpoint
;
1557 *lenptr
= sizeof (little_breakpoint
);
1558 return little_breakpoint
;
1564 /* Return the pc of the first real instruction. We assume that this
1565 machine uses register windows.
1567 If we have debug info ( line-number info, in particular ) we simply skip
1568 the code associated with the first function line effectively skipping
1569 the prologue code. It works even in cases like
1572 { int local_var = 1;
1576 because, for this source code, both Xtensa compilers will generate two
1577 separate entries ( with the same line number ) in dwarf line-number
1578 section to make sure there is a boundary between the prologue code and
1579 the rest of the function.
1581 If there is no debug info, we need to analyze the code. */
1584 xtensa_skip_prologue (CORE_ADDR start_pc
)
1586 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc
);
1588 if (ISA_USE_WINDOWED_REGISTERS
)
1591 struct symtab_and_line prologue_sal
;
1593 op1
= read_memory_integer (start_pc
, 1);
1594 if (!XTENSA_IS_ENTRY (op1
))
1597 prologue_sal
= find_pc_line (start_pc
, 0);
1598 if (prologue_sal
.line
!= 0)
1599 return prologue_sal
.end
;
1601 return start_pc
+ XTENSA_ENTRY_LENGTH
;
1605 internal_error (__FILE__
, __LINE__
,
1606 _("non-windowed configurations are not supported"));
1612 /* CONFIGURATION CHECK */
1614 /* Verify the current configuration. */
1617 xtensa_verify_config (struct gdbarch
*gdbarch
)
1619 struct ui_file
*log
;
1620 struct cleanup
*cleanups
;
1621 struct gdbarch_tdep
*tdep
;
1625 tdep
= gdbarch_tdep (gdbarch
);
1626 log
= mem_fileopen ();
1627 cleanups
= make_cleanup_ui_file_delete (log
);
1629 /* Verify that we got a reasonable number of AREGS. */
1630 if ((tdep
->num_aregs
& -tdep
->num_aregs
) != tdep
->num_aregs
)
1631 fprintf_unfiltered (log
, "\n\tnum_aregs: Number of AR registers (%d) "
1632 "is not a power of two!", tdep
->num_aregs
);
1634 /* Verify that certain registers exist. */
1635 if (tdep
->pc_regnum
== -1)
1636 fprintf_unfiltered (log
, "\n\tpc_regnum: No PC register");
1637 if (tdep
->ps_regnum
== -1)
1638 fprintf_unfiltered (log
, "\n\tps_regnum: No PS register");
1639 if (tdep
->wb_regnum
== -1)
1640 fprintf_unfiltered (log
, "\n\twb_regnum: No WB register");
1641 if (tdep
->ws_regnum
== -1)
1642 fprintf_unfiltered (log
, "\n\tws_regnum: No WS register");
1643 if (tdep
->ar_base
== -1)
1644 fprintf_unfiltered (log
, "\n\tar_base: No AR registers");
1645 if (tdep
->a0_base
== -1)
1646 fprintf_unfiltered (log
, "\n\ta0_base: No Ax registers");
1648 buf
= ui_file_xstrdup (log
, &dummy
);
1649 make_cleanup (xfree
, buf
);
1650 if (strlen (buf
) > 0)
1651 internal_error (__FILE__
, __LINE__
,
1652 _("the following are invalid: %s"), buf
);
1653 do_cleanups (cleanups
);
1657 /* Module "constructor" function. */
1659 static struct gdbarch
*
1660 xtensa_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1662 struct gdbarch_tdep
*tdep
;
1663 struct gdbarch
*gdbarch
;
1664 struct xtensa_abi_handler
*abi_handler
;
1666 DEBUGTRACE ("gdbarch_init()\n");
1668 /* We have to set the byte order before we call gdbarch_alloc. */
1669 info
.byte_order
= xtensa_config_byte_order (&info
);
1671 tdep
= xtensa_config_tdep (&info
);
1672 gdbarch
= gdbarch_alloc (&info
, tdep
);
1674 /* Verify our configuration. */
1675 xtensa_verify_config (gdbarch
);
1677 /* Pseudo-Register read/write */
1678 set_gdbarch_pseudo_register_read (gdbarch
, xtensa_pseudo_register_read
);
1679 set_gdbarch_pseudo_register_write (gdbarch
, xtensa_pseudo_register_write
);
1681 /* Set target information. */
1682 set_gdbarch_num_regs (gdbarch
, tdep
->num_regs
);
1683 set_gdbarch_num_pseudo_regs (gdbarch
, tdep
->num_pseudo_regs
);
1684 set_gdbarch_sp_regnum (gdbarch
, tdep
->a0_base
+ 1);
1685 set_gdbarch_pc_regnum (gdbarch
, tdep
->pc_regnum
);
1686 set_gdbarch_ps_regnum (gdbarch
, tdep
->ps_regnum
);
1688 /* Renumber registers for known formats (stab, dwarf, and dwarf2). */
1689 set_gdbarch_stab_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
1690 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
1691 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
1693 /* We provide our own function to get register information. */
1694 set_gdbarch_register_name (gdbarch
, xtensa_register_name
);
1695 set_gdbarch_register_type (gdbarch
, xtensa_register_type
);
1697 /* To call functions from GDB using dummy frame */
1698 set_gdbarch_push_dummy_call (gdbarch
, xtensa_push_dummy_call
);
1700 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
1702 set_gdbarch_return_value (gdbarch
, xtensa_return_value
);
1704 /* Advance PC across any prologue instructions to reach "real" code. */
1705 set_gdbarch_skip_prologue (gdbarch
, xtensa_skip_prologue
);
1707 /* Stack grows downward. */
1708 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1710 /* Set breakpoints. */
1711 set_gdbarch_breakpoint_from_pc (gdbarch
, xtensa_breakpoint_from_pc
);
1713 /* After breakpoint instruction or illegal instruction, pc still
1714 points at break instruction, so don't decrement. */
1715 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
1717 /* We don't skip args. */
1718 set_gdbarch_frame_args_skip (gdbarch
, 0);
1720 set_gdbarch_unwind_pc (gdbarch
, xtensa_unwind_pc
);
1722 set_gdbarch_frame_align (gdbarch
, xtensa_frame_align
);
1724 set_gdbarch_unwind_dummy_id (gdbarch
, xtensa_unwind_dummy_id
);
1726 /* Frame handling. */
1727 frame_base_set_default (gdbarch
, &xtensa_frame_base
);
1728 frame_unwind_append_sniffer (gdbarch
, xtensa_frame_sniffer
);
1730 set_gdbarch_print_insn (gdbarch
, print_insn_xtensa
);
1732 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
1734 xtensa_add_reggroups (gdbarch
);
1735 set_gdbarch_register_reggroup_p (gdbarch
, xtensa_register_reggroup_p
);
1737 set_gdbarch_regset_from_core_section (gdbarch
,
1738 xtensa_regset_from_core_section
);
1744 /* Dump xtensa tdep structure. */
1747 xtensa_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
1749 error (_("xtensa_dump_tdep(): not implemented"));
1754 _initialize_xtensa_tdep (void)
1756 struct cmd_list_element
*c
;
1758 gdbarch_register (bfd_arch_xtensa
, xtensa_gdbarch_init
, xtensa_dump_tdep
);
1759 xtensa_init_reggroups ();
1761 add_setshow_zinteger_cmd ("xtensa",
1763 &xtensa_debug_level
, _("\
1764 Set Xtensa debugging."), _("\
1765 Show Xtensa debugging."), _("\
1766 When non-zero, Xtensa-specific debugging is enabled. \
1767 Can be 1, 2, 3, or 4 indicating the level of debugging."),
1770 &setdebuglist
, &showdebuglist
);