1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 /* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION
22 whenever the "tdep" structure changes in an incompatible way. */
24 #define XTENSA_TDEP_VERSION 0x60
26 /* Xtensa register type. */
30 xtRegisterTypeArRegfile
= 1, /* Register File ar0..arXX. */
31 xtRegisterTypeSpecialReg
, /* CPU states, such as PS, Booleans, (rsr). */
32 xtRegisterTypeUserReg
, /* User defined registers (rur). */
33 xtRegisterTypeTieRegfile
, /* User define register files. */
34 xtRegisterTypeTieState
, /* TIE States (mapped on user regs). */
35 xtRegisterTypeMapped
, /* Mapped on Special Registers. */
36 xtRegisterTypeUnmapped
, /* Special case of masked registers. */
37 xtRegisterTypeWindow
, /* Live window registers (a0..a15). */
38 xtRegisterTypeVirtual
, /* PC, FP. */
40 } xtensa_register_type_t
;
43 /* Xtensa register group. */
45 #define XTENSA_MAX_COPROCESSOR 0x08 /* Number of Xtensa coprocessors. */
49 xtRegisterGroupUnknown
= 0,
50 xtRegisterGroupRegFile
= 0x0001, /* Register files without ARx. */
51 xtRegisterGroupAddrReg
= 0x0002, /* ARx. */
52 xtRegisterGroupSpecialReg
= 0x0004, /* SRxx. */
53 xtRegisterGroupUserReg
= 0x0008, /* URxx. */
54 xtRegisterGroupState
= 0x0010, /* States. */
56 xtRegisterGroupGeneral
= 0x0100, /* General registers, Ax, SR. */
57 xtRegisterGroupUser
= 0x0200, /* User registers. */
58 xtRegisterGroupFloat
= 0x0400, /* Floating Point. */
59 xtRegisterGroupVectra
= 0x0800, /* Vectra. */
60 xtRegisterGroupSystem
= 0x1000, /* System. */
62 xtRegisterGroupCP0
= 0x01000000, /* CP0. */
63 xtRegisterGroupCP1
= 0x02000000, /* CP1. */
64 xtRegisterGroupCP2
= 0x04000000, /* CP2. */
65 xtRegisterGroupCP3
= 0x08000000, /* CP3. */
66 xtRegisterGroupCP4
= 0x10000000, /* CP4. */
67 xtRegisterGroupCP5
= 0x20000000, /* CP5. */
68 xtRegisterGroupCP6
= 0x40000000, /* CP6. */
69 xtRegisterGroupCP7
= 0x80000000, /* CP7. */
71 } xtensa_register_group_t
;
74 /* Xtensa target flags. */
78 xtTargetFlagsNonVisibleRegs
= 0x0001,
79 xtTargetFlagsUseFetchStore
= 0x0002,
80 } xtensa_target_flags_t
;
83 /* Xtensa ELF core file register set representation ('.reg' section).
84 Copied from target-side ELF header <xtensa/elf.h>. */
86 typedef unsigned long xtensa_elf_greg_t
;
90 xtensa_elf_greg_t xchal_config_id0
;
91 xtensa_elf_greg_t xchal_config_id1
;
92 xtensa_elf_greg_t cpux
;
93 xtensa_elf_greg_t cpuy
;
96 xtensa_elf_greg_t exccause
;
97 xtensa_elf_greg_t excvaddr
;
98 xtensa_elf_greg_t windowbase
;
99 xtensa_elf_greg_t windowstart
;
100 xtensa_elf_greg_t lbeg
;
101 xtensa_elf_greg_t lend
;
102 xtensa_elf_greg_t lcount
;
103 xtensa_elf_greg_t sar
;
104 xtensa_elf_greg_t syscall
;
105 xtensa_elf_greg_t ar
[0]; /* variable size (per config). */
106 } xtensa_elf_gregset_t
;
108 #define SIZEOF_GREGSET (sizeof (xtensa_elf_gregset_t) + gdbarch_tdep (current_gdbarch)->num_aregs * 4)
109 #define XTENSA_ELF_NGREG (SIZEOF_GREGSET / sizeof(xtensa_elf_greg_t))
124 xtensa_reg_mask_t
*mask
;
128 /* Xtensa register representation. */
132 char* name
; /* Register name. */
133 int offset
; /* Offset. */
134 xtensa_register_type_t type
; /* Register type. */
135 xtensa_register_group_t group
;/* Register group. */
136 struct type
* ctype
; /* C-type. */
137 int bit_size
; /* The actual bit size in the target. */
138 int byte_size
; /* Actual space allocated in registers[]. */
139 int align
; /* Alignment for this register. */
141 unsigned int target_number
; /* Register target number. */
143 int flags
; /* Flags. */
145 const xtensa_mask_t
*mask
; /* Register is a compilation of other regs. */
146 const char *fetch
; /* Instruction sequence to fetch register. */
147 const char *store
; /* Instruction sequence to store register. */
151 #define XTENSA_REGISTER_FLAGS_PRIVILEDGED 0x0001
152 #define XTENSA_REGISTER_FLAGS_READABLE 0x0002
153 #define XTENSA_REGISTER_FLAGS_WRITABLE 0x0004
154 #define XTENSA_REGISTER_FLAGS_VOLATILE 0x0008
157 /* Call-ABI for stack frame. */
161 CallAbiDefault
= 0, /* Any 'callX' instructions; default stack. */
162 CallAbiCall0Only
, /* Only 'call0' instructions; flat stack. */
166 /* Xtensa-specific target dependencies. */
170 unsigned int target_flags
;
172 /* Spill location for TIE register files under ocd. */
174 unsigned int spill_location
;
175 unsigned int spill_size
;
177 char *unused
; /* Placeholder for compatibility. */
178 call_abi_t call_abi
; /* Calling convention. */
180 /* CPU configuration. */
182 unsigned int debug_interrupt_level
;
184 unsigned int icache_line_bytes
;
185 unsigned int dcache_line_bytes
;
186 unsigned int dcache_writeback
;
188 unsigned int isa_use_windowed_registers
;
189 unsigned int isa_use_density_instructions
;
190 unsigned int isa_use_exceptions
;
191 unsigned int isa_use_ext_l32r
;
192 unsigned int isa_max_insn_size
; /* Maximum instruction length. */
193 unsigned int debug_num_ibreaks
; /* Number of IBREAKs. */
194 unsigned int debug_num_dbreaks
;
198 xtensa_register_t
* regmap
;
200 unsigned int num_regs
; /* Number of registers in regmap. */
201 unsigned int num_pseudo_regs
; /* Number of pseudo registers. */
202 unsigned int num_aregs
; /* Size of register file. */
203 unsigned int num_contexts
;
205 int ar_base
; /* Register number for AR0. */
206 int a0_base
; /* Register number for A0 (pseudo). */
207 int wb_regnum
; /* Register number for WB. */
208 int ws_regnum
; /* Register number for WS. */
209 int pc_regnum
; /* Register number for PC. */
210 int ps_regnum
; /* Register number for PS. */
211 int lbeg_regnum
; /* Register numbers for count regs. */
214 int sar_regnum
; /* Register number of SAR. */
215 int litbase_regnum
; /* Register number of LITBASE. */
217 int interrupt_regnum
; /* Register number for interrupt. */
218 int interrupt2_regnum
; /* Register number for interrupt2. */
219 int cpenable_regnum
; /* Register number for cpenable. */
220 int debugcause_regnum
; /* Register number for debugcause. */
221 int exccause_regnum
; /* Register number for exccause. */
222 int excvaddr_regnum
; /* Register number for excvaddr. */
224 int max_register_raw_size
;
225 int max_register_virtual_size
;
226 unsigned long *fp_layout
; /* Layout of custom/TIE regs in 'FP' area. */
227 unsigned int fp_layout_bytes
; /* Size of layout information (in bytes). */
228 unsigned long *gregmap
;
234 /* We assign fixed numbers to the registers of the "current" window
235 (i.e., relative to WB). The registers get remapped via the reg_map
236 data structure to their corresponding register in the AR register
237 file (see xtensa-tdep.c). */