gdb/xtensa-tdep.h

   1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
   2
   3    Copyright (C) 2003-2015 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20
  21 #include "arch/xtensa.h"
  22
  23 /* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION
  24    whenever the "tdep" structure changes in an incompatible way.  */
  25
  26 #define XTENSA_TDEP_VERSION 0x60
  27
  28 /*  Xtensa register type.  */
  29
  30 typedef enum
  31 {
  32   xtRegisterTypeArRegfile = 1,  /* Register File ar0..arXX.  */
  33   xtRegisterTypeSpecialReg,     /* CPU states, such as PS, Booleans, (rsr).  */
  34   xtRegisterTypeUserReg,        /* User defined registers (rur).  */
  35   xtRegisterTypeTieRegfile,     /* User define register files.  */
  36   xtRegisterTypeTieState,       /* TIE States (mapped on user regs).  */
  37   xtRegisterTypeMapped,         /* Mapped on Special Registers.  */
  38   xtRegisterTypeUnmapped,       /* Special case of masked registers.  */
  39   xtRegisterTypeWindow,         /* Live window registers (a0..a15).  */
  40   xtRegisterTypeVirtual,        /* PC, FP.  */
  41   xtRegisterTypeUnknown
  42 } xtensa_register_type_t;
  43
  44
  45 /*  Xtensa register group.  */
  46
  47 #define XTENSA_MAX_COPROCESSOR  0x10  /* Number of Xtensa coprocessors.  */
  48
  49 typedef enum
  50 {
  51   xtRegisterGroupUnknown = 0,
  52   xtRegisterGroupRegFile        = 0x0001,    /* Register files without ARx.  */
  53   xtRegisterGroupAddrReg        = 0x0002,    /* ARx.  */
  54   xtRegisterGroupSpecialReg     = 0x0004,    /* SRxx.  */
  55   xtRegisterGroupUserReg        = 0x0008,    /* URxx.  */
  56   xtRegisterGroupState          = 0x0010,    /* States.  */
  57
  58   xtRegisterGroupGeneral        = 0x0100,    /* General registers, Ax, SR.  */
  59   xtRegisterGroupUser           = 0x0200,    /* User registers.  */
  60   xtRegisterGroupFloat          = 0x0400,    /* Floating Point.  */
  61   xtRegisterGroupVectra         = 0x0800,    /* Vectra.  */
  62   xtRegisterGroupSystem         = 0x1000,    /* System.  */
  63
  64   xtRegisterGroupNCP        = 0x00800000,    /* Non-CP non-base opt/custom.  */
  65   xtRegisterGroupCP0        = 0x01000000,    /* CP0.  */
  66   xtRegisterGroupCP1        = 0x02000000,    /* CP1.  */
  67   xtRegisterGroupCP2        = 0x04000000,    /* CP2.  */
  68   xtRegisterGroupCP3        = 0x08000000,    /* CP3.  */
  69   xtRegisterGroupCP4        = 0x10000000,    /* CP4.  */
  70   xtRegisterGroupCP5        = 0x20000000,    /* CP5.  */
  71   xtRegisterGroupCP6        = 0x40000000,    /* CP6.  */
  72   xtRegisterGroupCP7        = 0x80000000,    /* CP7.  */
  73
  74 } xtensa_register_group_t;
  75
  76
  77 /*  Xtensa target flags.  */
  78
  79 typedef enum
  80 {
  81   xtTargetFlagsNonVisibleRegs   = 0x0001,
  82   xtTargetFlagsUseFetchStore    = 0x0002,
  83 } xtensa_target_flags_t;
  84
  85
  86 /*  Mask.  */
  87
  88 typedef struct
  89 {
  90   int reg_num;
  91   int bit_start;
  92   int bit_size;
  93 } xtensa_reg_mask_t;
  94
  95 typedef struct
  96 {
  97   int count;
  98   xtensa_reg_mask_t *mask;
  99 } xtensa_mask_t;
 100
 101
 102 /*  Xtensa register representation.  */
 103
 104 typedef struct
 105 {
 106   char* name;                   /* Register name.  */
 107   int offset;                   /* Offset.  */
 108   xtensa_register_type_t type;  /* Register type.  */
 109   xtensa_register_group_t group;/* Register group.  */
 110   struct type* ctype;           /* C-type.  */
 111   int bit_size;                 /* The actual bit size in the target.  */
 112   int byte_size;                /* Actual space allocated in registers[].  */
 113   int align;                    /* Alignment for this register.  */
 114
 115   unsigned int target_number;   /* Register target number.  */
 116
 117   int flags;                    /* Flags.  */
 118   int coprocessor;              /* Coprocessor num, -1 for non-CP, else -2.  */
 119
 120   const xtensa_mask_t *mask;    /* Register is a compilation of other regs.  */
 121   const char *fetch;            /* Instruction sequence to fetch register.  */
 122   const char *store;            /* Instruction sequence to store register.  */
 123 } xtensa_register_t;
 124
 125 /*  For xtensa-config.c to expand to the structure above.  */
 126 #define XTREG(index,ofs,bsz,sz,al,tnum,flg,cp,ty,gr,name,fet,sto,mas,ct,x,y) \
 127         {#name, ofs, ty, ((gr) | ((xtRegisterGroupNCP >> 2) << (cp + 2))), \
 128          ct, bsz, sz, al, tnum, flg, cp, mas, fet, sto},
 129 #define XTREG_END {0, 0, 0, 0, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0},
 130
 131 #define XTENSA_REGISTER_FLAGS_PRIVILEGED        0x0001
 132 #define XTENSA_REGISTER_FLAGS_READABLE          0x0002
 133 #define XTENSA_REGISTER_FLAGS_WRITABLE          0x0004
 134 #define XTENSA_REGISTER_FLAGS_VOLATILE          0x0008
 135
 136 /*  Call-ABI for stack frame.  */
 137
 138 typedef enum
 139 {
 140   CallAbiDefault = 0,           /* Any 'callX' instructions; default stack.  */
 141   CallAbiCall0Only,             /* Only 'call0' instructions; flat stack.  */
 142 } call_abi_t;
 143
 144
 145 struct ctype_cache
 146 {
 147   struct ctype_cache *next;
 148   int size;
 149   struct type *virtual_type;
 150 };
 151
 152 /*  Xtensa-specific target dependencies.  */
 153
 154 struct gdbarch_tdep
 155 {
 156   unsigned int target_flags;
 157
 158   /* Spill location for TIE register files under ocd.  */
 159
 160   unsigned int spill_location;
 161   unsigned int spill_size;
 162
 163   char *unused;                         /* Placeholder for compatibility.  */
 164   call_abi_t call_abi;                  /* Calling convention.  */
 165
 166   /* CPU configuration.  */
 167
 168   unsigned int debug_interrupt_level;
 169
 170   unsigned int icache_line_bytes;
 171   unsigned int dcache_line_bytes;
 172   unsigned int dcache_writeback;
 173
 174   unsigned int isa_use_windowed_registers;
 175   unsigned int isa_use_density_instructions;
 176   unsigned int isa_use_exceptions;
 177   unsigned int isa_use_ext_l32r;
 178   unsigned int isa_max_insn_size;       /* Maximum instruction length.  */
 179   unsigned int debug_num_ibreaks;       /* Number of IBREAKs.  */
 180   unsigned int debug_num_dbreaks;
 181
 182   /* Register map.  */
 183
 184   xtensa_register_t* regmap;
 185
 186   unsigned int num_regs;        /* Number of registers in register map.  */
 187   unsigned int num_nopriv_regs; /* Number of non-privileged registers.  */
 188   unsigned int num_pseudo_regs; /* Number of pseudo registers.  */
 189   unsigned int num_aregs;       /* Size of register file.  */
 190   unsigned int num_contexts;
 191
 192   int ar_base;                  /* Register number for AR0.  */
 193   int a0_base;                  /* Register number for A0 (pseudo).  */
 194   int wb_regnum;                /* Register number for WB.  */
 195   int ws_regnum;                /* Register number for WS.  */
 196   int pc_regnum;                /* Register number for PC.  */
 197   int ps_regnum;                /* Register number for PS.  */
 198   int lbeg_regnum;              /* Register numbers for count regs.  */
 199   int lend_regnum;
 200   int lcount_regnum;
 201   int sar_regnum;               /* Register number of SAR.  */
 202   int litbase_regnum;           /* Register number of LITBASE.  */
 203
 204   int interrupt_regnum;         /* Register number for interrupt.  */
 205   int interrupt2_regnum;        /* Register number for interrupt2.  */
 206   int cpenable_regnum;          /* Register number for cpenable.  */
 207   int debugcause_regnum;        /* Register number for debugcause.  */
 208   int exccause_regnum;          /* Register number for exccause.  */
 209   int excvaddr_regnum;          /* Register number for excvaddr.  */
 210
 211   int max_register_raw_size;
 212   int max_register_virtual_size;
 213   unsigned long *fp_layout;     /* Layout of custom/TIE regs in 'FP' area.  */
 214   unsigned int fp_layout_bytes; /* Size of layout information (in bytes).  */
 215   unsigned long *gregmap;
 216
 217   /* Cached register types.  */
 218   struct ctype_cache *type_entries;
 219 };
 220
 221 /* Macro to instantiate a gdbarch_tdep structure.  */
 222
 223 #define XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spillsz)           \
 224         {                                                       \
 225           .target_flags = 0,                                    \
 226           .spill_location = -1,                                 \
 227           .spill_size = (spillsz),                              \
 228           .unused = 0,                                          \
 229           .call_abi = (XSHAL_ABI == XTHAL_ABI_CALL0             \
 230                        ? CallAbiCall0Only                       \
 231                        : CallAbiDefault),                       \
 232           .debug_interrupt_level = XCHAL_DEBUGLEVEL,            \
 233           .icache_line_bytes = XCHAL_ICACHE_LINESIZE,           \
 234           .dcache_line_bytes = XCHAL_DCACHE_LINESIZE,           \
 235           .dcache_writeback = XCHAL_DCACHE_IS_WRITEBACK,        \
 236           .isa_use_windowed_registers = (XSHAL_ABI != XTHAL_ABI_CALL0), \
 237           .isa_use_density_instructions = XCHAL_HAVE_DENSITY,   \
 238           .isa_use_exceptions = XCHAL_HAVE_EXCEPTIONS,          \
 239           .isa_use_ext_l32r = XSHAL_USE_ABSOLUTE_LITERALS,      \
 240           .isa_max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE,      \
 241           .debug_num_ibreaks = XCHAL_NUM_IBREAK,                \
 242           .debug_num_dbreaks = XCHAL_NUM_DBREAK,                \
 243           .regmap = rmap,                       \
 244           .num_regs = 0,                        \
 245           .num_nopriv_regs = 0,                 \
 246           .num_pseudo_regs = 0,                 \
 247           .num_aregs = XCHAL_NUM_AREGS,         \
 248           .num_contexts = XCHAL_NUM_CONTEXTS,   \
 249           .ar_base = -1,                        \
 250           .a0_base = -1,                        \
 251           .wb_regnum = -1,                      \
 252           .ws_regnum = -1,                      \
 253           .pc_regnum = -1,                      \
 254           .ps_regnum = -1,                      \
 255           .lbeg_regnum = -1,                    \
 256           .lend_regnum = -1,                    \
 257           .lcount_regnum = -1,                  \
 258           .sar_regnum = -1,                     \
 259           .litbase_regnum = -1,                 \
 260           .interrupt_regnum = -1,               \
 261           .interrupt2_regnum = -1,              \
 262           .cpenable_regnum = -1,                \
 263           .debugcause_regnum = -1,              \
 264           .exccause_regnum = -1,                \
 265           .excvaddr_regnum = -1,                \
 266           .max_register_raw_size = 0,           \
 267           .max_register_virtual_size = 0,       \
 268           .fp_layout = 0,                       \
 269           .fp_layout_bytes = 0,                 \
 270           .gregmap = 0,                         \
 271         }
 272 #define XTENSA_CONFIG_INSTANTIATE(rmap,spill_size)      \
 273         struct gdbarch_tdep xtensa_tdep = \
 274           XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spill_size);
 275
 276 #ifndef XCHAL_NUM_CONTEXTS
 277 #define XCHAL_NUM_CONTEXTS      0
 278 #endif
 279 #ifndef XCHAL_HAVE_EXCEPTIONS
 280 #define XCHAL_HAVE_EXCEPTIONS   1
 281 #endif
 282 #define WB_SHIFT          2
 283
 284 /* We assign fixed numbers to the registers of the "current" window
 285    (i.e., relative to WB).  The registers get remapped via the reg_map
 286    data structure to their corresponding register in the AR register
 287    file (see xtensa-tdep.c).  */
 288