1 /* GNU/Linux/AArch64 specific low level interface, for the remote server for
4 Copyright (C) 2009-2021 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "linux-low.h"
24 #include "nat/aarch64-linux.h"
25 #include "nat/aarch64-linux-hw-point.h"
26 #include "arch/aarch64-insn.h"
27 #include "linux-aarch32-low.h"
28 #include "elf/common.h"
30 #include "tracepoint.h"
35 #include "nat/gdb_ptrace.h"
36 #include <asm/ptrace.h>
41 #include "gdb_proc_service.h"
42 #include "arch/aarch64.h"
43 #include "arch/aarch64-mte-linux.h"
44 #include "linux-aarch32-tdesc.h"
45 #include "linux-aarch64-tdesc.h"
46 #include "nat/aarch64-mte-linux-ptrace.h"
47 #include "nat/aarch64-sve-linux-ptrace.h"
58 /* Linux target op definitions for the AArch64 architecture. */
60 class aarch64_target
: public linux_process_target
64 const regs_info
*get_regs_info () override
;
66 int breakpoint_kind_from_pc (CORE_ADDR
*pcptr
) override
;
68 int breakpoint_kind_from_current_state (CORE_ADDR
*pcptr
) override
;
70 const gdb_byte
*sw_breakpoint_from_kind (int kind
, int *size
) override
;
72 bool supports_z_point_type (char z_type
) override
;
74 bool supports_tracepoints () override
;
76 bool supports_fast_tracepoints () override
;
78 int install_fast_tracepoint_jump_pad
79 (CORE_ADDR tpoint
, CORE_ADDR tpaddr
, CORE_ADDR collector
,
80 CORE_ADDR lockaddr
, ULONGEST orig_size
, CORE_ADDR
*jump_entry
,
81 CORE_ADDR
*trampoline
, ULONGEST
*trampoline_size
,
82 unsigned char *jjump_pad_insn
, ULONGEST
*jjump_pad_insn_size
,
83 CORE_ADDR
*adjusted_insn_addr
, CORE_ADDR
*adjusted_insn_addr_end
,
86 int get_min_fast_tracepoint_insn_len () override
;
88 struct emit_ops
*emit_ops () override
;
90 bool supports_memory_tagging () override
;
92 bool fetch_memtags (CORE_ADDR address
, size_t len
,
93 gdb::byte_vector
&tags
, int type
) override
;
95 bool store_memtags (CORE_ADDR address
, size_t len
,
96 const gdb::byte_vector
&tags
, int type
) override
;
100 void low_arch_setup () override
;
102 bool low_cannot_fetch_register (int regno
) override
;
104 bool low_cannot_store_register (int regno
) override
;
106 bool low_supports_breakpoints () override
;
108 CORE_ADDR
low_get_pc (regcache
*regcache
) override
;
110 void low_set_pc (regcache
*regcache
, CORE_ADDR newpc
) override
;
112 bool low_breakpoint_at (CORE_ADDR pc
) override
;
114 int low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
115 int size
, raw_breakpoint
*bp
) override
;
117 int low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
118 int size
, raw_breakpoint
*bp
) override
;
120 bool low_stopped_by_watchpoint () override
;
122 CORE_ADDR
low_stopped_data_address () override
;
124 bool low_siginfo_fixup (siginfo_t
*native
, gdb_byte
*inf
,
125 int direction
) override
;
127 arch_process_info
*low_new_process () override
;
129 void low_delete_process (arch_process_info
*info
) override
;
131 void low_new_thread (lwp_info
*) override
;
133 void low_delete_thread (arch_lwp_info
*) override
;
135 void low_new_fork (process_info
*parent
, process_info
*child
) override
;
137 void low_prepare_to_resume (lwp_info
*lwp
) override
;
139 int low_get_thread_area (int lwpid
, CORE_ADDR
*addrp
) override
;
141 bool low_supports_range_stepping () override
;
143 bool low_supports_catch_syscall () override
;
145 void low_get_syscall_trapinfo (regcache
*regcache
, int *sysno
) override
;
148 /* The singleton target ops object. */
150 static aarch64_target the_aarch64_target
;
153 aarch64_target::low_cannot_fetch_register (int regno
)
155 gdb_assert_not_reached ("linux target op low_cannot_fetch_register "
156 "is not implemented by the target");
160 aarch64_target::low_cannot_store_register (int regno
)
162 gdb_assert_not_reached ("linux target op low_cannot_store_register "
163 "is not implemented by the target");
167 aarch64_target::low_prepare_to_resume (lwp_info
*lwp
)
169 aarch64_linux_prepare_to_resume (lwp
);
172 /* Per-process arch-specific data we want to keep. */
174 struct arch_process_info
176 /* Hardware breakpoint/watchpoint data.
177 The reason for them to be per-process rather than per-thread is
178 due to the lack of information in the gdbserver environment;
179 gdbserver is not told that whether a requested hardware
180 breakpoint/watchpoint is thread specific or not, so it has to set
181 each hw bp/wp for every thread in the current process. The
182 higher level bp/wp management in gdb will resume a thread if a hw
183 bp/wp trap is not expected for it. Since the hw bp/wp setting is
184 same for each thread, it is reasonable for the data to live here.
186 struct aarch64_debug_reg_state debug_reg_state
;
189 /* Return true if the size of register 0 is 8 byte. */
192 is_64bit_tdesc (void)
194 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
196 return register_size (regcache
->tdesc
, 0) == 8;
200 aarch64_fill_gregset (struct regcache
*regcache
, void *buf
)
202 struct user_pt_regs
*regset
= (struct user_pt_regs
*) buf
;
205 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
206 collect_register (regcache
, AARCH64_X0_REGNUM
+ i
, ®set
->regs
[i
]);
207 collect_register (regcache
, AARCH64_SP_REGNUM
, ®set
->sp
);
208 collect_register (regcache
, AARCH64_PC_REGNUM
, ®set
->pc
);
209 collect_register (regcache
, AARCH64_CPSR_REGNUM
, ®set
->pstate
);
213 aarch64_store_gregset (struct regcache
*regcache
, const void *buf
)
215 const struct user_pt_regs
*regset
= (const struct user_pt_regs
*) buf
;
218 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
219 supply_register (regcache
, AARCH64_X0_REGNUM
+ i
, ®set
->regs
[i
]);
220 supply_register (regcache
, AARCH64_SP_REGNUM
, ®set
->sp
);
221 supply_register (regcache
, AARCH64_PC_REGNUM
, ®set
->pc
);
222 supply_register (regcache
, AARCH64_CPSR_REGNUM
, ®set
->pstate
);
226 aarch64_fill_fpregset (struct regcache
*regcache
, void *buf
)
228 struct user_fpsimd_state
*regset
= (struct user_fpsimd_state
*) buf
;
231 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
232 collect_register (regcache
, AARCH64_V0_REGNUM
+ i
, ®set
->vregs
[i
]);
233 collect_register (regcache
, AARCH64_FPSR_REGNUM
, ®set
->fpsr
);
234 collect_register (regcache
, AARCH64_FPCR_REGNUM
, ®set
->fpcr
);
238 aarch64_store_fpregset (struct regcache
*regcache
, const void *buf
)
240 const struct user_fpsimd_state
*regset
241 = (const struct user_fpsimd_state
*) buf
;
244 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
245 supply_register (regcache
, AARCH64_V0_REGNUM
+ i
, ®set
->vregs
[i
]);
246 supply_register (regcache
, AARCH64_FPSR_REGNUM
, ®set
->fpsr
);
247 supply_register (regcache
, AARCH64_FPCR_REGNUM
, ®set
->fpcr
);
250 /* Store the pauth registers to regcache. */
253 aarch64_store_pauthregset (struct regcache
*regcache
, const void *buf
)
255 uint64_t *pauth_regset
= (uint64_t *) buf
;
256 int pauth_base
= find_regno (regcache
->tdesc
, "pauth_dmask");
261 supply_register (regcache
, AARCH64_PAUTH_DMASK_REGNUM (pauth_base
),
263 supply_register (regcache
, AARCH64_PAUTH_CMASK_REGNUM (pauth_base
),
267 /* Fill BUF with the MTE registers from the regcache. */
270 aarch64_fill_mteregset (struct regcache
*regcache
, void *buf
)
272 uint64_t *mte_regset
= (uint64_t *) buf
;
273 int mte_base
= find_regno (regcache
->tdesc
, "tag_ctl");
275 collect_register (regcache
, mte_base
, mte_regset
);
278 /* Store the MTE registers to regcache. */
281 aarch64_store_mteregset (struct regcache
*regcache
, const void *buf
)
283 uint64_t *mte_regset
= (uint64_t *) buf
;
284 int mte_base
= find_regno (regcache
->tdesc
, "tag_ctl");
286 /* Tag Control register */
287 supply_register (regcache
, mte_base
, mte_regset
);
291 aarch64_target::low_supports_breakpoints ()
296 /* Implementation of linux target ops method "low_get_pc". */
299 aarch64_target::low_get_pc (regcache
*regcache
)
301 if (register_size (regcache
->tdesc
, 0) == 8)
302 return linux_get_pc_64bit (regcache
);
304 return linux_get_pc_32bit (regcache
);
307 /* Implementation of linux target ops method "low_set_pc". */
310 aarch64_target::low_set_pc (regcache
*regcache
, CORE_ADDR pc
)
312 if (register_size (regcache
->tdesc
, 0) == 8)
313 linux_set_pc_64bit (regcache
, pc
);
315 linux_set_pc_32bit (regcache
, pc
);
318 #define aarch64_breakpoint_len 4
320 /* AArch64 BRK software debug mode instruction.
321 This instruction needs to match gdb/aarch64-tdep.c
322 (aarch64_default_breakpoint). */
323 static const gdb_byte aarch64_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
325 /* Implementation of linux target ops method "low_breakpoint_at". */
328 aarch64_target::low_breakpoint_at (CORE_ADDR where
)
330 if (is_64bit_tdesc ())
332 gdb_byte insn
[aarch64_breakpoint_len
];
334 read_memory (where
, (unsigned char *) &insn
, aarch64_breakpoint_len
);
335 if (memcmp (insn
, aarch64_breakpoint
, aarch64_breakpoint_len
) == 0)
341 return arm_breakpoint_at (where
);
345 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state
*state
)
349 for (i
= 0; i
< AARCH64_HBP_MAX_NUM
; ++i
)
351 state
->dr_addr_bp
[i
] = 0;
352 state
->dr_ctrl_bp
[i
] = 0;
353 state
->dr_ref_count_bp
[i
] = 0;
356 for (i
= 0; i
< AARCH64_HWP_MAX_NUM
; ++i
)
358 state
->dr_addr_wp
[i
] = 0;
359 state
->dr_ctrl_wp
[i
] = 0;
360 state
->dr_ref_count_wp
[i
] = 0;
364 /* Return the pointer to the debug register state structure in the
365 current process' arch-specific data area. */
367 struct aarch64_debug_reg_state
*
368 aarch64_get_debug_reg_state (pid_t pid
)
370 struct process_info
*proc
= find_process_pid (pid
);
372 return &proc
->priv
->arch_private
->debug_reg_state
;
375 /* Implementation of target ops method "supports_z_point_type". */
378 aarch64_target::supports_z_point_type (char z_type
)
384 case Z_PACKET_WRITE_WP
:
385 case Z_PACKET_READ_WP
:
386 case Z_PACKET_ACCESS_WP
:
393 /* Implementation of linux target ops method "low_insert_point".
395 It actually only records the info of the to-be-inserted bp/wp;
396 the actual insertion will happen when threads are resumed. */
399 aarch64_target::low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
400 int len
, raw_breakpoint
*bp
)
403 enum target_hw_bp_type targ_type
;
404 struct aarch64_debug_reg_state
*state
405 = aarch64_get_debug_reg_state (pid_of (current_thread
));
408 fprintf (stderr
, "insert_point on entry (addr=0x%08lx, len=%d)\n",
409 (unsigned long) addr
, len
);
411 /* Determine the type from the raw breakpoint type. */
412 targ_type
= raw_bkpt_type_to_target_hw_bp_type (type
);
414 if (targ_type
!= hw_execute
)
416 if (aarch64_linux_region_ok_for_watchpoint (addr
, len
))
417 ret
= aarch64_handle_watchpoint (targ_type
, addr
, len
,
418 1 /* is_insert */, state
);
426 /* LEN is 3 means the breakpoint is set on a 32-bit thumb
427 instruction. Set it to 2 to correctly encode length bit
428 mask in hardware/watchpoint control register. */
431 ret
= aarch64_handle_breakpoint (targ_type
, addr
, len
,
432 1 /* is_insert */, state
);
436 aarch64_show_debug_reg_state (state
, "insert_point", addr
, len
,
442 /* Implementation of linux target ops method "low_remove_point".
444 It actually only records the info of the to-be-removed bp/wp,
445 the actual removal will be done when threads are resumed. */
448 aarch64_target::low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
449 int len
, raw_breakpoint
*bp
)
452 enum target_hw_bp_type targ_type
;
453 struct aarch64_debug_reg_state
*state
454 = aarch64_get_debug_reg_state (pid_of (current_thread
));
457 fprintf (stderr
, "remove_point on entry (addr=0x%08lx, len=%d)\n",
458 (unsigned long) addr
, len
);
460 /* Determine the type from the raw breakpoint type. */
461 targ_type
= raw_bkpt_type_to_target_hw_bp_type (type
);
463 /* Set up state pointers. */
464 if (targ_type
!= hw_execute
)
466 aarch64_handle_watchpoint (targ_type
, addr
, len
, 0 /* is_insert */,
472 /* LEN is 3 means the breakpoint is set on a 32-bit thumb
473 instruction. Set it to 2 to correctly encode length bit
474 mask in hardware/watchpoint control register. */
477 ret
= aarch64_handle_breakpoint (targ_type
, addr
, len
,
478 0 /* is_insert */, state
);
482 aarch64_show_debug_reg_state (state
, "remove_point", addr
, len
,
488 /* Return the address only having significant bits. This is used to ignore
489 the top byte (TBI). */
492 address_significant (CORE_ADDR addr
)
494 /* Clear insignificant bits of a target address and sign extend resulting
498 CORE_ADDR sign
= (CORE_ADDR
) 1 << (addr_bit
- 1);
499 addr
&= ((CORE_ADDR
) 1 << addr_bit
) - 1;
500 addr
= (addr
^ sign
) - sign
;
505 /* Implementation of linux target ops method "low_stopped_data_address". */
508 aarch64_target::low_stopped_data_address ()
512 struct aarch64_debug_reg_state
*state
;
514 pid
= lwpid_of (current_thread
);
516 /* Get the siginfo. */
517 if (ptrace (PTRACE_GETSIGINFO
, pid
, NULL
, &siginfo
) != 0)
518 return (CORE_ADDR
) 0;
520 /* Need to be a hardware breakpoint/watchpoint trap. */
521 if (siginfo
.si_signo
!= SIGTRAP
522 || (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
523 return (CORE_ADDR
) 0;
525 /* Make sure to ignore the top byte, otherwise we may not recognize a
526 hardware watchpoint hit. The stopped data addresses coming from the
527 kernel can potentially be tagged addresses. */
528 const CORE_ADDR addr_trap
529 = address_significant ((CORE_ADDR
) siginfo
.si_addr
);
531 /* Check if the address matches any watched address. */
532 state
= aarch64_get_debug_reg_state (pid_of (current_thread
));
533 for (i
= aarch64_num_wp_regs
- 1; i
>= 0; --i
)
535 const unsigned int offset
536 = aarch64_watchpoint_offset (state
->dr_ctrl_wp
[i
]);
537 const unsigned int len
= aarch64_watchpoint_length (state
->dr_ctrl_wp
[i
]);
538 const CORE_ADDR addr_watch
= state
->dr_addr_wp
[i
] + offset
;
539 const CORE_ADDR addr_watch_aligned
= align_down (state
->dr_addr_wp
[i
], 8);
540 const CORE_ADDR addr_orig
= state
->dr_addr_orig_wp
[i
];
542 if (state
->dr_ref_count_wp
[i
]
543 && DR_CONTROL_ENABLED (state
->dr_ctrl_wp
[i
])
544 && addr_trap
>= addr_watch_aligned
545 && addr_trap
< addr_watch
+ len
)
547 /* ADDR_TRAP reports the first address of the memory range
548 accessed by the CPU, regardless of what was the memory
549 range watched. Thus, a large CPU access that straddles
550 the ADDR_WATCH..ADDR_WATCH+LEN range may result in an
551 ADDR_TRAP that is lower than the
552 ADDR_WATCH..ADDR_WATCH+LEN range. E.g.:
554 addr: | 4 | 5 | 6 | 7 | 8 |
555 |---- range watched ----|
556 |----------- range accessed ------------|
558 In this case, ADDR_TRAP will be 4.
560 To match a watchpoint known to GDB core, we must never
561 report *ADDR_P outside of any ADDR_WATCH..ADDR_WATCH+LEN
562 range. ADDR_WATCH <= ADDR_TRAP < ADDR_ORIG is a false
563 positive on kernels older than 4.10. See PR
569 return (CORE_ADDR
) 0;
572 /* Implementation of linux target ops method "low_stopped_by_watchpoint". */
575 aarch64_target::low_stopped_by_watchpoint ()
577 return (low_stopped_data_address () != 0);
580 /* Fetch the thread-local storage pointer for libthread_db. */
583 ps_get_thread_area (struct ps_prochandle
*ph
,
584 lwpid_t lwpid
, int idx
, void **base
)
586 return aarch64_ps_get_thread_area (ph
, lwpid
, idx
, base
,
590 /* Implementation of linux target ops method "low_siginfo_fixup". */
593 aarch64_target::low_siginfo_fixup (siginfo_t
*native
, gdb_byte
*inf
,
596 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
597 if (!is_64bit_tdesc ())
600 aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo
*) inf
,
603 aarch64_siginfo_from_compat_siginfo (native
,
604 (struct compat_siginfo
*) inf
);
612 /* Implementation of linux target ops method "low_new_process". */
615 aarch64_target::low_new_process ()
617 struct arch_process_info
*info
= XCNEW (struct arch_process_info
);
619 aarch64_init_debug_reg_state (&info
->debug_reg_state
);
624 /* Implementation of linux target ops method "low_delete_process". */
627 aarch64_target::low_delete_process (arch_process_info
*info
)
633 aarch64_target::low_new_thread (lwp_info
*lwp
)
635 aarch64_linux_new_thread (lwp
);
639 aarch64_target::low_delete_thread (arch_lwp_info
*arch_lwp
)
641 aarch64_linux_delete_thread (arch_lwp
);
644 /* Implementation of linux target ops method "low_new_fork". */
647 aarch64_target::low_new_fork (process_info
*parent
,
650 /* These are allocated by linux_add_process. */
651 gdb_assert (parent
->priv
!= NULL
652 && parent
->priv
->arch_private
!= NULL
);
653 gdb_assert (child
->priv
!= NULL
654 && child
->priv
->arch_private
!= NULL
);
656 /* Linux kernel before 2.6.33 commit
657 72f674d203cd230426437cdcf7dd6f681dad8b0d
658 will inherit hardware debug registers from parent
659 on fork/vfork/clone. Newer Linux kernels create such tasks with
660 zeroed debug registers.
662 GDB core assumes the child inherits the watchpoints/hw
663 breakpoints of the parent, and will remove them all from the
664 forked off process. Copy the debug registers mirrors into the
665 new process so that all breakpoints and watchpoints can be
666 removed together. The debug registers mirror will become zeroed
667 in the end before detaching the forked off process, thus making
668 this compatible with older Linux kernels too. */
670 *child
->priv
->arch_private
= *parent
->priv
->arch_private
;
673 /* Wrapper for aarch64_sve_regs_copy_to_reg_buf. */
676 aarch64_sve_regs_copy_to_regcache (struct regcache
*regcache
, const void *buf
)
678 return aarch64_sve_regs_copy_to_reg_buf (regcache
, buf
);
681 /* Wrapper for aarch64_sve_regs_copy_from_reg_buf. */
684 aarch64_sve_regs_copy_from_regcache (struct regcache
*regcache
, void *buf
)
686 return aarch64_sve_regs_copy_from_reg_buf (regcache
, buf
);
689 /* Array containing all the possible register sets for AArch64/Linux. During
690 architecture setup, these will be checked against the HWCAP/HWCAP2 bits for
691 validity and enabled/disabled accordingly.
693 Their sizes are set to 0 here, but they will be adjusted later depending
694 on whether each register set is available or not. */
695 static struct regset_info aarch64_regsets
[] =
698 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PRSTATUS
,
700 aarch64_fill_gregset
, aarch64_store_gregset
},
701 /* Floating Point (FPU) registers. */
702 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_FPREGSET
,
704 aarch64_fill_fpregset
, aarch64_store_fpregset
706 /* Scalable Vector Extension (SVE) registers. */
707 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_ARM_SVE
,
709 aarch64_sve_regs_copy_from_regcache
, aarch64_sve_regs_copy_to_regcache
712 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_ARM_PAC_MASK
,
714 nullptr, aarch64_store_pauthregset
},
715 /* Tagged address control / MTE registers. */
716 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_ARM_TAGGED_ADDR_CTRL
,
718 aarch64_fill_mteregset
, aarch64_store_mteregset
},
722 static struct regsets_info aarch64_regsets_info
=
724 aarch64_regsets
, /* regsets */
726 nullptr, /* disabled_regsets */
729 static struct regs_info regs_info_aarch64
=
731 nullptr, /* regset_bitmap */
732 nullptr, /* usrregs */
733 &aarch64_regsets_info
,
736 /* Given FEATURES, adjust the available register sets by setting their
737 sizes. A size of 0 means the register set is disabled and won't be
741 aarch64_adjust_register_sets (const struct aarch64_features
&features
)
743 struct regset_info
*regset
;
745 for (regset
= aarch64_regsets
; regset
->size
>= 0; regset
++)
747 switch (regset
->nt_type
)
750 /* General purpose registers are always present. */
751 regset
->size
= sizeof (struct user_pt_regs
);
754 /* This is unavailable when SVE is present. */
756 regset
->size
= sizeof (struct user_fpsimd_state
);
760 regset
->size
= SVE_PT_SIZE (AARCH64_MAX_SVE_VQ
, SVE_PT_REGS_SVE
);
762 case NT_ARM_PAC_MASK
:
764 regset
->size
= AARCH64_PAUTH_REGS_SIZE
;
766 case NT_ARM_TAGGED_ADDR_CTRL
:
768 regset
->size
= AARCH64_LINUX_SIZEOF_MTE
;
771 gdb_assert_not_reached ("Unknown register set found.");
776 /* Matches HWCAP_PACA in kernel header arch/arm64/include/uapi/asm/hwcap.h. */
777 #define AARCH64_HWCAP_PACA (1 << 30)
779 /* Implementation of linux target ops method "low_arch_setup". */
782 aarch64_target::low_arch_setup ()
784 unsigned int machine
;
788 tid
= lwpid_of (current_thread
);
790 is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
794 struct aarch64_features features
;
796 uint64_t vq
= aarch64_sve_get_vq (tid
);
797 features
.sve
= (vq
> 0);
798 /* A-profile PAC is 64-bit only. */
799 features
.pauth
= linux_get_hwcap (8) & AARCH64_HWCAP_PACA
;
800 /* A-profile MTE is 64-bit only. */
801 features
.mte
= linux_get_hwcap2 (8) & HWCAP2_MTE
;
803 current_process ()->tdesc
804 = aarch64_linux_read_description (vq
, features
.pauth
, features
.mte
);
806 /* Adjust the register sets we should use for this particular set of
808 aarch64_adjust_register_sets (features
);
811 current_process ()->tdesc
= aarch32_linux_read_description ();
813 aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread
));
816 /* Implementation of linux target ops method "get_regs_info". */
819 aarch64_target::get_regs_info ()
821 if (!is_64bit_tdesc ())
822 return ®s_info_aarch32
;
824 /* AArch64 64-bit registers. */
825 return ®s_info_aarch64
;
828 /* Implementation of target ops method "supports_tracepoints". */
831 aarch64_target::supports_tracepoints ()
833 if (current_thread
== NULL
)
837 /* We don't support tracepoints on aarch32 now. */
838 return is_64bit_tdesc ();
842 /* Implementation of linux target ops method "low_get_thread_area". */
845 aarch64_target::low_get_thread_area (int lwpid
, CORE_ADDR
*addrp
)
850 iovec
.iov_base
= ®
;
851 iovec
.iov_len
= sizeof (reg
);
853 if (ptrace (PTRACE_GETREGSET
, lwpid
, NT_ARM_TLS
, &iovec
) != 0)
862 aarch64_target::low_supports_catch_syscall ()
867 /* Implementation of linux target ops method "low_get_syscall_trapinfo". */
870 aarch64_target::low_get_syscall_trapinfo (regcache
*regcache
, int *sysno
)
872 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
878 collect_register_by_name (regcache
, "x8", &l_sysno
);
879 *sysno
= (int) l_sysno
;
882 collect_register_by_name (regcache
, "r7", sysno
);
885 /* List of condition codes that we need. */
887 enum aarch64_condition_codes
898 enum aarch64_operand_type
904 /* Representation of an operand. At this time, it only supports register
905 and immediate types. */
907 struct aarch64_operand
909 /* Type of the operand. */
910 enum aarch64_operand_type type
;
912 /* Value of the operand according to the type. */
916 struct aarch64_register reg
;
920 /* List of registers that we are currently using, we can add more here as
921 we need to use them. */
923 /* General purpose scratch registers (64 bit). */
924 static const struct aarch64_register x0
= { 0, 1 };
925 static const struct aarch64_register x1
= { 1, 1 };
926 static const struct aarch64_register x2
= { 2, 1 };
927 static const struct aarch64_register x3
= { 3, 1 };
928 static const struct aarch64_register x4
= { 4, 1 };
930 /* General purpose scratch registers (32 bit). */
931 static const struct aarch64_register w0
= { 0, 0 };
932 static const struct aarch64_register w2
= { 2, 0 };
934 /* Intra-procedure scratch registers. */
935 static const struct aarch64_register ip0
= { 16, 1 };
937 /* Special purpose registers. */
938 static const struct aarch64_register fp
= { 29, 1 };
939 static const struct aarch64_register lr
= { 30, 1 };
940 static const struct aarch64_register sp
= { 31, 1 };
941 static const struct aarch64_register xzr
= { 31, 1 };
943 /* Dynamically allocate a new register. If we know the register
944 statically, we should make it a global as above instead of using this
947 static struct aarch64_register
948 aarch64_register (unsigned num
, int is64
)
950 return (struct aarch64_register
) { num
, is64
};
953 /* Helper function to create a register operand, for instructions with
954 different types of operands.
957 p += emit_mov (p, x0, register_operand (x1)); */
959 static struct aarch64_operand
960 register_operand (struct aarch64_register reg
)
962 struct aarch64_operand operand
;
964 operand
.type
= OPERAND_REGISTER
;
970 /* Helper function to create an immediate operand, for instructions with
971 different types of operands.
974 p += emit_mov (p, x0, immediate_operand (12)); */
976 static struct aarch64_operand
977 immediate_operand (uint32_t imm
)
979 struct aarch64_operand operand
;
981 operand
.type
= OPERAND_IMMEDIATE
;
987 /* Helper function to create an offset memory operand.
990 p += emit_ldr (p, x0, sp, offset_memory_operand (16)); */
992 static struct aarch64_memory_operand
993 offset_memory_operand (int32_t offset
)
995 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_OFFSET
, offset
};
998 /* Helper function to create a pre-index memory operand.
1001 p += emit_ldr (p, x0, sp, preindex_memory_operand (16)); */
1003 static struct aarch64_memory_operand
1004 preindex_memory_operand (int32_t index
)
1006 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_PREINDEX
, index
};
1009 /* Helper function to create a post-index memory operand.
1012 p += emit_ldr (p, x0, sp, postindex_memory_operand (16)); */
1014 static struct aarch64_memory_operand
1015 postindex_memory_operand (int32_t index
)
1017 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_POSTINDEX
, index
};
1020 /* System control registers. These special registers can be written and
1021 read with the MRS and MSR instructions.
1023 - NZCV: Condition flags. GDB refers to this register under the CPSR
1025 - FPSR: Floating-point status register.
1026 - FPCR: Floating-point control registers.
1027 - TPIDR_EL0: Software thread ID register. */
1029 enum aarch64_system_control_registers
1031 /* op0 op1 crn crm op2 */
1032 NZCV
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x2 << 3) | 0x0,
1033 FPSR
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x1,
1034 FPCR
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x0,
1035 TPIDR_EL0
= (0x1 << 14) | (0x3 << 11) | (0xd << 7) | (0x0 << 3) | 0x2
1038 /* Write a BLR instruction into *BUF.
1042 RN is the register to branch to. */
1045 emit_blr (uint32_t *buf
, struct aarch64_register rn
)
1047 return aarch64_emit_insn (buf
, BLR
| ENCODE (rn
.num
, 5, 5));
1050 /* Write a RET instruction into *BUF.
1054 RN is the register to branch to. */
1057 emit_ret (uint32_t *buf
, struct aarch64_register rn
)
1059 return aarch64_emit_insn (buf
, RET
| ENCODE (rn
.num
, 5, 5));
1063 emit_load_store_pair (uint32_t *buf
, enum aarch64_opcodes opcode
,
1064 struct aarch64_register rt
,
1065 struct aarch64_register rt2
,
1066 struct aarch64_register rn
,
1067 struct aarch64_memory_operand operand
)
1071 uint32_t write_back
;
1074 opc
= ENCODE (2, 2, 30);
1076 opc
= ENCODE (0, 2, 30);
1078 switch (operand
.type
)
1080 case MEMORY_OPERAND_OFFSET
:
1082 pre_index
= ENCODE (1, 1, 24);
1083 write_back
= ENCODE (0, 1, 23);
1086 case MEMORY_OPERAND_POSTINDEX
:
1088 pre_index
= ENCODE (0, 1, 24);
1089 write_back
= ENCODE (1, 1, 23);
1092 case MEMORY_OPERAND_PREINDEX
:
1094 pre_index
= ENCODE (1, 1, 24);
1095 write_back
= ENCODE (1, 1, 23);
1102 return aarch64_emit_insn (buf
, opcode
| opc
| pre_index
| write_back
1103 | ENCODE (operand
.index
>> 3, 7, 15)
1104 | ENCODE (rt2
.num
, 5, 10)
1105 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
1108 /* Write a STP instruction into *BUF.
1110 STP rt, rt2, [rn, #offset]
1111 STP rt, rt2, [rn, #index]!
1112 STP rt, rt2, [rn], #index
1114 RT and RT2 are the registers to store.
1115 RN is the base address register.
1116 OFFSET is the immediate to add to the base address. It is limited to a
1117 -512 .. 504 range (7 bits << 3). */
1120 emit_stp (uint32_t *buf
, struct aarch64_register rt
,
1121 struct aarch64_register rt2
, struct aarch64_register rn
,
1122 struct aarch64_memory_operand operand
)
1124 return emit_load_store_pair (buf
, STP
, rt
, rt2
, rn
, operand
);
1127 /* Write a LDP instruction into *BUF.
1129 LDP rt, rt2, [rn, #offset]
1130 LDP rt, rt2, [rn, #index]!
1131 LDP rt, rt2, [rn], #index
1133 RT and RT2 are the registers to store.
1134 RN is the base address register.
1135 OFFSET is the immediate to add to the base address. It is limited to a
1136 -512 .. 504 range (7 bits << 3). */
1139 emit_ldp (uint32_t *buf
, struct aarch64_register rt
,
1140 struct aarch64_register rt2
, struct aarch64_register rn
,
1141 struct aarch64_memory_operand operand
)
1143 return emit_load_store_pair (buf
, LDP
, rt
, rt2
, rn
, operand
);
1146 /* Write a LDP (SIMD&VFP) instruction using Q registers into *BUF.
1148 LDP qt, qt2, [rn, #offset]
1150 RT and RT2 are the Q registers to store.
1151 RN is the base address register.
1152 OFFSET is the immediate to add to the base address. It is limited to
1153 -1024 .. 1008 range (7 bits << 4). */
1156 emit_ldp_q_offset (uint32_t *buf
, unsigned rt
, unsigned rt2
,
1157 struct aarch64_register rn
, int32_t offset
)
1159 uint32_t opc
= ENCODE (2, 2, 30);
1160 uint32_t pre_index
= ENCODE (1, 1, 24);
1162 return aarch64_emit_insn (buf
, LDP_SIMD_VFP
| opc
| pre_index
1163 | ENCODE (offset
>> 4, 7, 15)
1164 | ENCODE (rt2
, 5, 10)
1165 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
, 5, 0));
1168 /* Write a STP (SIMD&VFP) instruction using Q registers into *BUF.
1170 STP qt, qt2, [rn, #offset]
1172 RT and RT2 are the Q registers to store.
1173 RN is the base address register.
1174 OFFSET is the immediate to add to the base address. It is limited to
1175 -1024 .. 1008 range (7 bits << 4). */
1178 emit_stp_q_offset (uint32_t *buf
, unsigned rt
, unsigned rt2
,
1179 struct aarch64_register rn
, int32_t offset
)
1181 uint32_t opc
= ENCODE (2, 2, 30);
1182 uint32_t pre_index
= ENCODE (1, 1, 24);
1184 return aarch64_emit_insn (buf
, STP_SIMD_VFP
| opc
| pre_index
1185 | ENCODE (offset
>> 4, 7, 15)
1186 | ENCODE (rt2
, 5, 10)
1187 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
, 5, 0));
1190 /* Write a LDRH instruction into *BUF.
1192 LDRH wt, [xn, #offset]
1193 LDRH wt, [xn, #index]!
1194 LDRH wt, [xn], #index
1196 RT is the register to store.
1197 RN is the base address register.
1198 OFFSET is the immediate to add to the base address. It is limited to
1199 0 .. 32760 range (12 bits << 3). */
1202 emit_ldrh (uint32_t *buf
, struct aarch64_register rt
,
1203 struct aarch64_register rn
,
1204 struct aarch64_memory_operand operand
)
1206 return aarch64_emit_load_store (buf
, 1, LDR
, rt
, rn
, operand
);
1209 /* Write a LDRB instruction into *BUF.
1211 LDRB wt, [xn, #offset]
1212 LDRB wt, [xn, #index]!
1213 LDRB wt, [xn], #index
1215 RT is the register to store.
1216 RN is the base address register.
1217 OFFSET is the immediate to add to the base address. It is limited to
1218 0 .. 32760 range (12 bits << 3). */
1221 emit_ldrb (uint32_t *buf
, struct aarch64_register rt
,
1222 struct aarch64_register rn
,
1223 struct aarch64_memory_operand operand
)
1225 return aarch64_emit_load_store (buf
, 0, LDR
, rt
, rn
, operand
);
1230 /* Write a STR instruction into *BUF.
1232 STR rt, [rn, #offset]
1233 STR rt, [rn, #index]!
1234 STR rt, [rn], #index
1236 RT is the register to store.
1237 RN is the base address register.
1238 OFFSET is the immediate to add to the base address. It is limited to
1239 0 .. 32760 range (12 bits << 3). */
1242 emit_str (uint32_t *buf
, struct aarch64_register rt
,
1243 struct aarch64_register rn
,
1244 struct aarch64_memory_operand operand
)
1246 return aarch64_emit_load_store (buf
, rt
.is64
? 3 : 2, STR
, rt
, rn
, operand
);
1249 /* Helper function emitting an exclusive load or store instruction. */
1252 emit_load_store_exclusive (uint32_t *buf
, uint32_t size
,
1253 enum aarch64_opcodes opcode
,
1254 struct aarch64_register rs
,
1255 struct aarch64_register rt
,
1256 struct aarch64_register rt2
,
1257 struct aarch64_register rn
)
1259 return aarch64_emit_insn (buf
, opcode
| ENCODE (size
, 2, 30)
1260 | ENCODE (rs
.num
, 5, 16) | ENCODE (rt2
.num
, 5, 10)
1261 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
1264 /* Write a LAXR instruction into *BUF.
1268 RT is the destination register.
1269 RN is the base address register. */
1272 emit_ldaxr (uint32_t *buf
, struct aarch64_register rt
,
1273 struct aarch64_register rn
)
1275 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, LDAXR
, xzr
, rt
,
1279 /* Write a STXR instruction into *BUF.
1283 RS is the result register, it indicates if the store succeeded or not.
1284 RT is the destination register.
1285 RN is the base address register. */
1288 emit_stxr (uint32_t *buf
, struct aarch64_register rs
,
1289 struct aarch64_register rt
, struct aarch64_register rn
)
1291 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, STXR
, rs
, rt
,
1295 /* Write a STLR instruction into *BUF.
1299 RT is the register to store.
1300 RN is the base address register. */
1303 emit_stlr (uint32_t *buf
, struct aarch64_register rt
,
1304 struct aarch64_register rn
)
1306 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, STLR
, xzr
, rt
,
1310 /* Helper function for data processing instructions with register sources. */
1313 emit_data_processing_reg (uint32_t *buf
, uint32_t opcode
,
1314 struct aarch64_register rd
,
1315 struct aarch64_register rn
,
1316 struct aarch64_register rm
)
1318 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1320 return aarch64_emit_insn (buf
, opcode
| size
| ENCODE (rm
.num
, 5, 16)
1321 | ENCODE (rn
.num
, 5, 5) | ENCODE (rd
.num
, 5, 0));
1324 /* Helper function for data processing instructions taking either a register
1328 emit_data_processing (uint32_t *buf
, enum aarch64_opcodes opcode
,
1329 struct aarch64_register rd
,
1330 struct aarch64_register rn
,
1331 struct aarch64_operand operand
)
1333 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1334 /* The opcode is different for register and immediate source operands. */
1335 uint32_t operand_opcode
;
1337 if (operand
.type
== OPERAND_IMMEDIATE
)
1339 /* xxx1 000x xxxx xxxx xxxx xxxx xxxx xxxx */
1340 operand_opcode
= ENCODE (8, 4, 25);
1342 return aarch64_emit_insn (buf
, opcode
| operand_opcode
| size
1343 | ENCODE (operand
.imm
, 12, 10)
1344 | ENCODE (rn
.num
, 5, 5)
1345 | ENCODE (rd
.num
, 5, 0));
1349 /* xxx0 101x xxxx xxxx xxxx xxxx xxxx xxxx */
1350 operand_opcode
= ENCODE (5, 4, 25);
1352 return emit_data_processing_reg (buf
, opcode
| operand_opcode
, rd
,
1357 /* Write an ADD instruction into *BUF.
1362 This function handles both an immediate and register add.
1364 RD is the destination register.
1365 RN is the input register.
1366 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
1367 OPERAND_REGISTER. */
1370 emit_add (uint32_t *buf
, struct aarch64_register rd
,
1371 struct aarch64_register rn
, struct aarch64_operand operand
)
1373 return emit_data_processing (buf
, ADD
, rd
, rn
, operand
);
1376 /* Write a SUB instruction into *BUF.
1381 This function handles both an immediate and register sub.
1383 RD is the destination register.
1384 RN is the input register.
1385 IMM is the immediate to substract to RN. */
1388 emit_sub (uint32_t *buf
, struct aarch64_register rd
,
1389 struct aarch64_register rn
, struct aarch64_operand operand
)
1391 return emit_data_processing (buf
, SUB
, rd
, rn
, operand
);
1394 /* Write a MOV instruction into *BUF.
1399 This function handles both a wide immediate move and a register move,
1400 with the condition that the source register is not xzr. xzr and the
1401 stack pointer share the same encoding and this function only supports
1404 RD is the destination register.
1405 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
1406 OPERAND_REGISTER. */
1409 emit_mov (uint32_t *buf
, struct aarch64_register rd
,
1410 struct aarch64_operand operand
)
1412 if (operand
.type
== OPERAND_IMMEDIATE
)
1414 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1415 /* Do not shift the immediate. */
1416 uint32_t shift
= ENCODE (0, 2, 21);
1418 return aarch64_emit_insn (buf
, MOV
| size
| shift
1419 | ENCODE (operand
.imm
, 16, 5)
1420 | ENCODE (rd
.num
, 5, 0));
1423 return emit_add (buf
, rd
, operand
.reg
, immediate_operand (0));
1426 /* Write a MOVK instruction into *BUF.
1428 MOVK rd, #imm, lsl #shift
1430 RD is the destination register.
1431 IMM is the immediate.
1432 SHIFT is the logical shift left to apply to IMM. */
1435 emit_movk (uint32_t *buf
, struct aarch64_register rd
, uint32_t imm
,
1438 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1440 return aarch64_emit_insn (buf
, MOVK
| size
| ENCODE (shift
, 2, 21) |
1441 ENCODE (imm
, 16, 5) | ENCODE (rd
.num
, 5, 0));
1444 /* Write instructions into *BUF in order to move ADDR into a register.
1445 ADDR can be a 64-bit value.
1447 This function will emit a series of MOV and MOVK instructions, such as:
1450 MOVK xd, #(addr >> 16), lsl #16
1451 MOVK xd, #(addr >> 32), lsl #32
1452 MOVK xd, #(addr >> 48), lsl #48 */
1455 emit_mov_addr (uint32_t *buf
, struct aarch64_register rd
, CORE_ADDR addr
)
1459 /* The MOV (wide immediate) instruction clears to top bits of the
1461 p
+= emit_mov (p
, rd
, immediate_operand (addr
& 0xffff));
1463 if ((addr
>> 16) != 0)
1464 p
+= emit_movk (p
, rd
, (addr
>> 16) & 0xffff, 1);
1468 if ((addr
>> 32) != 0)
1469 p
+= emit_movk (p
, rd
, (addr
>> 32) & 0xffff, 2);
1473 if ((addr
>> 48) != 0)
1474 p
+= emit_movk (p
, rd
, (addr
>> 48) & 0xffff, 3);
1479 /* Write a SUBS instruction into *BUF.
1483 This instruction update the condition flags.
1485 RD is the destination register.
1486 RN and RM are the source registers. */
1489 emit_subs (uint32_t *buf
, struct aarch64_register rd
,
1490 struct aarch64_register rn
, struct aarch64_operand operand
)
1492 return emit_data_processing (buf
, SUBS
, rd
, rn
, operand
);
1495 /* Write a CMP instruction into *BUF.
1499 This instruction is an alias of SUBS xzr, rn, rm.
1501 RN and RM are the registers to compare. */
1504 emit_cmp (uint32_t *buf
, struct aarch64_register rn
,
1505 struct aarch64_operand operand
)
1507 return emit_subs (buf
, xzr
, rn
, operand
);
1510 /* Write a AND instruction into *BUF.
1514 RD is the destination register.
1515 RN and RM are the source registers. */
1518 emit_and (uint32_t *buf
, struct aarch64_register rd
,
1519 struct aarch64_register rn
, struct aarch64_register rm
)
1521 return emit_data_processing_reg (buf
, AND
, rd
, rn
, rm
);
1524 /* Write a ORR instruction into *BUF.
1528 RD is the destination register.
1529 RN and RM are the source registers. */
1532 emit_orr (uint32_t *buf
, struct aarch64_register rd
,
1533 struct aarch64_register rn
, struct aarch64_register rm
)
1535 return emit_data_processing_reg (buf
, ORR
, rd
, rn
, rm
);
1538 /* Write a ORN instruction into *BUF.
1542 RD is the destination register.
1543 RN and RM are the source registers. */
1546 emit_orn (uint32_t *buf
, struct aarch64_register rd
,
1547 struct aarch64_register rn
, struct aarch64_register rm
)
1549 return emit_data_processing_reg (buf
, ORN
, rd
, rn
, rm
);
1552 /* Write a EOR instruction into *BUF.
1556 RD is the destination register.
1557 RN and RM are the source registers. */
1560 emit_eor (uint32_t *buf
, struct aarch64_register rd
,
1561 struct aarch64_register rn
, struct aarch64_register rm
)
1563 return emit_data_processing_reg (buf
, EOR
, rd
, rn
, rm
);
1566 /* Write a MVN instruction into *BUF.
1570 This is an alias for ORN rd, xzr, rm.
1572 RD is the destination register.
1573 RM is the source register. */
1576 emit_mvn (uint32_t *buf
, struct aarch64_register rd
,
1577 struct aarch64_register rm
)
1579 return emit_orn (buf
, rd
, xzr
, rm
);
1582 /* Write a LSLV instruction into *BUF.
1586 RD is the destination register.
1587 RN and RM are the source registers. */
1590 emit_lslv (uint32_t *buf
, struct aarch64_register rd
,
1591 struct aarch64_register rn
, struct aarch64_register rm
)
1593 return emit_data_processing_reg (buf
, LSLV
, rd
, rn
, rm
);
1596 /* Write a LSRV instruction into *BUF.
1600 RD is the destination register.
1601 RN and RM are the source registers. */
1604 emit_lsrv (uint32_t *buf
, struct aarch64_register rd
,
1605 struct aarch64_register rn
, struct aarch64_register rm
)
1607 return emit_data_processing_reg (buf
, LSRV
, rd
, rn
, rm
);
1610 /* Write a ASRV instruction into *BUF.
1614 RD is the destination register.
1615 RN and RM are the source registers. */
1618 emit_asrv (uint32_t *buf
, struct aarch64_register rd
,
1619 struct aarch64_register rn
, struct aarch64_register rm
)
1621 return emit_data_processing_reg (buf
, ASRV
, rd
, rn
, rm
);
1624 /* Write a MUL instruction into *BUF.
1628 RD is the destination register.
1629 RN and RM are the source registers. */
1632 emit_mul (uint32_t *buf
, struct aarch64_register rd
,
1633 struct aarch64_register rn
, struct aarch64_register rm
)
1635 return emit_data_processing_reg (buf
, MUL
, rd
, rn
, rm
);
1638 /* Write a MRS instruction into *BUF. The register size is 64-bit.
1642 RT is the destination register.
1643 SYSTEM_REG is special purpose register to read. */
1646 emit_mrs (uint32_t *buf
, struct aarch64_register rt
,
1647 enum aarch64_system_control_registers system_reg
)
1649 return aarch64_emit_insn (buf
, MRS
| ENCODE (system_reg
, 15, 5)
1650 | ENCODE (rt
.num
, 5, 0));
1653 /* Write a MSR instruction into *BUF. The register size is 64-bit.
1657 SYSTEM_REG is special purpose register to write.
1658 RT is the input register. */
1661 emit_msr (uint32_t *buf
, enum aarch64_system_control_registers system_reg
,
1662 struct aarch64_register rt
)
1664 return aarch64_emit_insn (buf
, MSR
| ENCODE (system_reg
, 15, 5)
1665 | ENCODE (rt
.num
, 5, 0));
1668 /* Write a SEVL instruction into *BUF.
1670 This is a hint instruction telling the hardware to trigger an event. */
1673 emit_sevl (uint32_t *buf
)
1675 return aarch64_emit_insn (buf
, SEVL
);
1678 /* Write a WFE instruction into *BUF.
1680 This is a hint instruction telling the hardware to wait for an event. */
1683 emit_wfe (uint32_t *buf
)
1685 return aarch64_emit_insn (buf
, WFE
);
1688 /* Write a SBFM instruction into *BUF.
1690 SBFM rd, rn, #immr, #imms
1692 This instruction moves the bits from #immr to #imms into the
1693 destination, sign extending the result.
1695 RD is the destination register.
1696 RN is the source register.
1697 IMMR is the bit number to start at (least significant bit).
1698 IMMS is the bit number to stop at (most significant bit). */
1701 emit_sbfm (uint32_t *buf
, struct aarch64_register rd
,
1702 struct aarch64_register rn
, uint32_t immr
, uint32_t imms
)
1704 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1705 uint32_t n
= ENCODE (rd
.is64
, 1, 22);
1707 return aarch64_emit_insn (buf
, SBFM
| size
| n
| ENCODE (immr
, 6, 16)
1708 | ENCODE (imms
, 6, 10) | ENCODE (rn
.num
, 5, 5)
1709 | ENCODE (rd
.num
, 5, 0));
1712 /* Write a SBFX instruction into *BUF.
1714 SBFX rd, rn, #lsb, #width
1716 This instruction moves #width bits from #lsb into the destination, sign
1717 extending the result. This is an alias for:
1719 SBFM rd, rn, #lsb, #(lsb + width - 1)
1721 RD is the destination register.
1722 RN is the source register.
1723 LSB is the bit number to start at (least significant bit).
1724 WIDTH is the number of bits to move. */
1727 emit_sbfx (uint32_t *buf
, struct aarch64_register rd
,
1728 struct aarch64_register rn
, uint32_t lsb
, uint32_t width
)
1730 return emit_sbfm (buf
, rd
, rn
, lsb
, lsb
+ width
- 1);
1733 /* Write a UBFM instruction into *BUF.
1735 UBFM rd, rn, #immr, #imms
1737 This instruction moves the bits from #immr to #imms into the
1738 destination, extending the result with zeros.
1740 RD is the destination register.
1741 RN is the source register.
1742 IMMR is the bit number to start at (least significant bit).
1743 IMMS is the bit number to stop at (most significant bit). */
1746 emit_ubfm (uint32_t *buf
, struct aarch64_register rd
,
1747 struct aarch64_register rn
, uint32_t immr
, uint32_t imms
)
1749 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1750 uint32_t n
= ENCODE (rd
.is64
, 1, 22);
1752 return aarch64_emit_insn (buf
, UBFM
| size
| n
| ENCODE (immr
, 6, 16)
1753 | ENCODE (imms
, 6, 10) | ENCODE (rn
.num
, 5, 5)
1754 | ENCODE (rd
.num
, 5, 0));
1757 /* Write a UBFX instruction into *BUF.
1759 UBFX rd, rn, #lsb, #width
1761 This instruction moves #width bits from #lsb into the destination,
1762 extending the result with zeros. This is an alias for:
1764 UBFM rd, rn, #lsb, #(lsb + width - 1)
1766 RD is the destination register.
1767 RN is the source register.
1768 LSB is the bit number to start at (least significant bit).
1769 WIDTH is the number of bits to move. */
1772 emit_ubfx (uint32_t *buf
, struct aarch64_register rd
,
1773 struct aarch64_register rn
, uint32_t lsb
, uint32_t width
)
1775 return emit_ubfm (buf
, rd
, rn
, lsb
, lsb
+ width
- 1);
1778 /* Write a CSINC instruction into *BUF.
1780 CSINC rd, rn, rm, cond
1782 This instruction conditionally increments rn or rm and places the result
1783 in rd. rn is chosen is the condition is true.
1785 RD is the destination register.
1786 RN and RM are the source registers.
1787 COND is the encoded condition. */
1790 emit_csinc (uint32_t *buf
, struct aarch64_register rd
,
1791 struct aarch64_register rn
, struct aarch64_register rm
,
1794 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1796 return aarch64_emit_insn (buf
, CSINC
| size
| ENCODE (rm
.num
, 5, 16)
1797 | ENCODE (cond
, 4, 12) | ENCODE (rn
.num
, 5, 5)
1798 | ENCODE (rd
.num
, 5, 0));
1801 /* Write a CSET instruction into *BUF.
1805 This instruction conditionally write 1 or 0 in the destination register.
1806 1 is written if the condition is true. This is an alias for:
1808 CSINC rd, xzr, xzr, !cond
1810 Note that the condition needs to be inverted.
1812 RD is the destination register.
1813 RN and RM are the source registers.
1814 COND is the encoded condition. */
1817 emit_cset (uint32_t *buf
, struct aarch64_register rd
, unsigned cond
)
1819 /* The least significant bit of the condition needs toggling in order to
1821 return emit_csinc (buf
, rd
, xzr
, xzr
, cond
^ 0x1);
1824 /* Write LEN instructions from BUF into the inferior memory at *TO.
1826 Note instructions are always little endian on AArch64, unlike data. */
1829 append_insns (CORE_ADDR
*to
, size_t len
, const uint32_t *buf
)
1831 size_t byte_len
= len
* sizeof (uint32_t);
1832 #if (__BYTE_ORDER == __BIG_ENDIAN)
1833 uint32_t *le_buf
= (uint32_t *) xmalloc (byte_len
);
1836 for (i
= 0; i
< len
; i
++)
1837 le_buf
[i
] = htole32 (buf
[i
]);
1839 target_write_memory (*to
, (const unsigned char *) le_buf
, byte_len
);
1843 target_write_memory (*to
, (const unsigned char *) buf
, byte_len
);
1849 /* Sub-class of struct aarch64_insn_data, store information of
1850 instruction relocation for fast tracepoint. Visitor can
1851 relocate an instruction from BASE.INSN_ADDR to NEW_ADDR and save
1852 the relocated instructions in buffer pointed by INSN_PTR. */
1854 struct aarch64_insn_relocation_data
1856 struct aarch64_insn_data base
;
1858 /* The new address the instruction is relocated to. */
1860 /* Pointer to the buffer of relocated instruction(s). */
1864 /* Implementation of aarch64_insn_visitor method "b". */
1867 aarch64_ftrace_insn_reloc_b (const int is_bl
, const int32_t offset
,
1868 struct aarch64_insn_data
*data
)
1870 struct aarch64_insn_relocation_data
*insn_reloc
1871 = (struct aarch64_insn_relocation_data
*) data
;
1873 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1875 if (can_encode_int32 (new_offset
, 28))
1876 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, is_bl
, new_offset
);
1879 /* Implementation of aarch64_insn_visitor method "b_cond". */
1882 aarch64_ftrace_insn_reloc_b_cond (const unsigned cond
, const int32_t offset
,
1883 struct aarch64_insn_data
*data
)
1885 struct aarch64_insn_relocation_data
*insn_reloc
1886 = (struct aarch64_insn_relocation_data
*) data
;
1888 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1890 if (can_encode_int32 (new_offset
, 21))
1892 insn_reloc
->insn_ptr
+= emit_bcond (insn_reloc
->insn_ptr
, cond
,
1895 else if (can_encode_int32 (new_offset
, 28))
1897 /* The offset is out of range for a conditional branch
1898 instruction but not for a unconditional branch. We can use
1899 the following instructions instead:
1901 B.COND TAKEN ; If cond is true, then jump to TAKEN.
1902 B NOT_TAKEN ; Else jump over TAKEN and continue.
1909 insn_reloc
->insn_ptr
+= emit_bcond (insn_reloc
->insn_ptr
, cond
, 8);
1910 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
1911 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, new_offset
- 8);
1915 /* Implementation of aarch64_insn_visitor method "cb". */
1918 aarch64_ftrace_insn_reloc_cb (const int32_t offset
, const int is_cbnz
,
1919 const unsigned rn
, int is64
,
1920 struct aarch64_insn_data
*data
)
1922 struct aarch64_insn_relocation_data
*insn_reloc
1923 = (struct aarch64_insn_relocation_data
*) data
;
1925 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1927 if (can_encode_int32 (new_offset
, 21))
1929 insn_reloc
->insn_ptr
+= emit_cb (insn_reloc
->insn_ptr
, is_cbnz
,
1930 aarch64_register (rn
, is64
), new_offset
);
1932 else if (can_encode_int32 (new_offset
, 28))
1934 /* The offset is out of range for a compare and branch
1935 instruction but not for a unconditional branch. We can use
1936 the following instructions instead:
1938 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
1939 B NOT_TAKEN ; Else jump over TAKEN and continue.
1945 insn_reloc
->insn_ptr
+= emit_cb (insn_reloc
->insn_ptr
, is_cbnz
,
1946 aarch64_register (rn
, is64
), 8);
1947 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
1948 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, new_offset
- 8);
1952 /* Implementation of aarch64_insn_visitor method "tb". */
1955 aarch64_ftrace_insn_reloc_tb (const int32_t offset
, int is_tbnz
,
1956 const unsigned rt
, unsigned bit
,
1957 struct aarch64_insn_data
*data
)
1959 struct aarch64_insn_relocation_data
*insn_reloc
1960 = (struct aarch64_insn_relocation_data
*) data
;
1962 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1964 if (can_encode_int32 (new_offset
, 16))
1966 insn_reloc
->insn_ptr
+= emit_tb (insn_reloc
->insn_ptr
, is_tbnz
, bit
,
1967 aarch64_register (rt
, 1), new_offset
);
1969 else if (can_encode_int32 (new_offset
, 28))
1971 /* The offset is out of range for a test bit and branch
1972 instruction but not for a unconditional branch. We can use
1973 the following instructions instead:
1975 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
1976 B NOT_TAKEN ; Else jump over TAKEN and continue.
1982 insn_reloc
->insn_ptr
+= emit_tb (insn_reloc
->insn_ptr
, is_tbnz
, bit
,
1983 aarch64_register (rt
, 1), 8);
1984 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
1985 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0,
1990 /* Implementation of aarch64_insn_visitor method "adr". */
1993 aarch64_ftrace_insn_reloc_adr (const int32_t offset
, const unsigned rd
,
1995 struct aarch64_insn_data
*data
)
1997 struct aarch64_insn_relocation_data
*insn_reloc
1998 = (struct aarch64_insn_relocation_data
*) data
;
1999 /* We know exactly the address the ADR{P,} instruction will compute.
2000 We can just write it to the destination register. */
2001 CORE_ADDR address
= data
->insn_addr
+ offset
;
2005 /* Clear the lower 12 bits of the offset to get the 4K page. */
2006 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
2007 aarch64_register (rd
, 1),
2011 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
2012 aarch64_register (rd
, 1), address
);
2015 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
2018 aarch64_ftrace_insn_reloc_ldr_literal (const int32_t offset
, const int is_sw
,
2019 const unsigned rt
, const int is64
,
2020 struct aarch64_insn_data
*data
)
2022 struct aarch64_insn_relocation_data
*insn_reloc
2023 = (struct aarch64_insn_relocation_data
*) data
;
2024 CORE_ADDR address
= data
->insn_addr
+ offset
;
2026 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
2027 aarch64_register (rt
, 1), address
);
2029 /* We know exactly what address to load from, and what register we
2032 MOV xd, #(oldloc + offset)
2033 MOVK xd, #((oldloc + offset) >> 16), lsl #16
2036 LDR xd, [xd] ; or LDRSW xd, [xd]
2041 insn_reloc
->insn_ptr
+= emit_ldrsw (insn_reloc
->insn_ptr
,
2042 aarch64_register (rt
, 1),
2043 aarch64_register (rt
, 1),
2044 offset_memory_operand (0));
2046 insn_reloc
->insn_ptr
+= emit_ldr (insn_reloc
->insn_ptr
,
2047 aarch64_register (rt
, is64
),
2048 aarch64_register (rt
, 1),
2049 offset_memory_operand (0));
2052 /* Implementation of aarch64_insn_visitor method "others". */
2055 aarch64_ftrace_insn_reloc_others (const uint32_t insn
,
2056 struct aarch64_insn_data
*data
)
2058 struct aarch64_insn_relocation_data
*insn_reloc
2059 = (struct aarch64_insn_relocation_data
*) data
;
2061 /* The instruction is not PC relative. Just re-emit it at the new
2063 insn_reloc
->insn_ptr
+= aarch64_emit_insn (insn_reloc
->insn_ptr
, insn
);
2066 static const struct aarch64_insn_visitor visitor
=
2068 aarch64_ftrace_insn_reloc_b
,
2069 aarch64_ftrace_insn_reloc_b_cond
,
2070 aarch64_ftrace_insn_reloc_cb
,
2071 aarch64_ftrace_insn_reloc_tb
,
2072 aarch64_ftrace_insn_reloc_adr
,
2073 aarch64_ftrace_insn_reloc_ldr_literal
,
2074 aarch64_ftrace_insn_reloc_others
,
2078 aarch64_target::supports_fast_tracepoints ()
2083 /* Implementation of target ops method
2084 "install_fast_tracepoint_jump_pad". */
2087 aarch64_target::install_fast_tracepoint_jump_pad
2088 (CORE_ADDR tpoint
, CORE_ADDR tpaddr
, CORE_ADDR collector
,
2089 CORE_ADDR lockaddr
, ULONGEST orig_size
, CORE_ADDR
*jump_entry
,
2090 CORE_ADDR
*trampoline
, ULONGEST
*trampoline_size
,
2091 unsigned char *jjump_pad_insn
, ULONGEST
*jjump_pad_insn_size
,
2092 CORE_ADDR
*adjusted_insn_addr
, CORE_ADDR
*adjusted_insn_addr_end
,
2100 CORE_ADDR buildaddr
= *jump_entry
;
2101 struct aarch64_insn_relocation_data insn_data
;
2103 /* We need to save the current state on the stack both to restore it
2104 later and to collect register values when the tracepoint is hit.
2106 The saved registers are pushed in a layout that needs to be in sync
2107 with aarch64_ft_collect_regmap (see linux-aarch64-ipa.c). Later on
2108 the supply_fast_tracepoint_registers function will fill in the
2109 register cache from a pointer to saved registers on the stack we build
2112 For simplicity, we set the size of each cell on the stack to 16 bytes.
2113 This way one cell can hold any register type, from system registers
2114 to the 128 bit SIMD&FP registers. Furthermore, the stack pointer
2115 has to be 16 bytes aligned anyway.
2117 Note that the CPSR register does not exist on AArch64. Instead we
2118 can access system bits describing the process state with the
2119 MRS/MSR instructions, namely the condition flags. We save them as
2120 if they are part of a CPSR register because that's how GDB
2121 interprets these system bits. At the moment, only the condition
2122 flags are saved in CPSR (NZCV).
2124 Stack layout, each cell is 16 bytes (descending):
2126 High *-------- SIMD&FP registers from 31 down to 0. --------*
2132 *---- General purpose registers from 30 down to 0. ----*
2138 *------------- Special purpose registers. -------------*
2141 | CPSR (NZCV) | 5 cells
2144 *------------- collecting_t object --------------------*
2145 | TPIDR_EL0 | struct tracepoint * |
2146 Low *------------------------------------------------------*
2148 After this stack is set up, we issue a call to the collector, passing
2149 it the saved registers at (SP + 16). */
2151 /* Push SIMD&FP registers on the stack:
2153 SUB sp, sp, #(32 * 16)
2155 STP q30, q31, [sp, #(30 * 16)]
2160 p
+= emit_sub (p
, sp
, sp
, immediate_operand (32 * 16));
2161 for (i
= 30; i
>= 0; i
-= 2)
2162 p
+= emit_stp_q_offset (p
, i
, i
+ 1, sp
, i
* 16);
2164 /* Push general purpose registers on the stack. Note that we do not need
2165 to push x31 as it represents the xzr register and not the stack
2166 pointer in a STR instruction.
2168 SUB sp, sp, #(31 * 16)
2170 STR x30, [sp, #(30 * 16)]
2175 p
+= emit_sub (p
, sp
, sp
, immediate_operand (31 * 16));
2176 for (i
= 30; i
>= 0; i
-= 1)
2177 p
+= emit_str (p
, aarch64_register (i
, 1), sp
,
2178 offset_memory_operand (i
* 16));
2180 /* Make space for 5 more cells.
2182 SUB sp, sp, #(5 * 16)
2185 p
+= emit_sub (p
, sp
, sp
, immediate_operand (5 * 16));
2190 ADD x4, sp, #((32 + 31 + 5) * 16)
2191 STR x4, [sp, #(4 * 16)]
2194 p
+= emit_add (p
, x4
, sp
, immediate_operand ((32 + 31 + 5) * 16));
2195 p
+= emit_str (p
, x4
, sp
, offset_memory_operand (4 * 16));
2197 /* Save PC (tracepoint address):
2202 STR x3, [sp, #(3 * 16)]
2206 p
+= emit_mov_addr (p
, x3
, tpaddr
);
2207 p
+= emit_str (p
, x3
, sp
, offset_memory_operand (3 * 16));
2209 /* Save CPSR (NZCV), FPSR and FPCR:
2215 STR x2, [sp, #(2 * 16)]
2216 STR x1, [sp, #(1 * 16)]
2217 STR x0, [sp, #(0 * 16)]
2220 p
+= emit_mrs (p
, x2
, NZCV
);
2221 p
+= emit_mrs (p
, x1
, FPSR
);
2222 p
+= emit_mrs (p
, x0
, FPCR
);
2223 p
+= emit_str (p
, x2
, sp
, offset_memory_operand (2 * 16));
2224 p
+= emit_str (p
, x1
, sp
, offset_memory_operand (1 * 16));
2225 p
+= emit_str (p
, x0
, sp
, offset_memory_operand (0 * 16));
2227 /* Push the collecting_t object. It consist of the address of the
2228 tracepoint and an ID for the current thread. We get the latter by
2229 reading the tpidr_el0 system register. It corresponds to the
2230 NT_ARM_TLS register accessible with ptrace.
2237 STP x0, x1, [sp, #-16]!
2241 p
+= emit_mov_addr (p
, x0
, tpoint
);
2242 p
+= emit_mrs (p
, x1
, TPIDR_EL0
);
2243 p
+= emit_stp (p
, x0
, x1
, sp
, preindex_memory_operand (-16));
2247 The shared memory for the lock is at lockaddr. It will hold zero
2248 if no-one is holding the lock, otherwise it contains the address of
2249 the collecting_t object on the stack of the thread which acquired it.
2251 At this stage, the stack pointer points to this thread's collecting_t
2254 We use the following registers:
2255 - x0: Address of the lock.
2256 - x1: Pointer to collecting_t object.
2257 - x2: Scratch register.
2263 ; Trigger an event local to this core. So the following WFE
2264 ; instruction is ignored.
2267 ; Wait for an event. The event is triggered by either the SEVL
2268 ; or STLR instructions (store release).
2271 ; Atomically read at lockaddr. This marks the memory location as
2272 ; exclusive. This instruction also has memory constraints which
2273 ; make sure all previous data reads and writes are done before
2277 ; Try again if another thread holds the lock.
2280 ; We can lock it! Write the address of the collecting_t object.
2281 ; This instruction will fail if the memory location is not marked
2282 ; as exclusive anymore. If it succeeds, it will remove the
2283 ; exclusive mark on the memory location. This way, if another
2284 ; thread executes this instruction before us, we will fail and try
2291 p
+= emit_mov_addr (p
, x0
, lockaddr
);
2292 p
+= emit_mov (p
, x1
, register_operand (sp
));
2296 p
+= emit_ldaxr (p
, x2
, x0
);
2297 p
+= emit_cb (p
, 1, w2
, -2 * 4);
2298 p
+= emit_stxr (p
, w2
, x1
, x0
);
2299 p
+= emit_cb (p
, 1, x2
, -4 * 4);
2301 /* Call collector (struct tracepoint *, unsigned char *):
2306 ; Saved registers start after the collecting_t object.
2309 ; We use an intra-procedure-call scratch register.
2310 MOV ip0, #(collector)
2313 ; And call back to C!
2318 p
+= emit_mov_addr (p
, x0
, tpoint
);
2319 p
+= emit_add (p
, x1
, sp
, immediate_operand (16));
2321 p
+= emit_mov_addr (p
, ip0
, collector
);
2322 p
+= emit_blr (p
, ip0
);
2324 /* Release the lock.
2329 ; This instruction is a normal store with memory ordering
2330 ; constraints. Thanks to this we do not have to put a data
2331 ; barrier instruction to make sure all data read and writes are done
2332 ; before this instruction is executed. Furthermore, this instruction
2333 ; will trigger an event, letting other threads know they can grab
2338 p
+= emit_mov_addr (p
, x0
, lockaddr
);
2339 p
+= emit_stlr (p
, xzr
, x0
);
2341 /* Free collecting_t object:
2346 p
+= emit_add (p
, sp
, sp
, immediate_operand (16));
2348 /* Restore CPSR (NZCV), FPSR and FPCR. And free all special purpose
2349 registers from the stack.
2351 LDR x2, [sp, #(2 * 16)]
2352 LDR x1, [sp, #(1 * 16)]
2353 LDR x0, [sp, #(0 * 16)]
2359 ADD sp, sp #(5 * 16)
2362 p
+= emit_ldr (p
, x2
, sp
, offset_memory_operand (2 * 16));
2363 p
+= emit_ldr (p
, x1
, sp
, offset_memory_operand (1 * 16));
2364 p
+= emit_ldr (p
, x0
, sp
, offset_memory_operand (0 * 16));
2365 p
+= emit_msr (p
, NZCV
, x2
);
2366 p
+= emit_msr (p
, FPSR
, x1
);
2367 p
+= emit_msr (p
, FPCR
, x0
);
2369 p
+= emit_add (p
, sp
, sp
, immediate_operand (5 * 16));
2371 /* Pop general purpose registers:
2375 LDR x30, [sp, #(30 * 16)]
2377 ADD sp, sp, #(31 * 16)
2380 for (i
= 0; i
<= 30; i
+= 1)
2381 p
+= emit_ldr (p
, aarch64_register (i
, 1), sp
,
2382 offset_memory_operand (i
* 16));
2383 p
+= emit_add (p
, sp
, sp
, immediate_operand (31 * 16));
2385 /* Pop SIMD&FP registers:
2389 LDP q30, q31, [sp, #(30 * 16)]
2391 ADD sp, sp, #(32 * 16)
2394 for (i
= 0; i
<= 30; i
+= 2)
2395 p
+= emit_ldp_q_offset (p
, i
, i
+ 1, sp
, i
* 16);
2396 p
+= emit_add (p
, sp
, sp
, immediate_operand (32 * 16));
2398 /* Write the code into the inferior memory. */
2399 append_insns (&buildaddr
, p
- buf
, buf
);
2401 /* Now emit the relocated instruction. */
2402 *adjusted_insn_addr
= buildaddr
;
2403 target_read_uint32 (tpaddr
, &insn
);
2405 insn_data
.base
.insn_addr
= tpaddr
;
2406 insn_data
.new_addr
= buildaddr
;
2407 insn_data
.insn_ptr
= buf
;
2409 aarch64_relocate_instruction (insn
, &visitor
,
2410 (struct aarch64_insn_data
*) &insn_data
);
2412 /* We may not have been able to relocate the instruction. */
2413 if (insn_data
.insn_ptr
== buf
)
2416 "E.Could not relocate instruction from %s to %s.",
2417 core_addr_to_string_nz (tpaddr
),
2418 core_addr_to_string_nz (buildaddr
));
2422 append_insns (&buildaddr
, insn_data
.insn_ptr
- buf
, buf
);
2423 *adjusted_insn_addr_end
= buildaddr
;
2425 /* Go back to the start of the buffer. */
2428 /* Emit a branch back from the jump pad. */
2429 offset
= (tpaddr
+ orig_size
- buildaddr
);
2430 if (!can_encode_int32 (offset
, 28))
2433 "E.Jump back from jump pad too far from tracepoint "
2434 "(offset 0x%" PRIx64
" cannot be encoded in 28 bits).",
2439 p
+= emit_b (p
, 0, offset
);
2440 append_insns (&buildaddr
, p
- buf
, buf
);
2442 /* Give the caller a branch instruction into the jump pad. */
2443 offset
= (*jump_entry
- tpaddr
);
2444 if (!can_encode_int32 (offset
, 28))
2447 "E.Jump pad too far from tracepoint "
2448 "(offset 0x%" PRIx64
" cannot be encoded in 28 bits).",
2453 emit_b ((uint32_t *) jjump_pad_insn
, 0, offset
);
2454 *jjump_pad_insn_size
= 4;
2456 /* Return the end address of our pad. */
2457 *jump_entry
= buildaddr
;
2462 /* Helper function writing LEN instructions from START into
2463 current_insn_ptr. */
2466 emit_ops_insns (const uint32_t *start
, int len
)
2468 CORE_ADDR buildaddr
= current_insn_ptr
;
2471 debug_printf ("Adding %d instrucions at %s\n",
2472 len
, paddress (buildaddr
));
2474 append_insns (&buildaddr
, len
, start
);
2475 current_insn_ptr
= buildaddr
;
2478 /* Pop a register from the stack. */
2481 emit_pop (uint32_t *buf
, struct aarch64_register rt
)
2483 return emit_ldr (buf
, rt
, sp
, postindex_memory_operand (1 * 16));
2486 /* Push a register on the stack. */
2489 emit_push (uint32_t *buf
, struct aarch64_register rt
)
2491 return emit_str (buf
, rt
, sp
, preindex_memory_operand (-1 * 16));
2494 /* Implementation of emit_ops method "emit_prologue". */
2497 aarch64_emit_prologue (void)
2502 /* This function emit a prologue for the following function prototype:
2504 enum eval_result_type f (unsigned char *regs,
2507 The first argument is a buffer of raw registers. The second
2508 argument is the result of
2509 evaluating the expression, which will be set to whatever is on top of
2510 the stack at the end.
2512 The stack set up by the prologue is as such:
2514 High *------------------------------------------------------*
2517 | x1 (ULONGEST *value) |
2518 | x0 (unsigned char *regs) |
2519 Low *------------------------------------------------------*
2521 As we are implementing a stack machine, each opcode can expand the
2522 stack so we never know how far we are from the data saved by this
2523 prologue. In order to be able refer to value and regs later, we save
2524 the current stack pointer in the frame pointer. This way, it is not
2525 clobbered when calling C functions.
2527 Finally, throughout every operation, we are using register x0 as the
2528 top of the stack, and x1 as a scratch register. */
2530 p
+= emit_stp (p
, x0
, x1
, sp
, preindex_memory_operand (-2 * 16));
2531 p
+= emit_str (p
, lr
, sp
, offset_memory_operand (3 * 8));
2532 p
+= emit_str (p
, fp
, sp
, offset_memory_operand (2 * 8));
2534 p
+= emit_add (p
, fp
, sp
, immediate_operand (2 * 8));
2537 emit_ops_insns (buf
, p
- buf
);
2540 /* Implementation of emit_ops method "emit_epilogue". */
2543 aarch64_emit_epilogue (void)
2548 /* Store the result of the expression (x0) in *value. */
2549 p
+= emit_sub (p
, x1
, fp
, immediate_operand (1 * 8));
2550 p
+= emit_ldr (p
, x1
, x1
, offset_memory_operand (0));
2551 p
+= emit_str (p
, x0
, x1
, offset_memory_operand (0));
2553 /* Restore the previous state. */
2554 p
+= emit_add (p
, sp
, fp
, immediate_operand (2 * 8));
2555 p
+= emit_ldp (p
, fp
, lr
, fp
, offset_memory_operand (0));
2557 /* Return expr_eval_no_error. */
2558 p
+= emit_mov (p
, x0
, immediate_operand (expr_eval_no_error
));
2559 p
+= emit_ret (p
, lr
);
2561 emit_ops_insns (buf
, p
- buf
);
2564 /* Implementation of emit_ops method "emit_add". */
2567 aarch64_emit_add (void)
2572 p
+= emit_pop (p
, x1
);
2573 p
+= emit_add (p
, x0
, x1
, register_operand (x0
));
2575 emit_ops_insns (buf
, p
- buf
);
2578 /* Implementation of emit_ops method "emit_sub". */
2581 aarch64_emit_sub (void)
2586 p
+= emit_pop (p
, x1
);
2587 p
+= emit_sub (p
, x0
, x1
, register_operand (x0
));
2589 emit_ops_insns (buf
, p
- buf
);
2592 /* Implementation of emit_ops method "emit_mul". */
2595 aarch64_emit_mul (void)
2600 p
+= emit_pop (p
, x1
);
2601 p
+= emit_mul (p
, x0
, x1
, x0
);
2603 emit_ops_insns (buf
, p
- buf
);
2606 /* Implementation of emit_ops method "emit_lsh". */
2609 aarch64_emit_lsh (void)
2614 p
+= emit_pop (p
, x1
);
2615 p
+= emit_lslv (p
, x0
, x1
, x0
);
2617 emit_ops_insns (buf
, p
- buf
);
2620 /* Implementation of emit_ops method "emit_rsh_signed". */
2623 aarch64_emit_rsh_signed (void)
2628 p
+= emit_pop (p
, x1
);
2629 p
+= emit_asrv (p
, x0
, x1
, x0
);
2631 emit_ops_insns (buf
, p
- buf
);
2634 /* Implementation of emit_ops method "emit_rsh_unsigned". */
2637 aarch64_emit_rsh_unsigned (void)
2642 p
+= emit_pop (p
, x1
);
2643 p
+= emit_lsrv (p
, x0
, x1
, x0
);
2645 emit_ops_insns (buf
, p
- buf
);
2648 /* Implementation of emit_ops method "emit_ext". */
2651 aarch64_emit_ext (int arg
)
2656 p
+= emit_sbfx (p
, x0
, x0
, 0, arg
);
2658 emit_ops_insns (buf
, p
- buf
);
2661 /* Implementation of emit_ops method "emit_log_not". */
2664 aarch64_emit_log_not (void)
2669 /* If the top of the stack is 0, replace it with 1. Else replace it with
2672 p
+= emit_cmp (p
, x0
, immediate_operand (0));
2673 p
+= emit_cset (p
, x0
, EQ
);
2675 emit_ops_insns (buf
, p
- buf
);
2678 /* Implementation of emit_ops method "emit_bit_and". */
2681 aarch64_emit_bit_and (void)
2686 p
+= emit_pop (p
, x1
);
2687 p
+= emit_and (p
, x0
, x0
, x1
);
2689 emit_ops_insns (buf
, p
- buf
);
2692 /* Implementation of emit_ops method "emit_bit_or". */
2695 aarch64_emit_bit_or (void)
2700 p
+= emit_pop (p
, x1
);
2701 p
+= emit_orr (p
, x0
, x0
, x1
);
2703 emit_ops_insns (buf
, p
- buf
);
2706 /* Implementation of emit_ops method "emit_bit_xor". */
2709 aarch64_emit_bit_xor (void)
2714 p
+= emit_pop (p
, x1
);
2715 p
+= emit_eor (p
, x0
, x0
, x1
);
2717 emit_ops_insns (buf
, p
- buf
);
2720 /* Implementation of emit_ops method "emit_bit_not". */
2723 aarch64_emit_bit_not (void)
2728 p
+= emit_mvn (p
, x0
, x0
);
2730 emit_ops_insns (buf
, p
- buf
);
2733 /* Implementation of emit_ops method "emit_equal". */
2736 aarch64_emit_equal (void)
2741 p
+= emit_pop (p
, x1
);
2742 p
+= emit_cmp (p
, x0
, register_operand (x1
));
2743 p
+= emit_cset (p
, x0
, EQ
);
2745 emit_ops_insns (buf
, p
- buf
);
2748 /* Implementation of emit_ops method "emit_less_signed". */
2751 aarch64_emit_less_signed (void)
2756 p
+= emit_pop (p
, x1
);
2757 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2758 p
+= emit_cset (p
, x0
, LT
);
2760 emit_ops_insns (buf
, p
- buf
);
2763 /* Implementation of emit_ops method "emit_less_unsigned". */
2766 aarch64_emit_less_unsigned (void)
2771 p
+= emit_pop (p
, x1
);
2772 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2773 p
+= emit_cset (p
, x0
, LO
);
2775 emit_ops_insns (buf
, p
- buf
);
2778 /* Implementation of emit_ops method "emit_ref". */
2781 aarch64_emit_ref (int size
)
2789 p
+= emit_ldrb (p
, w0
, x0
, offset_memory_operand (0));
2792 p
+= emit_ldrh (p
, w0
, x0
, offset_memory_operand (0));
2795 p
+= emit_ldr (p
, w0
, x0
, offset_memory_operand (0));
2798 p
+= emit_ldr (p
, x0
, x0
, offset_memory_operand (0));
2801 /* Unknown size, bail on compilation. */
2806 emit_ops_insns (buf
, p
- buf
);
2809 /* Implementation of emit_ops method "emit_if_goto". */
2812 aarch64_emit_if_goto (int *offset_p
, int *size_p
)
2817 /* The Z flag is set or cleared here. */
2818 p
+= emit_cmp (p
, x0
, immediate_operand (0));
2819 /* This instruction must not change the Z flag. */
2820 p
+= emit_pop (p
, x0
);
2821 /* Branch over the next instruction if x0 == 0. */
2822 p
+= emit_bcond (p
, EQ
, 8);
2824 /* The NOP instruction will be patched with an unconditional branch. */
2826 *offset_p
= (p
- buf
) * 4;
2831 emit_ops_insns (buf
, p
- buf
);
2834 /* Implementation of emit_ops method "emit_goto". */
2837 aarch64_emit_goto (int *offset_p
, int *size_p
)
2842 /* The NOP instruction will be patched with an unconditional branch. */
2849 emit_ops_insns (buf
, p
- buf
);
2852 /* Implementation of emit_ops method "write_goto_address". */
2855 aarch64_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2859 emit_b (&insn
, 0, to
- from
);
2860 append_insns (&from
, 1, &insn
);
2863 /* Implementation of emit_ops method "emit_const". */
2866 aarch64_emit_const (LONGEST num
)
2871 p
+= emit_mov_addr (p
, x0
, num
);
2873 emit_ops_insns (buf
, p
- buf
);
2876 /* Implementation of emit_ops method "emit_call". */
2879 aarch64_emit_call (CORE_ADDR fn
)
2884 p
+= emit_mov_addr (p
, ip0
, fn
);
2885 p
+= emit_blr (p
, ip0
);
2887 emit_ops_insns (buf
, p
- buf
);
2890 /* Implementation of emit_ops method "emit_reg". */
2893 aarch64_emit_reg (int reg
)
2898 /* Set x0 to unsigned char *regs. */
2899 p
+= emit_sub (p
, x0
, fp
, immediate_operand (2 * 8));
2900 p
+= emit_ldr (p
, x0
, x0
, offset_memory_operand (0));
2901 p
+= emit_mov (p
, x1
, immediate_operand (reg
));
2903 emit_ops_insns (buf
, p
- buf
);
2905 aarch64_emit_call (get_raw_reg_func_addr ());
2908 /* Implementation of emit_ops method "emit_pop". */
2911 aarch64_emit_pop (void)
2916 p
+= emit_pop (p
, x0
);
2918 emit_ops_insns (buf
, p
- buf
);
2921 /* Implementation of emit_ops method "emit_stack_flush". */
2924 aarch64_emit_stack_flush (void)
2929 p
+= emit_push (p
, x0
);
2931 emit_ops_insns (buf
, p
- buf
);
2934 /* Implementation of emit_ops method "emit_zero_ext". */
2937 aarch64_emit_zero_ext (int arg
)
2942 p
+= emit_ubfx (p
, x0
, x0
, 0, arg
);
2944 emit_ops_insns (buf
, p
- buf
);
2947 /* Implementation of emit_ops method "emit_swap". */
2950 aarch64_emit_swap (void)
2955 p
+= emit_ldr (p
, x1
, sp
, offset_memory_operand (0 * 16));
2956 p
+= emit_str (p
, x0
, sp
, offset_memory_operand (0 * 16));
2957 p
+= emit_mov (p
, x0
, register_operand (x1
));
2959 emit_ops_insns (buf
, p
- buf
);
2962 /* Implementation of emit_ops method "emit_stack_adjust". */
2965 aarch64_emit_stack_adjust (int n
)
2967 /* This is not needed with our design. */
2971 p
+= emit_add (p
, sp
, sp
, immediate_operand (n
* 16));
2973 emit_ops_insns (buf
, p
- buf
);
2976 /* Implementation of emit_ops method "emit_int_call_1". */
2979 aarch64_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2984 p
+= emit_mov (p
, x0
, immediate_operand (arg1
));
2986 emit_ops_insns (buf
, p
- buf
);
2988 aarch64_emit_call (fn
);
2991 /* Implementation of emit_ops method "emit_void_call_2". */
2994 aarch64_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2999 /* Push x0 on the stack. */
3000 aarch64_emit_stack_flush ();
3002 /* Setup arguments for the function call:
3005 x1: top of the stack
3010 p
+= emit_mov (p
, x1
, register_operand (x0
));
3011 p
+= emit_mov (p
, x0
, immediate_operand (arg1
));
3013 emit_ops_insns (buf
, p
- buf
);
3015 aarch64_emit_call (fn
);
3018 aarch64_emit_pop ();
3021 /* Implementation of emit_ops method "emit_eq_goto". */
3024 aarch64_emit_eq_goto (int *offset_p
, int *size_p
)
3029 p
+= emit_pop (p
, x1
);
3030 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3031 /* Branch over the next instruction if x0 != x1. */
3032 p
+= emit_bcond (p
, NE
, 8);
3033 /* The NOP instruction will be patched with an unconditional branch. */
3035 *offset_p
= (p
- buf
) * 4;
3040 emit_ops_insns (buf
, p
- buf
);
3043 /* Implementation of emit_ops method "emit_ne_goto". */
3046 aarch64_emit_ne_goto (int *offset_p
, int *size_p
)
3051 p
+= emit_pop (p
, x1
);
3052 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3053 /* Branch over the next instruction if x0 == x1. */
3054 p
+= emit_bcond (p
, EQ
, 8);
3055 /* The NOP instruction will be patched with an unconditional branch. */
3057 *offset_p
= (p
- buf
) * 4;
3062 emit_ops_insns (buf
, p
- buf
);
3065 /* Implementation of emit_ops method "emit_lt_goto". */
3068 aarch64_emit_lt_goto (int *offset_p
, int *size_p
)
3073 p
+= emit_pop (p
, x1
);
3074 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3075 /* Branch over the next instruction if x0 >= x1. */
3076 p
+= emit_bcond (p
, GE
, 8);
3077 /* The NOP instruction will be patched with an unconditional branch. */
3079 *offset_p
= (p
- buf
) * 4;
3084 emit_ops_insns (buf
, p
- buf
);
3087 /* Implementation of emit_ops method "emit_le_goto". */
3090 aarch64_emit_le_goto (int *offset_p
, int *size_p
)
3095 p
+= emit_pop (p
, x1
);
3096 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3097 /* Branch over the next instruction if x0 > x1. */
3098 p
+= emit_bcond (p
, GT
, 8);
3099 /* The NOP instruction will be patched with an unconditional branch. */
3101 *offset_p
= (p
- buf
) * 4;
3106 emit_ops_insns (buf
, p
- buf
);
3109 /* Implementation of emit_ops method "emit_gt_goto". */
3112 aarch64_emit_gt_goto (int *offset_p
, int *size_p
)
3117 p
+= emit_pop (p
, x1
);
3118 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3119 /* Branch over the next instruction if x0 <= x1. */
3120 p
+= emit_bcond (p
, LE
, 8);
3121 /* The NOP instruction will be patched with an unconditional branch. */
3123 *offset_p
= (p
- buf
) * 4;
3128 emit_ops_insns (buf
, p
- buf
);
3131 /* Implementation of emit_ops method "emit_ge_got". */
3134 aarch64_emit_ge_got (int *offset_p
, int *size_p
)
3139 p
+= emit_pop (p
, x1
);
3140 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3141 /* Branch over the next instruction if x0 <= x1. */
3142 p
+= emit_bcond (p
, LT
, 8);
3143 /* The NOP instruction will be patched with an unconditional branch. */
3145 *offset_p
= (p
- buf
) * 4;
3150 emit_ops_insns (buf
, p
- buf
);
3153 static struct emit_ops aarch64_emit_ops_impl
=
3155 aarch64_emit_prologue
,
3156 aarch64_emit_epilogue
,
3161 aarch64_emit_rsh_signed
,
3162 aarch64_emit_rsh_unsigned
,
3164 aarch64_emit_log_not
,
3165 aarch64_emit_bit_and
,
3166 aarch64_emit_bit_or
,
3167 aarch64_emit_bit_xor
,
3168 aarch64_emit_bit_not
,
3170 aarch64_emit_less_signed
,
3171 aarch64_emit_less_unsigned
,
3173 aarch64_emit_if_goto
,
3175 aarch64_write_goto_address
,
3180 aarch64_emit_stack_flush
,
3181 aarch64_emit_zero_ext
,
3183 aarch64_emit_stack_adjust
,
3184 aarch64_emit_int_call_1
,
3185 aarch64_emit_void_call_2
,
3186 aarch64_emit_eq_goto
,
3187 aarch64_emit_ne_goto
,
3188 aarch64_emit_lt_goto
,
3189 aarch64_emit_le_goto
,
3190 aarch64_emit_gt_goto
,
3191 aarch64_emit_ge_got
,
3194 /* Implementation of target ops method "emit_ops". */
3197 aarch64_target::emit_ops ()
3199 return &aarch64_emit_ops_impl
;
3202 /* Implementation of target ops method
3203 "get_min_fast_tracepoint_insn_len". */
3206 aarch64_target::get_min_fast_tracepoint_insn_len ()
3211 /* Implementation of linux target ops method "low_supports_range_stepping". */
3214 aarch64_target::low_supports_range_stepping ()
3219 /* Implementation of target ops method "sw_breakpoint_from_kind". */
3222 aarch64_target::sw_breakpoint_from_kind (int kind
, int *size
)
3224 if (is_64bit_tdesc ())
3226 *size
= aarch64_breakpoint_len
;
3227 return aarch64_breakpoint
;
3230 return arm_sw_breakpoint_from_kind (kind
, size
);
3233 /* Implementation of target ops method "breakpoint_kind_from_pc". */
3236 aarch64_target::breakpoint_kind_from_pc (CORE_ADDR
*pcptr
)
3238 if (is_64bit_tdesc ())
3239 return aarch64_breakpoint_len
;
3241 return arm_breakpoint_kind_from_pc (pcptr
);
3244 /* Implementation of the target ops method
3245 "breakpoint_kind_from_current_state". */
3248 aarch64_target::breakpoint_kind_from_current_state (CORE_ADDR
*pcptr
)
3250 if (is_64bit_tdesc ())
3251 return aarch64_breakpoint_len
;
3253 return arm_breakpoint_kind_from_current_state (pcptr
);
3256 /* Returns true if memory tagging is supported. */
3258 aarch64_target::supports_memory_tagging ()
3260 if (current_thread
== NULL
)
3262 /* We don't have any processes running, so don't attempt to
3263 use linux_get_hwcap2 as it will try to fetch the current
3264 thread id. Instead, just fetch the auxv from the self
3266 #ifdef HAVE_GETAUXVAL
3267 return (getauxval (AT_HWCAP2
) & HWCAP2_MTE
) != 0;
3273 return (linux_get_hwcap2 (8) & HWCAP2_MTE
) != 0;
3277 aarch64_target::fetch_memtags (CORE_ADDR address
, size_t len
,
3278 gdb::byte_vector
&tags
, int type
)
3280 /* Allocation tags are per-process, so any tid is fine. */
3281 int tid
= lwpid_of (current_thread
);
3283 /* Allocation tag? */
3284 if (type
== static_cast <int> (aarch64_memtag_type::mte_allocation
))
3285 return aarch64_mte_fetch_memtags (tid
, address
, len
, tags
);
3291 aarch64_target::store_memtags (CORE_ADDR address
, size_t len
,
3292 const gdb::byte_vector
&tags
, int type
)
3294 /* Allocation tags are per-process, so any tid is fine. */
3295 int tid
= lwpid_of (current_thread
);
3297 /* Allocation tag? */
3298 if (type
== static_cast <int> (aarch64_memtag_type::mte_allocation
))
3299 return aarch64_mte_store_memtags (tid
, address
, len
, tags
);
3304 /* The linux target ops object. */
3306 linux_process_target
*the_linux_target
= &the_aarch64_target
;
3309 initialize_low_arch (void)
3311 initialize_low_arch_aarch32 ();
3313 initialize_regsets_info (&aarch64_regsets_info
);