gdbserver/linux-crisv32-low.cc

   1 /* GNU/Linux/CRIS specific low level interface, for the remote server for GDB.
   2    Copyright (C) 1995-2020 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #include "server.h"
  20 #include "linux-low.h"
  21 #include "nat/gdb_ptrace.h"
  22
  23 /* Linux target op definitions for the CRIS architecture.  */
  24
  25 class crisv32_target : public linux_process_target
  26 {
  27 public:
  28
  29   const regs_info *get_regs_info () override;
  30
  31 protected:
  32
  33   void low_arch_setup () override;
  34 };
  35
  36 /* The singleton target ops object.  */
  37
  38 static crisv32_target the_crisv32_target;
  39
  40 /* Defined in auto-generated file reg-crisv32.c.  */
  41 void init_registers_crisv32 (void);
  42 extern const struct target_desc *tdesc_crisv32;
  43
  44 /* CRISv32 */
  45 #define cris_num_regs 49
  46
  47 #ifndef PTRACE_GET_THREAD_AREA
  48 #define PTRACE_GET_THREAD_AREA 25
  49 #endif
  50
  51 /* Note: Ignoring USP (having the stack pointer in two locations causes trouble
  52    without any significant gain).  */
  53
  54 /* Locations need to match <include/asm/arch/ptrace.h>.  */
  55 static int cris_regmap[] = {
  56   1*4, 2*4, 3*4, 4*4,
  57   5*4, 6*4, 7*4, 8*4,
  58   9*4, 10*4, 11*4, 12*4,
  59   13*4, 14*4, 24*4, 15*4,
  60
  61   -1, -1, -1, 16*4,
  62   -1, 22*4, 23*4, 17*4,
  63   -1, -1, 21*4, 20*4,
  64   -1, 19*4, -1, 18*4,
  65
  66   25*4,
  67
  68   26*4, -1,   -1,   29*4,
  69   30*4, 31*4, 32*4, 33*4,
  70   34*4, 35*4, 36*4, 37*4,
  71   38*4, 39*4, 40*4, -1
  72
  73 };
  74
  75 static const unsigned short cris_breakpoint = 0xe938;
  76 #define cris_breakpoint_len 2
  77
  78 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind".  */
  79
  80 static const gdb_byte *
  81 cris_sw_breakpoint_from_kind (int kind, int *size)
  82 {
  83   *size = cris_breakpoint_len;
  84   return (const gdb_byte *) &cris_breakpoint;
  85 }
  86
  87 static int
  88 cris_breakpoint_at (CORE_ADDR where)
  89 {
  90   unsigned short insn;
  91
  92   the_target->read_memory (where, (unsigned char *) &insn,
  93                            cris_breakpoint_len);
  94   if (insn == cris_breakpoint)
  95     return 1;
  96
  97   /* If necessary, recognize more trap instructions here.  GDB only uses the
  98      one.  */
  99   return 0;
 100 }
 101
 102 static void
 103 cris_write_data_breakpoint (struct regcache *regcache,
 104                             int bp, unsigned long start, unsigned long end)
 105 {
 106   switch (bp)
 107     {
 108     case 0:
 109       supply_register_by_name (regcache, "s3", &start);
 110       supply_register_by_name (regcache, "s4", &end);
 111       break;
 112     case 1:
 113       supply_register_by_name (regcache, "s5", &start);
 114       supply_register_by_name (regcache, "s6", &end);
 115       break;
 116     case 2:
 117       supply_register_by_name (regcache, "s7", &start);
 118       supply_register_by_name (regcache, "s8", &end);
 119       break;
 120     case 3:
 121       supply_register_by_name (regcache, "s9", &start);
 122       supply_register_by_name (regcache, "s10", &end);
 123       break;
 124     case 4:
 125       supply_register_by_name (regcache, "s11", &start);
 126       supply_register_by_name (regcache, "s12", &end);
 127       break;
 128     case 5:
 129       supply_register_by_name (regcache, "s13", &start);
 130       supply_register_by_name (regcache, "s14", &end);
 131       break;
 132     }
 133 }
 134
 135 static int
 136 cris_supports_z_point_type (char z_type)
 137 {
 138   switch (z_type)
 139     {
 140     case Z_PACKET_WRITE_WP:
 141     case Z_PACKET_READ_WP:
 142     case Z_PACKET_ACCESS_WP:
 143       return 1;
 144     default:
 145       return 0;
 146     }
 147 }
 148
 149 static int
 150 cris_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
 151                    int len, struct raw_breakpoint *bp)
 152 {
 153   int bp;
 154   unsigned long bp_ctrl;
 155   unsigned long start, end;
 156   unsigned long ccs;
 157   struct regcache *regcache;
 158
 159   regcache = get_thread_regcache (current_thread, 1);
 160
 161   /* Read watchpoints are set as access watchpoints, because of GDB's
 162      inability to deal with pure read watchpoints.  */
 163   if (type == raw_bkpt_type_read_wp)
 164     type = raw_bkpt_type_access_wp;
 165
 166   /* Get the configuration register.  */
 167   collect_register_by_name (regcache, "s0", &bp_ctrl);
 168
 169   /* The watchpoint allocation scheme is the simplest possible.
 170      For example, if a region is watched for read and
 171      a write watch is requested, a new watchpoint will
 172      be used.  Also, if a watch for a region that is already
 173      covered by one or more existing watchpoints, a new
 174      watchpoint will be used.  */
 175
 176   /* First, find a free data watchpoint.  */
 177   for (bp = 0; bp < 6; bp++)
 178     {
 179       /* Each data watchpoint's control registers occupy 2 bits
 180          (hence the 3), starting at bit 2 for D0 (hence the 2)
 181          with 4 bits between for each watchpoint (yes, the 4).  */
 182       if (!(bp_ctrl & (0x3 << (2 + (bp * 4)))))
 183         break;
 184     }
 185
 186   if (bp > 5)
 187     {
 188       /* We're out of watchpoints.  */
 189       return -1;
 190     }
 191
 192   /* Configure the control register first.  */
 193   if (type == raw_bkpt_type_read_wp || type == raw_bkpt_type_access_wp)
 194     {
 195       /* Trigger on read.  */
 196       bp_ctrl |= (1 << (2 + bp * 4));
 197     }
 198   if (type == raw_bkpt_type_write_wp || type == raw_bkpt_type_access_wp)
 199     {
 200       /* Trigger on write.  */
 201       bp_ctrl |= (2 << (2 + bp * 4));
 202     }
 203
 204   /* Setup the configuration register.  */
 205   supply_register_by_name (regcache, "s0", &bp_ctrl);
 206
 207   /* Setup the range.  */
 208   start = addr;
 209   end = addr + len - 1;
 210
 211   /* Configure the watchpoint register.  */
 212   cris_write_data_breakpoint (regcache, bp, start, end);
 213
 214   collect_register_by_name (regcache, "ccs", &ccs);
 215   /* Set the S1 flag to enable watchpoints.  */
 216   ccs |= (1 << 19);
 217   supply_register_by_name (regcache, "ccs", &ccs);
 218
 219   return 0;
 220 }
 221
 222 static int
 223 cris_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, int len,
 224                    struct raw_breakpoint *bp)
 225 {
 226   int bp;
 227   unsigned long bp_ctrl;
 228   unsigned long start, end;
 229   struct regcache *regcache;
 230   unsigned long bp_d_regs[12];
 231
 232   regcache = get_thread_regcache (current_thread, 1);
 233
 234   /* Read watchpoints are set as access watchpoints, because of GDB's
 235      inability to deal with pure read watchpoints.  */
 236   if (type == raw_bkpt_type_read_wp)
 237     type = raw_bkpt_type_access_wp;
 238
 239   /* Get the configuration register.  */
 240   collect_register_by_name (regcache, "s0", &bp_ctrl);
 241
 242   /* Try to find a watchpoint that is configured for the
 243      specified range, then check that read/write also matches.  */
 244
 245   /* Ugly pointer arithmetic, since I cannot rely on a
 246      single switch (addr) as there may be several watchpoints with
 247      the same start address for example.  */
 248
 249   /* Get all range registers to simplify search.  */
 250   collect_register_by_name (regcache, "s3", &bp_d_regs[0]);
 251   collect_register_by_name (regcache, "s4", &bp_d_regs[1]);
 252   collect_register_by_name (regcache, "s5", &bp_d_regs[2]);
 253   collect_register_by_name (regcache, "s6", &bp_d_regs[3]);
 254   collect_register_by_name (regcache, "s7", &bp_d_regs[4]);
 255   collect_register_by_name (regcache, "s8", &bp_d_regs[5]);
 256   collect_register_by_name (regcache, "s9", &bp_d_regs[6]);
 257   collect_register_by_name (regcache, "s10", &bp_d_regs[7]);
 258   collect_register_by_name (regcache, "s11", &bp_d_regs[8]);
 259   collect_register_by_name (regcache, "s12", &bp_d_regs[9]);
 260   collect_register_by_name (regcache, "s13", &bp_d_regs[10]);
 261   collect_register_by_name (regcache, "s14", &bp_d_regs[11]);
 262
 263   for (bp = 0; bp < 6; bp++)
 264     {
 265       if (bp_d_regs[bp * 2] == addr
 266           && bp_d_regs[bp * 2 + 1] == (addr + len - 1)) {
 267         /* Matching range.  */
 268         int bitpos = 2 + bp * 4;
 269         int rw_bits;
 270
 271         /* Read/write bits for this BP.  */
 272         rw_bits = (bp_ctrl & (0x3 << bitpos)) >> bitpos;
 273
 274         if ((type == raw_bkpt_type_read_wp && rw_bits == 0x1)
 275             || (type == raw_bkpt_type_write_wp && rw_bits == 0x2)
 276             || (type == raw_bkpt_type_access_wp && rw_bits == 0x3))
 277           {
 278             /* Read/write matched.  */
 279             break;
 280           }
 281       }
 282     }
 283
 284   if (bp > 5)
 285     {
 286       /* No watchpoint matched.  */
 287       return -1;
 288     }
 289
 290   /* Found a matching watchpoint.  Now, deconfigure it by
 291      both disabling read/write in bp_ctrl and zeroing its
 292      start/end addresses.  */
 293   bp_ctrl &= ~(3 << (2 + (bp * 4)));
 294   /* Setup the configuration register.  */
 295   supply_register_by_name (regcache, "s0", &bp_ctrl);
 296
 297   start = end = 0;
 298   /* Configure the watchpoint register.  */
 299   cris_write_data_breakpoint (regcache, bp, start, end);
 300
 301   /* Note that we don't clear the S1 flag here.  It's done when continuing.  */
 302   return 0;
 303 }
 304
 305 static int
 306 cris_stopped_by_watchpoint (void)
 307 {
 308   unsigned long exs;
 309   struct regcache *regcache = get_thread_regcache (current_thread, 1);
 310
 311   collect_register_by_name (regcache, "exs", &exs);
 312
 313   return (((exs & 0xff00) >> 8) == 0xc);
 314 }
 315
 316 static CORE_ADDR
 317 cris_stopped_data_address (void)
 318 {
 319   unsigned long eda;
 320   struct regcache *regcache = get_thread_regcache (current_thread, 1);
 321
 322   collect_register_by_name (regcache, "eda", &eda);
 323
 324   /* FIXME: Possibly adjust to match watched range.  */
 325   return eda;
 326 }
 327
 328 ps_err_e
 329 ps_get_thread_area (struct ps_prochandle *ph,
 330                     lwpid_t lwpid, int idx, void **base)
 331 {
 332   if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
 333     return PS_ERR;
 334
 335   /* IDX is the bias from the thread pointer to the beginning of the
 336      thread descriptor.  It has to be subtracted due to implementation
 337      quirks in libthread_db.  */
 338   *base = (void *) ((char *) *base - idx);
 339   return PS_OK;
 340 }
 341
 342 static void
 343 cris_fill_gregset (struct regcache *regcache, void *buf)
 344 {
 345   int i;
 346
 347   for (i = 0; i < cris_num_regs; i++)
 348     {
 349       if (cris_regmap[i] != -1)
 350         collect_register (regcache, i, ((char *) buf) + cris_regmap[i]);
 351     }
 352 }
 353
 354 static void
 355 cris_store_gregset (struct regcache *regcache, const void *buf)
 356 {
 357   int i;
 358
 359   for (i = 0; i < cris_num_regs; i++)
 360     {
 361       if (cris_regmap[i] != -1)
 362         supply_register (regcache, i, ((char *) buf) + cris_regmap[i]);
 363     }
 364 }
 365
 366 void
 367 crisv32_target::low_arch_setup ()
 368 {
 369   current_process ()->tdesc = tdesc_crisv32;
 370 }
 371
 372 /* Support for hardware single step.  */
 373
 374 static int
 375 cris_supports_hardware_single_step (void)
 376 {
 377   return 1;
 378 }
 379
 380 static struct regset_info cris_regsets[] = {
 381   { PTRACE_GETREGS, PTRACE_SETREGS, 0, cris_num_regs * 4,
 382     GENERAL_REGS, cris_fill_gregset, cris_store_gregset },
 383   NULL_REGSET
 384 };
 385
 386
 387 static struct regsets_info cris_regsets_info =
 388   {
 389     cris_regsets, /* regsets */
 390     0, /* num_regsets */
 391     NULL, /* disabled_regsets */
 392   };
 393
 394 static struct usrregs_info cris_usrregs_info =
 395   {
 396     cris_num_regs,
 397     cris_regmap,
 398   };
 399
 400 static struct regs_info myregs_info =
 401   {
 402     NULL, /* regset_bitmap */
 403     &cris_usrregs_info,
 404     &cris_regsets_info
 405   };
 406
 407 const regs_info *
 408 crisv32_target::get_regs_info ()
 409 {
 410   return &myregs_info;
 411 }
 412
 413 struct linux_target_ops the_low_target = {
 414   NULL,
 415   NULL,
 416   NULL, /* fetch_register */
 417   linux_get_pc_32bit,
 418   linux_set_pc_32bit,
 419   NULL, /* breakpoint_kind_from_pc */
 420   cris_sw_breakpoint_from_kind,
 421   NULL, /* get_next_pcs */
 422   0,
 423   cris_breakpoint_at,
 424   cris_supports_z_point_type,
 425   cris_insert_point,
 426   cris_remove_point,
 427   cris_stopped_by_watchpoint,
 428   cris_stopped_data_address,
 429   NULL, /* collect_ptrace_register */
 430   NULL, /* supply_ptrace_register */
 431   NULL, /* siginfo_fixup */
 432   NULL, /* new_process */
 433   NULL, /* delete_process */
 434   NULL, /* new_thread */
 435   NULL, /* delete_thread */
 436   NULL, /* new_fork */
 437   NULL, /* prepare_to_resume */
 438   NULL, /* process_qsupported */
 439   NULL, /* supports_tracepoints */
 440   NULL, /* get_thread_area */
 441   NULL, /* install_fast_tracepoint_jump_pad */
 442   NULL, /* emit_ops */
 443   NULL, /* get_min_fast_tracepoint_insn_len */
 444   NULL, /* supports_range_stepping */
 445   NULL, /* breakpoint_kind_from_current_state */
 446   cris_supports_hardware_single_step,
 447 };
 448
 449 /* The linux target ops object.  */
 450
 451 linux_process_target *the_linux_target = &the_crisv32_target;
 452
 453 void
 454 initialize_low_arch (void)
 455 {
 456   init_registers_crisv32 ();
 457
 458   initialize_regsets_info (&cris_regsets_info);
 459 }