1 /* GNU/Linux/CRIS specific low level interface, for the remote server for GDB.
2 Copyright (C) 1995-2020 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 #include "linux-low.h"
21 #include "nat/gdb_ptrace.h"
23 /* Linux target op definitions for the CRIS architecture. */
25 class crisv32_target
: public linux_process_target
31 void low_arch_setup () override
;
34 /* The singleton target ops object. */
36 static crisv32_target the_crisv32_target
;
38 /* Defined in auto-generated file reg-crisv32.c. */
39 void init_registers_crisv32 (void);
40 extern const struct target_desc
*tdesc_crisv32
;
43 #define cris_num_regs 49
45 #ifndef PTRACE_GET_THREAD_AREA
46 #define PTRACE_GET_THREAD_AREA 25
49 /* Note: Ignoring USP (having the stack pointer in two locations causes trouble
50 without any significant gain). */
52 /* Locations need to match <include/asm/arch/ptrace.h>. */
53 static int cris_regmap
[] = {
56 9*4, 10*4, 11*4, 12*4,
57 13*4, 14*4, 24*4, 15*4,
67 30*4, 31*4, 32*4, 33*4,
68 34*4, 35*4, 36*4, 37*4,
73 static const unsigned short cris_breakpoint
= 0xe938;
74 #define cris_breakpoint_len 2
76 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
78 static const gdb_byte
*
79 cris_sw_breakpoint_from_kind (int kind
, int *size
)
81 *size
= cris_breakpoint_len
;
82 return (const gdb_byte
*) &cris_breakpoint
;
86 cris_breakpoint_at (CORE_ADDR where
)
90 the_target
->read_memory (where
, (unsigned char *) &insn
,
92 if (insn
== cris_breakpoint
)
95 /* If necessary, recognize more trap instructions here. GDB only uses the
101 cris_write_data_breakpoint (struct regcache
*regcache
,
102 int bp
, unsigned long start
, unsigned long end
)
107 supply_register_by_name (regcache
, "s3", &start
);
108 supply_register_by_name (regcache
, "s4", &end
);
111 supply_register_by_name (regcache
, "s5", &start
);
112 supply_register_by_name (regcache
, "s6", &end
);
115 supply_register_by_name (regcache
, "s7", &start
);
116 supply_register_by_name (regcache
, "s8", &end
);
119 supply_register_by_name (regcache
, "s9", &start
);
120 supply_register_by_name (regcache
, "s10", &end
);
123 supply_register_by_name (regcache
, "s11", &start
);
124 supply_register_by_name (regcache
, "s12", &end
);
127 supply_register_by_name (regcache
, "s13", &start
);
128 supply_register_by_name (regcache
, "s14", &end
);
134 cris_supports_z_point_type (char z_type
)
138 case Z_PACKET_WRITE_WP
:
139 case Z_PACKET_READ_WP
:
140 case Z_PACKET_ACCESS_WP
:
148 cris_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
149 int len
, struct raw_breakpoint
*bp
)
152 unsigned long bp_ctrl
;
153 unsigned long start
, end
;
155 struct regcache
*regcache
;
157 regcache
= get_thread_regcache (current_thread
, 1);
159 /* Read watchpoints are set as access watchpoints, because of GDB's
160 inability to deal with pure read watchpoints. */
161 if (type
== raw_bkpt_type_read_wp
)
162 type
= raw_bkpt_type_access_wp
;
164 /* Get the configuration register. */
165 collect_register_by_name (regcache
, "s0", &bp_ctrl
);
167 /* The watchpoint allocation scheme is the simplest possible.
168 For example, if a region is watched for read and
169 a write watch is requested, a new watchpoint will
170 be used. Also, if a watch for a region that is already
171 covered by one or more existing watchpoints, a new
172 watchpoint will be used. */
174 /* First, find a free data watchpoint. */
175 for (bp
= 0; bp
< 6; bp
++)
177 /* Each data watchpoint's control registers occupy 2 bits
178 (hence the 3), starting at bit 2 for D0 (hence the 2)
179 with 4 bits between for each watchpoint (yes, the 4). */
180 if (!(bp_ctrl
& (0x3 << (2 + (bp
* 4)))))
186 /* We're out of watchpoints. */
190 /* Configure the control register first. */
191 if (type
== raw_bkpt_type_read_wp
|| type
== raw_bkpt_type_access_wp
)
193 /* Trigger on read. */
194 bp_ctrl
|= (1 << (2 + bp
* 4));
196 if (type
== raw_bkpt_type_write_wp
|| type
== raw_bkpt_type_access_wp
)
198 /* Trigger on write. */
199 bp_ctrl
|= (2 << (2 + bp
* 4));
202 /* Setup the configuration register. */
203 supply_register_by_name (regcache
, "s0", &bp_ctrl
);
205 /* Setup the range. */
207 end
= addr
+ len
- 1;
209 /* Configure the watchpoint register. */
210 cris_write_data_breakpoint (regcache
, bp
, start
, end
);
212 collect_register_by_name (regcache
, "ccs", &ccs
);
213 /* Set the S1 flag to enable watchpoints. */
215 supply_register_by_name (regcache
, "ccs", &ccs
);
221 cris_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
, int len
,
222 struct raw_breakpoint
*bp
)
225 unsigned long bp_ctrl
;
226 unsigned long start
, end
;
227 struct regcache
*regcache
;
228 unsigned long bp_d_regs
[12];
230 regcache
= get_thread_regcache (current_thread
, 1);
232 /* Read watchpoints are set as access watchpoints, because of GDB's
233 inability to deal with pure read watchpoints. */
234 if (type
== raw_bkpt_type_read_wp
)
235 type
= raw_bkpt_type_access_wp
;
237 /* Get the configuration register. */
238 collect_register_by_name (regcache
, "s0", &bp_ctrl
);
240 /* Try to find a watchpoint that is configured for the
241 specified range, then check that read/write also matches. */
243 /* Ugly pointer arithmetic, since I cannot rely on a
244 single switch (addr) as there may be several watchpoints with
245 the same start address for example. */
247 /* Get all range registers to simplify search. */
248 collect_register_by_name (regcache
, "s3", &bp_d_regs
[0]);
249 collect_register_by_name (regcache
, "s4", &bp_d_regs
[1]);
250 collect_register_by_name (regcache
, "s5", &bp_d_regs
[2]);
251 collect_register_by_name (regcache
, "s6", &bp_d_regs
[3]);
252 collect_register_by_name (regcache
, "s7", &bp_d_regs
[4]);
253 collect_register_by_name (regcache
, "s8", &bp_d_regs
[5]);
254 collect_register_by_name (regcache
, "s9", &bp_d_regs
[6]);
255 collect_register_by_name (regcache
, "s10", &bp_d_regs
[7]);
256 collect_register_by_name (regcache
, "s11", &bp_d_regs
[8]);
257 collect_register_by_name (regcache
, "s12", &bp_d_regs
[9]);
258 collect_register_by_name (regcache
, "s13", &bp_d_regs
[10]);
259 collect_register_by_name (regcache
, "s14", &bp_d_regs
[11]);
261 for (bp
= 0; bp
< 6; bp
++)
263 if (bp_d_regs
[bp
* 2] == addr
264 && bp_d_regs
[bp
* 2 + 1] == (addr
+ len
- 1)) {
265 /* Matching range. */
266 int bitpos
= 2 + bp
* 4;
269 /* Read/write bits for this BP. */
270 rw_bits
= (bp_ctrl
& (0x3 << bitpos
)) >> bitpos
;
272 if ((type
== raw_bkpt_type_read_wp
&& rw_bits
== 0x1)
273 || (type
== raw_bkpt_type_write_wp
&& rw_bits
== 0x2)
274 || (type
== raw_bkpt_type_access_wp
&& rw_bits
== 0x3))
276 /* Read/write matched. */
284 /* No watchpoint matched. */
288 /* Found a matching watchpoint. Now, deconfigure it by
289 both disabling read/write in bp_ctrl and zeroing its
290 start/end addresses. */
291 bp_ctrl
&= ~(3 << (2 + (bp
* 4)));
292 /* Setup the configuration register. */
293 supply_register_by_name (regcache
, "s0", &bp_ctrl
);
296 /* Configure the watchpoint register. */
297 cris_write_data_breakpoint (regcache
, bp
, start
, end
);
299 /* Note that we don't clear the S1 flag here. It's done when continuing. */
304 cris_stopped_by_watchpoint (void)
307 struct regcache
*regcache
= get_thread_regcache (current_thread
, 1);
309 collect_register_by_name (regcache
, "exs", &exs
);
311 return (((exs
& 0xff00) >> 8) == 0xc);
315 cris_stopped_data_address (void)
318 struct regcache
*regcache
= get_thread_regcache (current_thread
, 1);
320 collect_register_by_name (regcache
, "eda", &eda
);
322 /* FIXME: Possibly adjust to match watched range. */
327 ps_get_thread_area (struct ps_prochandle
*ph
,
328 lwpid_t lwpid
, int idx
, void **base
)
330 if (ptrace (PTRACE_GET_THREAD_AREA
, lwpid
, NULL
, base
) != 0)
333 /* IDX is the bias from the thread pointer to the beginning of the
334 thread descriptor. It has to be subtracted due to implementation
335 quirks in libthread_db. */
336 *base
= (void *) ((char *) *base
- idx
);
341 cris_fill_gregset (struct regcache
*regcache
, void *buf
)
345 for (i
= 0; i
< cris_num_regs
; i
++)
347 if (cris_regmap
[i
] != -1)
348 collect_register (regcache
, i
, ((char *) buf
) + cris_regmap
[i
]);
353 cris_store_gregset (struct regcache
*regcache
, const void *buf
)
357 for (i
= 0; i
< cris_num_regs
; i
++)
359 if (cris_regmap
[i
] != -1)
360 supply_register (regcache
, i
, ((char *) buf
) + cris_regmap
[i
]);
365 crisv32_target::low_arch_setup ()
367 current_process ()->tdesc
= tdesc_crisv32
;
370 /* Support for hardware single step. */
373 cris_supports_hardware_single_step (void)
378 static struct regset_info cris_regsets
[] = {
379 { PTRACE_GETREGS
, PTRACE_SETREGS
, 0, cris_num_regs
* 4,
380 GENERAL_REGS
, cris_fill_gregset
, cris_store_gregset
},
385 static struct regsets_info cris_regsets_info
=
387 cris_regsets
, /* regsets */
389 NULL
, /* disabled_regsets */
392 static struct usrregs_info cris_usrregs_info
=
398 static struct regs_info regs_info
=
400 NULL
, /* regset_bitmap */
405 static const struct regs_info
*
406 cris_regs_info (void)
411 struct linux_target_ops the_low_target
= {
415 NULL
, /* fetch_register */
418 NULL
, /* breakpoint_kind_from_pc */
419 cris_sw_breakpoint_from_kind
,
420 NULL
, /* get_next_pcs */
423 cris_supports_z_point_type
,
426 cris_stopped_by_watchpoint
,
427 cris_stopped_data_address
,
428 NULL
, /* collect_ptrace_register */
429 NULL
, /* supply_ptrace_register */
430 NULL
, /* siginfo_fixup */
431 NULL
, /* new_process */
432 NULL
, /* delete_process */
433 NULL
, /* new_thread */
434 NULL
, /* delete_thread */
436 NULL
, /* prepare_to_resume */
437 NULL
, /* process_qsupported */
438 NULL
, /* supports_tracepoints */
439 NULL
, /* get_thread_area */
440 NULL
, /* install_fast_tracepoint_jump_pad */
442 NULL
, /* get_min_fast_tracepoint_insn_len */
443 NULL
, /* supports_range_stepping */
444 NULL
, /* breakpoint_kind_from_current_state */
445 cris_supports_hardware_single_step
,
448 /* The linux target ops object. */
450 linux_process_target
*the_linux_target
= &the_crisv32_target
;
453 initialize_low_arch (void)
455 init_registers_crisv32 ();
457 initialize_regsets_info (&cris_regsets_info
);