1 /* GNU/Linux/PowerPC specific low level interface, for the remote server for
3 Copyright (C) 1995-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "linux-low.h"
23 #include "elf/common.h"
26 #include <asm/ptrace.h>
28 #include "arch/ppc-linux-common.h"
29 #include "arch/ppc-linux-tdesc.h"
30 #include "nat/ppc-linux.h"
31 #include "nat/linux-ptrace.h"
32 #include "linux-ppc-tdesc-init.h"
34 #include "tracepoint.h"
36 #define PPC_FIELD(value, from, len) \
37 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
38 #define PPC_SEXT(v, bs) \
39 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
40 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
41 - ((CORE_ADDR) 1 << ((bs) - 1)))
42 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
43 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
44 #define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
45 #define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
47 /* Linux target op definitions for the PowerPC architecture. */
49 class ppc_target
: public linux_process_target
53 const regs_info
*get_regs_info () override
;
57 void low_arch_setup () override
;
59 bool low_cannot_fetch_register (int regno
) override
;
61 bool low_cannot_store_register (int regno
) override
;
64 /* The singleton target ops object. */
66 static ppc_target the_ppc_target
;
68 /* Holds the AT_HWCAP auxv entry. */
70 static unsigned long ppc_hwcap
;
72 /* Holds the AT_HWCAP2 auxv entry. */
74 static unsigned long ppc_hwcap2
;
77 #define ppc_num_regs 73
80 /* We use a constant for FPSCR instead of PT_FPSCR, because
81 many shipped PPC64 kernels had the wrong value in ptrace.h. */
82 static int ppc_regmap
[] =
83 {PT_R0
* 8, PT_R1
* 8, PT_R2
* 8, PT_R3
* 8,
84 PT_R4
* 8, PT_R5
* 8, PT_R6
* 8, PT_R7
* 8,
85 PT_R8
* 8, PT_R9
* 8, PT_R10
* 8, PT_R11
* 8,
86 PT_R12
* 8, PT_R13
* 8, PT_R14
* 8, PT_R15
* 8,
87 PT_R16
* 8, PT_R17
* 8, PT_R18
* 8, PT_R19
* 8,
88 PT_R20
* 8, PT_R21
* 8, PT_R22
* 8, PT_R23
* 8,
89 PT_R24
* 8, PT_R25
* 8, PT_R26
* 8, PT_R27
* 8,
90 PT_R28
* 8, PT_R29
* 8, PT_R30
* 8, PT_R31
* 8,
91 PT_FPR0
*8, PT_FPR0
*8 + 8, PT_FPR0
*8+16, PT_FPR0
*8+24,
92 PT_FPR0
*8+32, PT_FPR0
*8+40, PT_FPR0
*8+48, PT_FPR0
*8+56,
93 PT_FPR0
*8+64, PT_FPR0
*8+72, PT_FPR0
*8+80, PT_FPR0
*8+88,
94 PT_FPR0
*8+96, PT_FPR0
*8+104, PT_FPR0
*8+112, PT_FPR0
*8+120,
95 PT_FPR0
*8+128, PT_FPR0
*8+136, PT_FPR0
*8+144, PT_FPR0
*8+152,
96 PT_FPR0
*8+160, PT_FPR0
*8+168, PT_FPR0
*8+176, PT_FPR0
*8+184,
97 PT_FPR0
*8+192, PT_FPR0
*8+200, PT_FPR0
*8+208, PT_FPR0
*8+216,
98 PT_FPR0
*8+224, PT_FPR0
*8+232, PT_FPR0
*8+240, PT_FPR0
*8+248,
99 PT_NIP
* 8, PT_MSR
* 8, PT_CCR
* 8, PT_LNK
* 8,
100 PT_CTR
* 8, PT_XER
* 8, PT_FPR0
*8 + 256,
101 PT_ORIG_R3
* 8, PT_TRAP
* 8 };
103 /* Currently, don't check/send MQ. */
104 static int ppc_regmap
[] =
105 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
106 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
107 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
108 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
109 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
110 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
111 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
112 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
113 PT_FPR0
*4, PT_FPR0
*4 + 8, PT_FPR0
*4+16, PT_FPR0
*4+24,
114 PT_FPR0
*4+32, PT_FPR0
*4+40, PT_FPR0
*4+48, PT_FPR0
*4+56,
115 PT_FPR0
*4+64, PT_FPR0
*4+72, PT_FPR0
*4+80, PT_FPR0
*4+88,
116 PT_FPR0
*4+96, PT_FPR0
*4+104, PT_FPR0
*4+112, PT_FPR0
*4+120,
117 PT_FPR0
*4+128, PT_FPR0
*4+136, PT_FPR0
*4+144, PT_FPR0
*4+152,
118 PT_FPR0
*4+160, PT_FPR0
*4+168, PT_FPR0
*4+176, PT_FPR0
*4+184,
119 PT_FPR0
*4+192, PT_FPR0
*4+200, PT_FPR0
*4+208, PT_FPR0
*4+216,
120 PT_FPR0
*4+224, PT_FPR0
*4+232, PT_FPR0
*4+240, PT_FPR0
*4+248,
121 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
122 PT_CTR
* 4, PT_XER
* 4, PT_FPSCR
* 4,
123 PT_ORIG_R3
* 4, PT_TRAP
* 4
126 static int ppc_regmap_e500
[] =
127 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
128 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
129 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
130 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
131 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
132 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
133 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
134 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
143 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
144 PT_CTR
* 4, PT_XER
* 4, -1,
145 PT_ORIG_R3
* 4, PT_TRAP
* 4
149 /* Check whether the kernel provides a register set with number
150 REGSET_ID of size REGSETSIZE for process/thread TID. */
153 ppc_check_regset (int tid
, int regset_id
, int regsetsize
)
155 void *buf
= alloca (regsetsize
);
159 iov
.iov_len
= regsetsize
;
161 if (ptrace (PTRACE_GETREGSET
, tid
, regset_id
, &iov
) >= 0
168 ppc_target::low_cannot_store_register (int regno
)
170 const struct target_desc
*tdesc
= current_process ()->tdesc
;
172 #ifndef __powerpc64__
173 /* Some kernels do not allow us to store fpscr. */
174 if (!(ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
175 && regno
== find_regno (tdesc
, "fpscr"))
179 /* Some kernels do not allow us to store orig_r3 or trap. */
180 if (regno
== find_regno (tdesc
, "orig_r3")
181 || regno
== find_regno (tdesc
, "trap"))
188 ppc_target::low_cannot_fetch_register (int regno
)
194 ppc_collect_ptrace_register (struct regcache
*regcache
, int regno
, char *buf
)
196 memset (buf
, 0, sizeof (long));
198 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
200 /* Little-endian values always sit at the left end of the buffer. */
201 collect_register (regcache
, regno
, buf
);
203 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
205 /* Big-endian values sit at the right end of the buffer. In case of
206 registers whose sizes are smaller than sizeof (long), we must use a
207 padding to access them correctly. */
208 int size
= register_size (regcache
->tdesc
, regno
);
210 if (size
< sizeof (long))
211 collect_register (regcache
, regno
, buf
+ sizeof (long) - size
);
213 collect_register (regcache
, regno
, buf
);
216 perror_with_name ("Unexpected byte order");
220 ppc_supply_ptrace_register (struct regcache
*regcache
,
221 int regno
, const char *buf
)
223 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
225 /* Little-endian values always sit at the left end of the buffer. */
226 supply_register (regcache
, regno
, buf
);
228 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
230 /* Big-endian values sit at the right end of the buffer. In case of
231 registers whose sizes are smaller than sizeof (long), we must use a
232 padding to access them correctly. */
233 int size
= register_size (regcache
->tdesc
, regno
);
235 if (size
< sizeof (long))
236 supply_register (regcache
, regno
, buf
+ sizeof (long) - size
);
238 supply_register (regcache
, regno
, buf
);
241 perror_with_name ("Unexpected byte order");
245 ppc_get_pc (struct regcache
*regcache
)
247 if (register_size (regcache
->tdesc
, 0) == 4)
250 collect_register_by_name (regcache
, "pc", &pc
);
251 return (CORE_ADDR
) pc
;
256 collect_register_by_name (regcache
, "pc", &pc
);
257 return (CORE_ADDR
) pc
;
262 ppc_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
264 if (register_size (regcache
->tdesc
, 0) == 4)
266 unsigned int newpc
= pc
;
267 supply_register_by_name (regcache
, "pc", &newpc
);
271 unsigned long newpc
= pc
;
272 supply_register_by_name (regcache
, "pc", &newpc
);
276 #ifndef __powerpc64__
277 static int ppc_regmap_adjusted
;
281 /* Correct in either endianness.
282 This instruction is "twge r2, r2", which GDB uses as a software
284 static const unsigned int ppc_breakpoint
= 0x7d821008;
285 #define ppc_breakpoint_len 4
287 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
289 static const gdb_byte
*
290 ppc_sw_breakpoint_from_kind (int kind
, int *size
)
292 *size
= ppc_breakpoint_len
;
293 return (const gdb_byte
*) &ppc_breakpoint
;
297 ppc_breakpoint_at (CORE_ADDR where
)
301 the_target
->read_memory (where
, (unsigned char *) &insn
, 4);
302 if (insn
== ppc_breakpoint
)
304 /* If necessary, recognize more trap instructions here. GDB only uses
310 /* Implement supports_z_point_type target-ops.
311 Returns true if type Z_TYPE breakpoint is supported.
313 Handling software breakpoint at server side, so tracepoints
314 and breakpoints can be inserted at the same location. */
317 ppc_supports_z_point_type (char z_type
)
324 case Z_PACKET_WRITE_WP
:
325 case Z_PACKET_ACCESS_WP
:
331 /* Implement insert_point target-ops.
332 Returns 0 on success, -1 on failure and 1 on unsupported. */
335 ppc_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
336 int size
, struct raw_breakpoint
*bp
)
340 case raw_bkpt_type_sw
:
341 return insert_memory_breakpoint (bp
);
343 case raw_bkpt_type_hw
:
344 case raw_bkpt_type_write_wp
:
345 case raw_bkpt_type_access_wp
:
352 /* Implement remove_point target-ops.
353 Returns 0 on success, -1 on failure and 1 on unsupported. */
356 ppc_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
357 int size
, struct raw_breakpoint
*bp
)
361 case raw_bkpt_type_sw
:
362 return remove_memory_breakpoint (bp
);
364 case raw_bkpt_type_hw
:
365 case raw_bkpt_type_write_wp
:
366 case raw_bkpt_type_access_wp
:
373 /* Provide only a fill function for the general register set. ps_lgetregs
374 will use this for NPTL support. */
376 static void ppc_fill_gregset (struct regcache
*regcache
, void *buf
)
380 for (i
= 0; i
< 32; i
++)
381 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
383 for (i
= 64; i
< 70; i
++)
384 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
386 for (i
= 71; i
< 73; i
++)
387 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
390 /* Program Priority Register regset fill function. */
393 ppc_fill_pprregset (struct regcache
*regcache
, void *buf
)
395 char *ppr
= (char *) buf
;
397 collect_register_by_name (regcache
, "ppr", ppr
);
400 /* Program Priority Register regset store function. */
403 ppc_store_pprregset (struct regcache
*regcache
, const void *buf
)
405 const char *ppr
= (const char *) buf
;
407 supply_register_by_name (regcache
, "ppr", ppr
);
410 /* Data Stream Control Register regset fill function. */
413 ppc_fill_dscrregset (struct regcache
*regcache
, void *buf
)
415 char *dscr
= (char *) buf
;
417 collect_register_by_name (regcache
, "dscr", dscr
);
420 /* Data Stream Control Register regset store function. */
423 ppc_store_dscrregset (struct regcache
*regcache
, const void *buf
)
425 const char *dscr
= (const char *) buf
;
427 supply_register_by_name (regcache
, "dscr", dscr
);
430 /* Target Address Register regset fill function. */
433 ppc_fill_tarregset (struct regcache
*regcache
, void *buf
)
435 char *tar
= (char *) buf
;
437 collect_register_by_name (regcache
, "tar", tar
);
440 /* Target Address Register regset store function. */
443 ppc_store_tarregset (struct regcache
*regcache
, const void *buf
)
445 const char *tar
= (const char *) buf
;
447 supply_register_by_name (regcache
, "tar", tar
);
450 /* Event-Based Branching regset store function. Unless the inferior
451 has a perf event open, ptrace can return in error when reading and
452 writing to the regset, with ENODATA. For reading, the registers
453 will correctly show as unavailable. For writing, gdbserver
454 currently only caches any register writes from P and G packets and
455 the stub always tries to write all the regsets when resuming the
456 inferior, which would result in frequent warnings. For this
457 reason, we don't define a fill function. This also means that the
458 client-side regcache will be dirty if the user tries to write to
459 the EBB registers. G packets that the client sends to write to
460 unrelated registers will also include data for EBB registers, even
461 if they are unavailable. */
464 ppc_store_ebbregset (struct regcache
*regcache
, const void *buf
)
466 const char *regset
= (const char *) buf
;
468 /* The order in the kernel regset is: EBBRR, EBBHR, BESCR. In the
469 .dat file is BESCR, EBBHR, EBBRR. */
470 supply_register_by_name (regcache
, "ebbrr", ®set
[0]);
471 supply_register_by_name (regcache
, "ebbhr", ®set
[8]);
472 supply_register_by_name (regcache
, "bescr", ®set
[16]);
475 /* Performance Monitoring Unit regset fill function. */
478 ppc_fill_pmuregset (struct regcache
*regcache
, void *buf
)
480 char *regset
= (char *) buf
;
482 /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0.
483 In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */
484 collect_register_by_name (regcache
, "siar", ®set
[0]);
485 collect_register_by_name (regcache
, "sdar", ®set
[8]);
486 collect_register_by_name (regcache
, "sier", ®set
[16]);
487 collect_register_by_name (regcache
, "mmcr2", ®set
[24]);
488 collect_register_by_name (regcache
, "mmcr0", ®set
[32]);
491 /* Performance Monitoring Unit regset store function. */
494 ppc_store_pmuregset (struct regcache
*regcache
, const void *buf
)
496 const char *regset
= (const char *) buf
;
498 supply_register_by_name (regcache
, "siar", ®set
[0]);
499 supply_register_by_name (regcache
, "sdar", ®set
[8]);
500 supply_register_by_name (regcache
, "sier", ®set
[16]);
501 supply_register_by_name (regcache
, "mmcr2", ®set
[24]);
502 supply_register_by_name (regcache
, "mmcr0", ®set
[32]);
505 /* Hardware Transactional Memory special-purpose register regset fill
509 ppc_fill_tm_sprregset (struct regcache
*regcache
, void *buf
)
512 char *regset
= (char *) buf
;
514 base
= find_regno (regcache
->tdesc
, "tfhar");
515 for (i
= 0; i
< 3; i
++)
516 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
519 /* Hardware Transactional Memory special-purpose register regset store
523 ppc_store_tm_sprregset (struct regcache
*regcache
, const void *buf
)
526 const char *regset
= (const char *) buf
;
528 base
= find_regno (regcache
->tdesc
, "tfhar");
529 for (i
= 0; i
< 3; i
++)
530 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
533 /* For the same reasons as the EBB regset, none of the HTM
534 checkpointed regsets have a fill function. These registers are
535 only available if the inferior is in a transaction. */
537 /* Hardware Transactional Memory checkpointed general-purpose regset
541 ppc_store_tm_cgprregset (struct regcache
*regcache
, const void *buf
)
543 int i
, base
, size
, endian_offset
;
544 const char *regset
= (const char *) buf
;
546 base
= find_regno (regcache
->tdesc
, "cr0");
547 size
= register_size (regcache
->tdesc
, base
);
549 gdb_assert (size
== 4 || size
== 8);
551 for (i
= 0; i
< 32; i
++)
552 supply_register (regcache
, base
+ i
, ®set
[i
* size
]);
556 if ((size
== 8) && (__BYTE_ORDER
== __BIG_ENDIAN
))
559 supply_register_by_name (regcache
, "ccr",
560 ®set
[PT_CCR
* size
+ endian_offset
]);
562 supply_register_by_name (regcache
, "cxer",
563 ®set
[PT_XER
* size
+ endian_offset
]);
565 supply_register_by_name (regcache
, "clr", ®set
[PT_LNK
* size
]);
566 supply_register_by_name (regcache
, "cctr", ®set
[PT_CTR
* size
]);
569 /* Hardware Transactional Memory checkpointed floating-point regset
573 ppc_store_tm_cfprregset (struct regcache
*regcache
, const void *buf
)
576 const char *regset
= (const char *) buf
;
578 base
= find_regno (regcache
->tdesc
, "cf0");
580 for (i
= 0; i
< 32; i
++)
581 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
583 supply_register_by_name (regcache
, "cfpscr", ®set
[32 * 8]);
586 /* Hardware Transactional Memory checkpointed vector regset store
590 ppc_store_tm_cvrregset (struct regcache
*regcache
, const void *buf
)
593 const char *regset
= (const char *) buf
;
596 base
= find_regno (regcache
->tdesc
, "cvr0");
598 for (i
= 0; i
< 32; i
++)
599 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
601 if (__BYTE_ORDER
== __BIG_ENDIAN
)
604 supply_register_by_name (regcache
, "cvscr",
605 ®set
[32 * 16 + vscr_offset
]);
607 supply_register_by_name (regcache
, "cvrsave", ®set
[33 * 16]);
610 /* Hardware Transactional Memory checkpointed vector-scalar regset
614 ppc_store_tm_cvsxregset (struct regcache
*regcache
, const void *buf
)
617 const char *regset
= (const char *) buf
;
619 base
= find_regno (regcache
->tdesc
, "cvs0h");
620 for (i
= 0; i
< 32; i
++)
621 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
624 /* Hardware Transactional Memory checkpointed Program Priority
625 Register regset store function. */
628 ppc_store_tm_cpprregset (struct regcache
*regcache
, const void *buf
)
630 const char *cppr
= (const char *) buf
;
632 supply_register_by_name (regcache
, "cppr", cppr
);
635 /* Hardware Transactional Memory checkpointed Data Stream Control
636 Register regset store function. */
639 ppc_store_tm_cdscrregset (struct regcache
*regcache
, const void *buf
)
641 const char *cdscr
= (const char *) buf
;
643 supply_register_by_name (regcache
, "cdscr", cdscr
);
646 /* Hardware Transactional Memory checkpointed Target Address Register
647 regset store function. */
650 ppc_store_tm_ctarregset (struct regcache
*regcache
, const void *buf
)
652 const char *ctar
= (const char *) buf
;
654 supply_register_by_name (regcache
, "ctar", ctar
);
658 ppc_fill_vsxregset (struct regcache
*regcache
, void *buf
)
661 char *regset
= (char *) buf
;
663 base
= find_regno (regcache
->tdesc
, "vs0h");
664 for (i
= 0; i
< 32; i
++)
665 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
669 ppc_store_vsxregset (struct regcache
*regcache
, const void *buf
)
672 const char *regset
= (const char *) buf
;
674 base
= find_regno (regcache
->tdesc
, "vs0h");
675 for (i
= 0; i
< 32; i
++)
676 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
680 ppc_fill_vrregset (struct regcache
*regcache
, void *buf
)
683 char *regset
= (char *) buf
;
686 base
= find_regno (regcache
->tdesc
, "vr0");
687 for (i
= 0; i
< 32; i
++)
688 collect_register (regcache
, base
+ i
, ®set
[i
* 16]);
690 if (__BYTE_ORDER
== __BIG_ENDIAN
)
693 collect_register_by_name (regcache
, "vscr",
694 ®set
[32 * 16 + vscr_offset
]);
696 collect_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
700 ppc_store_vrregset (struct regcache
*regcache
, const void *buf
)
703 const char *regset
= (const char *) buf
;
706 base
= find_regno (regcache
->tdesc
, "vr0");
707 for (i
= 0; i
< 32; i
++)
708 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
710 if (__BYTE_ORDER
== __BIG_ENDIAN
)
713 supply_register_by_name (regcache
, "vscr",
714 ®set
[32 * 16 + vscr_offset
]);
715 supply_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
718 struct gdb_evrregset_t
720 unsigned long evr
[32];
721 unsigned long long acc
;
722 unsigned long spefscr
;
726 ppc_fill_evrregset (struct regcache
*regcache
, void *buf
)
729 struct gdb_evrregset_t
*regset
= (struct gdb_evrregset_t
*) buf
;
731 ev0
= find_regno (regcache
->tdesc
, "ev0h");
732 for (i
= 0; i
< 32; i
++)
733 collect_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
735 collect_register_by_name (regcache
, "acc", ®set
->acc
);
736 collect_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
740 ppc_store_evrregset (struct regcache
*regcache
, const void *buf
)
743 const struct gdb_evrregset_t
*regset
= (const struct gdb_evrregset_t
*) buf
;
745 ev0
= find_regno (regcache
->tdesc
, "ev0h");
746 for (i
= 0; i
< 32; i
++)
747 supply_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
749 supply_register_by_name (regcache
, "acc", ®set
->acc
);
750 supply_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
753 /* Support for hardware single step. */
756 ppc_supports_hardware_single_step (void)
761 static struct regset_info ppc_regsets
[] = {
762 /* List the extra register sets before GENERAL_REGS. That way we will
763 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
764 general registers. Some kernels support these, but not the newer
765 PPC_PTRACE_GETREGS. */
766 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CTAR
, 0, EXTENDED_REGS
,
767 NULL
, ppc_store_tm_ctarregset
},
768 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CDSCR
, 0, EXTENDED_REGS
,
769 NULL
, ppc_store_tm_cdscrregset
},
770 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CPPR
, 0, EXTENDED_REGS
,
771 NULL
, ppc_store_tm_cpprregset
},
772 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVSX
, 0, EXTENDED_REGS
,
773 NULL
, ppc_store_tm_cvsxregset
},
774 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVMX
, 0, EXTENDED_REGS
,
775 NULL
, ppc_store_tm_cvrregset
},
776 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CFPR
, 0, EXTENDED_REGS
,
777 NULL
, ppc_store_tm_cfprregset
},
778 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CGPR
, 0, EXTENDED_REGS
,
779 NULL
, ppc_store_tm_cgprregset
},
780 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_SPR
, 0, EXTENDED_REGS
,
781 ppc_fill_tm_sprregset
, ppc_store_tm_sprregset
},
782 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_EBB
, 0, EXTENDED_REGS
,
783 NULL
, ppc_store_ebbregset
},
784 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PMU
, 0, EXTENDED_REGS
,
785 ppc_fill_pmuregset
, ppc_store_pmuregset
},
786 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TAR
, 0, EXTENDED_REGS
,
787 ppc_fill_tarregset
, ppc_store_tarregset
},
788 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PPR
, 0, EXTENDED_REGS
,
789 ppc_fill_pprregset
, ppc_store_pprregset
},
790 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_DSCR
, 0, EXTENDED_REGS
,
791 ppc_fill_dscrregset
, ppc_store_dscrregset
},
792 { PTRACE_GETVSXREGS
, PTRACE_SETVSXREGS
, 0, 0, EXTENDED_REGS
,
793 ppc_fill_vsxregset
, ppc_store_vsxregset
},
794 { PTRACE_GETVRREGS
, PTRACE_SETVRREGS
, 0, 0, EXTENDED_REGS
,
795 ppc_fill_vrregset
, ppc_store_vrregset
},
796 { PTRACE_GETEVRREGS
, PTRACE_SETEVRREGS
, 0, 0, EXTENDED_REGS
,
797 ppc_fill_evrregset
, ppc_store_evrregset
},
798 { 0, 0, 0, 0, GENERAL_REGS
, ppc_fill_gregset
, NULL
},
802 static struct usrregs_info ppc_usrregs_info
=
808 static struct regsets_info ppc_regsets_info
=
810 ppc_regsets
, /* regsets */
812 NULL
, /* disabled_regsets */
815 static struct regs_info myregs_info
=
817 NULL
, /* regset_bitmap */
823 ppc_target::get_regs_info ()
829 ppc_target::low_arch_setup ()
831 const struct target_desc
*tdesc
;
832 struct regset_info
*regset
;
833 struct ppc_linux_features features
= ppc_linux_no_features
;
835 int tid
= lwpid_of (current_thread
);
837 features
.wordsize
= ppc_linux_target_wordsize (tid
);
839 if (features
.wordsize
== 4)
840 tdesc
= tdesc_powerpc_32l
;
842 tdesc
= tdesc_powerpc_64l
;
844 current_process ()->tdesc
= tdesc
;
846 /* The value of current_process ()->tdesc needs to be set for this
848 ppc_hwcap
= linux_get_hwcap (features
.wordsize
);
849 ppc_hwcap2
= linux_get_hwcap2 (features
.wordsize
);
851 features
.isa205
= ppc_linux_has_isa205 (ppc_hwcap
);
853 if (ppc_hwcap
& PPC_FEATURE_HAS_VSX
)
856 if (ppc_hwcap
& PPC_FEATURE_HAS_ALTIVEC
)
857 features
.altivec
= true;
859 if ((ppc_hwcap2
& PPC_FEATURE2_DSCR
)
860 && ppc_check_regset (tid
, NT_PPC_DSCR
, PPC_LINUX_SIZEOF_DSCRREGSET
)
861 && ppc_check_regset (tid
, NT_PPC_PPR
, PPC_LINUX_SIZEOF_PPRREGSET
))
863 features
.ppr_dscr
= true;
864 if ((ppc_hwcap2
& PPC_FEATURE2_ARCH_2_07
)
865 && (ppc_hwcap2
& PPC_FEATURE2_TAR
)
866 && (ppc_hwcap2
& PPC_FEATURE2_EBB
)
867 && ppc_check_regset (tid
, NT_PPC_TAR
,
868 PPC_LINUX_SIZEOF_TARREGSET
)
869 && ppc_check_regset (tid
, NT_PPC_EBB
,
870 PPC_LINUX_SIZEOF_EBBREGSET
)
871 && ppc_check_regset (tid
, NT_PPC_PMU
,
872 PPC_LINUX_SIZEOF_PMUREGSET
))
874 features
.isa207
= true;
875 if ((ppc_hwcap2
& PPC_FEATURE2_HTM
)
876 && ppc_check_regset (tid
, NT_PPC_TM_SPR
,
877 PPC_LINUX_SIZEOF_TM_SPRREGSET
))
882 tdesc
= ppc_linux_match_description (features
);
884 /* On 32-bit machines, check for SPE registers.
885 Set the low target's regmap field as appropriately. */
886 #ifndef __powerpc64__
887 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
888 tdesc
= tdesc_powerpc_e500l
;
890 if (!ppc_regmap_adjusted
)
892 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
893 ppc_usrregs_info
.regmap
= ppc_regmap_e500
;
895 /* If the FPSCR is 64-bit wide, we need to fetch the whole
896 64-bit slot and not just its second word. The PT_FPSCR
897 supplied in a 32-bit GDB compilation doesn't reflect
899 if (register_size (tdesc
, 70) == 8)
900 ppc_regmap
[70] = (48 + 2*32) * sizeof (long);
902 ppc_regmap_adjusted
= 1;
906 current_process ()->tdesc
= tdesc
;
908 for (regset
= ppc_regsets
; regset
->size
>= 0; regset
++)
909 switch (regset
->get_request
)
911 case PTRACE_GETVRREGS
:
912 regset
->size
= features
.altivec
? PPC_LINUX_SIZEOF_VRREGSET
: 0;
914 case PTRACE_GETVSXREGS
:
915 regset
->size
= features
.vsx
? PPC_LINUX_SIZEOF_VSXREGSET
: 0;
917 case PTRACE_GETEVRREGS
:
918 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
919 regset
->size
= 32 * 4 + 8 + 4;
923 case PTRACE_GETREGSET
:
924 switch (regset
->nt_type
)
927 regset
->size
= (features
.ppr_dscr
?
928 PPC_LINUX_SIZEOF_PPRREGSET
: 0);
931 regset
->size
= (features
.ppr_dscr
?
932 PPC_LINUX_SIZEOF_DSCRREGSET
: 0);
935 regset
->size
= (features
.isa207
?
936 PPC_LINUX_SIZEOF_TARREGSET
: 0);
939 regset
->size
= (features
.isa207
?
940 PPC_LINUX_SIZEOF_EBBREGSET
: 0);
943 regset
->size
= (features
.isa207
?
944 PPC_LINUX_SIZEOF_PMUREGSET
: 0);
947 regset
->size
= (features
.htm
?
948 PPC_LINUX_SIZEOF_TM_SPRREGSET
: 0);
951 if (features
.wordsize
== 4)
952 regset
->size
= (features
.htm
?
953 PPC32_LINUX_SIZEOF_CGPRREGSET
: 0);
955 regset
->size
= (features
.htm
?
956 PPC64_LINUX_SIZEOF_CGPRREGSET
: 0);
959 regset
->size
= (features
.htm
?
960 PPC_LINUX_SIZEOF_CFPRREGSET
: 0);
963 regset
->size
= (features
.htm
?
964 PPC_LINUX_SIZEOF_CVMXREGSET
: 0);
967 regset
->size
= (features
.htm
?
968 PPC_LINUX_SIZEOF_CVSXREGSET
: 0);
971 regset
->size
= (features
.htm
?
972 PPC_LINUX_SIZEOF_CPPRREGSET
: 0);
974 case NT_PPC_TM_CDSCR
:
975 regset
->size
= (features
.htm
?
976 PPC_LINUX_SIZEOF_CDSCRREGSET
: 0);
979 regset
->size
= (features
.htm
?
980 PPC_LINUX_SIZEOF_CTARREGSET
: 0);
991 /* Implementation of linux_target_ops method "supports_tracepoints". */
994 ppc_supports_tracepoints (void)
999 /* Get the thread area address. This is used to recognize which
1000 thread is which when tracing with the in-process agent library. We
1001 don't read anything from the address, and treat it as opaque; it's
1002 the address itself that we assume is unique per-thread. */
1005 ppc_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
1007 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
1008 struct thread_info
*thr
= get_lwp_thread (lwp
);
1009 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
1012 #ifdef __powerpc64__
1013 if (register_size (regcache
->tdesc
, 0) == 8)
1014 collect_register_by_name (regcache
, "r13", &tp
);
1017 collect_register_by_name (regcache
, "r2", &tp
);
1024 #ifdef __powerpc64__
1026 /* Older glibc doesn't provide this. */
1028 #ifndef EF_PPC64_ABI
1029 #define EF_PPC64_ABI 3
1032 /* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
1036 is_elfv2_inferior (void)
1038 /* To be used as fallback if we're unable to determine the right result -
1039 assume inferior uses the same ABI as gdbserver. */
1041 const int def_res
= 1;
1043 const int def_res
= 0;
1048 const struct target_desc
*tdesc
= current_process ()->tdesc
;
1049 int wordsize
= register_size (tdesc
, 0);
1051 if (!linux_get_auxv (wordsize
, AT_PHDR
, &phdr
))
1054 /* Assume ELF header is at the beginning of the page where program headers
1055 are located. If it doesn't look like one, bail. */
1057 read_inferior_memory (phdr
& ~0xfff, (unsigned char *) &ehdr
, sizeof ehdr
);
1058 if (memcmp(ehdr
.e_ident
, ELFMAG
, SELFMAG
))
1061 return (ehdr
.e_flags
& EF_PPC64_ABI
) == 2;
1066 /* Generate a ds-form instruction in BUF and return the number of bytes written
1069 | OPCD | RST | RA | DS |XO| */
1071 __attribute__((unused
)) /* Maybe unused due to conditional compilation. */
1073 gen_ds_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int ds
, int xo
)
1077 gdb_assert ((opcd
& ~0x3f) == 0);
1078 gdb_assert ((rst
& ~0x1f) == 0);
1079 gdb_assert ((ra
& ~0x1f) == 0);
1080 gdb_assert ((xo
& ~0x3) == 0);
1082 insn
= (rst
<< 21) | (ra
<< 16) | (ds
& 0xfffc) | (xo
& 0x3);
1083 *buf
= (opcd
<< 26) | insn
;
1087 /* Followings are frequently used ds-form instructions. */
1089 #define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
1090 #define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
1091 #define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
1092 #define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
1094 /* Generate a d-form instruction in BUF.
1097 | OPCD | RST | RA | D | */
1100 gen_d_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int si
)
1104 gdb_assert ((opcd
& ~0x3f) == 0);
1105 gdb_assert ((rst
& ~0x1f) == 0);
1106 gdb_assert ((ra
& ~0x1f) == 0);
1108 insn
= (rst
<< 21) | (ra
<< 16) | (si
& 0xffff);
1109 *buf
= (opcd
<< 26) | insn
;
1113 /* Followings are frequently used d-form instructions. */
1115 #define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
1116 #define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
1117 #define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
1118 #define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
1119 #define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
1120 #define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
1121 #define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
1122 #define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
1123 #define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
1125 /* Generate a xfx-form instruction in BUF and return the number of bytes
1129 | OPCD | RST | RI | XO |/| */
1132 gen_xfx_form (uint32_t *buf
, int opcd
, int rst
, int ri
, int xo
)
1135 unsigned int n
= ((ri
& 0x1f) << 5) | ((ri
>> 5) & 0x1f);
1137 gdb_assert ((opcd
& ~0x3f) == 0);
1138 gdb_assert ((rst
& ~0x1f) == 0);
1139 gdb_assert ((xo
& ~0x3ff) == 0);
1141 insn
= (rst
<< 21) | (n
<< 11) | (xo
<< 1);
1142 *buf
= (opcd
<< 26) | insn
;
1146 /* Followings are frequently used xfx-form instructions. */
1148 #define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
1149 #define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
1150 #define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
1151 #define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
1152 #define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
1154 #define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
1157 /* Generate a x-form instruction in BUF and return the number of bytes written.
1160 | OPCD | RST | RA | RB | XO |RC| */
1163 gen_x_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int rb
, int xo
, int rc
)
1167 gdb_assert ((opcd
& ~0x3f) == 0);
1168 gdb_assert ((rst
& ~0x1f) == 0);
1169 gdb_assert ((ra
& ~0x1f) == 0);
1170 gdb_assert ((rb
& ~0x1f) == 0);
1171 gdb_assert ((xo
& ~0x3ff) == 0);
1172 gdb_assert ((rc
& ~1) == 0);
1174 insn
= (rst
<< 21) | (ra
<< 16) | (rb
<< 11) | (xo
<< 1) | rc
;
1175 *buf
= (opcd
<< 26) | insn
;
1179 /* Followings are frequently used x-form instructions. */
1181 #define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
1182 #define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
1183 #define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
1184 #define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
1185 /* Assume bf = cr7. */
1186 #define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
1189 /* Generate a md-form instruction in BUF and return the number of bytes written.
1191 0 6 11 16 21 27 30 31 32
1192 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
1195 gen_md_form (uint32_t *buf
, int opcd
, int rs
, int ra
, int sh
, int mb
,
1199 unsigned int n
= ((mb
& 0x1f) << 1) | ((mb
>> 5) & 0x1);
1200 unsigned int sh0_4
= sh
& 0x1f;
1201 unsigned int sh5
= (sh
>> 5) & 1;
1203 gdb_assert ((opcd
& ~0x3f) == 0);
1204 gdb_assert ((rs
& ~0x1f) == 0);
1205 gdb_assert ((ra
& ~0x1f) == 0);
1206 gdb_assert ((sh
& ~0x3f) == 0);
1207 gdb_assert ((mb
& ~0x3f) == 0);
1208 gdb_assert ((xo
& ~0x7) == 0);
1209 gdb_assert ((rc
& ~0x1) == 0);
1211 insn
= (rs
<< 21) | (ra
<< 16) | (sh0_4
<< 11) | (n
<< 5)
1212 | (sh5
<< 1) | (xo
<< 2) | (rc
& 1);
1213 *buf
= (opcd
<< 26) | insn
;
1217 /* The following are frequently used md-form instructions. */
1219 #define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1220 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1221 #define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1222 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1224 /* Generate a i-form instruction in BUF and return the number of bytes written.
1227 | OPCD | LI |AA|LK| */
1230 gen_i_form (uint32_t *buf
, int opcd
, int li
, int aa
, int lk
)
1234 gdb_assert ((opcd
& ~0x3f) == 0);
1236 insn
= (li
& 0x3fffffc) | (aa
& 1) | (lk
& 1);
1237 *buf
= (opcd
<< 26) | insn
;
1241 /* The following are frequently used i-form instructions. */
1243 #define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1244 #define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1246 /* Generate a b-form instruction in BUF and return the number of bytes written.
1249 | OPCD | BO | BI | BD |AA|LK| */
1252 gen_b_form (uint32_t *buf
, int opcd
, int bo
, int bi
, int bd
,
1257 gdb_assert ((opcd
& ~0x3f) == 0);
1258 gdb_assert ((bo
& ~0x1f) == 0);
1259 gdb_assert ((bi
& ~0x1f) == 0);
1261 insn
= (bo
<< 21) | (bi
<< 16) | (bd
& 0xfffc) | (aa
& 1) | (lk
& 1);
1262 *buf
= (opcd
<< 26) | insn
;
1266 /* The following are frequently used b-form instructions. */
1267 /* Assume bi = cr7. */
1268 #define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1270 /* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1271 respectively. They are primary used for save/restore GPRs in jump-pad,
1272 not used for bytecode compiling. */
1274 #ifdef __powerpc64__
1275 #define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1276 GEN_LD (buf, rt, ra, si) : \
1277 GEN_LWZ (buf, rt, ra, si))
1278 #define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1279 GEN_STD (buf, rt, ra, si) : \
1280 GEN_STW (buf, rt, ra, si))
1282 #define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1283 #define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1286 /* Generate a sequence of instructions to load IMM in the register REG.
1287 Write the instructions in BUF and return the number of bytes written. */
1290 gen_limm (uint32_t *buf
, int reg
, uint64_t imm
, int is_64
)
1294 if ((imm
+ 32768) < 65536)
1296 /* li reg, imm[15:0] */
1297 p
+= GEN_LI (p
, reg
, imm
);
1299 else if ((imm
>> 32) == 0)
1301 /* lis reg, imm[31:16]
1302 ori reg, reg, imm[15:0]
1303 rldicl reg, reg, 0, 32 */
1304 p
+= GEN_LIS (p
, reg
, (imm
>> 16) & 0xffff);
1305 if ((imm
& 0xffff) != 0)
1306 p
+= GEN_ORI (p
, reg
, reg
, imm
& 0xffff);
1307 /* Clear upper 32-bit if sign-bit is set. */
1308 if (imm
& (1u << 31) && is_64
)
1309 p
+= GEN_RLDICL (p
, reg
, reg
, 0, 32);
1314 /* lis reg, <imm[63:48]>
1315 ori reg, reg, <imm[48:32]>
1316 rldicr reg, reg, 32, 31
1317 oris reg, reg, <imm[31:16]>
1318 ori reg, reg, <imm[15:0]> */
1319 p
+= GEN_LIS (p
, reg
, ((imm
>> 48) & 0xffff));
1320 if (((imm
>> 32) & 0xffff) != 0)
1321 p
+= GEN_ORI (p
, reg
, reg
, ((imm
>> 32) & 0xffff));
1322 p
+= GEN_RLDICR (p
, reg
, reg
, 32, 31);
1323 if (((imm
>> 16) & 0xffff) != 0)
1324 p
+= GEN_ORIS (p
, reg
, reg
, ((imm
>> 16) & 0xffff));
1325 if ((imm
& 0xffff) != 0)
1326 p
+= GEN_ORI (p
, reg
, reg
, (imm
& 0xffff));
1332 /* Generate a sequence for atomically exchange at location LOCK.
1333 This code sequence clobbers r6, r7, r8. LOCK is the location for
1334 the atomic-xchg, OLD_VALUE is expected old value stored in the
1335 location, and R_NEW is a register for the new value. */
1338 gen_atomic_xchg (uint32_t *buf
, CORE_ADDR lock
, int old_value
, int r_new
,
1341 const int r_lock
= 6;
1342 const int r_old
= 7;
1343 const int r_tmp
= 8;
1347 1: lwarx TMP, 0, LOCK
1353 p
+= gen_limm (p
, r_lock
, lock
, is_64
);
1354 p
+= gen_limm (p
, r_old
, old_value
, is_64
);
1356 p
+= GEN_LWARX (p
, r_tmp
, 0, r_lock
);
1357 p
+= GEN_CMPW (p
, r_tmp
, r_old
);
1358 p
+= GEN_BNE (p
, -8);
1359 p
+= GEN_STWCX (p
, r_new
, 0, r_lock
);
1360 p
+= GEN_BNE (p
, -16);
1365 /* Generate a sequence of instructions for calling a function
1366 at address of FN. Return the number of bytes are written in BUF. */
1369 gen_call (uint32_t *buf
, CORE_ADDR fn
, int is_64
, int is_opd
)
1373 /* Must be called by r12 for caller to calculate TOC address. */
1374 p
+= gen_limm (p
, 12, fn
, is_64
);
1377 p
+= GEN_LOAD (p
, 11, 12, 16, is_64
);
1378 p
+= GEN_LOAD (p
, 2, 12, 8, is_64
);
1379 p
+= GEN_LOAD (p
, 12, 12, 0, is_64
);
1381 p
+= GEN_MTSPR (p
, 12, 9); /* mtctr r12 */
1382 *p
++ = 0x4e800421; /* bctrl */
1387 /* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1388 of instruction. This function is used to adjust pc-relative instructions
1392 ppc_relocate_instruction (CORE_ADDR
*to
, CORE_ADDR oldloc
)
1397 read_inferior_memory (oldloc
, (unsigned char *) &insn
, 4);
1398 op6
= PPC_OP6 (insn
);
1400 if (op6
== 18 && (insn
& 2) == 0)
1402 /* branch && AA = 0 */
1403 rel
= PPC_LI (insn
);
1404 newrel
= (oldloc
- *to
) + rel
;
1406 /* Out of range. Cannot relocate instruction. */
1407 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1410 insn
= (insn
& ~0x3fffffc) | (newrel
& 0x3fffffc);
1412 else if (op6
== 16 && (insn
& 2) == 0)
1414 /* conditional branch && AA = 0 */
1416 /* If the new relocation is too big for even a 26-bit unconditional
1417 branch, there is nothing we can do. Just abort.
1419 Otherwise, if it can be fit in 16-bit conditional branch, just
1420 copy the instruction and relocate the address.
1422 If the it's big for conditional-branch (16-bit), try to invert the
1423 condition and jump with 26-bit branch. For example,
1434 After this transform, we are actually jump from *TO+4 instead of *TO,
1435 so check the relocation again because it will be 1-insn farther then
1436 before if *TO is after OLDLOC.
1439 For BDNZT (or so) is transformed from
1451 See also "BO field encodings". */
1453 rel
= PPC_BD (insn
);
1454 newrel
= (oldloc
- *to
) + rel
;
1456 if (newrel
< (1 << 15) && newrel
>= -(1 << 15))
1457 insn
= (insn
& ~0xfffc) | (newrel
& 0xfffc);
1458 else if ((PPC_BO (insn
) & 0x14) == 0x4 || (PPC_BO (insn
) & 0x14) == 0x10)
1462 /* Out of range. Cannot relocate instruction. */
1463 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1466 if ((PPC_BO (insn
) & 0x14) == 0x4)
1468 else if ((PPC_BO (insn
) & 0x14) == 0x10)
1471 /* Jump over the unconditional branch. */
1472 insn
= (insn
& ~0xfffc) | 0x8;
1473 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1476 /* Build a unconditional branch and copy LK bit. */
1477 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1478 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1483 else if ((PPC_BO (insn
) & 0x14) == 0)
1485 uint32_t bdnz_insn
= (16 << 26) | (0x10 << 21) | 12;
1486 uint32_t bf_insn
= (16 << 26) | (0x4 << 21) | 8;
1490 /* Out of range. Cannot relocate instruction. */
1491 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1494 /* Copy BI field. */
1495 bf_insn
|= (insn
& 0x1f0000);
1497 /* Invert condition. */
1498 bdnz_insn
|= (insn
^ (1 << 22)) & (1 << 22);
1499 bf_insn
|= (insn
^ (1 << 24)) & (1 << 24);
1501 target_write_memory (*to
, (unsigned char *) &bdnz_insn
, 4);
1503 target_write_memory (*to
, (unsigned char *) &bf_insn
, 4);
1506 /* Build a unconditional branch and copy LK bit. */
1507 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1508 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1513 else /* (BO & 0x14) == 0x14, branch always. */
1515 /* Out of range. Cannot relocate instruction. */
1516 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1519 /* Build a unconditional branch and copy LK bit. */
1520 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1521 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1528 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1532 /* Implement install_fast_tracepoint_jump_pad of target_ops.
1533 See target.h for details. */
1536 ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1537 CORE_ADDR collector
,
1540 CORE_ADDR
*jump_entry
,
1541 CORE_ADDR
*trampoline
,
1542 ULONGEST
*trampoline_size
,
1543 unsigned char *jjump_pad_insn
,
1544 ULONGEST
*jjump_pad_insn_size
,
1545 CORE_ADDR
*adjusted_insn_addr
,
1546 CORE_ADDR
*adjusted_insn_addr_end
,
1552 CORE_ADDR buildaddr
= *jump_entry
;
1553 const CORE_ADDR entryaddr
= *jump_entry
;
1554 int rsz
, min_frame
, frame_size
, tp_reg
;
1555 #ifdef __powerpc64__
1556 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
1557 int is_64
= register_size (regcache
->tdesc
, 0) == 8;
1558 int is_opd
= is_64
&& !is_elfv2_inferior ();
1560 int is_64
= 0, is_opd
= 0;
1563 #ifdef __powerpc64__
1566 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1569 frame_size
= (40 * rsz
) + min_frame
;
1577 frame_size
= (40 * rsz
) + min_frame
;
1579 #ifdef __powerpc64__
1583 /* Stack frame layout for this jump pad,
1585 High thread_area (r13/r2) |
1586 tpoint - collecting_t obj
1596 R0 - collected registers
1602 The code flow of this jump pad,
1607 4. Call gdb_collector
1608 5. Restore GPR and SPR
1610 7. Build a jump for back to the program
1611 8. Copy/relocate original instruction
1612 9. Build a jump for replacing original instruction. */
1614 /* Adjust stack pointer. */
1616 p
+= GEN_STDU (p
, 1, 1, -frame_size
); /* stdu r1,-frame_size(r1) */
1618 p
+= GEN_STWU (p
, 1, 1, -frame_size
); /* stwu r1,-frame_size(r1) */
1620 /* Store GPRs. Save R1 later, because it had just been modified, but
1621 we want the original value. */
1622 for (j
= 2; j
< 32; j
++)
1623 p
+= GEN_STORE (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1624 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1625 /* Set r0 to the original value of r1 before adjusting stack frame,
1626 and then save it. */
1627 p
+= GEN_ADDI (p
, 0, 1, frame_size
);
1628 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 1 * rsz
, is_64
);
1630 /* Save CR, XER, LR, and CTR. */
1631 p
+= GEN_MFCR (p
, 3); /* mfcr r3 */
1632 p
+= GEN_MFSPR (p
, 4, 1); /* mfxer r4 */
1633 p
+= GEN_MFSPR (p
, 5, 8); /* mflr r5 */
1634 p
+= GEN_MFSPR (p
, 6, 9); /* mfctr r6 */
1635 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
);/* std r3, 32(r1) */
1636 p
+= GEN_STORE (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
);/* std r4, 33(r1) */
1637 p
+= GEN_STORE (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
);/* std r5, 34(r1) */
1638 p
+= GEN_STORE (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
);/* std r6, 35(r1) */
1640 /* Save PC<tpaddr> */
1641 p
+= gen_limm (p
, 3, tpaddr
, is_64
);
1642 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 36 * rsz
, is_64
);
1645 /* Setup arguments to collector. */
1646 /* Set r4 to collected registers. */
1647 p
+= GEN_ADDI (p
, 4, 1, min_frame
);
1648 /* Set r3 to TPOINT. */
1649 p
+= gen_limm (p
, 3, tpoint
, is_64
);
1651 /* Prepare collecting_t object for lock. */
1652 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 37 * rsz
, is_64
);
1653 p
+= GEN_STORE (p
, tp_reg
, 1, min_frame
+ 38 * rsz
, is_64
);
1654 /* Set R5 to collecting object. */
1655 p
+= GEN_ADDI (p
, 5, 1, 37 * rsz
);
1657 p
+= GEN_LWSYNC (p
);
1658 p
+= gen_atomic_xchg (p
, lockaddr
, 0, 5, is_64
);
1659 p
+= GEN_LWSYNC (p
);
1661 /* Call to collector. */
1662 p
+= gen_call (p
, collector
, is_64
, is_opd
);
1664 /* Simply write 0 to release the lock. */
1665 p
+= gen_limm (p
, 3, lockaddr
, is_64
);
1666 p
+= gen_limm (p
, 4, 0, is_64
);
1667 p
+= GEN_LWSYNC (p
);
1668 p
+= GEN_STORE (p
, 4, 3, 0, is_64
);
1670 /* Restore stack and registers. */
1671 p
+= GEN_LOAD (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
); /* ld r3, 32(r1) */
1672 p
+= GEN_LOAD (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
); /* ld r4, 33(r1) */
1673 p
+= GEN_LOAD (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
); /* ld r5, 34(r1) */
1674 p
+= GEN_LOAD (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
); /* ld r6, 35(r1) */
1675 p
+= GEN_MTCR (p
, 3); /* mtcr r3 */
1676 p
+= GEN_MTSPR (p
, 4, 1); /* mtxer r4 */
1677 p
+= GEN_MTSPR (p
, 5, 8); /* mtlr r5 */
1678 p
+= GEN_MTSPR (p
, 6, 9); /* mtctr r6 */
1681 for (j
= 2; j
< 32; j
++)
1682 p
+= GEN_LOAD (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1683 p
+= GEN_LOAD (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1685 p
+= GEN_ADDI (p
, 1, 1, frame_size
);
1687 /* Flush instructions to inferior memory. */
1688 target_write_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1690 /* Now, insert the original instruction to execute in the jump pad. */
1691 *adjusted_insn_addr
= buildaddr
+ (p
- buf
) * 4;
1692 *adjusted_insn_addr_end
= *adjusted_insn_addr
;
1693 ppc_relocate_instruction (adjusted_insn_addr_end
, tpaddr
);
1695 /* Verify the relocation size. If should be 4 for normal copy,
1696 8 or 12 for some conditional branch. */
1697 if ((*adjusted_insn_addr_end
- *adjusted_insn_addr
== 0)
1698 || (*adjusted_insn_addr_end
- *adjusted_insn_addr
> 12))
1700 sprintf (err
, "E.Unexpected instruction length = %d"
1701 "when relocate instruction.",
1702 (int) (*adjusted_insn_addr_end
- *adjusted_insn_addr
));
1706 buildaddr
= *adjusted_insn_addr_end
;
1708 /* Finally, write a jump back to the program. */
1709 offset
= (tpaddr
+ 4) - buildaddr
;
1710 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1712 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1713 "(offset 0x%x > 26-bit).", offset
);
1717 p
+= GEN_B (p
, offset
);
1718 target_write_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1719 *jump_entry
= buildaddr
+ (p
- buf
) * 4;
1721 /* The jump pad is now built. Wire in a jump to our jump pad. This
1722 is always done last (by our caller actually), so that we can
1723 install fast tracepoints with threads running. This relies on
1724 the agent's atomic write support. */
1725 offset
= entryaddr
- tpaddr
;
1726 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1728 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1729 "(offset 0x%x > 26-bit).", offset
);
1733 GEN_B ((uint32_t *) jjump_pad_insn
, offset
);
1734 *jjump_pad_insn_size
= 4;
1739 /* Returns the minimum instruction length for installing a tracepoint. */
1742 ppc_get_min_fast_tracepoint_insn_len (void)
1747 /* Emits a given buffer into the target at current_insn_ptr. Length
1748 is in units of 32-bit words. */
1751 emit_insns (uint32_t *buf
, int n
)
1753 n
= n
* sizeof (uint32_t);
1754 target_write_memory (current_insn_ptr
, (unsigned char *) buf
, n
);
1755 current_insn_ptr
+= n
;
1758 #define __EMIT_ASM(NAME, INSNS) \
1761 extern uint32_t start_bcax_ ## NAME []; \
1762 extern uint32_t end_bcax_ ## NAME []; \
1763 emit_insns (start_bcax_ ## NAME, \
1764 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1765 __asm__ (".section .text.__ppcbcax\n\t" \
1766 "start_bcax_" #NAME ":\n\t" \
1768 "end_bcax_" #NAME ":\n\t" \
1772 #define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1773 #define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1777 Bytecode execution stack frame - 32-bit
1779 | LR save area (SP + 4)
1780 SP' -> +- Back chain (SP + 0)
1781 | Save r31 for access saved arguments
1782 | Save r30 for bytecode stack pointer
1783 | Save r4 for incoming argument *value
1784 | Save r3 for incoming argument regs
1785 r30 -> +- Bytecode execution stack
1787 | 64-byte (8 doublewords) at initial.
1788 | Expand stack as needed.
1791 | Some padding for minimum stack frame and 16-byte alignment.
1793 SP +- Back-chain (SP')
1799 r30 is the stack-pointer for bytecode machine.
1800 It should point to next-empty, so we can use LDU for pop.
1801 r3 is used for cache of the high part of TOP value.
1802 It was the first argument, pointer to regs.
1803 r4 is used for cache of the low part of TOP value.
1804 It was the second argument, pointer to the result.
1805 We should set *result = TOP after leaving this function.
1808 * To restore stack at epilogue
1810 * To check stack is big enough for bytecode execution.
1812 * To return execution result.
1817 /* Regardless of endian, register 3 is always high part, 4 is low part.
1818 These defines are used when the register pair is stored/loaded.
1819 Likewise, to simplify code, have a similiar define for 5:6. */
1821 #if __BYTE_ORDER == __LITTLE_ENDIAN
1822 #define TOP_FIRST "4"
1823 #define TOP_SECOND "3"
1824 #define TMP_FIRST "6"
1825 #define TMP_SECOND "5"
1827 #define TOP_FIRST "3"
1828 #define TOP_SECOND "4"
1829 #define TMP_FIRST "5"
1830 #define TMP_SECOND "6"
1833 /* Emit prologue in inferior memory. See above comments. */
1836 ppc_emit_prologue (void)
1838 EMIT_ASM (/* Save return address. */
1841 /* Adjust SP. 96 is the initial frame size. */
1843 /* Save r30 and incoming arguments. */
1844 "stw 31, 96-4(1) \n"
1845 "stw 30, 96-8(1) \n"
1846 "stw 4, 96-12(1) \n"
1847 "stw 3, 96-16(1) \n"
1848 /* Point r31 to original r1 for access arguments. */
1850 /* Set r30 to pointing stack-top. */
1852 /* Initial r3/TOP to 0. */
1857 /* Emit epilogue in inferior memory. See above comments. */
1860 ppc_emit_epilogue (void)
1862 EMIT_ASM (/* *result = TOP */
1864 "stw " TOP_FIRST
", 0(5) \n"
1865 "stw " TOP_SECOND
", 4(5) \n"
1866 /* Restore registers. */
1873 /* Return 0 for no-error. */
1879 /* TOP = stack[--sp] + TOP */
1884 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1885 "lwz " TMP_SECOND
", 4(30)\n"
1890 /* TOP = stack[--sp] - TOP */
1895 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1896 "lwz " TMP_SECOND
", 4(30) \n"
1898 "subfe 3, 3, 5 \n");
1901 /* TOP = stack[--sp] * TOP */
1906 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1907 "lwz " TMP_SECOND
", 4(30) \n"
1916 /* TOP = stack[--sp] << TOP */
1921 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1922 "lwz " TMP_SECOND
", 4(30) \n"
1923 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1924 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1925 "slw 5, 5, 4\n" /* Shift high part left */
1926 "slw 4, 6, 4\n" /* Shift low part left */
1927 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1928 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1930 "or 3, 7, 3\n"); /* Assemble high part */
1933 /* Top = stack[--sp] >> TOP
1934 (Arithmetic shift right) */
1937 ppc_emit_rsh_signed (void)
1939 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1940 "lwz " TMP_SECOND
", 4(30) \n"
1941 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1942 "sraw 3, 5, 4\n" /* Shift high part right */
1944 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
1945 "sraw 4, 5, 7\n" /* Shift high to low */
1948 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
1949 "srw 4, 6, 4\n" /* Shift low part right */
1950 "slw 5, 5, 7\n" /* Shift high to low */
1951 "or 4, 4, 5\n" /* Assemble low part */
1955 /* Top = stack[--sp] >> TOP
1956 (Logical shift right) */
1959 ppc_emit_rsh_unsigned (void)
1961 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1962 "lwz " TMP_SECOND
", 4(30) \n"
1963 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1964 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1965 "srw 6, 6, 4\n" /* Shift low part right */
1966 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
1967 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
1969 "srw 3, 5, 4\n" /* Shift high part right */
1970 "or 4, 6, 7\n"); /* Assemble low part */
1973 /* Emit code for signed-extension specified by ARG. */
1976 ppc_emit_ext (int arg
)
1981 EMIT_ASM ("extsb 4, 4\n"
1985 EMIT_ASM ("extsh 4, 4\n"
1989 EMIT_ASM ("srawi 3, 4, 31");
1996 /* Emit code for zero-extension specified by ARG. */
1999 ppc_emit_zero_ext (int arg
)
2004 EMIT_ASM ("clrlwi 4,4,24\n"
2008 EMIT_ASM ("clrlwi 4,4,16\n"
2012 EMIT_ASM ("li 3, 0");
2020 i.e., TOP = (TOP == 0) ? 1 : 0; */
2023 ppc_emit_log_not (void)
2025 EMIT_ASM ("or 4, 3, 4 \n"
2031 /* TOP = stack[--sp] & TOP */
2034 ppc_emit_bit_and (void)
2036 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2037 "lwz " TMP_SECOND
", 4(30) \n"
2042 /* TOP = stack[--sp] | TOP */
2045 ppc_emit_bit_or (void)
2047 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2048 "lwz " TMP_SECOND
", 4(30) \n"
2053 /* TOP = stack[--sp] ^ TOP */
2056 ppc_emit_bit_xor (void)
2058 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2059 "lwz " TMP_SECOND
", 4(30) \n"
2065 i.e., TOP = ~(TOP | TOP) */
2068 ppc_emit_bit_not (void)
2070 EMIT_ASM ("nor 3, 3, 3 \n"
2074 /* TOP = stack[--sp] == TOP */
2077 ppc_emit_equal (void)
2079 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2080 "lwz " TMP_SECOND
", 4(30) \n"
2089 /* TOP = stack[--sp] < TOP
2090 (Signed comparison) */
2093 ppc_emit_less_signed (void)
2095 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2096 "lwz " TMP_SECOND
", 4(30) \n"
2099 /* CR6 bit 0 = low less and high equal */
2100 "crand 6*4+0, 6*4+0, 7*4+2\n"
2101 /* CR7 bit 0 = (low less and high equal) or high less */
2102 "cror 7*4+0, 7*4+0, 6*4+0\n"
2104 "rlwinm 4, 4, 29, 31, 31 \n"
2108 /* TOP = stack[--sp] < TOP
2109 (Unsigned comparison) */
2112 ppc_emit_less_unsigned (void)
2114 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2115 "lwz " TMP_SECOND
", 4(30) \n"
2118 /* CR6 bit 0 = low less and high equal */
2119 "crand 6*4+0, 6*4+0, 7*4+2\n"
2120 /* CR7 bit 0 = (low less and high equal) or high less */
2121 "cror 7*4+0, 7*4+0, 6*4+0\n"
2123 "rlwinm 4, 4, 29, 31, 31 \n"
2127 /* Access the memory address in TOP in size of SIZE.
2128 Zero-extend the read value. */
2131 ppc_emit_ref (int size
)
2136 EMIT_ASM ("lbz 4, 0(4)\n"
2140 EMIT_ASM ("lhz 4, 0(4)\n"
2144 EMIT_ASM ("lwz 4, 0(4)\n"
2148 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2149 EMIT_ASM ("lwz 3, 4(4)\n"
2152 EMIT_ASM ("lwz 3, 0(4)\n"
2161 ppc_emit_const (LONGEST num
)
2166 p
+= gen_limm (p
, 3, num
>> 32 & 0xffffffff, 0);
2167 p
+= gen_limm (p
, 4, num
& 0xffffffff, 0);
2169 emit_insns (buf
, p
- buf
);
2170 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2173 /* Set TOP to the value of register REG by calling get_raw_reg function
2174 with two argument, collected buffer and register number. */
2177 ppc_emit_reg (int reg
)
2182 /* fctx->regs is passed in r3 and then saved in -16(31). */
2183 p
+= GEN_LWZ (p
, 3, 31, -16);
2184 p
+= GEN_LI (p
, 4, reg
); /* li r4, reg */
2185 p
+= gen_call (p
, get_raw_reg_func_addr (), 0, 0);
2187 emit_insns (buf
, p
- buf
);
2188 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2190 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2192 EMIT_ASM ("mr 5, 4\n"
2198 /* TOP = stack[--sp] */
2203 EMIT_ASM ("lwzu " TOP_FIRST
", 8(30) \n"
2204 "lwz " TOP_SECOND
", 4(30) \n");
2207 /* stack[sp++] = TOP
2209 Because we may use up bytecode stack, expand 8 doublewords more
2213 ppc_emit_stack_flush (void)
2215 /* Make sure bytecode stack is big enough before push.
2216 Otherwise, expand 64-byte more. */
2218 EMIT_ASM (" stw " TOP_FIRST
", 0(30) \n"
2219 " stw " TOP_SECOND
", 4(30)\n"
2220 " addi 5, 30, -(8 + 8) \n"
2223 " stwu 31, -64(1) \n"
2224 "1:addi 30, 30, -8 \n");
2227 /* Swap TOP and stack[sp-1] */
2230 ppc_emit_swap (void)
2232 EMIT_ASM ("lwz " TMP_FIRST
", 8(30) \n"
2233 "lwz " TMP_SECOND
", 12(30) \n"
2234 "stw " TOP_FIRST
", 8(30) \n"
2235 "stw " TOP_SECOND
", 12(30) \n"
2240 /* Discard N elements in the stack. Also used for ppc64. */
2243 ppc_emit_stack_adjust (int n
)
2255 p
+= GEN_ADDI (p
, 30, 30, n
);
2257 emit_insns (buf
, p
- buf
);
2258 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2261 /* Call function FN. */
2264 ppc_emit_call (CORE_ADDR fn
)
2269 p
+= gen_call (p
, fn
, 0, 0);
2271 emit_insns (buf
, p
- buf
);
2272 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2275 /* FN's prototype is `LONGEST(*fn)(int)'.
2280 ppc_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2285 /* Setup argument. arg1 is a 16-bit value. */
2286 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2287 p
+= gen_call (p
, fn
, 0, 0);
2289 emit_insns (buf
, p
- buf
);
2290 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2292 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2294 EMIT_ASM ("mr 5, 4\n"
2300 /* FN's prototype is `void(*fn)(int,LONGEST)'.
2303 TOP should be preserved/restored before/after the call. */
2306 ppc_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2311 /* Save TOP. 0(30) is next-empty. */
2312 p
+= GEN_STW (p
, 3, 30, 0);
2313 p
+= GEN_STW (p
, 4, 30, 4);
2315 /* Setup argument. arg1 is a 16-bit value. */
2316 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2318 p
+= GEN_MR (p
, 5, 4);
2319 p
+= GEN_MR (p
, 6, 3);
2323 p
+= GEN_MR (p
, 5, 3);
2324 p
+= GEN_MR (p
, 6, 4);
2326 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2327 p
+= gen_call (p
, fn
, 0, 0);
2330 p
+= GEN_LWZ (p
, 3, 30, 0);
2331 p
+= GEN_LWZ (p
, 4, 30, 4);
2333 emit_insns (buf
, p
- buf
);
2334 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2337 /* Note in the following goto ops:
2339 When emitting goto, the target address is later relocated by
2340 write_goto_address. OFFSET_P is the offset of the branch instruction
2341 in the code sequence, and SIZE_P is how to relocate the instruction,
2342 recognized by ppc_write_goto_address. In current implementation,
2343 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2346 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2349 ppc_emit_if_goto (int *offset_p
, int *size_p
)
2351 EMIT_ASM ("or. 3, 3, 4 \n"
2352 "lwzu " TOP_FIRST
", 8(30) \n"
2353 "lwz " TOP_SECOND
", 4(30) \n"
2362 /* Unconditional goto. Also used for ppc64. */
2365 ppc_emit_goto (int *offset_p
, int *size_p
)
2367 EMIT_ASM ("1:b 1b");
2375 /* Goto if stack[--sp] == TOP */
2378 ppc_emit_eq_goto (int *offset_p
, int *size_p
)
2380 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2381 "lwz " TMP_SECOND
", 4(30) \n"
2385 "lwzu " TOP_FIRST
", 8(30) \n"
2386 "lwz " TOP_SECOND
", 4(30) \n"
2395 /* Goto if stack[--sp] != TOP */
2398 ppc_emit_ne_goto (int *offset_p
, int *size_p
)
2400 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2401 "lwz " TMP_SECOND
", 4(30) \n"
2405 "lwzu " TOP_FIRST
", 8(30) \n"
2406 "lwz " TOP_SECOND
", 4(30) \n"
2415 /* Goto if stack[--sp] < TOP */
2418 ppc_emit_lt_goto (int *offset_p
, int *size_p
)
2420 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2421 "lwz " TMP_SECOND
", 4(30) \n"
2424 /* CR6 bit 0 = low less and high equal */
2425 "crand 6*4+0, 6*4+0, 7*4+2\n"
2426 /* CR7 bit 0 = (low less and high equal) or high less */
2427 "cror 7*4+0, 7*4+0, 6*4+0\n"
2428 "lwzu " TOP_FIRST
", 8(30) \n"
2429 "lwz " TOP_SECOND
", 4(30)\n"
2438 /* Goto if stack[--sp] <= TOP */
2441 ppc_emit_le_goto (int *offset_p
, int *size_p
)
2443 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2444 "lwz " TMP_SECOND
", 4(30) \n"
2447 /* CR6 bit 0 = low less/equal and high equal */
2448 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2449 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2450 "cror 7*4+0, 7*4+0, 6*4+0\n"
2451 "lwzu " TOP_FIRST
", 8(30) \n"
2452 "lwz " TOP_SECOND
", 4(30)\n"
2461 /* Goto if stack[--sp] > TOP */
2464 ppc_emit_gt_goto (int *offset_p
, int *size_p
)
2466 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2467 "lwz " TMP_SECOND
", 4(30) \n"
2470 /* CR6 bit 0 = low greater and high equal */
2471 "crand 6*4+0, 6*4+1, 7*4+2\n"
2472 /* CR7 bit 0 = (low greater and high equal) or high greater */
2473 "cror 7*4+0, 7*4+1, 6*4+0\n"
2474 "lwzu " TOP_FIRST
", 8(30) \n"
2475 "lwz " TOP_SECOND
", 4(30)\n"
2484 /* Goto if stack[--sp] >= TOP */
2487 ppc_emit_ge_goto (int *offset_p
, int *size_p
)
2489 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2490 "lwz " TMP_SECOND
", 4(30) \n"
2493 /* CR6 bit 0 = low ge and high equal */
2494 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2495 /* CR7 bit 0 = (low ge and high equal) or high greater */
2496 "cror 7*4+0, 7*4+1, 6*4+0\n"
2497 "lwzu " TOP_FIRST
", 8(30)\n"
2498 "lwz " TOP_SECOND
", 4(30)\n"
2507 /* Relocate previous emitted branch instruction. FROM is the address
2508 of the branch instruction, TO is the goto target address, and SIZE
2509 if the value we set by *SIZE_P before. Currently, it is either
2510 24 or 14 of branch and conditional-branch instruction.
2511 Also used for ppc64. */
2514 ppc_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2516 long rel
= to
- from
;
2520 read_inferior_memory (from
, (unsigned char *) &insn
, 4);
2521 opcd
= (insn
>> 26) & 0x3f;
2527 || (rel
>= (1 << 15) || rel
< -(1 << 15)))
2529 insn
= (insn
& ~0xfffc) | (rel
& 0xfffc);
2533 || (rel
>= (1 << 25) || rel
< -(1 << 25)))
2535 insn
= (insn
& ~0x3fffffc) | (rel
& 0x3fffffc);
2542 target_write_memory (from
, (unsigned char *) &insn
, 4);
2545 /* Table of emit ops for 32-bit. */
2547 static struct emit_ops ppc_emit_ops_impl
=
2555 ppc_emit_rsh_signed
,
2556 ppc_emit_rsh_unsigned
,
2564 ppc_emit_less_signed
,
2565 ppc_emit_less_unsigned
,
2569 ppc_write_goto_address
,
2574 ppc_emit_stack_flush
,
2577 ppc_emit_stack_adjust
,
2578 ppc_emit_int_call_1
,
2579 ppc_emit_void_call_2
,
2588 #ifdef __powerpc64__
2592 Bytecode execution stack frame - 64-bit
2594 | LR save area (SP + 16)
2595 | CR save area (SP + 8)
2596 SP' -> +- Back chain (SP + 0)
2597 | Save r31 for access saved arguments
2598 | Save r30 for bytecode stack pointer
2599 | Save r4 for incoming argument *value
2600 | Save r3 for incoming argument regs
2601 r30 -> +- Bytecode execution stack
2603 | 64-byte (8 doublewords) at initial.
2604 | Expand stack as needed.
2607 | Some padding for minimum stack frame.
2609 SP +- Back-chain (SP')
2612 = 112 + (4 * 8) + 64
2615 r30 is the stack-pointer for bytecode machine.
2616 It should point to next-empty, so we can use LDU for pop.
2617 r3 is used for cache of TOP value.
2618 It was the first argument, pointer to regs.
2619 r4 is the second argument, pointer to the result.
2620 We should set *result = TOP after leaving this function.
2623 * To restore stack at epilogue
2625 * To check stack is big enough for bytecode execution.
2626 => r30 - 8 > SP + 112
2627 * To return execution result.
2632 /* Emit prologue in inferior memory. See above comments. */
2635 ppc64v1_emit_prologue (void)
2637 /* On ELFv1, function pointers really point to function descriptor,
2638 so emit one here. We don't care about contents of words 1 and 2,
2639 so let them just overlap out code. */
2640 uint64_t opd
= current_insn_ptr
+ 8;
2643 /* Mind the strict aliasing rules. */
2644 memcpy (buf
, &opd
, sizeof buf
);
2646 EMIT_ASM (/* Save return address. */
2649 /* Save r30 and incoming arguments. */
2654 /* Point r31 to current r1 for access arguments. */
2656 /* Adjust SP. 208 is the initial frame size. */
2657 "stdu 1, -208(1) \n"
2658 /* Set r30 to pointing stack-top. */
2659 "addi 30, 1, 168 \n"
2660 /* Initial r3/TOP to 0. */
2664 /* Emit prologue in inferior memory. See above comments. */
2667 ppc64v2_emit_prologue (void)
2669 EMIT_ASM (/* Save return address. */
2672 /* Save r30 and incoming arguments. */
2677 /* Point r31 to current r1 for access arguments. */
2679 /* Adjust SP. 208 is the initial frame size. */
2680 "stdu 1, -208(1) \n"
2681 /* Set r30 to pointing stack-top. */
2682 "addi 30, 1, 168 \n"
2683 /* Initial r3/TOP to 0. */
2687 /* Emit epilogue in inferior memory. See above comments. */
2690 ppc64_emit_epilogue (void)
2692 EMIT_ASM (/* Restore SP. */
2697 /* Restore registers. */
2702 /* Return 0 for no-error. */
2708 /* TOP = stack[--sp] + TOP */
2711 ppc64_emit_add (void)
2713 EMIT_ASM ("ldu 4, 8(30) \n"
2717 /* TOP = stack[--sp] - TOP */
2720 ppc64_emit_sub (void)
2722 EMIT_ASM ("ldu 4, 8(30) \n"
2726 /* TOP = stack[--sp] * TOP */
2729 ppc64_emit_mul (void)
2731 EMIT_ASM ("ldu 4, 8(30) \n"
2732 "mulld 3, 4, 3 \n");
2735 /* TOP = stack[--sp] << TOP */
2738 ppc64_emit_lsh (void)
2740 EMIT_ASM ("ldu 4, 8(30) \n"
2744 /* Top = stack[--sp] >> TOP
2745 (Arithmetic shift right) */
2748 ppc64_emit_rsh_signed (void)
2750 EMIT_ASM ("ldu 4, 8(30) \n"
2754 /* Top = stack[--sp] >> TOP
2755 (Logical shift right) */
2758 ppc64_emit_rsh_unsigned (void)
2760 EMIT_ASM ("ldu 4, 8(30) \n"
2764 /* Emit code for signed-extension specified by ARG. */
2767 ppc64_emit_ext (int arg
)
2772 EMIT_ASM ("extsb 3, 3");
2775 EMIT_ASM ("extsh 3, 3");
2778 EMIT_ASM ("extsw 3, 3");
2785 /* Emit code for zero-extension specified by ARG. */
2788 ppc64_emit_zero_ext (int arg
)
2793 EMIT_ASM ("rldicl 3,3,0,56");
2796 EMIT_ASM ("rldicl 3,3,0,48");
2799 EMIT_ASM ("rldicl 3,3,0,32");
2807 i.e., TOP = (TOP == 0) ? 1 : 0; */
2810 ppc64_emit_log_not (void)
2812 EMIT_ASM ("cntlzd 3, 3 \n"
2816 /* TOP = stack[--sp] & TOP */
2819 ppc64_emit_bit_and (void)
2821 EMIT_ASM ("ldu 4, 8(30) \n"
2825 /* TOP = stack[--sp] | TOP */
2828 ppc64_emit_bit_or (void)
2830 EMIT_ASM ("ldu 4, 8(30) \n"
2834 /* TOP = stack[--sp] ^ TOP */
2837 ppc64_emit_bit_xor (void)
2839 EMIT_ASM ("ldu 4, 8(30) \n"
2844 i.e., TOP = ~(TOP | TOP) */
2847 ppc64_emit_bit_not (void)
2849 EMIT_ASM ("nor 3, 3, 3 \n");
2852 /* TOP = stack[--sp] == TOP */
2855 ppc64_emit_equal (void)
2857 EMIT_ASM ("ldu 4, 8(30) \n"
2863 /* TOP = stack[--sp] < TOP
2864 (Signed comparison) */
2867 ppc64_emit_less_signed (void)
2869 EMIT_ASM ("ldu 4, 8(30) \n"
2872 "rlwinm 3, 3, 29, 31, 31 \n");
2875 /* TOP = stack[--sp] < TOP
2876 (Unsigned comparison) */
2879 ppc64_emit_less_unsigned (void)
2881 EMIT_ASM ("ldu 4, 8(30) \n"
2884 "rlwinm 3, 3, 29, 31, 31 \n");
2887 /* Access the memory address in TOP in size of SIZE.
2888 Zero-extend the read value. */
2891 ppc64_emit_ref (int size
)
2896 EMIT_ASM ("lbz 3, 0(3)");
2899 EMIT_ASM ("lhz 3, 0(3)");
2902 EMIT_ASM ("lwz 3, 0(3)");
2905 EMIT_ASM ("ld 3, 0(3)");
2913 ppc64_emit_const (LONGEST num
)
2918 p
+= gen_limm (p
, 3, num
, 1);
2920 emit_insns (buf
, p
- buf
);
2921 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2924 /* Set TOP to the value of register REG by calling get_raw_reg function
2925 with two argument, collected buffer and register number. */
2928 ppc64v1_emit_reg (int reg
)
2933 /* fctx->regs is passed in r3 and then saved in 176(1). */
2934 p
+= GEN_LD (p
, 3, 31, -32);
2935 p
+= GEN_LI (p
, 4, reg
);
2936 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2937 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 1);
2938 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2940 emit_insns (buf
, p
- buf
);
2941 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2944 /* Likewise, for ELFv2. */
2947 ppc64v2_emit_reg (int reg
)
2952 /* fctx->regs is passed in r3 and then saved in 176(1). */
2953 p
+= GEN_LD (p
, 3, 31, -32);
2954 p
+= GEN_LI (p
, 4, reg
);
2955 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2956 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 0);
2957 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2959 emit_insns (buf
, p
- buf
);
2960 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2963 /* TOP = stack[--sp] */
2966 ppc64_emit_pop (void)
2968 EMIT_ASM ("ldu 3, 8(30)");
2971 /* stack[sp++] = TOP
2973 Because we may use up bytecode stack, expand 8 doublewords more
2977 ppc64_emit_stack_flush (void)
2979 /* Make sure bytecode stack is big enough before push.
2980 Otherwise, expand 64-byte more. */
2982 EMIT_ASM (" std 3, 0(30) \n"
2983 " addi 4, 30, -(112 + 8) \n"
2986 " stdu 31, -64(1) \n"
2987 "1:addi 30, 30, -8 \n");
2990 /* Swap TOP and stack[sp-1] */
2993 ppc64_emit_swap (void)
2995 EMIT_ASM ("ld 4, 8(30) \n"
3000 /* Call function FN - ELFv1. */
3003 ppc64v1_emit_call (CORE_ADDR fn
)
3008 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3009 p
+= gen_call (p
, fn
, 1, 1);
3010 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3012 emit_insns (buf
, p
- buf
);
3013 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3016 /* Call function FN - ELFv2. */
3019 ppc64v2_emit_call (CORE_ADDR fn
)
3024 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3025 p
+= gen_call (p
, fn
, 1, 0);
3026 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3028 emit_insns (buf
, p
- buf
);
3029 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3032 /* FN's prototype is `LONGEST(*fn)(int)'.
3037 ppc64v1_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3042 /* Setup argument. arg1 is a 16-bit value. */
3043 p
+= gen_limm (p
, 3, arg1
, 1);
3044 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3045 p
+= gen_call (p
, fn
, 1, 1);
3046 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3048 emit_insns (buf
, p
- buf
);
3049 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3052 /* Likewise for ELFv2. */
3055 ppc64v2_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3060 /* Setup argument. arg1 is a 16-bit value. */
3061 p
+= gen_limm (p
, 3, arg1
, 1);
3062 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3063 p
+= gen_call (p
, fn
, 1, 0);
3064 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3066 emit_insns (buf
, p
- buf
);
3067 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3070 /* FN's prototype is `void(*fn)(int,LONGEST)'.
3073 TOP should be preserved/restored before/after the call. */
3076 ppc64v1_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3081 /* Save TOP. 0(30) is next-empty. */
3082 p
+= GEN_STD (p
, 3, 30, 0);
3084 /* Setup argument. arg1 is a 16-bit value. */
3085 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3086 p
+= gen_limm (p
, 3, arg1
, 1);
3087 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3088 p
+= gen_call (p
, fn
, 1, 1);
3089 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3092 p
+= GEN_LD (p
, 3, 30, 0);
3094 emit_insns (buf
, p
- buf
);
3095 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3098 /* Likewise for ELFv2. */
3101 ppc64v2_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3106 /* Save TOP. 0(30) is next-empty. */
3107 p
+= GEN_STD (p
, 3, 30, 0);
3109 /* Setup argument. arg1 is a 16-bit value. */
3110 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3111 p
+= gen_limm (p
, 3, arg1
, 1);
3112 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3113 p
+= gen_call (p
, fn
, 1, 0);
3114 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3117 p
+= GEN_LD (p
, 3, 30, 0);
3119 emit_insns (buf
, p
- buf
);
3120 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3123 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
3126 ppc64_emit_if_goto (int *offset_p
, int *size_p
)
3128 EMIT_ASM ("cmpdi 7, 3, 0 \n"
3138 /* Goto if stack[--sp] == TOP */
3141 ppc64_emit_eq_goto (int *offset_p
, int *size_p
)
3143 EMIT_ASM ("ldu 4, 8(30) \n"
3154 /* Goto if stack[--sp] != TOP */
3157 ppc64_emit_ne_goto (int *offset_p
, int *size_p
)
3159 EMIT_ASM ("ldu 4, 8(30) \n"
3170 /* Goto if stack[--sp] < TOP */
3173 ppc64_emit_lt_goto (int *offset_p
, int *size_p
)
3175 EMIT_ASM ("ldu 4, 8(30) \n"
3186 /* Goto if stack[--sp] <= TOP */
3189 ppc64_emit_le_goto (int *offset_p
, int *size_p
)
3191 EMIT_ASM ("ldu 4, 8(30) \n"
3202 /* Goto if stack[--sp] > TOP */
3205 ppc64_emit_gt_goto (int *offset_p
, int *size_p
)
3207 EMIT_ASM ("ldu 4, 8(30) \n"
3218 /* Goto if stack[--sp] >= TOP */
3221 ppc64_emit_ge_goto (int *offset_p
, int *size_p
)
3223 EMIT_ASM ("ldu 4, 8(30) \n"
3234 /* Table of emit ops for 64-bit ELFv1. */
3236 static struct emit_ops ppc64v1_emit_ops_impl
=
3238 ppc64v1_emit_prologue
,
3239 ppc64_emit_epilogue
,
3244 ppc64_emit_rsh_signed
,
3245 ppc64_emit_rsh_unsigned
,
3253 ppc64_emit_less_signed
,
3254 ppc64_emit_less_unsigned
,
3258 ppc_write_goto_address
,
3263 ppc64_emit_stack_flush
,
3264 ppc64_emit_zero_ext
,
3266 ppc_emit_stack_adjust
,
3267 ppc64v1_emit_int_call_1
,
3268 ppc64v1_emit_void_call_2
,
3277 /* Table of emit ops for 64-bit ELFv2. */
3279 static struct emit_ops ppc64v2_emit_ops_impl
=
3281 ppc64v2_emit_prologue
,
3282 ppc64_emit_epilogue
,
3287 ppc64_emit_rsh_signed
,
3288 ppc64_emit_rsh_unsigned
,
3296 ppc64_emit_less_signed
,
3297 ppc64_emit_less_unsigned
,
3301 ppc_write_goto_address
,
3306 ppc64_emit_stack_flush
,
3307 ppc64_emit_zero_ext
,
3309 ppc_emit_stack_adjust
,
3310 ppc64v2_emit_int_call_1
,
3311 ppc64v2_emit_void_call_2
,
3322 /* Implementation of linux_target_ops method "emit_ops". */
3324 static struct emit_ops
*
3327 #ifdef __powerpc64__
3328 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3330 if (register_size (regcache
->tdesc
, 0) == 8)
3332 if (is_elfv2_inferior ())
3333 return &ppc64v2_emit_ops_impl
;
3335 return &ppc64v1_emit_ops_impl
;
3338 return &ppc_emit_ops_impl
;
3341 /* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3344 ppc_get_ipa_tdesc_idx (void)
3346 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3347 const struct target_desc
*tdesc
= regcache
->tdesc
;
3349 #ifdef __powerpc64__
3350 if (tdesc
== tdesc_powerpc_64l
)
3351 return PPC_TDESC_BASE
;
3352 if (tdesc
== tdesc_powerpc_altivec64l
)
3353 return PPC_TDESC_ALTIVEC
;
3354 if (tdesc
== tdesc_powerpc_vsx64l
)
3355 return PPC_TDESC_VSX
;
3356 if (tdesc
== tdesc_powerpc_isa205_64l
)
3357 return PPC_TDESC_ISA205
;
3358 if (tdesc
== tdesc_powerpc_isa205_altivec64l
)
3359 return PPC_TDESC_ISA205_ALTIVEC
;
3360 if (tdesc
== tdesc_powerpc_isa205_vsx64l
)
3361 return PPC_TDESC_ISA205_VSX
;
3362 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx64l
)
3363 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3364 if (tdesc
== tdesc_powerpc_isa207_vsx64l
)
3365 return PPC_TDESC_ISA207_VSX
;
3366 if (tdesc
== tdesc_powerpc_isa207_htm_vsx64l
)
3367 return PPC_TDESC_ISA207_HTM_VSX
;
3370 if (tdesc
== tdesc_powerpc_32l
)
3371 return PPC_TDESC_BASE
;
3372 if (tdesc
== tdesc_powerpc_altivec32l
)
3373 return PPC_TDESC_ALTIVEC
;
3374 if (tdesc
== tdesc_powerpc_vsx32l
)
3375 return PPC_TDESC_VSX
;
3376 if (tdesc
== tdesc_powerpc_isa205_32l
)
3377 return PPC_TDESC_ISA205
;
3378 if (tdesc
== tdesc_powerpc_isa205_altivec32l
)
3379 return PPC_TDESC_ISA205_ALTIVEC
;
3380 if (tdesc
== tdesc_powerpc_isa205_vsx32l
)
3381 return PPC_TDESC_ISA205_VSX
;
3382 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx32l
)
3383 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3384 if (tdesc
== tdesc_powerpc_isa207_vsx32l
)
3385 return PPC_TDESC_ISA207_VSX
;
3386 if (tdesc
== tdesc_powerpc_isa207_htm_vsx32l
)
3387 return PPC_TDESC_ISA207_HTM_VSX
;
3388 if (tdesc
== tdesc_powerpc_e500l
)
3389 return PPC_TDESC_E500
;
3394 struct linux_target_ops the_low_target
= {
3397 NULL
, /* breakpoint_kind_from_pc */
3398 ppc_sw_breakpoint_from_kind
,
3402 ppc_supports_z_point_type
,
3407 ppc_collect_ptrace_register
,
3408 ppc_supply_ptrace_register
,
3409 NULL
, /* siginfo_fixup */
3410 NULL
, /* new_process */
3411 NULL
, /* delete_process */
3412 NULL
, /* new_thread */
3413 NULL
, /* delete_thread */
3414 NULL
, /* new_fork */
3415 NULL
, /* prepare_to_resume */
3416 NULL
, /* process_qsupported */
3417 ppc_supports_tracepoints
,
3418 ppc_get_thread_area
,
3419 ppc_install_fast_tracepoint_jump_pad
,
3421 ppc_get_min_fast_tracepoint_insn_len
,
3422 NULL
, /* supports_range_stepping */
3423 NULL
, /* breakpoint_kind_from_current_state */
3424 ppc_supports_hardware_single_step
,
3425 NULL
, /* get_syscall_trapinfo */
3426 ppc_get_ipa_tdesc_idx
,
3429 /* The linux target ops object. */
3431 linux_process_target
*the_linux_target
= &the_ppc_target
;
3434 initialize_low_arch (void)
3436 /* Initialize the Linux target descriptions. */
3438 init_registers_powerpc_32l ();
3439 init_registers_powerpc_altivec32l ();
3440 init_registers_powerpc_vsx32l ();
3441 init_registers_powerpc_isa205_32l ();
3442 init_registers_powerpc_isa205_altivec32l ();
3443 init_registers_powerpc_isa205_vsx32l ();
3444 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
3445 init_registers_powerpc_isa207_vsx32l ();
3446 init_registers_powerpc_isa207_htm_vsx32l ();
3447 init_registers_powerpc_e500l ();
3449 init_registers_powerpc_64l ();
3450 init_registers_powerpc_altivec64l ();
3451 init_registers_powerpc_vsx64l ();
3452 init_registers_powerpc_isa205_64l ();
3453 init_registers_powerpc_isa205_altivec64l ();
3454 init_registers_powerpc_isa205_vsx64l ();
3455 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
3456 init_registers_powerpc_isa207_vsx64l ();
3457 init_registers_powerpc_isa207_htm_vsx64l ();
3460 initialize_regsets_info (&ppc_regsets_info
);