1 /* GNU/Linux/PowerPC specific low level interface, for the remote server for
3 Copyright (C) 1995-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "linux-low.h"
23 #include "elf/common.h"
26 #include <asm/ptrace.h>
28 #include "arch/ppc-linux-common.h"
29 #include "arch/ppc-linux-tdesc.h"
30 #include "nat/ppc-linux.h"
31 #include "nat/linux-ptrace.h"
32 #include "linux-ppc-tdesc-init.h"
34 #include "tracepoint.h"
36 #define PPC_FIELD(value, from, len) \
37 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
38 #define PPC_SEXT(v, bs) \
39 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
40 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
41 - ((CORE_ADDR) 1 << ((bs) - 1)))
42 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
43 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
44 #define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
45 #define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
47 /* Linux target op definitions for the PowerPC architecture. */
49 class ppc_target
: public linux_process_target
53 const regs_info
*get_regs_info () override
;
57 void low_arch_setup () override
;
59 bool low_cannot_fetch_register (int regno
) override
;
61 bool low_cannot_store_register (int regno
) override
;
63 bool low_supports_breakpoints () override
;
65 CORE_ADDR
low_get_pc (regcache
*regcache
) override
;
67 void low_set_pc (regcache
*regcache
, CORE_ADDR newpc
) override
;
70 /* The singleton target ops object. */
72 static ppc_target the_ppc_target
;
74 /* Holds the AT_HWCAP auxv entry. */
76 static unsigned long ppc_hwcap
;
78 /* Holds the AT_HWCAP2 auxv entry. */
80 static unsigned long ppc_hwcap2
;
83 #define ppc_num_regs 73
86 /* We use a constant for FPSCR instead of PT_FPSCR, because
87 many shipped PPC64 kernels had the wrong value in ptrace.h. */
88 static int ppc_regmap
[] =
89 {PT_R0
* 8, PT_R1
* 8, PT_R2
* 8, PT_R3
* 8,
90 PT_R4
* 8, PT_R5
* 8, PT_R6
* 8, PT_R7
* 8,
91 PT_R8
* 8, PT_R9
* 8, PT_R10
* 8, PT_R11
* 8,
92 PT_R12
* 8, PT_R13
* 8, PT_R14
* 8, PT_R15
* 8,
93 PT_R16
* 8, PT_R17
* 8, PT_R18
* 8, PT_R19
* 8,
94 PT_R20
* 8, PT_R21
* 8, PT_R22
* 8, PT_R23
* 8,
95 PT_R24
* 8, PT_R25
* 8, PT_R26
* 8, PT_R27
* 8,
96 PT_R28
* 8, PT_R29
* 8, PT_R30
* 8, PT_R31
* 8,
97 PT_FPR0
*8, PT_FPR0
*8 + 8, PT_FPR0
*8+16, PT_FPR0
*8+24,
98 PT_FPR0
*8+32, PT_FPR0
*8+40, PT_FPR0
*8+48, PT_FPR0
*8+56,
99 PT_FPR0
*8+64, PT_FPR0
*8+72, PT_FPR0
*8+80, PT_FPR0
*8+88,
100 PT_FPR0
*8+96, PT_FPR0
*8+104, PT_FPR0
*8+112, PT_FPR0
*8+120,
101 PT_FPR0
*8+128, PT_FPR0
*8+136, PT_FPR0
*8+144, PT_FPR0
*8+152,
102 PT_FPR0
*8+160, PT_FPR0
*8+168, PT_FPR0
*8+176, PT_FPR0
*8+184,
103 PT_FPR0
*8+192, PT_FPR0
*8+200, PT_FPR0
*8+208, PT_FPR0
*8+216,
104 PT_FPR0
*8+224, PT_FPR0
*8+232, PT_FPR0
*8+240, PT_FPR0
*8+248,
105 PT_NIP
* 8, PT_MSR
* 8, PT_CCR
* 8, PT_LNK
* 8,
106 PT_CTR
* 8, PT_XER
* 8, PT_FPR0
*8 + 256,
107 PT_ORIG_R3
* 8, PT_TRAP
* 8 };
109 /* Currently, don't check/send MQ. */
110 static int ppc_regmap
[] =
111 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
112 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
113 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
114 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
115 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
116 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
117 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
118 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
119 PT_FPR0
*4, PT_FPR0
*4 + 8, PT_FPR0
*4+16, PT_FPR0
*4+24,
120 PT_FPR0
*4+32, PT_FPR0
*4+40, PT_FPR0
*4+48, PT_FPR0
*4+56,
121 PT_FPR0
*4+64, PT_FPR0
*4+72, PT_FPR0
*4+80, PT_FPR0
*4+88,
122 PT_FPR0
*4+96, PT_FPR0
*4+104, PT_FPR0
*4+112, PT_FPR0
*4+120,
123 PT_FPR0
*4+128, PT_FPR0
*4+136, PT_FPR0
*4+144, PT_FPR0
*4+152,
124 PT_FPR0
*4+160, PT_FPR0
*4+168, PT_FPR0
*4+176, PT_FPR0
*4+184,
125 PT_FPR0
*4+192, PT_FPR0
*4+200, PT_FPR0
*4+208, PT_FPR0
*4+216,
126 PT_FPR0
*4+224, PT_FPR0
*4+232, PT_FPR0
*4+240, PT_FPR0
*4+248,
127 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
128 PT_CTR
* 4, PT_XER
* 4, PT_FPSCR
* 4,
129 PT_ORIG_R3
* 4, PT_TRAP
* 4
132 static int ppc_regmap_e500
[] =
133 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
134 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
135 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
136 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
137 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
138 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
139 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
140 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
149 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
150 PT_CTR
* 4, PT_XER
* 4, -1,
151 PT_ORIG_R3
* 4, PT_TRAP
* 4
155 /* Check whether the kernel provides a register set with number
156 REGSET_ID of size REGSETSIZE for process/thread TID. */
159 ppc_check_regset (int tid
, int regset_id
, int regsetsize
)
161 void *buf
= alloca (regsetsize
);
165 iov
.iov_len
= regsetsize
;
167 if (ptrace (PTRACE_GETREGSET
, tid
, regset_id
, &iov
) >= 0
174 ppc_target::low_cannot_store_register (int regno
)
176 const struct target_desc
*tdesc
= current_process ()->tdesc
;
178 #ifndef __powerpc64__
179 /* Some kernels do not allow us to store fpscr. */
180 if (!(ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
181 && regno
== find_regno (tdesc
, "fpscr"))
185 /* Some kernels do not allow us to store orig_r3 or trap. */
186 if (regno
== find_regno (tdesc
, "orig_r3")
187 || regno
== find_regno (tdesc
, "trap"))
194 ppc_target::low_cannot_fetch_register (int regno
)
200 ppc_collect_ptrace_register (struct regcache
*regcache
, int regno
, char *buf
)
202 memset (buf
, 0, sizeof (long));
204 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
206 /* Little-endian values always sit at the left end of the buffer. */
207 collect_register (regcache
, regno
, buf
);
209 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
211 /* Big-endian values sit at the right end of the buffer. In case of
212 registers whose sizes are smaller than sizeof (long), we must use a
213 padding to access them correctly. */
214 int size
= register_size (regcache
->tdesc
, regno
);
216 if (size
< sizeof (long))
217 collect_register (regcache
, regno
, buf
+ sizeof (long) - size
);
219 collect_register (regcache
, regno
, buf
);
222 perror_with_name ("Unexpected byte order");
226 ppc_supply_ptrace_register (struct regcache
*regcache
,
227 int regno
, const char *buf
)
229 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
231 /* Little-endian values always sit at the left end of the buffer. */
232 supply_register (regcache
, regno
, buf
);
234 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
236 /* Big-endian values sit at the right end of the buffer. In case of
237 registers whose sizes are smaller than sizeof (long), we must use a
238 padding to access them correctly. */
239 int size
= register_size (regcache
->tdesc
, regno
);
241 if (size
< sizeof (long))
242 supply_register (regcache
, regno
, buf
+ sizeof (long) - size
);
244 supply_register (regcache
, regno
, buf
);
247 perror_with_name ("Unexpected byte order");
251 ppc_target::low_supports_breakpoints ()
257 ppc_target::low_get_pc (regcache
*regcache
)
259 if (register_size (regcache
->tdesc
, 0) == 4)
262 collect_register_by_name (regcache
, "pc", &pc
);
263 return (CORE_ADDR
) pc
;
268 collect_register_by_name (regcache
, "pc", &pc
);
269 return (CORE_ADDR
) pc
;
274 ppc_target::low_set_pc (regcache
*regcache
, CORE_ADDR pc
)
276 if (register_size (regcache
->tdesc
, 0) == 4)
278 unsigned int newpc
= pc
;
279 supply_register_by_name (regcache
, "pc", &newpc
);
283 unsigned long newpc
= pc
;
284 supply_register_by_name (regcache
, "pc", &newpc
);
288 #ifndef __powerpc64__
289 static int ppc_regmap_adjusted
;
293 /* Correct in either endianness.
294 This instruction is "twge r2, r2", which GDB uses as a software
296 static const unsigned int ppc_breakpoint
= 0x7d821008;
297 #define ppc_breakpoint_len 4
299 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
301 static const gdb_byte
*
302 ppc_sw_breakpoint_from_kind (int kind
, int *size
)
304 *size
= ppc_breakpoint_len
;
305 return (const gdb_byte
*) &ppc_breakpoint
;
309 ppc_breakpoint_at (CORE_ADDR where
)
313 the_target
->read_memory (where
, (unsigned char *) &insn
, 4);
314 if (insn
== ppc_breakpoint
)
316 /* If necessary, recognize more trap instructions here. GDB only uses
322 /* Implement supports_z_point_type target-ops.
323 Returns true if type Z_TYPE breakpoint is supported.
325 Handling software breakpoint at server side, so tracepoints
326 and breakpoints can be inserted at the same location. */
329 ppc_supports_z_point_type (char z_type
)
336 case Z_PACKET_WRITE_WP
:
337 case Z_PACKET_ACCESS_WP
:
343 /* Implement insert_point target-ops.
344 Returns 0 on success, -1 on failure and 1 on unsupported. */
347 ppc_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
348 int size
, struct raw_breakpoint
*bp
)
352 case raw_bkpt_type_sw
:
353 return insert_memory_breakpoint (bp
);
355 case raw_bkpt_type_hw
:
356 case raw_bkpt_type_write_wp
:
357 case raw_bkpt_type_access_wp
:
364 /* Implement remove_point target-ops.
365 Returns 0 on success, -1 on failure and 1 on unsupported. */
368 ppc_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
369 int size
, struct raw_breakpoint
*bp
)
373 case raw_bkpt_type_sw
:
374 return remove_memory_breakpoint (bp
);
376 case raw_bkpt_type_hw
:
377 case raw_bkpt_type_write_wp
:
378 case raw_bkpt_type_access_wp
:
385 /* Provide only a fill function for the general register set. ps_lgetregs
386 will use this for NPTL support. */
388 static void ppc_fill_gregset (struct regcache
*regcache
, void *buf
)
392 for (i
= 0; i
< 32; i
++)
393 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
395 for (i
= 64; i
< 70; i
++)
396 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
398 for (i
= 71; i
< 73; i
++)
399 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
402 /* Program Priority Register regset fill function. */
405 ppc_fill_pprregset (struct regcache
*regcache
, void *buf
)
407 char *ppr
= (char *) buf
;
409 collect_register_by_name (regcache
, "ppr", ppr
);
412 /* Program Priority Register regset store function. */
415 ppc_store_pprregset (struct regcache
*regcache
, const void *buf
)
417 const char *ppr
= (const char *) buf
;
419 supply_register_by_name (regcache
, "ppr", ppr
);
422 /* Data Stream Control Register regset fill function. */
425 ppc_fill_dscrregset (struct regcache
*regcache
, void *buf
)
427 char *dscr
= (char *) buf
;
429 collect_register_by_name (regcache
, "dscr", dscr
);
432 /* Data Stream Control Register regset store function. */
435 ppc_store_dscrregset (struct regcache
*regcache
, const void *buf
)
437 const char *dscr
= (const char *) buf
;
439 supply_register_by_name (regcache
, "dscr", dscr
);
442 /* Target Address Register regset fill function. */
445 ppc_fill_tarregset (struct regcache
*regcache
, void *buf
)
447 char *tar
= (char *) buf
;
449 collect_register_by_name (regcache
, "tar", tar
);
452 /* Target Address Register regset store function. */
455 ppc_store_tarregset (struct regcache
*regcache
, const void *buf
)
457 const char *tar
= (const char *) buf
;
459 supply_register_by_name (regcache
, "tar", tar
);
462 /* Event-Based Branching regset store function. Unless the inferior
463 has a perf event open, ptrace can return in error when reading and
464 writing to the regset, with ENODATA. For reading, the registers
465 will correctly show as unavailable. For writing, gdbserver
466 currently only caches any register writes from P and G packets and
467 the stub always tries to write all the regsets when resuming the
468 inferior, which would result in frequent warnings. For this
469 reason, we don't define a fill function. This also means that the
470 client-side regcache will be dirty if the user tries to write to
471 the EBB registers. G packets that the client sends to write to
472 unrelated registers will also include data for EBB registers, even
473 if they are unavailable. */
476 ppc_store_ebbregset (struct regcache
*regcache
, const void *buf
)
478 const char *regset
= (const char *) buf
;
480 /* The order in the kernel regset is: EBBRR, EBBHR, BESCR. In the
481 .dat file is BESCR, EBBHR, EBBRR. */
482 supply_register_by_name (regcache
, "ebbrr", ®set
[0]);
483 supply_register_by_name (regcache
, "ebbhr", ®set
[8]);
484 supply_register_by_name (regcache
, "bescr", ®set
[16]);
487 /* Performance Monitoring Unit regset fill function. */
490 ppc_fill_pmuregset (struct regcache
*regcache
, void *buf
)
492 char *regset
= (char *) buf
;
494 /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0.
495 In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */
496 collect_register_by_name (regcache
, "siar", ®set
[0]);
497 collect_register_by_name (regcache
, "sdar", ®set
[8]);
498 collect_register_by_name (regcache
, "sier", ®set
[16]);
499 collect_register_by_name (regcache
, "mmcr2", ®set
[24]);
500 collect_register_by_name (regcache
, "mmcr0", ®set
[32]);
503 /* Performance Monitoring Unit regset store function. */
506 ppc_store_pmuregset (struct regcache
*regcache
, const void *buf
)
508 const char *regset
= (const char *) buf
;
510 supply_register_by_name (regcache
, "siar", ®set
[0]);
511 supply_register_by_name (regcache
, "sdar", ®set
[8]);
512 supply_register_by_name (regcache
, "sier", ®set
[16]);
513 supply_register_by_name (regcache
, "mmcr2", ®set
[24]);
514 supply_register_by_name (regcache
, "mmcr0", ®set
[32]);
517 /* Hardware Transactional Memory special-purpose register regset fill
521 ppc_fill_tm_sprregset (struct regcache
*regcache
, void *buf
)
524 char *regset
= (char *) buf
;
526 base
= find_regno (regcache
->tdesc
, "tfhar");
527 for (i
= 0; i
< 3; i
++)
528 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
531 /* Hardware Transactional Memory special-purpose register regset store
535 ppc_store_tm_sprregset (struct regcache
*regcache
, const void *buf
)
538 const char *regset
= (const char *) buf
;
540 base
= find_regno (regcache
->tdesc
, "tfhar");
541 for (i
= 0; i
< 3; i
++)
542 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
545 /* For the same reasons as the EBB regset, none of the HTM
546 checkpointed regsets have a fill function. These registers are
547 only available if the inferior is in a transaction. */
549 /* Hardware Transactional Memory checkpointed general-purpose regset
553 ppc_store_tm_cgprregset (struct regcache
*regcache
, const void *buf
)
555 int i
, base
, size
, endian_offset
;
556 const char *regset
= (const char *) buf
;
558 base
= find_regno (regcache
->tdesc
, "cr0");
559 size
= register_size (regcache
->tdesc
, base
);
561 gdb_assert (size
== 4 || size
== 8);
563 for (i
= 0; i
< 32; i
++)
564 supply_register (regcache
, base
+ i
, ®set
[i
* size
]);
568 if ((size
== 8) && (__BYTE_ORDER
== __BIG_ENDIAN
))
571 supply_register_by_name (regcache
, "ccr",
572 ®set
[PT_CCR
* size
+ endian_offset
]);
574 supply_register_by_name (regcache
, "cxer",
575 ®set
[PT_XER
* size
+ endian_offset
]);
577 supply_register_by_name (regcache
, "clr", ®set
[PT_LNK
* size
]);
578 supply_register_by_name (regcache
, "cctr", ®set
[PT_CTR
* size
]);
581 /* Hardware Transactional Memory checkpointed floating-point regset
585 ppc_store_tm_cfprregset (struct regcache
*regcache
, const void *buf
)
588 const char *regset
= (const char *) buf
;
590 base
= find_regno (regcache
->tdesc
, "cf0");
592 for (i
= 0; i
< 32; i
++)
593 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
595 supply_register_by_name (regcache
, "cfpscr", ®set
[32 * 8]);
598 /* Hardware Transactional Memory checkpointed vector regset store
602 ppc_store_tm_cvrregset (struct regcache
*regcache
, const void *buf
)
605 const char *regset
= (const char *) buf
;
608 base
= find_regno (regcache
->tdesc
, "cvr0");
610 for (i
= 0; i
< 32; i
++)
611 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
613 if (__BYTE_ORDER
== __BIG_ENDIAN
)
616 supply_register_by_name (regcache
, "cvscr",
617 ®set
[32 * 16 + vscr_offset
]);
619 supply_register_by_name (regcache
, "cvrsave", ®set
[33 * 16]);
622 /* Hardware Transactional Memory checkpointed vector-scalar regset
626 ppc_store_tm_cvsxregset (struct regcache
*regcache
, const void *buf
)
629 const char *regset
= (const char *) buf
;
631 base
= find_regno (regcache
->tdesc
, "cvs0h");
632 for (i
= 0; i
< 32; i
++)
633 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
636 /* Hardware Transactional Memory checkpointed Program Priority
637 Register regset store function. */
640 ppc_store_tm_cpprregset (struct regcache
*regcache
, const void *buf
)
642 const char *cppr
= (const char *) buf
;
644 supply_register_by_name (regcache
, "cppr", cppr
);
647 /* Hardware Transactional Memory checkpointed Data Stream Control
648 Register regset store function. */
651 ppc_store_tm_cdscrregset (struct regcache
*regcache
, const void *buf
)
653 const char *cdscr
= (const char *) buf
;
655 supply_register_by_name (regcache
, "cdscr", cdscr
);
658 /* Hardware Transactional Memory checkpointed Target Address Register
659 regset store function. */
662 ppc_store_tm_ctarregset (struct regcache
*regcache
, const void *buf
)
664 const char *ctar
= (const char *) buf
;
666 supply_register_by_name (regcache
, "ctar", ctar
);
670 ppc_fill_vsxregset (struct regcache
*regcache
, void *buf
)
673 char *regset
= (char *) buf
;
675 base
= find_regno (regcache
->tdesc
, "vs0h");
676 for (i
= 0; i
< 32; i
++)
677 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
681 ppc_store_vsxregset (struct regcache
*regcache
, const void *buf
)
684 const char *regset
= (const char *) buf
;
686 base
= find_regno (regcache
->tdesc
, "vs0h");
687 for (i
= 0; i
< 32; i
++)
688 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
692 ppc_fill_vrregset (struct regcache
*regcache
, void *buf
)
695 char *regset
= (char *) buf
;
698 base
= find_regno (regcache
->tdesc
, "vr0");
699 for (i
= 0; i
< 32; i
++)
700 collect_register (regcache
, base
+ i
, ®set
[i
* 16]);
702 if (__BYTE_ORDER
== __BIG_ENDIAN
)
705 collect_register_by_name (regcache
, "vscr",
706 ®set
[32 * 16 + vscr_offset
]);
708 collect_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
712 ppc_store_vrregset (struct regcache
*regcache
, const void *buf
)
715 const char *regset
= (const char *) buf
;
718 base
= find_regno (regcache
->tdesc
, "vr0");
719 for (i
= 0; i
< 32; i
++)
720 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
722 if (__BYTE_ORDER
== __BIG_ENDIAN
)
725 supply_register_by_name (regcache
, "vscr",
726 ®set
[32 * 16 + vscr_offset
]);
727 supply_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
730 struct gdb_evrregset_t
732 unsigned long evr
[32];
733 unsigned long long acc
;
734 unsigned long spefscr
;
738 ppc_fill_evrregset (struct regcache
*regcache
, void *buf
)
741 struct gdb_evrregset_t
*regset
= (struct gdb_evrregset_t
*) buf
;
743 ev0
= find_regno (regcache
->tdesc
, "ev0h");
744 for (i
= 0; i
< 32; i
++)
745 collect_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
747 collect_register_by_name (regcache
, "acc", ®set
->acc
);
748 collect_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
752 ppc_store_evrregset (struct regcache
*regcache
, const void *buf
)
755 const struct gdb_evrregset_t
*regset
= (const struct gdb_evrregset_t
*) buf
;
757 ev0
= find_regno (regcache
->tdesc
, "ev0h");
758 for (i
= 0; i
< 32; i
++)
759 supply_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
761 supply_register_by_name (regcache
, "acc", ®set
->acc
);
762 supply_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
765 /* Support for hardware single step. */
768 ppc_supports_hardware_single_step (void)
773 static struct regset_info ppc_regsets
[] = {
774 /* List the extra register sets before GENERAL_REGS. That way we will
775 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
776 general registers. Some kernels support these, but not the newer
777 PPC_PTRACE_GETREGS. */
778 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CTAR
, 0, EXTENDED_REGS
,
779 NULL
, ppc_store_tm_ctarregset
},
780 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CDSCR
, 0, EXTENDED_REGS
,
781 NULL
, ppc_store_tm_cdscrregset
},
782 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CPPR
, 0, EXTENDED_REGS
,
783 NULL
, ppc_store_tm_cpprregset
},
784 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVSX
, 0, EXTENDED_REGS
,
785 NULL
, ppc_store_tm_cvsxregset
},
786 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVMX
, 0, EXTENDED_REGS
,
787 NULL
, ppc_store_tm_cvrregset
},
788 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CFPR
, 0, EXTENDED_REGS
,
789 NULL
, ppc_store_tm_cfprregset
},
790 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CGPR
, 0, EXTENDED_REGS
,
791 NULL
, ppc_store_tm_cgprregset
},
792 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_SPR
, 0, EXTENDED_REGS
,
793 ppc_fill_tm_sprregset
, ppc_store_tm_sprregset
},
794 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_EBB
, 0, EXTENDED_REGS
,
795 NULL
, ppc_store_ebbregset
},
796 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PMU
, 0, EXTENDED_REGS
,
797 ppc_fill_pmuregset
, ppc_store_pmuregset
},
798 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TAR
, 0, EXTENDED_REGS
,
799 ppc_fill_tarregset
, ppc_store_tarregset
},
800 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PPR
, 0, EXTENDED_REGS
,
801 ppc_fill_pprregset
, ppc_store_pprregset
},
802 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_DSCR
, 0, EXTENDED_REGS
,
803 ppc_fill_dscrregset
, ppc_store_dscrregset
},
804 { PTRACE_GETVSXREGS
, PTRACE_SETVSXREGS
, 0, 0, EXTENDED_REGS
,
805 ppc_fill_vsxregset
, ppc_store_vsxregset
},
806 { PTRACE_GETVRREGS
, PTRACE_SETVRREGS
, 0, 0, EXTENDED_REGS
,
807 ppc_fill_vrregset
, ppc_store_vrregset
},
808 { PTRACE_GETEVRREGS
, PTRACE_SETEVRREGS
, 0, 0, EXTENDED_REGS
,
809 ppc_fill_evrregset
, ppc_store_evrregset
},
810 { 0, 0, 0, 0, GENERAL_REGS
, ppc_fill_gregset
, NULL
},
814 static struct usrregs_info ppc_usrregs_info
=
820 static struct regsets_info ppc_regsets_info
=
822 ppc_regsets
, /* regsets */
824 NULL
, /* disabled_regsets */
827 static struct regs_info myregs_info
=
829 NULL
, /* regset_bitmap */
835 ppc_target::get_regs_info ()
841 ppc_target::low_arch_setup ()
843 const struct target_desc
*tdesc
;
844 struct regset_info
*regset
;
845 struct ppc_linux_features features
= ppc_linux_no_features
;
847 int tid
= lwpid_of (current_thread
);
849 features
.wordsize
= ppc_linux_target_wordsize (tid
);
851 if (features
.wordsize
== 4)
852 tdesc
= tdesc_powerpc_32l
;
854 tdesc
= tdesc_powerpc_64l
;
856 current_process ()->tdesc
= tdesc
;
858 /* The value of current_process ()->tdesc needs to be set for this
860 ppc_hwcap
= linux_get_hwcap (features
.wordsize
);
861 ppc_hwcap2
= linux_get_hwcap2 (features
.wordsize
);
863 features
.isa205
= ppc_linux_has_isa205 (ppc_hwcap
);
865 if (ppc_hwcap
& PPC_FEATURE_HAS_VSX
)
868 if (ppc_hwcap
& PPC_FEATURE_HAS_ALTIVEC
)
869 features
.altivec
= true;
871 if ((ppc_hwcap2
& PPC_FEATURE2_DSCR
)
872 && ppc_check_regset (tid
, NT_PPC_DSCR
, PPC_LINUX_SIZEOF_DSCRREGSET
)
873 && ppc_check_regset (tid
, NT_PPC_PPR
, PPC_LINUX_SIZEOF_PPRREGSET
))
875 features
.ppr_dscr
= true;
876 if ((ppc_hwcap2
& PPC_FEATURE2_ARCH_2_07
)
877 && (ppc_hwcap2
& PPC_FEATURE2_TAR
)
878 && (ppc_hwcap2
& PPC_FEATURE2_EBB
)
879 && ppc_check_regset (tid
, NT_PPC_TAR
,
880 PPC_LINUX_SIZEOF_TARREGSET
)
881 && ppc_check_regset (tid
, NT_PPC_EBB
,
882 PPC_LINUX_SIZEOF_EBBREGSET
)
883 && ppc_check_regset (tid
, NT_PPC_PMU
,
884 PPC_LINUX_SIZEOF_PMUREGSET
))
886 features
.isa207
= true;
887 if ((ppc_hwcap2
& PPC_FEATURE2_HTM
)
888 && ppc_check_regset (tid
, NT_PPC_TM_SPR
,
889 PPC_LINUX_SIZEOF_TM_SPRREGSET
))
894 tdesc
= ppc_linux_match_description (features
);
896 /* On 32-bit machines, check for SPE registers.
897 Set the low target's regmap field as appropriately. */
898 #ifndef __powerpc64__
899 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
900 tdesc
= tdesc_powerpc_e500l
;
902 if (!ppc_regmap_adjusted
)
904 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
905 ppc_usrregs_info
.regmap
= ppc_regmap_e500
;
907 /* If the FPSCR is 64-bit wide, we need to fetch the whole
908 64-bit slot and not just its second word. The PT_FPSCR
909 supplied in a 32-bit GDB compilation doesn't reflect
911 if (register_size (tdesc
, 70) == 8)
912 ppc_regmap
[70] = (48 + 2*32) * sizeof (long);
914 ppc_regmap_adjusted
= 1;
918 current_process ()->tdesc
= tdesc
;
920 for (regset
= ppc_regsets
; regset
->size
>= 0; regset
++)
921 switch (regset
->get_request
)
923 case PTRACE_GETVRREGS
:
924 regset
->size
= features
.altivec
? PPC_LINUX_SIZEOF_VRREGSET
: 0;
926 case PTRACE_GETVSXREGS
:
927 regset
->size
= features
.vsx
? PPC_LINUX_SIZEOF_VSXREGSET
: 0;
929 case PTRACE_GETEVRREGS
:
930 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
931 regset
->size
= 32 * 4 + 8 + 4;
935 case PTRACE_GETREGSET
:
936 switch (regset
->nt_type
)
939 regset
->size
= (features
.ppr_dscr
?
940 PPC_LINUX_SIZEOF_PPRREGSET
: 0);
943 regset
->size
= (features
.ppr_dscr
?
944 PPC_LINUX_SIZEOF_DSCRREGSET
: 0);
947 regset
->size
= (features
.isa207
?
948 PPC_LINUX_SIZEOF_TARREGSET
: 0);
951 regset
->size
= (features
.isa207
?
952 PPC_LINUX_SIZEOF_EBBREGSET
: 0);
955 regset
->size
= (features
.isa207
?
956 PPC_LINUX_SIZEOF_PMUREGSET
: 0);
959 regset
->size
= (features
.htm
?
960 PPC_LINUX_SIZEOF_TM_SPRREGSET
: 0);
963 if (features
.wordsize
== 4)
964 regset
->size
= (features
.htm
?
965 PPC32_LINUX_SIZEOF_CGPRREGSET
: 0);
967 regset
->size
= (features
.htm
?
968 PPC64_LINUX_SIZEOF_CGPRREGSET
: 0);
971 regset
->size
= (features
.htm
?
972 PPC_LINUX_SIZEOF_CFPRREGSET
: 0);
975 regset
->size
= (features
.htm
?
976 PPC_LINUX_SIZEOF_CVMXREGSET
: 0);
979 regset
->size
= (features
.htm
?
980 PPC_LINUX_SIZEOF_CVSXREGSET
: 0);
983 regset
->size
= (features
.htm
?
984 PPC_LINUX_SIZEOF_CPPRREGSET
: 0);
986 case NT_PPC_TM_CDSCR
:
987 regset
->size
= (features
.htm
?
988 PPC_LINUX_SIZEOF_CDSCRREGSET
: 0);
991 regset
->size
= (features
.htm
?
992 PPC_LINUX_SIZEOF_CTARREGSET
: 0);
1003 /* Implementation of linux_target_ops method "supports_tracepoints". */
1006 ppc_supports_tracepoints (void)
1011 /* Get the thread area address. This is used to recognize which
1012 thread is which when tracing with the in-process agent library. We
1013 don't read anything from the address, and treat it as opaque; it's
1014 the address itself that we assume is unique per-thread. */
1017 ppc_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
1019 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
1020 struct thread_info
*thr
= get_lwp_thread (lwp
);
1021 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
1024 #ifdef __powerpc64__
1025 if (register_size (regcache
->tdesc
, 0) == 8)
1026 collect_register_by_name (regcache
, "r13", &tp
);
1029 collect_register_by_name (regcache
, "r2", &tp
);
1036 #ifdef __powerpc64__
1038 /* Older glibc doesn't provide this. */
1040 #ifndef EF_PPC64_ABI
1041 #define EF_PPC64_ABI 3
1044 /* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
1048 is_elfv2_inferior (void)
1050 /* To be used as fallback if we're unable to determine the right result -
1051 assume inferior uses the same ABI as gdbserver. */
1053 const int def_res
= 1;
1055 const int def_res
= 0;
1060 const struct target_desc
*tdesc
= current_process ()->tdesc
;
1061 int wordsize
= register_size (tdesc
, 0);
1063 if (!linux_get_auxv (wordsize
, AT_PHDR
, &phdr
))
1066 /* Assume ELF header is at the beginning of the page where program headers
1067 are located. If it doesn't look like one, bail. */
1069 read_inferior_memory (phdr
& ~0xfff, (unsigned char *) &ehdr
, sizeof ehdr
);
1070 if (memcmp(ehdr
.e_ident
, ELFMAG
, SELFMAG
))
1073 return (ehdr
.e_flags
& EF_PPC64_ABI
) == 2;
1078 /* Generate a ds-form instruction in BUF and return the number of bytes written
1081 | OPCD | RST | RA | DS |XO| */
1083 __attribute__((unused
)) /* Maybe unused due to conditional compilation. */
1085 gen_ds_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int ds
, int xo
)
1089 gdb_assert ((opcd
& ~0x3f) == 0);
1090 gdb_assert ((rst
& ~0x1f) == 0);
1091 gdb_assert ((ra
& ~0x1f) == 0);
1092 gdb_assert ((xo
& ~0x3) == 0);
1094 insn
= (rst
<< 21) | (ra
<< 16) | (ds
& 0xfffc) | (xo
& 0x3);
1095 *buf
= (opcd
<< 26) | insn
;
1099 /* Followings are frequently used ds-form instructions. */
1101 #define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
1102 #define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
1103 #define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
1104 #define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
1106 /* Generate a d-form instruction in BUF.
1109 | OPCD | RST | RA | D | */
1112 gen_d_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int si
)
1116 gdb_assert ((opcd
& ~0x3f) == 0);
1117 gdb_assert ((rst
& ~0x1f) == 0);
1118 gdb_assert ((ra
& ~0x1f) == 0);
1120 insn
= (rst
<< 21) | (ra
<< 16) | (si
& 0xffff);
1121 *buf
= (opcd
<< 26) | insn
;
1125 /* Followings are frequently used d-form instructions. */
1127 #define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
1128 #define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
1129 #define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
1130 #define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
1131 #define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
1132 #define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
1133 #define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
1134 #define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
1135 #define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
1137 /* Generate a xfx-form instruction in BUF and return the number of bytes
1141 | OPCD | RST | RI | XO |/| */
1144 gen_xfx_form (uint32_t *buf
, int opcd
, int rst
, int ri
, int xo
)
1147 unsigned int n
= ((ri
& 0x1f) << 5) | ((ri
>> 5) & 0x1f);
1149 gdb_assert ((opcd
& ~0x3f) == 0);
1150 gdb_assert ((rst
& ~0x1f) == 0);
1151 gdb_assert ((xo
& ~0x3ff) == 0);
1153 insn
= (rst
<< 21) | (n
<< 11) | (xo
<< 1);
1154 *buf
= (opcd
<< 26) | insn
;
1158 /* Followings are frequently used xfx-form instructions. */
1160 #define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
1161 #define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
1162 #define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
1163 #define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
1164 #define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
1166 #define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
1169 /* Generate a x-form instruction in BUF and return the number of bytes written.
1172 | OPCD | RST | RA | RB | XO |RC| */
1175 gen_x_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int rb
, int xo
, int rc
)
1179 gdb_assert ((opcd
& ~0x3f) == 0);
1180 gdb_assert ((rst
& ~0x1f) == 0);
1181 gdb_assert ((ra
& ~0x1f) == 0);
1182 gdb_assert ((rb
& ~0x1f) == 0);
1183 gdb_assert ((xo
& ~0x3ff) == 0);
1184 gdb_assert ((rc
& ~1) == 0);
1186 insn
= (rst
<< 21) | (ra
<< 16) | (rb
<< 11) | (xo
<< 1) | rc
;
1187 *buf
= (opcd
<< 26) | insn
;
1191 /* Followings are frequently used x-form instructions. */
1193 #define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
1194 #define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
1195 #define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
1196 #define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
1197 /* Assume bf = cr7. */
1198 #define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
1201 /* Generate a md-form instruction in BUF and return the number of bytes written.
1203 0 6 11 16 21 27 30 31 32
1204 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
1207 gen_md_form (uint32_t *buf
, int opcd
, int rs
, int ra
, int sh
, int mb
,
1211 unsigned int n
= ((mb
& 0x1f) << 1) | ((mb
>> 5) & 0x1);
1212 unsigned int sh0_4
= sh
& 0x1f;
1213 unsigned int sh5
= (sh
>> 5) & 1;
1215 gdb_assert ((opcd
& ~0x3f) == 0);
1216 gdb_assert ((rs
& ~0x1f) == 0);
1217 gdb_assert ((ra
& ~0x1f) == 0);
1218 gdb_assert ((sh
& ~0x3f) == 0);
1219 gdb_assert ((mb
& ~0x3f) == 0);
1220 gdb_assert ((xo
& ~0x7) == 0);
1221 gdb_assert ((rc
& ~0x1) == 0);
1223 insn
= (rs
<< 21) | (ra
<< 16) | (sh0_4
<< 11) | (n
<< 5)
1224 | (sh5
<< 1) | (xo
<< 2) | (rc
& 1);
1225 *buf
= (opcd
<< 26) | insn
;
1229 /* The following are frequently used md-form instructions. */
1231 #define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1232 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1233 #define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1234 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1236 /* Generate a i-form instruction in BUF and return the number of bytes written.
1239 | OPCD | LI |AA|LK| */
1242 gen_i_form (uint32_t *buf
, int opcd
, int li
, int aa
, int lk
)
1246 gdb_assert ((opcd
& ~0x3f) == 0);
1248 insn
= (li
& 0x3fffffc) | (aa
& 1) | (lk
& 1);
1249 *buf
= (opcd
<< 26) | insn
;
1253 /* The following are frequently used i-form instructions. */
1255 #define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1256 #define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1258 /* Generate a b-form instruction in BUF and return the number of bytes written.
1261 | OPCD | BO | BI | BD |AA|LK| */
1264 gen_b_form (uint32_t *buf
, int opcd
, int bo
, int bi
, int bd
,
1269 gdb_assert ((opcd
& ~0x3f) == 0);
1270 gdb_assert ((bo
& ~0x1f) == 0);
1271 gdb_assert ((bi
& ~0x1f) == 0);
1273 insn
= (bo
<< 21) | (bi
<< 16) | (bd
& 0xfffc) | (aa
& 1) | (lk
& 1);
1274 *buf
= (opcd
<< 26) | insn
;
1278 /* The following are frequently used b-form instructions. */
1279 /* Assume bi = cr7. */
1280 #define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1282 /* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1283 respectively. They are primary used for save/restore GPRs in jump-pad,
1284 not used for bytecode compiling. */
1286 #ifdef __powerpc64__
1287 #define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1288 GEN_LD (buf, rt, ra, si) : \
1289 GEN_LWZ (buf, rt, ra, si))
1290 #define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1291 GEN_STD (buf, rt, ra, si) : \
1292 GEN_STW (buf, rt, ra, si))
1294 #define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1295 #define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1298 /* Generate a sequence of instructions to load IMM in the register REG.
1299 Write the instructions in BUF and return the number of bytes written. */
1302 gen_limm (uint32_t *buf
, int reg
, uint64_t imm
, int is_64
)
1306 if ((imm
+ 32768) < 65536)
1308 /* li reg, imm[15:0] */
1309 p
+= GEN_LI (p
, reg
, imm
);
1311 else if ((imm
>> 32) == 0)
1313 /* lis reg, imm[31:16]
1314 ori reg, reg, imm[15:0]
1315 rldicl reg, reg, 0, 32 */
1316 p
+= GEN_LIS (p
, reg
, (imm
>> 16) & 0xffff);
1317 if ((imm
& 0xffff) != 0)
1318 p
+= GEN_ORI (p
, reg
, reg
, imm
& 0xffff);
1319 /* Clear upper 32-bit if sign-bit is set. */
1320 if (imm
& (1u << 31) && is_64
)
1321 p
+= GEN_RLDICL (p
, reg
, reg
, 0, 32);
1326 /* lis reg, <imm[63:48]>
1327 ori reg, reg, <imm[48:32]>
1328 rldicr reg, reg, 32, 31
1329 oris reg, reg, <imm[31:16]>
1330 ori reg, reg, <imm[15:0]> */
1331 p
+= GEN_LIS (p
, reg
, ((imm
>> 48) & 0xffff));
1332 if (((imm
>> 32) & 0xffff) != 0)
1333 p
+= GEN_ORI (p
, reg
, reg
, ((imm
>> 32) & 0xffff));
1334 p
+= GEN_RLDICR (p
, reg
, reg
, 32, 31);
1335 if (((imm
>> 16) & 0xffff) != 0)
1336 p
+= GEN_ORIS (p
, reg
, reg
, ((imm
>> 16) & 0xffff));
1337 if ((imm
& 0xffff) != 0)
1338 p
+= GEN_ORI (p
, reg
, reg
, (imm
& 0xffff));
1344 /* Generate a sequence for atomically exchange at location LOCK.
1345 This code sequence clobbers r6, r7, r8. LOCK is the location for
1346 the atomic-xchg, OLD_VALUE is expected old value stored in the
1347 location, and R_NEW is a register for the new value. */
1350 gen_atomic_xchg (uint32_t *buf
, CORE_ADDR lock
, int old_value
, int r_new
,
1353 const int r_lock
= 6;
1354 const int r_old
= 7;
1355 const int r_tmp
= 8;
1359 1: lwarx TMP, 0, LOCK
1365 p
+= gen_limm (p
, r_lock
, lock
, is_64
);
1366 p
+= gen_limm (p
, r_old
, old_value
, is_64
);
1368 p
+= GEN_LWARX (p
, r_tmp
, 0, r_lock
);
1369 p
+= GEN_CMPW (p
, r_tmp
, r_old
);
1370 p
+= GEN_BNE (p
, -8);
1371 p
+= GEN_STWCX (p
, r_new
, 0, r_lock
);
1372 p
+= GEN_BNE (p
, -16);
1377 /* Generate a sequence of instructions for calling a function
1378 at address of FN. Return the number of bytes are written in BUF. */
1381 gen_call (uint32_t *buf
, CORE_ADDR fn
, int is_64
, int is_opd
)
1385 /* Must be called by r12 for caller to calculate TOC address. */
1386 p
+= gen_limm (p
, 12, fn
, is_64
);
1389 p
+= GEN_LOAD (p
, 11, 12, 16, is_64
);
1390 p
+= GEN_LOAD (p
, 2, 12, 8, is_64
);
1391 p
+= GEN_LOAD (p
, 12, 12, 0, is_64
);
1393 p
+= GEN_MTSPR (p
, 12, 9); /* mtctr r12 */
1394 *p
++ = 0x4e800421; /* bctrl */
1399 /* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1400 of instruction. This function is used to adjust pc-relative instructions
1404 ppc_relocate_instruction (CORE_ADDR
*to
, CORE_ADDR oldloc
)
1409 read_inferior_memory (oldloc
, (unsigned char *) &insn
, 4);
1410 op6
= PPC_OP6 (insn
);
1412 if (op6
== 18 && (insn
& 2) == 0)
1414 /* branch && AA = 0 */
1415 rel
= PPC_LI (insn
);
1416 newrel
= (oldloc
- *to
) + rel
;
1418 /* Out of range. Cannot relocate instruction. */
1419 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1422 insn
= (insn
& ~0x3fffffc) | (newrel
& 0x3fffffc);
1424 else if (op6
== 16 && (insn
& 2) == 0)
1426 /* conditional branch && AA = 0 */
1428 /* If the new relocation is too big for even a 26-bit unconditional
1429 branch, there is nothing we can do. Just abort.
1431 Otherwise, if it can be fit in 16-bit conditional branch, just
1432 copy the instruction and relocate the address.
1434 If the it's big for conditional-branch (16-bit), try to invert the
1435 condition and jump with 26-bit branch. For example,
1446 After this transform, we are actually jump from *TO+4 instead of *TO,
1447 so check the relocation again because it will be 1-insn farther then
1448 before if *TO is after OLDLOC.
1451 For BDNZT (or so) is transformed from
1463 See also "BO field encodings". */
1465 rel
= PPC_BD (insn
);
1466 newrel
= (oldloc
- *to
) + rel
;
1468 if (newrel
< (1 << 15) && newrel
>= -(1 << 15))
1469 insn
= (insn
& ~0xfffc) | (newrel
& 0xfffc);
1470 else if ((PPC_BO (insn
) & 0x14) == 0x4 || (PPC_BO (insn
) & 0x14) == 0x10)
1474 /* Out of range. Cannot relocate instruction. */
1475 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1478 if ((PPC_BO (insn
) & 0x14) == 0x4)
1480 else if ((PPC_BO (insn
) & 0x14) == 0x10)
1483 /* Jump over the unconditional branch. */
1484 insn
= (insn
& ~0xfffc) | 0x8;
1485 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1488 /* Build a unconditional branch and copy LK bit. */
1489 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1490 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1495 else if ((PPC_BO (insn
) & 0x14) == 0)
1497 uint32_t bdnz_insn
= (16 << 26) | (0x10 << 21) | 12;
1498 uint32_t bf_insn
= (16 << 26) | (0x4 << 21) | 8;
1502 /* Out of range. Cannot relocate instruction. */
1503 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1506 /* Copy BI field. */
1507 bf_insn
|= (insn
& 0x1f0000);
1509 /* Invert condition. */
1510 bdnz_insn
|= (insn
^ (1 << 22)) & (1 << 22);
1511 bf_insn
|= (insn
^ (1 << 24)) & (1 << 24);
1513 target_write_memory (*to
, (unsigned char *) &bdnz_insn
, 4);
1515 target_write_memory (*to
, (unsigned char *) &bf_insn
, 4);
1518 /* Build a unconditional branch and copy LK bit. */
1519 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1520 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1525 else /* (BO & 0x14) == 0x14, branch always. */
1527 /* Out of range. Cannot relocate instruction. */
1528 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1531 /* Build a unconditional branch and copy LK bit. */
1532 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1533 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1540 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1544 /* Implement install_fast_tracepoint_jump_pad of target_ops.
1545 See target.h for details. */
1548 ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1549 CORE_ADDR collector
,
1552 CORE_ADDR
*jump_entry
,
1553 CORE_ADDR
*trampoline
,
1554 ULONGEST
*trampoline_size
,
1555 unsigned char *jjump_pad_insn
,
1556 ULONGEST
*jjump_pad_insn_size
,
1557 CORE_ADDR
*adjusted_insn_addr
,
1558 CORE_ADDR
*adjusted_insn_addr_end
,
1564 CORE_ADDR buildaddr
= *jump_entry
;
1565 const CORE_ADDR entryaddr
= *jump_entry
;
1566 int rsz
, min_frame
, frame_size
, tp_reg
;
1567 #ifdef __powerpc64__
1568 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
1569 int is_64
= register_size (regcache
->tdesc
, 0) == 8;
1570 int is_opd
= is_64
&& !is_elfv2_inferior ();
1572 int is_64
= 0, is_opd
= 0;
1575 #ifdef __powerpc64__
1578 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1581 frame_size
= (40 * rsz
) + min_frame
;
1589 frame_size
= (40 * rsz
) + min_frame
;
1591 #ifdef __powerpc64__
1595 /* Stack frame layout for this jump pad,
1597 High thread_area (r13/r2) |
1598 tpoint - collecting_t obj
1608 R0 - collected registers
1614 The code flow of this jump pad,
1619 4. Call gdb_collector
1620 5. Restore GPR and SPR
1622 7. Build a jump for back to the program
1623 8. Copy/relocate original instruction
1624 9. Build a jump for replacing original instruction. */
1626 /* Adjust stack pointer. */
1628 p
+= GEN_STDU (p
, 1, 1, -frame_size
); /* stdu r1,-frame_size(r1) */
1630 p
+= GEN_STWU (p
, 1, 1, -frame_size
); /* stwu r1,-frame_size(r1) */
1632 /* Store GPRs. Save R1 later, because it had just been modified, but
1633 we want the original value. */
1634 for (j
= 2; j
< 32; j
++)
1635 p
+= GEN_STORE (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1636 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1637 /* Set r0 to the original value of r1 before adjusting stack frame,
1638 and then save it. */
1639 p
+= GEN_ADDI (p
, 0, 1, frame_size
);
1640 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 1 * rsz
, is_64
);
1642 /* Save CR, XER, LR, and CTR. */
1643 p
+= GEN_MFCR (p
, 3); /* mfcr r3 */
1644 p
+= GEN_MFSPR (p
, 4, 1); /* mfxer r4 */
1645 p
+= GEN_MFSPR (p
, 5, 8); /* mflr r5 */
1646 p
+= GEN_MFSPR (p
, 6, 9); /* mfctr r6 */
1647 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
);/* std r3, 32(r1) */
1648 p
+= GEN_STORE (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
);/* std r4, 33(r1) */
1649 p
+= GEN_STORE (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
);/* std r5, 34(r1) */
1650 p
+= GEN_STORE (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
);/* std r6, 35(r1) */
1652 /* Save PC<tpaddr> */
1653 p
+= gen_limm (p
, 3, tpaddr
, is_64
);
1654 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 36 * rsz
, is_64
);
1657 /* Setup arguments to collector. */
1658 /* Set r4 to collected registers. */
1659 p
+= GEN_ADDI (p
, 4, 1, min_frame
);
1660 /* Set r3 to TPOINT. */
1661 p
+= gen_limm (p
, 3, tpoint
, is_64
);
1663 /* Prepare collecting_t object for lock. */
1664 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 37 * rsz
, is_64
);
1665 p
+= GEN_STORE (p
, tp_reg
, 1, min_frame
+ 38 * rsz
, is_64
);
1666 /* Set R5 to collecting object. */
1667 p
+= GEN_ADDI (p
, 5, 1, 37 * rsz
);
1669 p
+= GEN_LWSYNC (p
);
1670 p
+= gen_atomic_xchg (p
, lockaddr
, 0, 5, is_64
);
1671 p
+= GEN_LWSYNC (p
);
1673 /* Call to collector. */
1674 p
+= gen_call (p
, collector
, is_64
, is_opd
);
1676 /* Simply write 0 to release the lock. */
1677 p
+= gen_limm (p
, 3, lockaddr
, is_64
);
1678 p
+= gen_limm (p
, 4, 0, is_64
);
1679 p
+= GEN_LWSYNC (p
);
1680 p
+= GEN_STORE (p
, 4, 3, 0, is_64
);
1682 /* Restore stack and registers. */
1683 p
+= GEN_LOAD (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
); /* ld r3, 32(r1) */
1684 p
+= GEN_LOAD (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
); /* ld r4, 33(r1) */
1685 p
+= GEN_LOAD (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
); /* ld r5, 34(r1) */
1686 p
+= GEN_LOAD (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
); /* ld r6, 35(r1) */
1687 p
+= GEN_MTCR (p
, 3); /* mtcr r3 */
1688 p
+= GEN_MTSPR (p
, 4, 1); /* mtxer r4 */
1689 p
+= GEN_MTSPR (p
, 5, 8); /* mtlr r5 */
1690 p
+= GEN_MTSPR (p
, 6, 9); /* mtctr r6 */
1693 for (j
= 2; j
< 32; j
++)
1694 p
+= GEN_LOAD (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1695 p
+= GEN_LOAD (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1697 p
+= GEN_ADDI (p
, 1, 1, frame_size
);
1699 /* Flush instructions to inferior memory. */
1700 target_write_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1702 /* Now, insert the original instruction to execute in the jump pad. */
1703 *adjusted_insn_addr
= buildaddr
+ (p
- buf
) * 4;
1704 *adjusted_insn_addr_end
= *adjusted_insn_addr
;
1705 ppc_relocate_instruction (adjusted_insn_addr_end
, tpaddr
);
1707 /* Verify the relocation size. If should be 4 for normal copy,
1708 8 or 12 for some conditional branch. */
1709 if ((*adjusted_insn_addr_end
- *adjusted_insn_addr
== 0)
1710 || (*adjusted_insn_addr_end
- *adjusted_insn_addr
> 12))
1712 sprintf (err
, "E.Unexpected instruction length = %d"
1713 "when relocate instruction.",
1714 (int) (*adjusted_insn_addr_end
- *adjusted_insn_addr
));
1718 buildaddr
= *adjusted_insn_addr_end
;
1720 /* Finally, write a jump back to the program. */
1721 offset
= (tpaddr
+ 4) - buildaddr
;
1722 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1724 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1725 "(offset 0x%x > 26-bit).", offset
);
1729 p
+= GEN_B (p
, offset
);
1730 target_write_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1731 *jump_entry
= buildaddr
+ (p
- buf
) * 4;
1733 /* The jump pad is now built. Wire in a jump to our jump pad. This
1734 is always done last (by our caller actually), so that we can
1735 install fast tracepoints with threads running. This relies on
1736 the agent's atomic write support. */
1737 offset
= entryaddr
- tpaddr
;
1738 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1740 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1741 "(offset 0x%x > 26-bit).", offset
);
1745 GEN_B ((uint32_t *) jjump_pad_insn
, offset
);
1746 *jjump_pad_insn_size
= 4;
1751 /* Returns the minimum instruction length for installing a tracepoint. */
1754 ppc_get_min_fast_tracepoint_insn_len (void)
1759 /* Emits a given buffer into the target at current_insn_ptr. Length
1760 is in units of 32-bit words. */
1763 emit_insns (uint32_t *buf
, int n
)
1765 n
= n
* sizeof (uint32_t);
1766 target_write_memory (current_insn_ptr
, (unsigned char *) buf
, n
);
1767 current_insn_ptr
+= n
;
1770 #define __EMIT_ASM(NAME, INSNS) \
1773 extern uint32_t start_bcax_ ## NAME []; \
1774 extern uint32_t end_bcax_ ## NAME []; \
1775 emit_insns (start_bcax_ ## NAME, \
1776 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1777 __asm__ (".section .text.__ppcbcax\n\t" \
1778 "start_bcax_" #NAME ":\n\t" \
1780 "end_bcax_" #NAME ":\n\t" \
1784 #define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1785 #define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1789 Bytecode execution stack frame - 32-bit
1791 | LR save area (SP + 4)
1792 SP' -> +- Back chain (SP + 0)
1793 | Save r31 for access saved arguments
1794 | Save r30 for bytecode stack pointer
1795 | Save r4 for incoming argument *value
1796 | Save r3 for incoming argument regs
1797 r30 -> +- Bytecode execution stack
1799 | 64-byte (8 doublewords) at initial.
1800 | Expand stack as needed.
1803 | Some padding for minimum stack frame and 16-byte alignment.
1805 SP +- Back-chain (SP')
1811 r30 is the stack-pointer for bytecode machine.
1812 It should point to next-empty, so we can use LDU for pop.
1813 r3 is used for cache of the high part of TOP value.
1814 It was the first argument, pointer to regs.
1815 r4 is used for cache of the low part of TOP value.
1816 It was the second argument, pointer to the result.
1817 We should set *result = TOP after leaving this function.
1820 * To restore stack at epilogue
1822 * To check stack is big enough for bytecode execution.
1824 * To return execution result.
1829 /* Regardless of endian, register 3 is always high part, 4 is low part.
1830 These defines are used when the register pair is stored/loaded.
1831 Likewise, to simplify code, have a similiar define for 5:6. */
1833 #if __BYTE_ORDER == __LITTLE_ENDIAN
1834 #define TOP_FIRST "4"
1835 #define TOP_SECOND "3"
1836 #define TMP_FIRST "6"
1837 #define TMP_SECOND "5"
1839 #define TOP_FIRST "3"
1840 #define TOP_SECOND "4"
1841 #define TMP_FIRST "5"
1842 #define TMP_SECOND "6"
1845 /* Emit prologue in inferior memory. See above comments. */
1848 ppc_emit_prologue (void)
1850 EMIT_ASM (/* Save return address. */
1853 /* Adjust SP. 96 is the initial frame size. */
1855 /* Save r30 and incoming arguments. */
1856 "stw 31, 96-4(1) \n"
1857 "stw 30, 96-8(1) \n"
1858 "stw 4, 96-12(1) \n"
1859 "stw 3, 96-16(1) \n"
1860 /* Point r31 to original r1 for access arguments. */
1862 /* Set r30 to pointing stack-top. */
1864 /* Initial r3/TOP to 0. */
1869 /* Emit epilogue in inferior memory. See above comments. */
1872 ppc_emit_epilogue (void)
1874 EMIT_ASM (/* *result = TOP */
1876 "stw " TOP_FIRST
", 0(5) \n"
1877 "stw " TOP_SECOND
", 4(5) \n"
1878 /* Restore registers. */
1885 /* Return 0 for no-error. */
1891 /* TOP = stack[--sp] + TOP */
1896 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1897 "lwz " TMP_SECOND
", 4(30)\n"
1902 /* TOP = stack[--sp] - TOP */
1907 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1908 "lwz " TMP_SECOND
", 4(30) \n"
1910 "subfe 3, 3, 5 \n");
1913 /* TOP = stack[--sp] * TOP */
1918 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1919 "lwz " TMP_SECOND
", 4(30) \n"
1928 /* TOP = stack[--sp] << TOP */
1933 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1934 "lwz " TMP_SECOND
", 4(30) \n"
1935 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1936 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1937 "slw 5, 5, 4\n" /* Shift high part left */
1938 "slw 4, 6, 4\n" /* Shift low part left */
1939 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1940 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1942 "or 3, 7, 3\n"); /* Assemble high part */
1945 /* Top = stack[--sp] >> TOP
1946 (Arithmetic shift right) */
1949 ppc_emit_rsh_signed (void)
1951 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1952 "lwz " TMP_SECOND
", 4(30) \n"
1953 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1954 "sraw 3, 5, 4\n" /* Shift high part right */
1956 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
1957 "sraw 4, 5, 7\n" /* Shift high to low */
1960 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
1961 "srw 4, 6, 4\n" /* Shift low part right */
1962 "slw 5, 5, 7\n" /* Shift high to low */
1963 "or 4, 4, 5\n" /* Assemble low part */
1967 /* Top = stack[--sp] >> TOP
1968 (Logical shift right) */
1971 ppc_emit_rsh_unsigned (void)
1973 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1974 "lwz " TMP_SECOND
", 4(30) \n"
1975 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1976 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1977 "srw 6, 6, 4\n" /* Shift low part right */
1978 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
1979 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
1981 "srw 3, 5, 4\n" /* Shift high part right */
1982 "or 4, 6, 7\n"); /* Assemble low part */
1985 /* Emit code for signed-extension specified by ARG. */
1988 ppc_emit_ext (int arg
)
1993 EMIT_ASM ("extsb 4, 4\n"
1997 EMIT_ASM ("extsh 4, 4\n"
2001 EMIT_ASM ("srawi 3, 4, 31");
2008 /* Emit code for zero-extension specified by ARG. */
2011 ppc_emit_zero_ext (int arg
)
2016 EMIT_ASM ("clrlwi 4,4,24\n"
2020 EMIT_ASM ("clrlwi 4,4,16\n"
2024 EMIT_ASM ("li 3, 0");
2032 i.e., TOP = (TOP == 0) ? 1 : 0; */
2035 ppc_emit_log_not (void)
2037 EMIT_ASM ("or 4, 3, 4 \n"
2043 /* TOP = stack[--sp] & TOP */
2046 ppc_emit_bit_and (void)
2048 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2049 "lwz " TMP_SECOND
", 4(30) \n"
2054 /* TOP = stack[--sp] | TOP */
2057 ppc_emit_bit_or (void)
2059 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2060 "lwz " TMP_SECOND
", 4(30) \n"
2065 /* TOP = stack[--sp] ^ TOP */
2068 ppc_emit_bit_xor (void)
2070 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2071 "lwz " TMP_SECOND
", 4(30) \n"
2077 i.e., TOP = ~(TOP | TOP) */
2080 ppc_emit_bit_not (void)
2082 EMIT_ASM ("nor 3, 3, 3 \n"
2086 /* TOP = stack[--sp] == TOP */
2089 ppc_emit_equal (void)
2091 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2092 "lwz " TMP_SECOND
", 4(30) \n"
2101 /* TOP = stack[--sp] < TOP
2102 (Signed comparison) */
2105 ppc_emit_less_signed (void)
2107 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2108 "lwz " TMP_SECOND
", 4(30) \n"
2111 /* CR6 bit 0 = low less and high equal */
2112 "crand 6*4+0, 6*4+0, 7*4+2\n"
2113 /* CR7 bit 0 = (low less and high equal) or high less */
2114 "cror 7*4+0, 7*4+0, 6*4+0\n"
2116 "rlwinm 4, 4, 29, 31, 31 \n"
2120 /* TOP = stack[--sp] < TOP
2121 (Unsigned comparison) */
2124 ppc_emit_less_unsigned (void)
2126 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2127 "lwz " TMP_SECOND
", 4(30) \n"
2130 /* CR6 bit 0 = low less and high equal */
2131 "crand 6*4+0, 6*4+0, 7*4+2\n"
2132 /* CR7 bit 0 = (low less and high equal) or high less */
2133 "cror 7*4+0, 7*4+0, 6*4+0\n"
2135 "rlwinm 4, 4, 29, 31, 31 \n"
2139 /* Access the memory address in TOP in size of SIZE.
2140 Zero-extend the read value. */
2143 ppc_emit_ref (int size
)
2148 EMIT_ASM ("lbz 4, 0(4)\n"
2152 EMIT_ASM ("lhz 4, 0(4)\n"
2156 EMIT_ASM ("lwz 4, 0(4)\n"
2160 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2161 EMIT_ASM ("lwz 3, 4(4)\n"
2164 EMIT_ASM ("lwz 3, 0(4)\n"
2173 ppc_emit_const (LONGEST num
)
2178 p
+= gen_limm (p
, 3, num
>> 32 & 0xffffffff, 0);
2179 p
+= gen_limm (p
, 4, num
& 0xffffffff, 0);
2181 emit_insns (buf
, p
- buf
);
2182 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2185 /* Set TOP to the value of register REG by calling get_raw_reg function
2186 with two argument, collected buffer and register number. */
2189 ppc_emit_reg (int reg
)
2194 /* fctx->regs is passed in r3 and then saved in -16(31). */
2195 p
+= GEN_LWZ (p
, 3, 31, -16);
2196 p
+= GEN_LI (p
, 4, reg
); /* li r4, reg */
2197 p
+= gen_call (p
, get_raw_reg_func_addr (), 0, 0);
2199 emit_insns (buf
, p
- buf
);
2200 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2202 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2204 EMIT_ASM ("mr 5, 4\n"
2210 /* TOP = stack[--sp] */
2215 EMIT_ASM ("lwzu " TOP_FIRST
", 8(30) \n"
2216 "lwz " TOP_SECOND
", 4(30) \n");
2219 /* stack[sp++] = TOP
2221 Because we may use up bytecode stack, expand 8 doublewords more
2225 ppc_emit_stack_flush (void)
2227 /* Make sure bytecode stack is big enough before push.
2228 Otherwise, expand 64-byte more. */
2230 EMIT_ASM (" stw " TOP_FIRST
", 0(30) \n"
2231 " stw " TOP_SECOND
", 4(30)\n"
2232 " addi 5, 30, -(8 + 8) \n"
2235 " stwu 31, -64(1) \n"
2236 "1:addi 30, 30, -8 \n");
2239 /* Swap TOP and stack[sp-1] */
2242 ppc_emit_swap (void)
2244 EMIT_ASM ("lwz " TMP_FIRST
", 8(30) \n"
2245 "lwz " TMP_SECOND
", 12(30) \n"
2246 "stw " TOP_FIRST
", 8(30) \n"
2247 "stw " TOP_SECOND
", 12(30) \n"
2252 /* Discard N elements in the stack. Also used for ppc64. */
2255 ppc_emit_stack_adjust (int n
)
2267 p
+= GEN_ADDI (p
, 30, 30, n
);
2269 emit_insns (buf
, p
- buf
);
2270 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2273 /* Call function FN. */
2276 ppc_emit_call (CORE_ADDR fn
)
2281 p
+= gen_call (p
, fn
, 0, 0);
2283 emit_insns (buf
, p
- buf
);
2284 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2287 /* FN's prototype is `LONGEST(*fn)(int)'.
2292 ppc_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2297 /* Setup argument. arg1 is a 16-bit value. */
2298 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2299 p
+= gen_call (p
, fn
, 0, 0);
2301 emit_insns (buf
, p
- buf
);
2302 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2304 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2306 EMIT_ASM ("mr 5, 4\n"
2312 /* FN's prototype is `void(*fn)(int,LONGEST)'.
2315 TOP should be preserved/restored before/after the call. */
2318 ppc_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2323 /* Save TOP. 0(30) is next-empty. */
2324 p
+= GEN_STW (p
, 3, 30, 0);
2325 p
+= GEN_STW (p
, 4, 30, 4);
2327 /* Setup argument. arg1 is a 16-bit value. */
2328 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2330 p
+= GEN_MR (p
, 5, 4);
2331 p
+= GEN_MR (p
, 6, 3);
2335 p
+= GEN_MR (p
, 5, 3);
2336 p
+= GEN_MR (p
, 6, 4);
2338 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2339 p
+= gen_call (p
, fn
, 0, 0);
2342 p
+= GEN_LWZ (p
, 3, 30, 0);
2343 p
+= GEN_LWZ (p
, 4, 30, 4);
2345 emit_insns (buf
, p
- buf
);
2346 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2349 /* Note in the following goto ops:
2351 When emitting goto, the target address is later relocated by
2352 write_goto_address. OFFSET_P is the offset of the branch instruction
2353 in the code sequence, and SIZE_P is how to relocate the instruction,
2354 recognized by ppc_write_goto_address. In current implementation,
2355 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2358 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2361 ppc_emit_if_goto (int *offset_p
, int *size_p
)
2363 EMIT_ASM ("or. 3, 3, 4 \n"
2364 "lwzu " TOP_FIRST
", 8(30) \n"
2365 "lwz " TOP_SECOND
", 4(30) \n"
2374 /* Unconditional goto. Also used for ppc64. */
2377 ppc_emit_goto (int *offset_p
, int *size_p
)
2379 EMIT_ASM ("1:b 1b");
2387 /* Goto if stack[--sp] == TOP */
2390 ppc_emit_eq_goto (int *offset_p
, int *size_p
)
2392 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2393 "lwz " TMP_SECOND
", 4(30) \n"
2397 "lwzu " TOP_FIRST
", 8(30) \n"
2398 "lwz " TOP_SECOND
", 4(30) \n"
2407 /* Goto if stack[--sp] != TOP */
2410 ppc_emit_ne_goto (int *offset_p
, int *size_p
)
2412 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2413 "lwz " TMP_SECOND
", 4(30) \n"
2417 "lwzu " TOP_FIRST
", 8(30) \n"
2418 "lwz " TOP_SECOND
", 4(30) \n"
2427 /* Goto if stack[--sp] < TOP */
2430 ppc_emit_lt_goto (int *offset_p
, int *size_p
)
2432 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2433 "lwz " TMP_SECOND
", 4(30) \n"
2436 /* CR6 bit 0 = low less and high equal */
2437 "crand 6*4+0, 6*4+0, 7*4+2\n"
2438 /* CR7 bit 0 = (low less and high equal) or high less */
2439 "cror 7*4+0, 7*4+0, 6*4+0\n"
2440 "lwzu " TOP_FIRST
", 8(30) \n"
2441 "lwz " TOP_SECOND
", 4(30)\n"
2450 /* Goto if stack[--sp] <= TOP */
2453 ppc_emit_le_goto (int *offset_p
, int *size_p
)
2455 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2456 "lwz " TMP_SECOND
", 4(30) \n"
2459 /* CR6 bit 0 = low less/equal and high equal */
2460 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2461 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2462 "cror 7*4+0, 7*4+0, 6*4+0\n"
2463 "lwzu " TOP_FIRST
", 8(30) \n"
2464 "lwz " TOP_SECOND
", 4(30)\n"
2473 /* Goto if stack[--sp] > TOP */
2476 ppc_emit_gt_goto (int *offset_p
, int *size_p
)
2478 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2479 "lwz " TMP_SECOND
", 4(30) \n"
2482 /* CR6 bit 0 = low greater and high equal */
2483 "crand 6*4+0, 6*4+1, 7*4+2\n"
2484 /* CR7 bit 0 = (low greater and high equal) or high greater */
2485 "cror 7*4+0, 7*4+1, 6*4+0\n"
2486 "lwzu " TOP_FIRST
", 8(30) \n"
2487 "lwz " TOP_SECOND
", 4(30)\n"
2496 /* Goto if stack[--sp] >= TOP */
2499 ppc_emit_ge_goto (int *offset_p
, int *size_p
)
2501 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2502 "lwz " TMP_SECOND
", 4(30) \n"
2505 /* CR6 bit 0 = low ge and high equal */
2506 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2507 /* CR7 bit 0 = (low ge and high equal) or high greater */
2508 "cror 7*4+0, 7*4+1, 6*4+0\n"
2509 "lwzu " TOP_FIRST
", 8(30)\n"
2510 "lwz " TOP_SECOND
", 4(30)\n"
2519 /* Relocate previous emitted branch instruction. FROM is the address
2520 of the branch instruction, TO is the goto target address, and SIZE
2521 if the value we set by *SIZE_P before. Currently, it is either
2522 24 or 14 of branch and conditional-branch instruction.
2523 Also used for ppc64. */
2526 ppc_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2528 long rel
= to
- from
;
2532 read_inferior_memory (from
, (unsigned char *) &insn
, 4);
2533 opcd
= (insn
>> 26) & 0x3f;
2539 || (rel
>= (1 << 15) || rel
< -(1 << 15)))
2541 insn
= (insn
& ~0xfffc) | (rel
& 0xfffc);
2545 || (rel
>= (1 << 25) || rel
< -(1 << 25)))
2547 insn
= (insn
& ~0x3fffffc) | (rel
& 0x3fffffc);
2554 target_write_memory (from
, (unsigned char *) &insn
, 4);
2557 /* Table of emit ops for 32-bit. */
2559 static struct emit_ops ppc_emit_ops_impl
=
2567 ppc_emit_rsh_signed
,
2568 ppc_emit_rsh_unsigned
,
2576 ppc_emit_less_signed
,
2577 ppc_emit_less_unsigned
,
2581 ppc_write_goto_address
,
2586 ppc_emit_stack_flush
,
2589 ppc_emit_stack_adjust
,
2590 ppc_emit_int_call_1
,
2591 ppc_emit_void_call_2
,
2600 #ifdef __powerpc64__
2604 Bytecode execution stack frame - 64-bit
2606 | LR save area (SP + 16)
2607 | CR save area (SP + 8)
2608 SP' -> +- Back chain (SP + 0)
2609 | Save r31 for access saved arguments
2610 | Save r30 for bytecode stack pointer
2611 | Save r4 for incoming argument *value
2612 | Save r3 for incoming argument regs
2613 r30 -> +- Bytecode execution stack
2615 | 64-byte (8 doublewords) at initial.
2616 | Expand stack as needed.
2619 | Some padding for minimum stack frame.
2621 SP +- Back-chain (SP')
2624 = 112 + (4 * 8) + 64
2627 r30 is the stack-pointer for bytecode machine.
2628 It should point to next-empty, so we can use LDU for pop.
2629 r3 is used for cache of TOP value.
2630 It was the first argument, pointer to regs.
2631 r4 is the second argument, pointer to the result.
2632 We should set *result = TOP after leaving this function.
2635 * To restore stack at epilogue
2637 * To check stack is big enough for bytecode execution.
2638 => r30 - 8 > SP + 112
2639 * To return execution result.
2644 /* Emit prologue in inferior memory. See above comments. */
2647 ppc64v1_emit_prologue (void)
2649 /* On ELFv1, function pointers really point to function descriptor,
2650 so emit one here. We don't care about contents of words 1 and 2,
2651 so let them just overlap out code. */
2652 uint64_t opd
= current_insn_ptr
+ 8;
2655 /* Mind the strict aliasing rules. */
2656 memcpy (buf
, &opd
, sizeof buf
);
2658 EMIT_ASM (/* Save return address. */
2661 /* Save r30 and incoming arguments. */
2666 /* Point r31 to current r1 for access arguments. */
2668 /* Adjust SP. 208 is the initial frame size. */
2669 "stdu 1, -208(1) \n"
2670 /* Set r30 to pointing stack-top. */
2671 "addi 30, 1, 168 \n"
2672 /* Initial r3/TOP to 0. */
2676 /* Emit prologue in inferior memory. See above comments. */
2679 ppc64v2_emit_prologue (void)
2681 EMIT_ASM (/* Save return address. */
2684 /* Save r30 and incoming arguments. */
2689 /* Point r31 to current r1 for access arguments. */
2691 /* Adjust SP. 208 is the initial frame size. */
2692 "stdu 1, -208(1) \n"
2693 /* Set r30 to pointing stack-top. */
2694 "addi 30, 1, 168 \n"
2695 /* Initial r3/TOP to 0. */
2699 /* Emit epilogue in inferior memory. See above comments. */
2702 ppc64_emit_epilogue (void)
2704 EMIT_ASM (/* Restore SP. */
2709 /* Restore registers. */
2714 /* Return 0 for no-error. */
2720 /* TOP = stack[--sp] + TOP */
2723 ppc64_emit_add (void)
2725 EMIT_ASM ("ldu 4, 8(30) \n"
2729 /* TOP = stack[--sp] - TOP */
2732 ppc64_emit_sub (void)
2734 EMIT_ASM ("ldu 4, 8(30) \n"
2738 /* TOP = stack[--sp] * TOP */
2741 ppc64_emit_mul (void)
2743 EMIT_ASM ("ldu 4, 8(30) \n"
2744 "mulld 3, 4, 3 \n");
2747 /* TOP = stack[--sp] << TOP */
2750 ppc64_emit_lsh (void)
2752 EMIT_ASM ("ldu 4, 8(30) \n"
2756 /* Top = stack[--sp] >> TOP
2757 (Arithmetic shift right) */
2760 ppc64_emit_rsh_signed (void)
2762 EMIT_ASM ("ldu 4, 8(30) \n"
2766 /* Top = stack[--sp] >> TOP
2767 (Logical shift right) */
2770 ppc64_emit_rsh_unsigned (void)
2772 EMIT_ASM ("ldu 4, 8(30) \n"
2776 /* Emit code for signed-extension specified by ARG. */
2779 ppc64_emit_ext (int arg
)
2784 EMIT_ASM ("extsb 3, 3");
2787 EMIT_ASM ("extsh 3, 3");
2790 EMIT_ASM ("extsw 3, 3");
2797 /* Emit code for zero-extension specified by ARG. */
2800 ppc64_emit_zero_ext (int arg
)
2805 EMIT_ASM ("rldicl 3,3,0,56");
2808 EMIT_ASM ("rldicl 3,3,0,48");
2811 EMIT_ASM ("rldicl 3,3,0,32");
2819 i.e., TOP = (TOP == 0) ? 1 : 0; */
2822 ppc64_emit_log_not (void)
2824 EMIT_ASM ("cntlzd 3, 3 \n"
2828 /* TOP = stack[--sp] & TOP */
2831 ppc64_emit_bit_and (void)
2833 EMIT_ASM ("ldu 4, 8(30) \n"
2837 /* TOP = stack[--sp] | TOP */
2840 ppc64_emit_bit_or (void)
2842 EMIT_ASM ("ldu 4, 8(30) \n"
2846 /* TOP = stack[--sp] ^ TOP */
2849 ppc64_emit_bit_xor (void)
2851 EMIT_ASM ("ldu 4, 8(30) \n"
2856 i.e., TOP = ~(TOP | TOP) */
2859 ppc64_emit_bit_not (void)
2861 EMIT_ASM ("nor 3, 3, 3 \n");
2864 /* TOP = stack[--sp] == TOP */
2867 ppc64_emit_equal (void)
2869 EMIT_ASM ("ldu 4, 8(30) \n"
2875 /* TOP = stack[--sp] < TOP
2876 (Signed comparison) */
2879 ppc64_emit_less_signed (void)
2881 EMIT_ASM ("ldu 4, 8(30) \n"
2884 "rlwinm 3, 3, 29, 31, 31 \n");
2887 /* TOP = stack[--sp] < TOP
2888 (Unsigned comparison) */
2891 ppc64_emit_less_unsigned (void)
2893 EMIT_ASM ("ldu 4, 8(30) \n"
2896 "rlwinm 3, 3, 29, 31, 31 \n");
2899 /* Access the memory address in TOP in size of SIZE.
2900 Zero-extend the read value. */
2903 ppc64_emit_ref (int size
)
2908 EMIT_ASM ("lbz 3, 0(3)");
2911 EMIT_ASM ("lhz 3, 0(3)");
2914 EMIT_ASM ("lwz 3, 0(3)");
2917 EMIT_ASM ("ld 3, 0(3)");
2925 ppc64_emit_const (LONGEST num
)
2930 p
+= gen_limm (p
, 3, num
, 1);
2932 emit_insns (buf
, p
- buf
);
2933 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2936 /* Set TOP to the value of register REG by calling get_raw_reg function
2937 with two argument, collected buffer and register number. */
2940 ppc64v1_emit_reg (int reg
)
2945 /* fctx->regs is passed in r3 and then saved in 176(1). */
2946 p
+= GEN_LD (p
, 3, 31, -32);
2947 p
+= GEN_LI (p
, 4, reg
);
2948 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2949 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 1);
2950 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2952 emit_insns (buf
, p
- buf
);
2953 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2956 /* Likewise, for ELFv2. */
2959 ppc64v2_emit_reg (int reg
)
2964 /* fctx->regs is passed in r3 and then saved in 176(1). */
2965 p
+= GEN_LD (p
, 3, 31, -32);
2966 p
+= GEN_LI (p
, 4, reg
);
2967 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2968 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 0);
2969 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2971 emit_insns (buf
, p
- buf
);
2972 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2975 /* TOP = stack[--sp] */
2978 ppc64_emit_pop (void)
2980 EMIT_ASM ("ldu 3, 8(30)");
2983 /* stack[sp++] = TOP
2985 Because we may use up bytecode stack, expand 8 doublewords more
2989 ppc64_emit_stack_flush (void)
2991 /* Make sure bytecode stack is big enough before push.
2992 Otherwise, expand 64-byte more. */
2994 EMIT_ASM (" std 3, 0(30) \n"
2995 " addi 4, 30, -(112 + 8) \n"
2998 " stdu 31, -64(1) \n"
2999 "1:addi 30, 30, -8 \n");
3002 /* Swap TOP and stack[sp-1] */
3005 ppc64_emit_swap (void)
3007 EMIT_ASM ("ld 4, 8(30) \n"
3012 /* Call function FN - ELFv1. */
3015 ppc64v1_emit_call (CORE_ADDR fn
)
3020 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3021 p
+= gen_call (p
, fn
, 1, 1);
3022 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3024 emit_insns (buf
, p
- buf
);
3025 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3028 /* Call function FN - ELFv2. */
3031 ppc64v2_emit_call (CORE_ADDR fn
)
3036 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3037 p
+= gen_call (p
, fn
, 1, 0);
3038 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3040 emit_insns (buf
, p
- buf
);
3041 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3044 /* FN's prototype is `LONGEST(*fn)(int)'.
3049 ppc64v1_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3054 /* Setup argument. arg1 is a 16-bit value. */
3055 p
+= gen_limm (p
, 3, arg1
, 1);
3056 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3057 p
+= gen_call (p
, fn
, 1, 1);
3058 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3060 emit_insns (buf
, p
- buf
);
3061 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3064 /* Likewise for ELFv2. */
3067 ppc64v2_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3072 /* Setup argument. arg1 is a 16-bit value. */
3073 p
+= gen_limm (p
, 3, arg1
, 1);
3074 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3075 p
+= gen_call (p
, fn
, 1, 0);
3076 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3078 emit_insns (buf
, p
- buf
);
3079 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3082 /* FN's prototype is `void(*fn)(int,LONGEST)'.
3085 TOP should be preserved/restored before/after the call. */
3088 ppc64v1_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3093 /* Save TOP. 0(30) is next-empty. */
3094 p
+= GEN_STD (p
, 3, 30, 0);
3096 /* Setup argument. arg1 is a 16-bit value. */
3097 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3098 p
+= gen_limm (p
, 3, arg1
, 1);
3099 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3100 p
+= gen_call (p
, fn
, 1, 1);
3101 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3104 p
+= GEN_LD (p
, 3, 30, 0);
3106 emit_insns (buf
, p
- buf
);
3107 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3110 /* Likewise for ELFv2. */
3113 ppc64v2_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3118 /* Save TOP. 0(30) is next-empty. */
3119 p
+= GEN_STD (p
, 3, 30, 0);
3121 /* Setup argument. arg1 is a 16-bit value. */
3122 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3123 p
+= gen_limm (p
, 3, arg1
, 1);
3124 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3125 p
+= gen_call (p
, fn
, 1, 0);
3126 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3129 p
+= GEN_LD (p
, 3, 30, 0);
3131 emit_insns (buf
, p
- buf
);
3132 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3135 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
3138 ppc64_emit_if_goto (int *offset_p
, int *size_p
)
3140 EMIT_ASM ("cmpdi 7, 3, 0 \n"
3150 /* Goto if stack[--sp] == TOP */
3153 ppc64_emit_eq_goto (int *offset_p
, int *size_p
)
3155 EMIT_ASM ("ldu 4, 8(30) \n"
3166 /* Goto if stack[--sp] != TOP */
3169 ppc64_emit_ne_goto (int *offset_p
, int *size_p
)
3171 EMIT_ASM ("ldu 4, 8(30) \n"
3182 /* Goto if stack[--sp] < TOP */
3185 ppc64_emit_lt_goto (int *offset_p
, int *size_p
)
3187 EMIT_ASM ("ldu 4, 8(30) \n"
3198 /* Goto if stack[--sp] <= TOP */
3201 ppc64_emit_le_goto (int *offset_p
, int *size_p
)
3203 EMIT_ASM ("ldu 4, 8(30) \n"
3214 /* Goto if stack[--sp] > TOP */
3217 ppc64_emit_gt_goto (int *offset_p
, int *size_p
)
3219 EMIT_ASM ("ldu 4, 8(30) \n"
3230 /* Goto if stack[--sp] >= TOP */
3233 ppc64_emit_ge_goto (int *offset_p
, int *size_p
)
3235 EMIT_ASM ("ldu 4, 8(30) \n"
3246 /* Table of emit ops for 64-bit ELFv1. */
3248 static struct emit_ops ppc64v1_emit_ops_impl
=
3250 ppc64v1_emit_prologue
,
3251 ppc64_emit_epilogue
,
3256 ppc64_emit_rsh_signed
,
3257 ppc64_emit_rsh_unsigned
,
3265 ppc64_emit_less_signed
,
3266 ppc64_emit_less_unsigned
,
3270 ppc_write_goto_address
,
3275 ppc64_emit_stack_flush
,
3276 ppc64_emit_zero_ext
,
3278 ppc_emit_stack_adjust
,
3279 ppc64v1_emit_int_call_1
,
3280 ppc64v1_emit_void_call_2
,
3289 /* Table of emit ops for 64-bit ELFv2. */
3291 static struct emit_ops ppc64v2_emit_ops_impl
=
3293 ppc64v2_emit_prologue
,
3294 ppc64_emit_epilogue
,
3299 ppc64_emit_rsh_signed
,
3300 ppc64_emit_rsh_unsigned
,
3308 ppc64_emit_less_signed
,
3309 ppc64_emit_less_unsigned
,
3313 ppc_write_goto_address
,
3318 ppc64_emit_stack_flush
,
3319 ppc64_emit_zero_ext
,
3321 ppc_emit_stack_adjust
,
3322 ppc64v2_emit_int_call_1
,
3323 ppc64v2_emit_void_call_2
,
3334 /* Implementation of linux_target_ops method "emit_ops". */
3336 static struct emit_ops
*
3339 #ifdef __powerpc64__
3340 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3342 if (register_size (regcache
->tdesc
, 0) == 8)
3344 if (is_elfv2_inferior ())
3345 return &ppc64v2_emit_ops_impl
;
3347 return &ppc64v1_emit_ops_impl
;
3350 return &ppc_emit_ops_impl
;
3353 /* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3356 ppc_get_ipa_tdesc_idx (void)
3358 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3359 const struct target_desc
*tdesc
= regcache
->tdesc
;
3361 #ifdef __powerpc64__
3362 if (tdesc
== tdesc_powerpc_64l
)
3363 return PPC_TDESC_BASE
;
3364 if (tdesc
== tdesc_powerpc_altivec64l
)
3365 return PPC_TDESC_ALTIVEC
;
3366 if (tdesc
== tdesc_powerpc_vsx64l
)
3367 return PPC_TDESC_VSX
;
3368 if (tdesc
== tdesc_powerpc_isa205_64l
)
3369 return PPC_TDESC_ISA205
;
3370 if (tdesc
== tdesc_powerpc_isa205_altivec64l
)
3371 return PPC_TDESC_ISA205_ALTIVEC
;
3372 if (tdesc
== tdesc_powerpc_isa205_vsx64l
)
3373 return PPC_TDESC_ISA205_VSX
;
3374 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx64l
)
3375 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3376 if (tdesc
== tdesc_powerpc_isa207_vsx64l
)
3377 return PPC_TDESC_ISA207_VSX
;
3378 if (tdesc
== tdesc_powerpc_isa207_htm_vsx64l
)
3379 return PPC_TDESC_ISA207_HTM_VSX
;
3382 if (tdesc
== tdesc_powerpc_32l
)
3383 return PPC_TDESC_BASE
;
3384 if (tdesc
== tdesc_powerpc_altivec32l
)
3385 return PPC_TDESC_ALTIVEC
;
3386 if (tdesc
== tdesc_powerpc_vsx32l
)
3387 return PPC_TDESC_VSX
;
3388 if (tdesc
== tdesc_powerpc_isa205_32l
)
3389 return PPC_TDESC_ISA205
;
3390 if (tdesc
== tdesc_powerpc_isa205_altivec32l
)
3391 return PPC_TDESC_ISA205_ALTIVEC
;
3392 if (tdesc
== tdesc_powerpc_isa205_vsx32l
)
3393 return PPC_TDESC_ISA205_VSX
;
3394 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx32l
)
3395 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3396 if (tdesc
== tdesc_powerpc_isa207_vsx32l
)
3397 return PPC_TDESC_ISA207_VSX
;
3398 if (tdesc
== tdesc_powerpc_isa207_htm_vsx32l
)
3399 return PPC_TDESC_ISA207_HTM_VSX
;
3400 if (tdesc
== tdesc_powerpc_e500l
)
3401 return PPC_TDESC_E500
;
3406 struct linux_target_ops the_low_target
= {
3407 ppc_sw_breakpoint_from_kind
,
3411 ppc_supports_z_point_type
,
3416 ppc_collect_ptrace_register
,
3417 ppc_supply_ptrace_register
,
3418 NULL
, /* siginfo_fixup */
3419 NULL
, /* new_process */
3420 NULL
, /* delete_process */
3421 NULL
, /* new_thread */
3422 NULL
, /* delete_thread */
3423 NULL
, /* new_fork */
3424 NULL
, /* prepare_to_resume */
3425 NULL
, /* process_qsupported */
3426 ppc_supports_tracepoints
,
3427 ppc_get_thread_area
,
3428 ppc_install_fast_tracepoint_jump_pad
,
3430 ppc_get_min_fast_tracepoint_insn_len
,
3431 NULL
, /* supports_range_stepping */
3432 ppc_supports_hardware_single_step
,
3433 NULL
, /* get_syscall_trapinfo */
3434 ppc_get_ipa_tdesc_idx
,
3437 /* The linux target ops object. */
3439 linux_process_target
*the_linux_target
= &the_ppc_target
;
3442 initialize_low_arch (void)
3444 /* Initialize the Linux target descriptions. */
3446 init_registers_powerpc_32l ();
3447 init_registers_powerpc_altivec32l ();
3448 init_registers_powerpc_vsx32l ();
3449 init_registers_powerpc_isa205_32l ();
3450 init_registers_powerpc_isa205_altivec32l ();
3451 init_registers_powerpc_isa205_vsx32l ();
3452 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
3453 init_registers_powerpc_isa207_vsx32l ();
3454 init_registers_powerpc_isa207_htm_vsx32l ();
3455 init_registers_powerpc_e500l ();
3457 init_registers_powerpc_64l ();
3458 init_registers_powerpc_altivec64l ();
3459 init_registers_powerpc_vsx64l ();
3460 init_registers_powerpc_isa205_64l ();
3461 init_registers_powerpc_isa205_altivec64l ();
3462 init_registers_powerpc_isa205_vsx64l ();
3463 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
3464 init_registers_powerpc_isa207_vsx64l ();
3465 init_registers_powerpc_isa207_htm_vsx64l ();
3468 initialize_regsets_info (&ppc_regsets_info
);