1 /* GNU/Linux/PowerPC specific low level interface, for the remote server for
3 Copyright (C) 1995-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "linux-low.h"
23 #include "elf/common.h"
26 #include <asm/ptrace.h>
28 #include "arch/ppc-linux-common.h"
29 #include "arch/ppc-linux-tdesc.h"
30 #include "nat/ppc-linux.h"
31 #include "nat/linux-ptrace.h"
32 #include "linux-ppc-tdesc-init.h"
34 #include "tracepoint.h"
36 #define PPC_FIELD(value, from, len) \
37 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
38 #define PPC_SEXT(v, bs) \
39 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
40 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
41 - ((CORE_ADDR) 1 << ((bs) - 1)))
42 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
43 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
44 #define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
45 #define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
47 /* Linux target op definitions for the PowerPC architecture. */
49 class ppc_target
: public linux_process_target
53 const regs_info
*get_regs_info () override
;
57 void low_arch_setup () override
;
60 /* The singleton target ops object. */
62 static ppc_target the_ppc_target
;
64 /* Holds the AT_HWCAP auxv entry. */
66 static unsigned long ppc_hwcap
;
68 /* Holds the AT_HWCAP2 auxv entry. */
70 static unsigned long ppc_hwcap2
;
73 #define ppc_num_regs 73
76 /* We use a constant for FPSCR instead of PT_FPSCR, because
77 many shipped PPC64 kernels had the wrong value in ptrace.h. */
78 static int ppc_regmap
[] =
79 {PT_R0
* 8, PT_R1
* 8, PT_R2
* 8, PT_R3
* 8,
80 PT_R4
* 8, PT_R5
* 8, PT_R6
* 8, PT_R7
* 8,
81 PT_R8
* 8, PT_R9
* 8, PT_R10
* 8, PT_R11
* 8,
82 PT_R12
* 8, PT_R13
* 8, PT_R14
* 8, PT_R15
* 8,
83 PT_R16
* 8, PT_R17
* 8, PT_R18
* 8, PT_R19
* 8,
84 PT_R20
* 8, PT_R21
* 8, PT_R22
* 8, PT_R23
* 8,
85 PT_R24
* 8, PT_R25
* 8, PT_R26
* 8, PT_R27
* 8,
86 PT_R28
* 8, PT_R29
* 8, PT_R30
* 8, PT_R31
* 8,
87 PT_FPR0
*8, PT_FPR0
*8 + 8, PT_FPR0
*8+16, PT_FPR0
*8+24,
88 PT_FPR0
*8+32, PT_FPR0
*8+40, PT_FPR0
*8+48, PT_FPR0
*8+56,
89 PT_FPR0
*8+64, PT_FPR0
*8+72, PT_FPR0
*8+80, PT_FPR0
*8+88,
90 PT_FPR0
*8+96, PT_FPR0
*8+104, PT_FPR0
*8+112, PT_FPR0
*8+120,
91 PT_FPR0
*8+128, PT_FPR0
*8+136, PT_FPR0
*8+144, PT_FPR0
*8+152,
92 PT_FPR0
*8+160, PT_FPR0
*8+168, PT_FPR0
*8+176, PT_FPR0
*8+184,
93 PT_FPR0
*8+192, PT_FPR0
*8+200, PT_FPR0
*8+208, PT_FPR0
*8+216,
94 PT_FPR0
*8+224, PT_FPR0
*8+232, PT_FPR0
*8+240, PT_FPR0
*8+248,
95 PT_NIP
* 8, PT_MSR
* 8, PT_CCR
* 8, PT_LNK
* 8,
96 PT_CTR
* 8, PT_XER
* 8, PT_FPR0
*8 + 256,
97 PT_ORIG_R3
* 8, PT_TRAP
* 8 };
99 /* Currently, don't check/send MQ. */
100 static int ppc_regmap
[] =
101 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
102 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
103 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
104 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
105 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
106 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
107 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
108 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
109 PT_FPR0
*4, PT_FPR0
*4 + 8, PT_FPR0
*4+16, PT_FPR0
*4+24,
110 PT_FPR0
*4+32, PT_FPR0
*4+40, PT_FPR0
*4+48, PT_FPR0
*4+56,
111 PT_FPR0
*4+64, PT_FPR0
*4+72, PT_FPR0
*4+80, PT_FPR0
*4+88,
112 PT_FPR0
*4+96, PT_FPR0
*4+104, PT_FPR0
*4+112, PT_FPR0
*4+120,
113 PT_FPR0
*4+128, PT_FPR0
*4+136, PT_FPR0
*4+144, PT_FPR0
*4+152,
114 PT_FPR0
*4+160, PT_FPR0
*4+168, PT_FPR0
*4+176, PT_FPR0
*4+184,
115 PT_FPR0
*4+192, PT_FPR0
*4+200, PT_FPR0
*4+208, PT_FPR0
*4+216,
116 PT_FPR0
*4+224, PT_FPR0
*4+232, PT_FPR0
*4+240, PT_FPR0
*4+248,
117 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
118 PT_CTR
* 4, PT_XER
* 4, PT_FPSCR
* 4,
119 PT_ORIG_R3
* 4, PT_TRAP
* 4
122 static int ppc_regmap_e500
[] =
123 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
124 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
125 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
126 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
127 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
128 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
129 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
130 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
139 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
140 PT_CTR
* 4, PT_XER
* 4, -1,
141 PT_ORIG_R3
* 4, PT_TRAP
* 4
145 /* Check whether the kernel provides a register set with number
146 REGSET_ID of size REGSETSIZE for process/thread TID. */
149 ppc_check_regset (int tid
, int regset_id
, int regsetsize
)
151 void *buf
= alloca (regsetsize
);
155 iov
.iov_len
= regsetsize
;
157 if (ptrace (PTRACE_GETREGSET
, tid
, regset_id
, &iov
) >= 0
164 ppc_cannot_store_register (int regno
)
166 const struct target_desc
*tdesc
= current_process ()->tdesc
;
168 #ifndef __powerpc64__
169 /* Some kernels do not allow us to store fpscr. */
170 if (!(ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
171 && regno
== find_regno (tdesc
, "fpscr"))
175 /* Some kernels do not allow us to store orig_r3 or trap. */
176 if (regno
== find_regno (tdesc
, "orig_r3")
177 || regno
== find_regno (tdesc
, "trap"))
184 ppc_cannot_fetch_register (int regno
)
190 ppc_collect_ptrace_register (struct regcache
*regcache
, int regno
, char *buf
)
192 memset (buf
, 0, sizeof (long));
194 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
196 /* Little-endian values always sit at the left end of the buffer. */
197 collect_register (regcache
, regno
, buf
);
199 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
201 /* Big-endian values sit at the right end of the buffer. In case of
202 registers whose sizes are smaller than sizeof (long), we must use a
203 padding to access them correctly. */
204 int size
= register_size (regcache
->tdesc
, regno
);
206 if (size
< sizeof (long))
207 collect_register (regcache
, regno
, buf
+ sizeof (long) - size
);
209 collect_register (regcache
, regno
, buf
);
212 perror_with_name ("Unexpected byte order");
216 ppc_supply_ptrace_register (struct regcache
*regcache
,
217 int regno
, const char *buf
)
219 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
221 /* Little-endian values always sit at the left end of the buffer. */
222 supply_register (regcache
, regno
, buf
);
224 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
226 /* Big-endian values sit at the right end of the buffer. In case of
227 registers whose sizes are smaller than sizeof (long), we must use a
228 padding to access them correctly. */
229 int size
= register_size (regcache
->tdesc
, regno
);
231 if (size
< sizeof (long))
232 supply_register (regcache
, regno
, buf
+ sizeof (long) - size
);
234 supply_register (regcache
, regno
, buf
);
237 perror_with_name ("Unexpected byte order");
241 ppc_get_pc (struct regcache
*regcache
)
243 if (register_size (regcache
->tdesc
, 0) == 4)
246 collect_register_by_name (regcache
, "pc", &pc
);
247 return (CORE_ADDR
) pc
;
252 collect_register_by_name (regcache
, "pc", &pc
);
253 return (CORE_ADDR
) pc
;
258 ppc_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
260 if (register_size (regcache
->tdesc
, 0) == 4)
262 unsigned int newpc
= pc
;
263 supply_register_by_name (regcache
, "pc", &newpc
);
267 unsigned long newpc
= pc
;
268 supply_register_by_name (regcache
, "pc", &newpc
);
272 #ifndef __powerpc64__
273 static int ppc_regmap_adjusted
;
277 /* Correct in either endianness.
278 This instruction is "twge r2, r2", which GDB uses as a software
280 static const unsigned int ppc_breakpoint
= 0x7d821008;
281 #define ppc_breakpoint_len 4
283 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
285 static const gdb_byte
*
286 ppc_sw_breakpoint_from_kind (int kind
, int *size
)
288 *size
= ppc_breakpoint_len
;
289 return (const gdb_byte
*) &ppc_breakpoint
;
293 ppc_breakpoint_at (CORE_ADDR where
)
297 the_target
->read_memory (where
, (unsigned char *) &insn
, 4);
298 if (insn
== ppc_breakpoint
)
300 /* If necessary, recognize more trap instructions here. GDB only uses
306 /* Implement supports_z_point_type target-ops.
307 Returns true if type Z_TYPE breakpoint is supported.
309 Handling software breakpoint at server side, so tracepoints
310 and breakpoints can be inserted at the same location. */
313 ppc_supports_z_point_type (char z_type
)
320 case Z_PACKET_WRITE_WP
:
321 case Z_PACKET_ACCESS_WP
:
327 /* Implement insert_point target-ops.
328 Returns 0 on success, -1 on failure and 1 on unsupported. */
331 ppc_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
332 int size
, struct raw_breakpoint
*bp
)
336 case raw_bkpt_type_sw
:
337 return insert_memory_breakpoint (bp
);
339 case raw_bkpt_type_hw
:
340 case raw_bkpt_type_write_wp
:
341 case raw_bkpt_type_access_wp
:
348 /* Implement remove_point target-ops.
349 Returns 0 on success, -1 on failure and 1 on unsupported. */
352 ppc_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
353 int size
, struct raw_breakpoint
*bp
)
357 case raw_bkpt_type_sw
:
358 return remove_memory_breakpoint (bp
);
360 case raw_bkpt_type_hw
:
361 case raw_bkpt_type_write_wp
:
362 case raw_bkpt_type_access_wp
:
369 /* Provide only a fill function for the general register set. ps_lgetregs
370 will use this for NPTL support. */
372 static void ppc_fill_gregset (struct regcache
*regcache
, void *buf
)
376 for (i
= 0; i
< 32; i
++)
377 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
379 for (i
= 64; i
< 70; i
++)
380 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
382 for (i
= 71; i
< 73; i
++)
383 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
386 /* Program Priority Register regset fill function. */
389 ppc_fill_pprregset (struct regcache
*regcache
, void *buf
)
391 char *ppr
= (char *) buf
;
393 collect_register_by_name (regcache
, "ppr", ppr
);
396 /* Program Priority Register regset store function. */
399 ppc_store_pprregset (struct regcache
*regcache
, const void *buf
)
401 const char *ppr
= (const char *) buf
;
403 supply_register_by_name (regcache
, "ppr", ppr
);
406 /* Data Stream Control Register regset fill function. */
409 ppc_fill_dscrregset (struct regcache
*regcache
, void *buf
)
411 char *dscr
= (char *) buf
;
413 collect_register_by_name (regcache
, "dscr", dscr
);
416 /* Data Stream Control Register regset store function. */
419 ppc_store_dscrregset (struct regcache
*regcache
, const void *buf
)
421 const char *dscr
= (const char *) buf
;
423 supply_register_by_name (regcache
, "dscr", dscr
);
426 /* Target Address Register regset fill function. */
429 ppc_fill_tarregset (struct regcache
*regcache
, void *buf
)
431 char *tar
= (char *) buf
;
433 collect_register_by_name (regcache
, "tar", tar
);
436 /* Target Address Register regset store function. */
439 ppc_store_tarregset (struct regcache
*regcache
, const void *buf
)
441 const char *tar
= (const char *) buf
;
443 supply_register_by_name (regcache
, "tar", tar
);
446 /* Event-Based Branching regset store function. Unless the inferior
447 has a perf event open, ptrace can return in error when reading and
448 writing to the regset, with ENODATA. For reading, the registers
449 will correctly show as unavailable. For writing, gdbserver
450 currently only caches any register writes from P and G packets and
451 the stub always tries to write all the regsets when resuming the
452 inferior, which would result in frequent warnings. For this
453 reason, we don't define a fill function. This also means that the
454 client-side regcache will be dirty if the user tries to write to
455 the EBB registers. G packets that the client sends to write to
456 unrelated registers will also include data for EBB registers, even
457 if they are unavailable. */
460 ppc_store_ebbregset (struct regcache
*regcache
, const void *buf
)
462 const char *regset
= (const char *) buf
;
464 /* The order in the kernel regset is: EBBRR, EBBHR, BESCR. In the
465 .dat file is BESCR, EBBHR, EBBRR. */
466 supply_register_by_name (regcache
, "ebbrr", ®set
[0]);
467 supply_register_by_name (regcache
, "ebbhr", ®set
[8]);
468 supply_register_by_name (regcache
, "bescr", ®set
[16]);
471 /* Performance Monitoring Unit regset fill function. */
474 ppc_fill_pmuregset (struct regcache
*regcache
, void *buf
)
476 char *regset
= (char *) buf
;
478 /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0.
479 In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */
480 collect_register_by_name (regcache
, "siar", ®set
[0]);
481 collect_register_by_name (regcache
, "sdar", ®set
[8]);
482 collect_register_by_name (regcache
, "sier", ®set
[16]);
483 collect_register_by_name (regcache
, "mmcr2", ®set
[24]);
484 collect_register_by_name (regcache
, "mmcr0", ®set
[32]);
487 /* Performance Monitoring Unit regset store function. */
490 ppc_store_pmuregset (struct regcache
*regcache
, const void *buf
)
492 const char *regset
= (const char *) buf
;
494 supply_register_by_name (regcache
, "siar", ®set
[0]);
495 supply_register_by_name (regcache
, "sdar", ®set
[8]);
496 supply_register_by_name (regcache
, "sier", ®set
[16]);
497 supply_register_by_name (regcache
, "mmcr2", ®set
[24]);
498 supply_register_by_name (regcache
, "mmcr0", ®set
[32]);
501 /* Hardware Transactional Memory special-purpose register regset fill
505 ppc_fill_tm_sprregset (struct regcache
*regcache
, void *buf
)
508 char *regset
= (char *) buf
;
510 base
= find_regno (regcache
->tdesc
, "tfhar");
511 for (i
= 0; i
< 3; i
++)
512 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
515 /* Hardware Transactional Memory special-purpose register regset store
519 ppc_store_tm_sprregset (struct regcache
*regcache
, const void *buf
)
522 const char *regset
= (const char *) buf
;
524 base
= find_regno (regcache
->tdesc
, "tfhar");
525 for (i
= 0; i
< 3; i
++)
526 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
529 /* For the same reasons as the EBB regset, none of the HTM
530 checkpointed regsets have a fill function. These registers are
531 only available if the inferior is in a transaction. */
533 /* Hardware Transactional Memory checkpointed general-purpose regset
537 ppc_store_tm_cgprregset (struct regcache
*regcache
, const void *buf
)
539 int i
, base
, size
, endian_offset
;
540 const char *regset
= (const char *) buf
;
542 base
= find_regno (regcache
->tdesc
, "cr0");
543 size
= register_size (regcache
->tdesc
, base
);
545 gdb_assert (size
== 4 || size
== 8);
547 for (i
= 0; i
< 32; i
++)
548 supply_register (regcache
, base
+ i
, ®set
[i
* size
]);
552 if ((size
== 8) && (__BYTE_ORDER
== __BIG_ENDIAN
))
555 supply_register_by_name (regcache
, "ccr",
556 ®set
[PT_CCR
* size
+ endian_offset
]);
558 supply_register_by_name (regcache
, "cxer",
559 ®set
[PT_XER
* size
+ endian_offset
]);
561 supply_register_by_name (regcache
, "clr", ®set
[PT_LNK
* size
]);
562 supply_register_by_name (regcache
, "cctr", ®set
[PT_CTR
* size
]);
565 /* Hardware Transactional Memory checkpointed floating-point regset
569 ppc_store_tm_cfprregset (struct regcache
*regcache
, const void *buf
)
572 const char *regset
= (const char *) buf
;
574 base
= find_regno (regcache
->tdesc
, "cf0");
576 for (i
= 0; i
< 32; i
++)
577 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
579 supply_register_by_name (regcache
, "cfpscr", ®set
[32 * 8]);
582 /* Hardware Transactional Memory checkpointed vector regset store
586 ppc_store_tm_cvrregset (struct regcache
*regcache
, const void *buf
)
589 const char *regset
= (const char *) buf
;
592 base
= find_regno (regcache
->tdesc
, "cvr0");
594 for (i
= 0; i
< 32; i
++)
595 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
597 if (__BYTE_ORDER
== __BIG_ENDIAN
)
600 supply_register_by_name (regcache
, "cvscr",
601 ®set
[32 * 16 + vscr_offset
]);
603 supply_register_by_name (regcache
, "cvrsave", ®set
[33 * 16]);
606 /* Hardware Transactional Memory checkpointed vector-scalar regset
610 ppc_store_tm_cvsxregset (struct regcache
*regcache
, const void *buf
)
613 const char *regset
= (const char *) buf
;
615 base
= find_regno (regcache
->tdesc
, "cvs0h");
616 for (i
= 0; i
< 32; i
++)
617 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
620 /* Hardware Transactional Memory checkpointed Program Priority
621 Register regset store function. */
624 ppc_store_tm_cpprregset (struct regcache
*regcache
, const void *buf
)
626 const char *cppr
= (const char *) buf
;
628 supply_register_by_name (regcache
, "cppr", cppr
);
631 /* Hardware Transactional Memory checkpointed Data Stream Control
632 Register regset store function. */
635 ppc_store_tm_cdscrregset (struct regcache
*regcache
, const void *buf
)
637 const char *cdscr
= (const char *) buf
;
639 supply_register_by_name (regcache
, "cdscr", cdscr
);
642 /* Hardware Transactional Memory checkpointed Target Address Register
643 regset store function. */
646 ppc_store_tm_ctarregset (struct regcache
*regcache
, const void *buf
)
648 const char *ctar
= (const char *) buf
;
650 supply_register_by_name (regcache
, "ctar", ctar
);
654 ppc_fill_vsxregset (struct regcache
*regcache
, void *buf
)
657 char *regset
= (char *) buf
;
659 base
= find_regno (regcache
->tdesc
, "vs0h");
660 for (i
= 0; i
< 32; i
++)
661 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
665 ppc_store_vsxregset (struct regcache
*regcache
, const void *buf
)
668 const char *regset
= (const char *) buf
;
670 base
= find_regno (regcache
->tdesc
, "vs0h");
671 for (i
= 0; i
< 32; i
++)
672 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
676 ppc_fill_vrregset (struct regcache
*regcache
, void *buf
)
679 char *regset
= (char *) buf
;
682 base
= find_regno (regcache
->tdesc
, "vr0");
683 for (i
= 0; i
< 32; i
++)
684 collect_register (regcache
, base
+ i
, ®set
[i
* 16]);
686 if (__BYTE_ORDER
== __BIG_ENDIAN
)
689 collect_register_by_name (regcache
, "vscr",
690 ®set
[32 * 16 + vscr_offset
]);
692 collect_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
696 ppc_store_vrregset (struct regcache
*regcache
, const void *buf
)
699 const char *regset
= (const char *) buf
;
702 base
= find_regno (regcache
->tdesc
, "vr0");
703 for (i
= 0; i
< 32; i
++)
704 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
706 if (__BYTE_ORDER
== __BIG_ENDIAN
)
709 supply_register_by_name (regcache
, "vscr",
710 ®set
[32 * 16 + vscr_offset
]);
711 supply_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
714 struct gdb_evrregset_t
716 unsigned long evr
[32];
717 unsigned long long acc
;
718 unsigned long spefscr
;
722 ppc_fill_evrregset (struct regcache
*regcache
, void *buf
)
725 struct gdb_evrregset_t
*regset
= (struct gdb_evrregset_t
*) buf
;
727 ev0
= find_regno (regcache
->tdesc
, "ev0h");
728 for (i
= 0; i
< 32; i
++)
729 collect_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
731 collect_register_by_name (regcache
, "acc", ®set
->acc
);
732 collect_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
736 ppc_store_evrregset (struct regcache
*regcache
, const void *buf
)
739 const struct gdb_evrregset_t
*regset
= (const struct gdb_evrregset_t
*) buf
;
741 ev0
= find_regno (regcache
->tdesc
, "ev0h");
742 for (i
= 0; i
< 32; i
++)
743 supply_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
745 supply_register_by_name (regcache
, "acc", ®set
->acc
);
746 supply_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
749 /* Support for hardware single step. */
752 ppc_supports_hardware_single_step (void)
757 static struct regset_info ppc_regsets
[] = {
758 /* List the extra register sets before GENERAL_REGS. That way we will
759 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
760 general registers. Some kernels support these, but not the newer
761 PPC_PTRACE_GETREGS. */
762 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CTAR
, 0, EXTENDED_REGS
,
763 NULL
, ppc_store_tm_ctarregset
},
764 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CDSCR
, 0, EXTENDED_REGS
,
765 NULL
, ppc_store_tm_cdscrregset
},
766 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CPPR
, 0, EXTENDED_REGS
,
767 NULL
, ppc_store_tm_cpprregset
},
768 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVSX
, 0, EXTENDED_REGS
,
769 NULL
, ppc_store_tm_cvsxregset
},
770 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVMX
, 0, EXTENDED_REGS
,
771 NULL
, ppc_store_tm_cvrregset
},
772 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CFPR
, 0, EXTENDED_REGS
,
773 NULL
, ppc_store_tm_cfprregset
},
774 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CGPR
, 0, EXTENDED_REGS
,
775 NULL
, ppc_store_tm_cgprregset
},
776 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_SPR
, 0, EXTENDED_REGS
,
777 ppc_fill_tm_sprregset
, ppc_store_tm_sprregset
},
778 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_EBB
, 0, EXTENDED_REGS
,
779 NULL
, ppc_store_ebbregset
},
780 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PMU
, 0, EXTENDED_REGS
,
781 ppc_fill_pmuregset
, ppc_store_pmuregset
},
782 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TAR
, 0, EXTENDED_REGS
,
783 ppc_fill_tarregset
, ppc_store_tarregset
},
784 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PPR
, 0, EXTENDED_REGS
,
785 ppc_fill_pprregset
, ppc_store_pprregset
},
786 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_DSCR
, 0, EXTENDED_REGS
,
787 ppc_fill_dscrregset
, ppc_store_dscrregset
},
788 { PTRACE_GETVSXREGS
, PTRACE_SETVSXREGS
, 0, 0, EXTENDED_REGS
,
789 ppc_fill_vsxregset
, ppc_store_vsxregset
},
790 { PTRACE_GETVRREGS
, PTRACE_SETVRREGS
, 0, 0, EXTENDED_REGS
,
791 ppc_fill_vrregset
, ppc_store_vrregset
},
792 { PTRACE_GETEVRREGS
, PTRACE_SETEVRREGS
, 0, 0, EXTENDED_REGS
,
793 ppc_fill_evrregset
, ppc_store_evrregset
},
794 { 0, 0, 0, 0, GENERAL_REGS
, ppc_fill_gregset
, NULL
},
798 static struct usrregs_info ppc_usrregs_info
=
804 static struct regsets_info ppc_regsets_info
=
806 ppc_regsets
, /* regsets */
808 NULL
, /* disabled_regsets */
811 static struct regs_info myregs_info
=
813 NULL
, /* regset_bitmap */
819 ppc_target::get_regs_info ()
825 ppc_target::low_arch_setup ()
827 const struct target_desc
*tdesc
;
828 struct regset_info
*regset
;
829 struct ppc_linux_features features
= ppc_linux_no_features
;
831 int tid
= lwpid_of (current_thread
);
833 features
.wordsize
= ppc_linux_target_wordsize (tid
);
835 if (features
.wordsize
== 4)
836 tdesc
= tdesc_powerpc_32l
;
838 tdesc
= tdesc_powerpc_64l
;
840 current_process ()->tdesc
= tdesc
;
842 /* The value of current_process ()->tdesc needs to be set for this
844 ppc_hwcap
= linux_get_hwcap (features
.wordsize
);
845 ppc_hwcap2
= linux_get_hwcap2 (features
.wordsize
);
847 features
.isa205
= ppc_linux_has_isa205 (ppc_hwcap
);
849 if (ppc_hwcap
& PPC_FEATURE_HAS_VSX
)
852 if (ppc_hwcap
& PPC_FEATURE_HAS_ALTIVEC
)
853 features
.altivec
= true;
855 if ((ppc_hwcap2
& PPC_FEATURE2_DSCR
)
856 && ppc_check_regset (tid
, NT_PPC_DSCR
, PPC_LINUX_SIZEOF_DSCRREGSET
)
857 && ppc_check_regset (tid
, NT_PPC_PPR
, PPC_LINUX_SIZEOF_PPRREGSET
))
859 features
.ppr_dscr
= true;
860 if ((ppc_hwcap2
& PPC_FEATURE2_ARCH_2_07
)
861 && (ppc_hwcap2
& PPC_FEATURE2_TAR
)
862 && (ppc_hwcap2
& PPC_FEATURE2_EBB
)
863 && ppc_check_regset (tid
, NT_PPC_TAR
,
864 PPC_LINUX_SIZEOF_TARREGSET
)
865 && ppc_check_regset (tid
, NT_PPC_EBB
,
866 PPC_LINUX_SIZEOF_EBBREGSET
)
867 && ppc_check_regset (tid
, NT_PPC_PMU
,
868 PPC_LINUX_SIZEOF_PMUREGSET
))
870 features
.isa207
= true;
871 if ((ppc_hwcap2
& PPC_FEATURE2_HTM
)
872 && ppc_check_regset (tid
, NT_PPC_TM_SPR
,
873 PPC_LINUX_SIZEOF_TM_SPRREGSET
))
878 tdesc
= ppc_linux_match_description (features
);
880 /* On 32-bit machines, check for SPE registers.
881 Set the low target's regmap field as appropriately. */
882 #ifndef __powerpc64__
883 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
884 tdesc
= tdesc_powerpc_e500l
;
886 if (!ppc_regmap_adjusted
)
888 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
889 ppc_usrregs_info
.regmap
= ppc_regmap_e500
;
891 /* If the FPSCR is 64-bit wide, we need to fetch the whole
892 64-bit slot and not just its second word. The PT_FPSCR
893 supplied in a 32-bit GDB compilation doesn't reflect
895 if (register_size (tdesc
, 70) == 8)
896 ppc_regmap
[70] = (48 + 2*32) * sizeof (long);
898 ppc_regmap_adjusted
= 1;
902 current_process ()->tdesc
= tdesc
;
904 for (regset
= ppc_regsets
; regset
->size
>= 0; regset
++)
905 switch (regset
->get_request
)
907 case PTRACE_GETVRREGS
:
908 regset
->size
= features
.altivec
? PPC_LINUX_SIZEOF_VRREGSET
: 0;
910 case PTRACE_GETVSXREGS
:
911 regset
->size
= features
.vsx
? PPC_LINUX_SIZEOF_VSXREGSET
: 0;
913 case PTRACE_GETEVRREGS
:
914 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
915 regset
->size
= 32 * 4 + 8 + 4;
919 case PTRACE_GETREGSET
:
920 switch (regset
->nt_type
)
923 regset
->size
= (features
.ppr_dscr
?
924 PPC_LINUX_SIZEOF_PPRREGSET
: 0);
927 regset
->size
= (features
.ppr_dscr
?
928 PPC_LINUX_SIZEOF_DSCRREGSET
: 0);
931 regset
->size
= (features
.isa207
?
932 PPC_LINUX_SIZEOF_TARREGSET
: 0);
935 regset
->size
= (features
.isa207
?
936 PPC_LINUX_SIZEOF_EBBREGSET
: 0);
939 regset
->size
= (features
.isa207
?
940 PPC_LINUX_SIZEOF_PMUREGSET
: 0);
943 regset
->size
= (features
.htm
?
944 PPC_LINUX_SIZEOF_TM_SPRREGSET
: 0);
947 if (features
.wordsize
== 4)
948 regset
->size
= (features
.htm
?
949 PPC32_LINUX_SIZEOF_CGPRREGSET
: 0);
951 regset
->size
= (features
.htm
?
952 PPC64_LINUX_SIZEOF_CGPRREGSET
: 0);
955 regset
->size
= (features
.htm
?
956 PPC_LINUX_SIZEOF_CFPRREGSET
: 0);
959 regset
->size
= (features
.htm
?
960 PPC_LINUX_SIZEOF_CVMXREGSET
: 0);
963 regset
->size
= (features
.htm
?
964 PPC_LINUX_SIZEOF_CVSXREGSET
: 0);
967 regset
->size
= (features
.htm
?
968 PPC_LINUX_SIZEOF_CPPRREGSET
: 0);
970 case NT_PPC_TM_CDSCR
:
971 regset
->size
= (features
.htm
?
972 PPC_LINUX_SIZEOF_CDSCRREGSET
: 0);
975 regset
->size
= (features
.htm
?
976 PPC_LINUX_SIZEOF_CTARREGSET
: 0);
987 /* Implementation of linux_target_ops method "supports_tracepoints". */
990 ppc_supports_tracepoints (void)
995 /* Get the thread area address. This is used to recognize which
996 thread is which when tracing with the in-process agent library. We
997 don't read anything from the address, and treat it as opaque; it's
998 the address itself that we assume is unique per-thread. */
1001 ppc_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
1003 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
1004 struct thread_info
*thr
= get_lwp_thread (lwp
);
1005 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
1008 #ifdef __powerpc64__
1009 if (register_size (regcache
->tdesc
, 0) == 8)
1010 collect_register_by_name (regcache
, "r13", &tp
);
1013 collect_register_by_name (regcache
, "r2", &tp
);
1020 #ifdef __powerpc64__
1022 /* Older glibc doesn't provide this. */
1024 #ifndef EF_PPC64_ABI
1025 #define EF_PPC64_ABI 3
1028 /* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
1032 is_elfv2_inferior (void)
1034 /* To be used as fallback if we're unable to determine the right result -
1035 assume inferior uses the same ABI as gdbserver. */
1037 const int def_res
= 1;
1039 const int def_res
= 0;
1044 const struct target_desc
*tdesc
= current_process ()->tdesc
;
1045 int wordsize
= register_size (tdesc
, 0);
1047 if (!linux_get_auxv (wordsize
, AT_PHDR
, &phdr
))
1050 /* Assume ELF header is at the beginning of the page where program headers
1051 are located. If it doesn't look like one, bail. */
1053 read_inferior_memory (phdr
& ~0xfff, (unsigned char *) &ehdr
, sizeof ehdr
);
1054 if (memcmp(ehdr
.e_ident
, ELFMAG
, SELFMAG
))
1057 return (ehdr
.e_flags
& EF_PPC64_ABI
) == 2;
1062 /* Generate a ds-form instruction in BUF and return the number of bytes written
1065 | OPCD | RST | RA | DS |XO| */
1067 __attribute__((unused
)) /* Maybe unused due to conditional compilation. */
1069 gen_ds_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int ds
, int xo
)
1073 gdb_assert ((opcd
& ~0x3f) == 0);
1074 gdb_assert ((rst
& ~0x1f) == 0);
1075 gdb_assert ((ra
& ~0x1f) == 0);
1076 gdb_assert ((xo
& ~0x3) == 0);
1078 insn
= (rst
<< 21) | (ra
<< 16) | (ds
& 0xfffc) | (xo
& 0x3);
1079 *buf
= (opcd
<< 26) | insn
;
1083 /* Followings are frequently used ds-form instructions. */
1085 #define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
1086 #define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
1087 #define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
1088 #define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
1090 /* Generate a d-form instruction in BUF.
1093 | OPCD | RST | RA | D | */
1096 gen_d_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int si
)
1100 gdb_assert ((opcd
& ~0x3f) == 0);
1101 gdb_assert ((rst
& ~0x1f) == 0);
1102 gdb_assert ((ra
& ~0x1f) == 0);
1104 insn
= (rst
<< 21) | (ra
<< 16) | (si
& 0xffff);
1105 *buf
= (opcd
<< 26) | insn
;
1109 /* Followings are frequently used d-form instructions. */
1111 #define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
1112 #define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
1113 #define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
1114 #define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
1115 #define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
1116 #define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
1117 #define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
1118 #define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
1119 #define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
1121 /* Generate a xfx-form instruction in BUF and return the number of bytes
1125 | OPCD | RST | RI | XO |/| */
1128 gen_xfx_form (uint32_t *buf
, int opcd
, int rst
, int ri
, int xo
)
1131 unsigned int n
= ((ri
& 0x1f) << 5) | ((ri
>> 5) & 0x1f);
1133 gdb_assert ((opcd
& ~0x3f) == 0);
1134 gdb_assert ((rst
& ~0x1f) == 0);
1135 gdb_assert ((xo
& ~0x3ff) == 0);
1137 insn
= (rst
<< 21) | (n
<< 11) | (xo
<< 1);
1138 *buf
= (opcd
<< 26) | insn
;
1142 /* Followings are frequently used xfx-form instructions. */
1144 #define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
1145 #define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
1146 #define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
1147 #define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
1148 #define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
1150 #define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
1153 /* Generate a x-form instruction in BUF and return the number of bytes written.
1156 | OPCD | RST | RA | RB | XO |RC| */
1159 gen_x_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int rb
, int xo
, int rc
)
1163 gdb_assert ((opcd
& ~0x3f) == 0);
1164 gdb_assert ((rst
& ~0x1f) == 0);
1165 gdb_assert ((ra
& ~0x1f) == 0);
1166 gdb_assert ((rb
& ~0x1f) == 0);
1167 gdb_assert ((xo
& ~0x3ff) == 0);
1168 gdb_assert ((rc
& ~1) == 0);
1170 insn
= (rst
<< 21) | (ra
<< 16) | (rb
<< 11) | (xo
<< 1) | rc
;
1171 *buf
= (opcd
<< 26) | insn
;
1175 /* Followings are frequently used x-form instructions. */
1177 #define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
1178 #define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
1179 #define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
1180 #define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
1181 /* Assume bf = cr7. */
1182 #define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
1185 /* Generate a md-form instruction in BUF and return the number of bytes written.
1187 0 6 11 16 21 27 30 31 32
1188 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
1191 gen_md_form (uint32_t *buf
, int opcd
, int rs
, int ra
, int sh
, int mb
,
1195 unsigned int n
= ((mb
& 0x1f) << 1) | ((mb
>> 5) & 0x1);
1196 unsigned int sh0_4
= sh
& 0x1f;
1197 unsigned int sh5
= (sh
>> 5) & 1;
1199 gdb_assert ((opcd
& ~0x3f) == 0);
1200 gdb_assert ((rs
& ~0x1f) == 0);
1201 gdb_assert ((ra
& ~0x1f) == 0);
1202 gdb_assert ((sh
& ~0x3f) == 0);
1203 gdb_assert ((mb
& ~0x3f) == 0);
1204 gdb_assert ((xo
& ~0x7) == 0);
1205 gdb_assert ((rc
& ~0x1) == 0);
1207 insn
= (rs
<< 21) | (ra
<< 16) | (sh0_4
<< 11) | (n
<< 5)
1208 | (sh5
<< 1) | (xo
<< 2) | (rc
& 1);
1209 *buf
= (opcd
<< 26) | insn
;
1213 /* The following are frequently used md-form instructions. */
1215 #define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1216 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1217 #define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1218 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1220 /* Generate a i-form instruction in BUF and return the number of bytes written.
1223 | OPCD | LI |AA|LK| */
1226 gen_i_form (uint32_t *buf
, int opcd
, int li
, int aa
, int lk
)
1230 gdb_assert ((opcd
& ~0x3f) == 0);
1232 insn
= (li
& 0x3fffffc) | (aa
& 1) | (lk
& 1);
1233 *buf
= (opcd
<< 26) | insn
;
1237 /* The following are frequently used i-form instructions. */
1239 #define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1240 #define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1242 /* Generate a b-form instruction in BUF and return the number of bytes written.
1245 | OPCD | BO | BI | BD |AA|LK| */
1248 gen_b_form (uint32_t *buf
, int opcd
, int bo
, int bi
, int bd
,
1253 gdb_assert ((opcd
& ~0x3f) == 0);
1254 gdb_assert ((bo
& ~0x1f) == 0);
1255 gdb_assert ((bi
& ~0x1f) == 0);
1257 insn
= (bo
<< 21) | (bi
<< 16) | (bd
& 0xfffc) | (aa
& 1) | (lk
& 1);
1258 *buf
= (opcd
<< 26) | insn
;
1262 /* The following are frequently used b-form instructions. */
1263 /* Assume bi = cr7. */
1264 #define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1266 /* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1267 respectively. They are primary used for save/restore GPRs in jump-pad,
1268 not used for bytecode compiling. */
1270 #ifdef __powerpc64__
1271 #define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1272 GEN_LD (buf, rt, ra, si) : \
1273 GEN_LWZ (buf, rt, ra, si))
1274 #define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1275 GEN_STD (buf, rt, ra, si) : \
1276 GEN_STW (buf, rt, ra, si))
1278 #define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1279 #define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1282 /* Generate a sequence of instructions to load IMM in the register REG.
1283 Write the instructions in BUF and return the number of bytes written. */
1286 gen_limm (uint32_t *buf
, int reg
, uint64_t imm
, int is_64
)
1290 if ((imm
+ 32768) < 65536)
1292 /* li reg, imm[15:0] */
1293 p
+= GEN_LI (p
, reg
, imm
);
1295 else if ((imm
>> 32) == 0)
1297 /* lis reg, imm[31:16]
1298 ori reg, reg, imm[15:0]
1299 rldicl reg, reg, 0, 32 */
1300 p
+= GEN_LIS (p
, reg
, (imm
>> 16) & 0xffff);
1301 if ((imm
& 0xffff) != 0)
1302 p
+= GEN_ORI (p
, reg
, reg
, imm
& 0xffff);
1303 /* Clear upper 32-bit if sign-bit is set. */
1304 if (imm
& (1u << 31) && is_64
)
1305 p
+= GEN_RLDICL (p
, reg
, reg
, 0, 32);
1310 /* lis reg, <imm[63:48]>
1311 ori reg, reg, <imm[48:32]>
1312 rldicr reg, reg, 32, 31
1313 oris reg, reg, <imm[31:16]>
1314 ori reg, reg, <imm[15:0]> */
1315 p
+= GEN_LIS (p
, reg
, ((imm
>> 48) & 0xffff));
1316 if (((imm
>> 32) & 0xffff) != 0)
1317 p
+= GEN_ORI (p
, reg
, reg
, ((imm
>> 32) & 0xffff));
1318 p
+= GEN_RLDICR (p
, reg
, reg
, 32, 31);
1319 if (((imm
>> 16) & 0xffff) != 0)
1320 p
+= GEN_ORIS (p
, reg
, reg
, ((imm
>> 16) & 0xffff));
1321 if ((imm
& 0xffff) != 0)
1322 p
+= GEN_ORI (p
, reg
, reg
, (imm
& 0xffff));
1328 /* Generate a sequence for atomically exchange at location LOCK.
1329 This code sequence clobbers r6, r7, r8. LOCK is the location for
1330 the atomic-xchg, OLD_VALUE is expected old value stored in the
1331 location, and R_NEW is a register for the new value. */
1334 gen_atomic_xchg (uint32_t *buf
, CORE_ADDR lock
, int old_value
, int r_new
,
1337 const int r_lock
= 6;
1338 const int r_old
= 7;
1339 const int r_tmp
= 8;
1343 1: lwarx TMP, 0, LOCK
1349 p
+= gen_limm (p
, r_lock
, lock
, is_64
);
1350 p
+= gen_limm (p
, r_old
, old_value
, is_64
);
1352 p
+= GEN_LWARX (p
, r_tmp
, 0, r_lock
);
1353 p
+= GEN_CMPW (p
, r_tmp
, r_old
);
1354 p
+= GEN_BNE (p
, -8);
1355 p
+= GEN_STWCX (p
, r_new
, 0, r_lock
);
1356 p
+= GEN_BNE (p
, -16);
1361 /* Generate a sequence of instructions for calling a function
1362 at address of FN. Return the number of bytes are written in BUF. */
1365 gen_call (uint32_t *buf
, CORE_ADDR fn
, int is_64
, int is_opd
)
1369 /* Must be called by r12 for caller to calculate TOC address. */
1370 p
+= gen_limm (p
, 12, fn
, is_64
);
1373 p
+= GEN_LOAD (p
, 11, 12, 16, is_64
);
1374 p
+= GEN_LOAD (p
, 2, 12, 8, is_64
);
1375 p
+= GEN_LOAD (p
, 12, 12, 0, is_64
);
1377 p
+= GEN_MTSPR (p
, 12, 9); /* mtctr r12 */
1378 *p
++ = 0x4e800421; /* bctrl */
1383 /* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1384 of instruction. This function is used to adjust pc-relative instructions
1388 ppc_relocate_instruction (CORE_ADDR
*to
, CORE_ADDR oldloc
)
1393 read_inferior_memory (oldloc
, (unsigned char *) &insn
, 4);
1394 op6
= PPC_OP6 (insn
);
1396 if (op6
== 18 && (insn
& 2) == 0)
1398 /* branch && AA = 0 */
1399 rel
= PPC_LI (insn
);
1400 newrel
= (oldloc
- *to
) + rel
;
1402 /* Out of range. Cannot relocate instruction. */
1403 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1406 insn
= (insn
& ~0x3fffffc) | (newrel
& 0x3fffffc);
1408 else if (op6
== 16 && (insn
& 2) == 0)
1410 /* conditional branch && AA = 0 */
1412 /* If the new relocation is too big for even a 26-bit unconditional
1413 branch, there is nothing we can do. Just abort.
1415 Otherwise, if it can be fit in 16-bit conditional branch, just
1416 copy the instruction and relocate the address.
1418 If the it's big for conditional-branch (16-bit), try to invert the
1419 condition and jump with 26-bit branch. For example,
1430 After this transform, we are actually jump from *TO+4 instead of *TO,
1431 so check the relocation again because it will be 1-insn farther then
1432 before if *TO is after OLDLOC.
1435 For BDNZT (or so) is transformed from
1447 See also "BO field encodings". */
1449 rel
= PPC_BD (insn
);
1450 newrel
= (oldloc
- *to
) + rel
;
1452 if (newrel
< (1 << 15) && newrel
>= -(1 << 15))
1453 insn
= (insn
& ~0xfffc) | (newrel
& 0xfffc);
1454 else if ((PPC_BO (insn
) & 0x14) == 0x4 || (PPC_BO (insn
) & 0x14) == 0x10)
1458 /* Out of range. Cannot relocate instruction. */
1459 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1462 if ((PPC_BO (insn
) & 0x14) == 0x4)
1464 else if ((PPC_BO (insn
) & 0x14) == 0x10)
1467 /* Jump over the unconditional branch. */
1468 insn
= (insn
& ~0xfffc) | 0x8;
1469 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1472 /* Build a unconditional branch and copy LK bit. */
1473 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1474 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1479 else if ((PPC_BO (insn
) & 0x14) == 0)
1481 uint32_t bdnz_insn
= (16 << 26) | (0x10 << 21) | 12;
1482 uint32_t bf_insn
= (16 << 26) | (0x4 << 21) | 8;
1486 /* Out of range. Cannot relocate instruction. */
1487 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1490 /* Copy BI field. */
1491 bf_insn
|= (insn
& 0x1f0000);
1493 /* Invert condition. */
1494 bdnz_insn
|= (insn
^ (1 << 22)) & (1 << 22);
1495 bf_insn
|= (insn
^ (1 << 24)) & (1 << 24);
1497 target_write_memory (*to
, (unsigned char *) &bdnz_insn
, 4);
1499 target_write_memory (*to
, (unsigned char *) &bf_insn
, 4);
1502 /* Build a unconditional branch and copy LK bit. */
1503 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1504 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1509 else /* (BO & 0x14) == 0x14, branch always. */
1511 /* Out of range. Cannot relocate instruction. */
1512 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1515 /* Build a unconditional branch and copy LK bit. */
1516 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1517 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1524 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1528 /* Implement install_fast_tracepoint_jump_pad of target_ops.
1529 See target.h for details. */
1532 ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1533 CORE_ADDR collector
,
1536 CORE_ADDR
*jump_entry
,
1537 CORE_ADDR
*trampoline
,
1538 ULONGEST
*trampoline_size
,
1539 unsigned char *jjump_pad_insn
,
1540 ULONGEST
*jjump_pad_insn_size
,
1541 CORE_ADDR
*adjusted_insn_addr
,
1542 CORE_ADDR
*adjusted_insn_addr_end
,
1548 CORE_ADDR buildaddr
= *jump_entry
;
1549 const CORE_ADDR entryaddr
= *jump_entry
;
1550 int rsz
, min_frame
, frame_size
, tp_reg
;
1551 #ifdef __powerpc64__
1552 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
1553 int is_64
= register_size (regcache
->tdesc
, 0) == 8;
1554 int is_opd
= is_64
&& !is_elfv2_inferior ();
1556 int is_64
= 0, is_opd
= 0;
1559 #ifdef __powerpc64__
1562 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1565 frame_size
= (40 * rsz
) + min_frame
;
1573 frame_size
= (40 * rsz
) + min_frame
;
1575 #ifdef __powerpc64__
1579 /* Stack frame layout for this jump pad,
1581 High thread_area (r13/r2) |
1582 tpoint - collecting_t obj
1592 R0 - collected registers
1598 The code flow of this jump pad,
1603 4. Call gdb_collector
1604 5. Restore GPR and SPR
1606 7. Build a jump for back to the program
1607 8. Copy/relocate original instruction
1608 9. Build a jump for replacing original instruction. */
1610 /* Adjust stack pointer. */
1612 p
+= GEN_STDU (p
, 1, 1, -frame_size
); /* stdu r1,-frame_size(r1) */
1614 p
+= GEN_STWU (p
, 1, 1, -frame_size
); /* stwu r1,-frame_size(r1) */
1616 /* Store GPRs. Save R1 later, because it had just been modified, but
1617 we want the original value. */
1618 for (j
= 2; j
< 32; j
++)
1619 p
+= GEN_STORE (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1620 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1621 /* Set r0 to the original value of r1 before adjusting stack frame,
1622 and then save it. */
1623 p
+= GEN_ADDI (p
, 0, 1, frame_size
);
1624 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 1 * rsz
, is_64
);
1626 /* Save CR, XER, LR, and CTR. */
1627 p
+= GEN_MFCR (p
, 3); /* mfcr r3 */
1628 p
+= GEN_MFSPR (p
, 4, 1); /* mfxer r4 */
1629 p
+= GEN_MFSPR (p
, 5, 8); /* mflr r5 */
1630 p
+= GEN_MFSPR (p
, 6, 9); /* mfctr r6 */
1631 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
);/* std r3, 32(r1) */
1632 p
+= GEN_STORE (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
);/* std r4, 33(r1) */
1633 p
+= GEN_STORE (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
);/* std r5, 34(r1) */
1634 p
+= GEN_STORE (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
);/* std r6, 35(r1) */
1636 /* Save PC<tpaddr> */
1637 p
+= gen_limm (p
, 3, tpaddr
, is_64
);
1638 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 36 * rsz
, is_64
);
1641 /* Setup arguments to collector. */
1642 /* Set r4 to collected registers. */
1643 p
+= GEN_ADDI (p
, 4, 1, min_frame
);
1644 /* Set r3 to TPOINT. */
1645 p
+= gen_limm (p
, 3, tpoint
, is_64
);
1647 /* Prepare collecting_t object for lock. */
1648 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 37 * rsz
, is_64
);
1649 p
+= GEN_STORE (p
, tp_reg
, 1, min_frame
+ 38 * rsz
, is_64
);
1650 /* Set R5 to collecting object. */
1651 p
+= GEN_ADDI (p
, 5, 1, 37 * rsz
);
1653 p
+= GEN_LWSYNC (p
);
1654 p
+= gen_atomic_xchg (p
, lockaddr
, 0, 5, is_64
);
1655 p
+= GEN_LWSYNC (p
);
1657 /* Call to collector. */
1658 p
+= gen_call (p
, collector
, is_64
, is_opd
);
1660 /* Simply write 0 to release the lock. */
1661 p
+= gen_limm (p
, 3, lockaddr
, is_64
);
1662 p
+= gen_limm (p
, 4, 0, is_64
);
1663 p
+= GEN_LWSYNC (p
);
1664 p
+= GEN_STORE (p
, 4, 3, 0, is_64
);
1666 /* Restore stack and registers. */
1667 p
+= GEN_LOAD (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
); /* ld r3, 32(r1) */
1668 p
+= GEN_LOAD (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
); /* ld r4, 33(r1) */
1669 p
+= GEN_LOAD (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
); /* ld r5, 34(r1) */
1670 p
+= GEN_LOAD (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
); /* ld r6, 35(r1) */
1671 p
+= GEN_MTCR (p
, 3); /* mtcr r3 */
1672 p
+= GEN_MTSPR (p
, 4, 1); /* mtxer r4 */
1673 p
+= GEN_MTSPR (p
, 5, 8); /* mtlr r5 */
1674 p
+= GEN_MTSPR (p
, 6, 9); /* mtctr r6 */
1677 for (j
= 2; j
< 32; j
++)
1678 p
+= GEN_LOAD (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1679 p
+= GEN_LOAD (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1681 p
+= GEN_ADDI (p
, 1, 1, frame_size
);
1683 /* Flush instructions to inferior memory. */
1684 target_write_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1686 /* Now, insert the original instruction to execute in the jump pad. */
1687 *adjusted_insn_addr
= buildaddr
+ (p
- buf
) * 4;
1688 *adjusted_insn_addr_end
= *adjusted_insn_addr
;
1689 ppc_relocate_instruction (adjusted_insn_addr_end
, tpaddr
);
1691 /* Verify the relocation size. If should be 4 for normal copy,
1692 8 or 12 for some conditional branch. */
1693 if ((*adjusted_insn_addr_end
- *adjusted_insn_addr
== 0)
1694 || (*adjusted_insn_addr_end
- *adjusted_insn_addr
> 12))
1696 sprintf (err
, "E.Unexpected instruction length = %d"
1697 "when relocate instruction.",
1698 (int) (*adjusted_insn_addr_end
- *adjusted_insn_addr
));
1702 buildaddr
= *adjusted_insn_addr_end
;
1704 /* Finally, write a jump back to the program. */
1705 offset
= (tpaddr
+ 4) - buildaddr
;
1706 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1708 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1709 "(offset 0x%x > 26-bit).", offset
);
1713 p
+= GEN_B (p
, offset
);
1714 target_write_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1715 *jump_entry
= buildaddr
+ (p
- buf
) * 4;
1717 /* The jump pad is now built. Wire in a jump to our jump pad. This
1718 is always done last (by our caller actually), so that we can
1719 install fast tracepoints with threads running. This relies on
1720 the agent's atomic write support. */
1721 offset
= entryaddr
- tpaddr
;
1722 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1724 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1725 "(offset 0x%x > 26-bit).", offset
);
1729 GEN_B ((uint32_t *) jjump_pad_insn
, offset
);
1730 *jjump_pad_insn_size
= 4;
1735 /* Returns the minimum instruction length for installing a tracepoint. */
1738 ppc_get_min_fast_tracepoint_insn_len (void)
1743 /* Emits a given buffer into the target at current_insn_ptr. Length
1744 is in units of 32-bit words. */
1747 emit_insns (uint32_t *buf
, int n
)
1749 n
= n
* sizeof (uint32_t);
1750 target_write_memory (current_insn_ptr
, (unsigned char *) buf
, n
);
1751 current_insn_ptr
+= n
;
1754 #define __EMIT_ASM(NAME, INSNS) \
1757 extern uint32_t start_bcax_ ## NAME []; \
1758 extern uint32_t end_bcax_ ## NAME []; \
1759 emit_insns (start_bcax_ ## NAME, \
1760 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1761 __asm__ (".section .text.__ppcbcax\n\t" \
1762 "start_bcax_" #NAME ":\n\t" \
1764 "end_bcax_" #NAME ":\n\t" \
1768 #define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1769 #define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1773 Bytecode execution stack frame - 32-bit
1775 | LR save area (SP + 4)
1776 SP' -> +- Back chain (SP + 0)
1777 | Save r31 for access saved arguments
1778 | Save r30 for bytecode stack pointer
1779 | Save r4 for incoming argument *value
1780 | Save r3 for incoming argument regs
1781 r30 -> +- Bytecode execution stack
1783 | 64-byte (8 doublewords) at initial.
1784 | Expand stack as needed.
1787 | Some padding for minimum stack frame and 16-byte alignment.
1789 SP +- Back-chain (SP')
1795 r30 is the stack-pointer for bytecode machine.
1796 It should point to next-empty, so we can use LDU for pop.
1797 r3 is used for cache of the high part of TOP value.
1798 It was the first argument, pointer to regs.
1799 r4 is used for cache of the low part of TOP value.
1800 It was the second argument, pointer to the result.
1801 We should set *result = TOP after leaving this function.
1804 * To restore stack at epilogue
1806 * To check stack is big enough for bytecode execution.
1808 * To return execution result.
1813 /* Regardless of endian, register 3 is always high part, 4 is low part.
1814 These defines are used when the register pair is stored/loaded.
1815 Likewise, to simplify code, have a similiar define for 5:6. */
1817 #if __BYTE_ORDER == __LITTLE_ENDIAN
1818 #define TOP_FIRST "4"
1819 #define TOP_SECOND "3"
1820 #define TMP_FIRST "6"
1821 #define TMP_SECOND "5"
1823 #define TOP_FIRST "3"
1824 #define TOP_SECOND "4"
1825 #define TMP_FIRST "5"
1826 #define TMP_SECOND "6"
1829 /* Emit prologue in inferior memory. See above comments. */
1832 ppc_emit_prologue (void)
1834 EMIT_ASM (/* Save return address. */
1837 /* Adjust SP. 96 is the initial frame size. */
1839 /* Save r30 and incoming arguments. */
1840 "stw 31, 96-4(1) \n"
1841 "stw 30, 96-8(1) \n"
1842 "stw 4, 96-12(1) \n"
1843 "stw 3, 96-16(1) \n"
1844 /* Point r31 to original r1 for access arguments. */
1846 /* Set r30 to pointing stack-top. */
1848 /* Initial r3/TOP to 0. */
1853 /* Emit epilogue in inferior memory. See above comments. */
1856 ppc_emit_epilogue (void)
1858 EMIT_ASM (/* *result = TOP */
1860 "stw " TOP_FIRST
", 0(5) \n"
1861 "stw " TOP_SECOND
", 4(5) \n"
1862 /* Restore registers. */
1869 /* Return 0 for no-error. */
1875 /* TOP = stack[--sp] + TOP */
1880 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1881 "lwz " TMP_SECOND
", 4(30)\n"
1886 /* TOP = stack[--sp] - TOP */
1891 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1892 "lwz " TMP_SECOND
", 4(30) \n"
1894 "subfe 3, 3, 5 \n");
1897 /* TOP = stack[--sp] * TOP */
1902 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1903 "lwz " TMP_SECOND
", 4(30) \n"
1912 /* TOP = stack[--sp] << TOP */
1917 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1918 "lwz " TMP_SECOND
", 4(30) \n"
1919 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1920 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1921 "slw 5, 5, 4\n" /* Shift high part left */
1922 "slw 4, 6, 4\n" /* Shift low part left */
1923 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1924 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1926 "or 3, 7, 3\n"); /* Assemble high part */
1929 /* Top = stack[--sp] >> TOP
1930 (Arithmetic shift right) */
1933 ppc_emit_rsh_signed (void)
1935 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1936 "lwz " TMP_SECOND
", 4(30) \n"
1937 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1938 "sraw 3, 5, 4\n" /* Shift high part right */
1940 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
1941 "sraw 4, 5, 7\n" /* Shift high to low */
1944 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
1945 "srw 4, 6, 4\n" /* Shift low part right */
1946 "slw 5, 5, 7\n" /* Shift high to low */
1947 "or 4, 4, 5\n" /* Assemble low part */
1951 /* Top = stack[--sp] >> TOP
1952 (Logical shift right) */
1955 ppc_emit_rsh_unsigned (void)
1957 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1958 "lwz " TMP_SECOND
", 4(30) \n"
1959 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1960 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1961 "srw 6, 6, 4\n" /* Shift low part right */
1962 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
1963 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
1965 "srw 3, 5, 4\n" /* Shift high part right */
1966 "or 4, 6, 7\n"); /* Assemble low part */
1969 /* Emit code for signed-extension specified by ARG. */
1972 ppc_emit_ext (int arg
)
1977 EMIT_ASM ("extsb 4, 4\n"
1981 EMIT_ASM ("extsh 4, 4\n"
1985 EMIT_ASM ("srawi 3, 4, 31");
1992 /* Emit code for zero-extension specified by ARG. */
1995 ppc_emit_zero_ext (int arg
)
2000 EMIT_ASM ("clrlwi 4,4,24\n"
2004 EMIT_ASM ("clrlwi 4,4,16\n"
2008 EMIT_ASM ("li 3, 0");
2016 i.e., TOP = (TOP == 0) ? 1 : 0; */
2019 ppc_emit_log_not (void)
2021 EMIT_ASM ("or 4, 3, 4 \n"
2027 /* TOP = stack[--sp] & TOP */
2030 ppc_emit_bit_and (void)
2032 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2033 "lwz " TMP_SECOND
", 4(30) \n"
2038 /* TOP = stack[--sp] | TOP */
2041 ppc_emit_bit_or (void)
2043 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2044 "lwz " TMP_SECOND
", 4(30) \n"
2049 /* TOP = stack[--sp] ^ TOP */
2052 ppc_emit_bit_xor (void)
2054 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2055 "lwz " TMP_SECOND
", 4(30) \n"
2061 i.e., TOP = ~(TOP | TOP) */
2064 ppc_emit_bit_not (void)
2066 EMIT_ASM ("nor 3, 3, 3 \n"
2070 /* TOP = stack[--sp] == TOP */
2073 ppc_emit_equal (void)
2075 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2076 "lwz " TMP_SECOND
", 4(30) \n"
2085 /* TOP = stack[--sp] < TOP
2086 (Signed comparison) */
2089 ppc_emit_less_signed (void)
2091 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2092 "lwz " TMP_SECOND
", 4(30) \n"
2095 /* CR6 bit 0 = low less and high equal */
2096 "crand 6*4+0, 6*4+0, 7*4+2\n"
2097 /* CR7 bit 0 = (low less and high equal) or high less */
2098 "cror 7*4+0, 7*4+0, 6*4+0\n"
2100 "rlwinm 4, 4, 29, 31, 31 \n"
2104 /* TOP = stack[--sp] < TOP
2105 (Unsigned comparison) */
2108 ppc_emit_less_unsigned (void)
2110 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2111 "lwz " TMP_SECOND
", 4(30) \n"
2114 /* CR6 bit 0 = low less and high equal */
2115 "crand 6*4+0, 6*4+0, 7*4+2\n"
2116 /* CR7 bit 0 = (low less and high equal) or high less */
2117 "cror 7*4+0, 7*4+0, 6*4+0\n"
2119 "rlwinm 4, 4, 29, 31, 31 \n"
2123 /* Access the memory address in TOP in size of SIZE.
2124 Zero-extend the read value. */
2127 ppc_emit_ref (int size
)
2132 EMIT_ASM ("lbz 4, 0(4)\n"
2136 EMIT_ASM ("lhz 4, 0(4)\n"
2140 EMIT_ASM ("lwz 4, 0(4)\n"
2144 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2145 EMIT_ASM ("lwz 3, 4(4)\n"
2148 EMIT_ASM ("lwz 3, 0(4)\n"
2157 ppc_emit_const (LONGEST num
)
2162 p
+= gen_limm (p
, 3, num
>> 32 & 0xffffffff, 0);
2163 p
+= gen_limm (p
, 4, num
& 0xffffffff, 0);
2165 emit_insns (buf
, p
- buf
);
2166 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2169 /* Set TOP to the value of register REG by calling get_raw_reg function
2170 with two argument, collected buffer and register number. */
2173 ppc_emit_reg (int reg
)
2178 /* fctx->regs is passed in r3 and then saved in -16(31). */
2179 p
+= GEN_LWZ (p
, 3, 31, -16);
2180 p
+= GEN_LI (p
, 4, reg
); /* li r4, reg */
2181 p
+= gen_call (p
, get_raw_reg_func_addr (), 0, 0);
2183 emit_insns (buf
, p
- buf
);
2184 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2186 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2188 EMIT_ASM ("mr 5, 4\n"
2194 /* TOP = stack[--sp] */
2199 EMIT_ASM ("lwzu " TOP_FIRST
", 8(30) \n"
2200 "lwz " TOP_SECOND
", 4(30) \n");
2203 /* stack[sp++] = TOP
2205 Because we may use up bytecode stack, expand 8 doublewords more
2209 ppc_emit_stack_flush (void)
2211 /* Make sure bytecode stack is big enough before push.
2212 Otherwise, expand 64-byte more. */
2214 EMIT_ASM (" stw " TOP_FIRST
", 0(30) \n"
2215 " stw " TOP_SECOND
", 4(30)\n"
2216 " addi 5, 30, -(8 + 8) \n"
2219 " stwu 31, -64(1) \n"
2220 "1:addi 30, 30, -8 \n");
2223 /* Swap TOP and stack[sp-1] */
2226 ppc_emit_swap (void)
2228 EMIT_ASM ("lwz " TMP_FIRST
", 8(30) \n"
2229 "lwz " TMP_SECOND
", 12(30) \n"
2230 "stw " TOP_FIRST
", 8(30) \n"
2231 "stw " TOP_SECOND
", 12(30) \n"
2236 /* Discard N elements in the stack. Also used for ppc64. */
2239 ppc_emit_stack_adjust (int n
)
2251 p
+= GEN_ADDI (p
, 30, 30, n
);
2253 emit_insns (buf
, p
- buf
);
2254 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2257 /* Call function FN. */
2260 ppc_emit_call (CORE_ADDR fn
)
2265 p
+= gen_call (p
, fn
, 0, 0);
2267 emit_insns (buf
, p
- buf
);
2268 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2271 /* FN's prototype is `LONGEST(*fn)(int)'.
2276 ppc_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2281 /* Setup argument. arg1 is a 16-bit value. */
2282 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2283 p
+= gen_call (p
, fn
, 0, 0);
2285 emit_insns (buf
, p
- buf
);
2286 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2288 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2290 EMIT_ASM ("mr 5, 4\n"
2296 /* FN's prototype is `void(*fn)(int,LONGEST)'.
2299 TOP should be preserved/restored before/after the call. */
2302 ppc_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2307 /* Save TOP. 0(30) is next-empty. */
2308 p
+= GEN_STW (p
, 3, 30, 0);
2309 p
+= GEN_STW (p
, 4, 30, 4);
2311 /* Setup argument. arg1 is a 16-bit value. */
2312 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2314 p
+= GEN_MR (p
, 5, 4);
2315 p
+= GEN_MR (p
, 6, 3);
2319 p
+= GEN_MR (p
, 5, 3);
2320 p
+= GEN_MR (p
, 6, 4);
2322 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2323 p
+= gen_call (p
, fn
, 0, 0);
2326 p
+= GEN_LWZ (p
, 3, 30, 0);
2327 p
+= GEN_LWZ (p
, 4, 30, 4);
2329 emit_insns (buf
, p
- buf
);
2330 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2333 /* Note in the following goto ops:
2335 When emitting goto, the target address is later relocated by
2336 write_goto_address. OFFSET_P is the offset of the branch instruction
2337 in the code sequence, and SIZE_P is how to relocate the instruction,
2338 recognized by ppc_write_goto_address. In current implementation,
2339 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2342 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2345 ppc_emit_if_goto (int *offset_p
, int *size_p
)
2347 EMIT_ASM ("or. 3, 3, 4 \n"
2348 "lwzu " TOP_FIRST
", 8(30) \n"
2349 "lwz " TOP_SECOND
", 4(30) \n"
2358 /* Unconditional goto. Also used for ppc64. */
2361 ppc_emit_goto (int *offset_p
, int *size_p
)
2363 EMIT_ASM ("1:b 1b");
2371 /* Goto if stack[--sp] == TOP */
2374 ppc_emit_eq_goto (int *offset_p
, int *size_p
)
2376 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2377 "lwz " TMP_SECOND
", 4(30) \n"
2381 "lwzu " TOP_FIRST
", 8(30) \n"
2382 "lwz " TOP_SECOND
", 4(30) \n"
2391 /* Goto if stack[--sp] != TOP */
2394 ppc_emit_ne_goto (int *offset_p
, int *size_p
)
2396 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2397 "lwz " TMP_SECOND
", 4(30) \n"
2401 "lwzu " TOP_FIRST
", 8(30) \n"
2402 "lwz " TOP_SECOND
", 4(30) \n"
2411 /* Goto if stack[--sp] < TOP */
2414 ppc_emit_lt_goto (int *offset_p
, int *size_p
)
2416 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2417 "lwz " TMP_SECOND
", 4(30) \n"
2420 /* CR6 bit 0 = low less and high equal */
2421 "crand 6*4+0, 6*4+0, 7*4+2\n"
2422 /* CR7 bit 0 = (low less and high equal) or high less */
2423 "cror 7*4+0, 7*4+0, 6*4+0\n"
2424 "lwzu " TOP_FIRST
", 8(30) \n"
2425 "lwz " TOP_SECOND
", 4(30)\n"
2434 /* Goto if stack[--sp] <= TOP */
2437 ppc_emit_le_goto (int *offset_p
, int *size_p
)
2439 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2440 "lwz " TMP_SECOND
", 4(30) \n"
2443 /* CR6 bit 0 = low less/equal and high equal */
2444 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2445 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2446 "cror 7*4+0, 7*4+0, 6*4+0\n"
2447 "lwzu " TOP_FIRST
", 8(30) \n"
2448 "lwz " TOP_SECOND
", 4(30)\n"
2457 /* Goto if stack[--sp] > TOP */
2460 ppc_emit_gt_goto (int *offset_p
, int *size_p
)
2462 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2463 "lwz " TMP_SECOND
", 4(30) \n"
2466 /* CR6 bit 0 = low greater and high equal */
2467 "crand 6*4+0, 6*4+1, 7*4+2\n"
2468 /* CR7 bit 0 = (low greater and high equal) or high greater */
2469 "cror 7*4+0, 7*4+1, 6*4+0\n"
2470 "lwzu " TOP_FIRST
", 8(30) \n"
2471 "lwz " TOP_SECOND
", 4(30)\n"
2480 /* Goto if stack[--sp] >= TOP */
2483 ppc_emit_ge_goto (int *offset_p
, int *size_p
)
2485 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2486 "lwz " TMP_SECOND
", 4(30) \n"
2489 /* CR6 bit 0 = low ge and high equal */
2490 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2491 /* CR7 bit 0 = (low ge and high equal) or high greater */
2492 "cror 7*4+0, 7*4+1, 6*4+0\n"
2493 "lwzu " TOP_FIRST
", 8(30)\n"
2494 "lwz " TOP_SECOND
", 4(30)\n"
2503 /* Relocate previous emitted branch instruction. FROM is the address
2504 of the branch instruction, TO is the goto target address, and SIZE
2505 if the value we set by *SIZE_P before. Currently, it is either
2506 24 or 14 of branch and conditional-branch instruction.
2507 Also used for ppc64. */
2510 ppc_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2512 long rel
= to
- from
;
2516 read_inferior_memory (from
, (unsigned char *) &insn
, 4);
2517 opcd
= (insn
>> 26) & 0x3f;
2523 || (rel
>= (1 << 15) || rel
< -(1 << 15)))
2525 insn
= (insn
& ~0xfffc) | (rel
& 0xfffc);
2529 || (rel
>= (1 << 25) || rel
< -(1 << 25)))
2531 insn
= (insn
& ~0x3fffffc) | (rel
& 0x3fffffc);
2538 target_write_memory (from
, (unsigned char *) &insn
, 4);
2541 /* Table of emit ops for 32-bit. */
2543 static struct emit_ops ppc_emit_ops_impl
=
2551 ppc_emit_rsh_signed
,
2552 ppc_emit_rsh_unsigned
,
2560 ppc_emit_less_signed
,
2561 ppc_emit_less_unsigned
,
2565 ppc_write_goto_address
,
2570 ppc_emit_stack_flush
,
2573 ppc_emit_stack_adjust
,
2574 ppc_emit_int_call_1
,
2575 ppc_emit_void_call_2
,
2584 #ifdef __powerpc64__
2588 Bytecode execution stack frame - 64-bit
2590 | LR save area (SP + 16)
2591 | CR save area (SP + 8)
2592 SP' -> +- Back chain (SP + 0)
2593 | Save r31 for access saved arguments
2594 | Save r30 for bytecode stack pointer
2595 | Save r4 for incoming argument *value
2596 | Save r3 for incoming argument regs
2597 r30 -> +- Bytecode execution stack
2599 | 64-byte (8 doublewords) at initial.
2600 | Expand stack as needed.
2603 | Some padding for minimum stack frame.
2605 SP +- Back-chain (SP')
2608 = 112 + (4 * 8) + 64
2611 r30 is the stack-pointer for bytecode machine.
2612 It should point to next-empty, so we can use LDU for pop.
2613 r3 is used for cache of TOP value.
2614 It was the first argument, pointer to regs.
2615 r4 is the second argument, pointer to the result.
2616 We should set *result = TOP after leaving this function.
2619 * To restore stack at epilogue
2621 * To check stack is big enough for bytecode execution.
2622 => r30 - 8 > SP + 112
2623 * To return execution result.
2628 /* Emit prologue in inferior memory. See above comments. */
2631 ppc64v1_emit_prologue (void)
2633 /* On ELFv1, function pointers really point to function descriptor,
2634 so emit one here. We don't care about contents of words 1 and 2,
2635 so let them just overlap out code. */
2636 uint64_t opd
= current_insn_ptr
+ 8;
2639 /* Mind the strict aliasing rules. */
2640 memcpy (buf
, &opd
, sizeof buf
);
2642 EMIT_ASM (/* Save return address. */
2645 /* Save r30 and incoming arguments. */
2650 /* Point r31 to current r1 for access arguments. */
2652 /* Adjust SP. 208 is the initial frame size. */
2653 "stdu 1, -208(1) \n"
2654 /* Set r30 to pointing stack-top. */
2655 "addi 30, 1, 168 \n"
2656 /* Initial r3/TOP to 0. */
2660 /* Emit prologue in inferior memory. See above comments. */
2663 ppc64v2_emit_prologue (void)
2665 EMIT_ASM (/* Save return address. */
2668 /* Save r30 and incoming arguments. */
2673 /* Point r31 to current r1 for access arguments. */
2675 /* Adjust SP. 208 is the initial frame size. */
2676 "stdu 1, -208(1) \n"
2677 /* Set r30 to pointing stack-top. */
2678 "addi 30, 1, 168 \n"
2679 /* Initial r3/TOP to 0. */
2683 /* Emit epilogue in inferior memory. See above comments. */
2686 ppc64_emit_epilogue (void)
2688 EMIT_ASM (/* Restore SP. */
2693 /* Restore registers. */
2698 /* Return 0 for no-error. */
2704 /* TOP = stack[--sp] + TOP */
2707 ppc64_emit_add (void)
2709 EMIT_ASM ("ldu 4, 8(30) \n"
2713 /* TOP = stack[--sp] - TOP */
2716 ppc64_emit_sub (void)
2718 EMIT_ASM ("ldu 4, 8(30) \n"
2722 /* TOP = stack[--sp] * TOP */
2725 ppc64_emit_mul (void)
2727 EMIT_ASM ("ldu 4, 8(30) \n"
2728 "mulld 3, 4, 3 \n");
2731 /* TOP = stack[--sp] << TOP */
2734 ppc64_emit_lsh (void)
2736 EMIT_ASM ("ldu 4, 8(30) \n"
2740 /* Top = stack[--sp] >> TOP
2741 (Arithmetic shift right) */
2744 ppc64_emit_rsh_signed (void)
2746 EMIT_ASM ("ldu 4, 8(30) \n"
2750 /* Top = stack[--sp] >> TOP
2751 (Logical shift right) */
2754 ppc64_emit_rsh_unsigned (void)
2756 EMIT_ASM ("ldu 4, 8(30) \n"
2760 /* Emit code for signed-extension specified by ARG. */
2763 ppc64_emit_ext (int arg
)
2768 EMIT_ASM ("extsb 3, 3");
2771 EMIT_ASM ("extsh 3, 3");
2774 EMIT_ASM ("extsw 3, 3");
2781 /* Emit code for zero-extension specified by ARG. */
2784 ppc64_emit_zero_ext (int arg
)
2789 EMIT_ASM ("rldicl 3,3,0,56");
2792 EMIT_ASM ("rldicl 3,3,0,48");
2795 EMIT_ASM ("rldicl 3,3,0,32");
2803 i.e., TOP = (TOP == 0) ? 1 : 0; */
2806 ppc64_emit_log_not (void)
2808 EMIT_ASM ("cntlzd 3, 3 \n"
2812 /* TOP = stack[--sp] & TOP */
2815 ppc64_emit_bit_and (void)
2817 EMIT_ASM ("ldu 4, 8(30) \n"
2821 /* TOP = stack[--sp] | TOP */
2824 ppc64_emit_bit_or (void)
2826 EMIT_ASM ("ldu 4, 8(30) \n"
2830 /* TOP = stack[--sp] ^ TOP */
2833 ppc64_emit_bit_xor (void)
2835 EMIT_ASM ("ldu 4, 8(30) \n"
2840 i.e., TOP = ~(TOP | TOP) */
2843 ppc64_emit_bit_not (void)
2845 EMIT_ASM ("nor 3, 3, 3 \n");
2848 /* TOP = stack[--sp] == TOP */
2851 ppc64_emit_equal (void)
2853 EMIT_ASM ("ldu 4, 8(30) \n"
2859 /* TOP = stack[--sp] < TOP
2860 (Signed comparison) */
2863 ppc64_emit_less_signed (void)
2865 EMIT_ASM ("ldu 4, 8(30) \n"
2868 "rlwinm 3, 3, 29, 31, 31 \n");
2871 /* TOP = stack[--sp] < TOP
2872 (Unsigned comparison) */
2875 ppc64_emit_less_unsigned (void)
2877 EMIT_ASM ("ldu 4, 8(30) \n"
2880 "rlwinm 3, 3, 29, 31, 31 \n");
2883 /* Access the memory address in TOP in size of SIZE.
2884 Zero-extend the read value. */
2887 ppc64_emit_ref (int size
)
2892 EMIT_ASM ("lbz 3, 0(3)");
2895 EMIT_ASM ("lhz 3, 0(3)");
2898 EMIT_ASM ("lwz 3, 0(3)");
2901 EMIT_ASM ("ld 3, 0(3)");
2909 ppc64_emit_const (LONGEST num
)
2914 p
+= gen_limm (p
, 3, num
, 1);
2916 emit_insns (buf
, p
- buf
);
2917 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2920 /* Set TOP to the value of register REG by calling get_raw_reg function
2921 with two argument, collected buffer and register number. */
2924 ppc64v1_emit_reg (int reg
)
2929 /* fctx->regs is passed in r3 and then saved in 176(1). */
2930 p
+= GEN_LD (p
, 3, 31, -32);
2931 p
+= GEN_LI (p
, 4, reg
);
2932 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2933 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 1);
2934 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2936 emit_insns (buf
, p
- buf
);
2937 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2940 /* Likewise, for ELFv2. */
2943 ppc64v2_emit_reg (int reg
)
2948 /* fctx->regs is passed in r3 and then saved in 176(1). */
2949 p
+= GEN_LD (p
, 3, 31, -32);
2950 p
+= GEN_LI (p
, 4, reg
);
2951 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2952 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 0);
2953 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2955 emit_insns (buf
, p
- buf
);
2956 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2959 /* TOP = stack[--sp] */
2962 ppc64_emit_pop (void)
2964 EMIT_ASM ("ldu 3, 8(30)");
2967 /* stack[sp++] = TOP
2969 Because we may use up bytecode stack, expand 8 doublewords more
2973 ppc64_emit_stack_flush (void)
2975 /* Make sure bytecode stack is big enough before push.
2976 Otherwise, expand 64-byte more. */
2978 EMIT_ASM (" std 3, 0(30) \n"
2979 " addi 4, 30, -(112 + 8) \n"
2982 " stdu 31, -64(1) \n"
2983 "1:addi 30, 30, -8 \n");
2986 /* Swap TOP and stack[sp-1] */
2989 ppc64_emit_swap (void)
2991 EMIT_ASM ("ld 4, 8(30) \n"
2996 /* Call function FN - ELFv1. */
2999 ppc64v1_emit_call (CORE_ADDR fn
)
3004 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3005 p
+= gen_call (p
, fn
, 1, 1);
3006 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3008 emit_insns (buf
, p
- buf
);
3009 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3012 /* Call function FN - ELFv2. */
3015 ppc64v2_emit_call (CORE_ADDR fn
)
3020 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3021 p
+= gen_call (p
, fn
, 1, 0);
3022 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3024 emit_insns (buf
, p
- buf
);
3025 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3028 /* FN's prototype is `LONGEST(*fn)(int)'.
3033 ppc64v1_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3038 /* Setup argument. arg1 is a 16-bit value. */
3039 p
+= gen_limm (p
, 3, arg1
, 1);
3040 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3041 p
+= gen_call (p
, fn
, 1, 1);
3042 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3044 emit_insns (buf
, p
- buf
);
3045 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3048 /* Likewise for ELFv2. */
3051 ppc64v2_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3056 /* Setup argument. arg1 is a 16-bit value. */
3057 p
+= gen_limm (p
, 3, arg1
, 1);
3058 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3059 p
+= gen_call (p
, fn
, 1, 0);
3060 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3062 emit_insns (buf
, p
- buf
);
3063 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3066 /* FN's prototype is `void(*fn)(int,LONGEST)'.
3069 TOP should be preserved/restored before/after the call. */
3072 ppc64v1_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3077 /* Save TOP. 0(30) is next-empty. */
3078 p
+= GEN_STD (p
, 3, 30, 0);
3080 /* Setup argument. arg1 is a 16-bit value. */
3081 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3082 p
+= gen_limm (p
, 3, arg1
, 1);
3083 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3084 p
+= gen_call (p
, fn
, 1, 1);
3085 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3088 p
+= GEN_LD (p
, 3, 30, 0);
3090 emit_insns (buf
, p
- buf
);
3091 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3094 /* Likewise for ELFv2. */
3097 ppc64v2_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3102 /* Save TOP. 0(30) is next-empty. */
3103 p
+= GEN_STD (p
, 3, 30, 0);
3105 /* Setup argument. arg1 is a 16-bit value. */
3106 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3107 p
+= gen_limm (p
, 3, arg1
, 1);
3108 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3109 p
+= gen_call (p
, fn
, 1, 0);
3110 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3113 p
+= GEN_LD (p
, 3, 30, 0);
3115 emit_insns (buf
, p
- buf
);
3116 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3119 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
3122 ppc64_emit_if_goto (int *offset_p
, int *size_p
)
3124 EMIT_ASM ("cmpdi 7, 3, 0 \n"
3134 /* Goto if stack[--sp] == TOP */
3137 ppc64_emit_eq_goto (int *offset_p
, int *size_p
)
3139 EMIT_ASM ("ldu 4, 8(30) \n"
3150 /* Goto if stack[--sp] != TOP */
3153 ppc64_emit_ne_goto (int *offset_p
, int *size_p
)
3155 EMIT_ASM ("ldu 4, 8(30) \n"
3166 /* Goto if stack[--sp] < TOP */
3169 ppc64_emit_lt_goto (int *offset_p
, int *size_p
)
3171 EMIT_ASM ("ldu 4, 8(30) \n"
3182 /* Goto if stack[--sp] <= TOP */
3185 ppc64_emit_le_goto (int *offset_p
, int *size_p
)
3187 EMIT_ASM ("ldu 4, 8(30) \n"
3198 /* Goto if stack[--sp] > TOP */
3201 ppc64_emit_gt_goto (int *offset_p
, int *size_p
)
3203 EMIT_ASM ("ldu 4, 8(30) \n"
3214 /* Goto if stack[--sp] >= TOP */
3217 ppc64_emit_ge_goto (int *offset_p
, int *size_p
)
3219 EMIT_ASM ("ldu 4, 8(30) \n"
3230 /* Table of emit ops for 64-bit ELFv1. */
3232 static struct emit_ops ppc64v1_emit_ops_impl
=
3234 ppc64v1_emit_prologue
,
3235 ppc64_emit_epilogue
,
3240 ppc64_emit_rsh_signed
,
3241 ppc64_emit_rsh_unsigned
,
3249 ppc64_emit_less_signed
,
3250 ppc64_emit_less_unsigned
,
3254 ppc_write_goto_address
,
3259 ppc64_emit_stack_flush
,
3260 ppc64_emit_zero_ext
,
3262 ppc_emit_stack_adjust
,
3263 ppc64v1_emit_int_call_1
,
3264 ppc64v1_emit_void_call_2
,
3273 /* Table of emit ops for 64-bit ELFv2. */
3275 static struct emit_ops ppc64v2_emit_ops_impl
=
3277 ppc64v2_emit_prologue
,
3278 ppc64_emit_epilogue
,
3283 ppc64_emit_rsh_signed
,
3284 ppc64_emit_rsh_unsigned
,
3292 ppc64_emit_less_signed
,
3293 ppc64_emit_less_unsigned
,
3297 ppc_write_goto_address
,
3302 ppc64_emit_stack_flush
,
3303 ppc64_emit_zero_ext
,
3305 ppc_emit_stack_adjust
,
3306 ppc64v2_emit_int_call_1
,
3307 ppc64v2_emit_void_call_2
,
3318 /* Implementation of linux_target_ops method "emit_ops". */
3320 static struct emit_ops
*
3323 #ifdef __powerpc64__
3324 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3326 if (register_size (regcache
->tdesc
, 0) == 8)
3328 if (is_elfv2_inferior ())
3329 return &ppc64v2_emit_ops_impl
;
3331 return &ppc64v1_emit_ops_impl
;
3334 return &ppc_emit_ops_impl
;
3337 /* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3340 ppc_get_ipa_tdesc_idx (void)
3342 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3343 const struct target_desc
*tdesc
= regcache
->tdesc
;
3345 #ifdef __powerpc64__
3346 if (tdesc
== tdesc_powerpc_64l
)
3347 return PPC_TDESC_BASE
;
3348 if (tdesc
== tdesc_powerpc_altivec64l
)
3349 return PPC_TDESC_ALTIVEC
;
3350 if (tdesc
== tdesc_powerpc_vsx64l
)
3351 return PPC_TDESC_VSX
;
3352 if (tdesc
== tdesc_powerpc_isa205_64l
)
3353 return PPC_TDESC_ISA205
;
3354 if (tdesc
== tdesc_powerpc_isa205_altivec64l
)
3355 return PPC_TDESC_ISA205_ALTIVEC
;
3356 if (tdesc
== tdesc_powerpc_isa205_vsx64l
)
3357 return PPC_TDESC_ISA205_VSX
;
3358 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx64l
)
3359 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3360 if (tdesc
== tdesc_powerpc_isa207_vsx64l
)
3361 return PPC_TDESC_ISA207_VSX
;
3362 if (tdesc
== tdesc_powerpc_isa207_htm_vsx64l
)
3363 return PPC_TDESC_ISA207_HTM_VSX
;
3366 if (tdesc
== tdesc_powerpc_32l
)
3367 return PPC_TDESC_BASE
;
3368 if (tdesc
== tdesc_powerpc_altivec32l
)
3369 return PPC_TDESC_ALTIVEC
;
3370 if (tdesc
== tdesc_powerpc_vsx32l
)
3371 return PPC_TDESC_VSX
;
3372 if (tdesc
== tdesc_powerpc_isa205_32l
)
3373 return PPC_TDESC_ISA205
;
3374 if (tdesc
== tdesc_powerpc_isa205_altivec32l
)
3375 return PPC_TDESC_ISA205_ALTIVEC
;
3376 if (tdesc
== tdesc_powerpc_isa205_vsx32l
)
3377 return PPC_TDESC_ISA205_VSX
;
3378 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx32l
)
3379 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3380 if (tdesc
== tdesc_powerpc_isa207_vsx32l
)
3381 return PPC_TDESC_ISA207_VSX
;
3382 if (tdesc
== tdesc_powerpc_isa207_htm_vsx32l
)
3383 return PPC_TDESC_ISA207_HTM_VSX
;
3384 if (tdesc
== tdesc_powerpc_e500l
)
3385 return PPC_TDESC_E500
;
3390 struct linux_target_ops the_low_target
= {
3391 ppc_cannot_fetch_register
,
3392 ppc_cannot_store_register
,
3393 NULL
, /* fetch_register */
3396 NULL
, /* breakpoint_kind_from_pc */
3397 ppc_sw_breakpoint_from_kind
,
3401 ppc_supports_z_point_type
,
3406 ppc_collect_ptrace_register
,
3407 ppc_supply_ptrace_register
,
3408 NULL
, /* siginfo_fixup */
3409 NULL
, /* new_process */
3410 NULL
, /* delete_process */
3411 NULL
, /* new_thread */
3412 NULL
, /* delete_thread */
3413 NULL
, /* new_fork */
3414 NULL
, /* prepare_to_resume */
3415 NULL
, /* process_qsupported */
3416 ppc_supports_tracepoints
,
3417 ppc_get_thread_area
,
3418 ppc_install_fast_tracepoint_jump_pad
,
3420 ppc_get_min_fast_tracepoint_insn_len
,
3421 NULL
, /* supports_range_stepping */
3422 NULL
, /* breakpoint_kind_from_current_state */
3423 ppc_supports_hardware_single_step
,
3424 NULL
, /* get_syscall_trapinfo */
3425 ppc_get_ipa_tdesc_idx
,
3428 /* The linux target ops object. */
3430 linux_process_target
*the_linux_target
= &the_ppc_target
;
3433 initialize_low_arch (void)
3435 /* Initialize the Linux target descriptions. */
3437 init_registers_powerpc_32l ();
3438 init_registers_powerpc_altivec32l ();
3439 init_registers_powerpc_vsx32l ();
3440 init_registers_powerpc_isa205_32l ();
3441 init_registers_powerpc_isa205_altivec32l ();
3442 init_registers_powerpc_isa205_vsx32l ();
3443 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
3444 init_registers_powerpc_isa207_vsx32l ();
3445 init_registers_powerpc_isa207_htm_vsx32l ();
3446 init_registers_powerpc_e500l ();
3448 init_registers_powerpc_64l ();
3449 init_registers_powerpc_altivec64l ();
3450 init_registers_powerpc_vsx64l ();
3451 init_registers_powerpc_isa205_64l ();
3452 init_registers_powerpc_isa205_altivec64l ();
3453 init_registers_powerpc_isa205_vsx64l ();
3454 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
3455 init_registers_powerpc_isa207_vsx64l ();
3456 init_registers_powerpc_isa207_htm_vsx64l ();
3459 initialize_regsets_info (&ppc_regsets_info
);