1 /* GNU/Linux/x86-64 specific low level interface, for the remote server
3 Copyright (C) 2002-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "linux-low.h"
27 #include "gdbsupport/x86-xstate.h"
28 #include "nat/gdb_ptrace.h"
31 #include "nat/amd64-linux-siginfo.h"
34 #include "gdb_proc_service.h"
35 /* Don't include elf/common.h if linux/elf.h got included by
36 gdb_proc_service.h. */
38 #include "elf/common.h"
41 #include "gdbsupport/agent.h"
43 #include "tracepoint.h"
45 #include "nat/linux-nat.h"
46 #include "nat/x86-linux.h"
47 #include "nat/x86-linux-dregs.h"
48 #include "linux-x86-tdesc.h"
51 static struct target_desc
*tdesc_amd64_linux_no_xml
;
53 static struct target_desc
*tdesc_i386_linux_no_xml
;
56 static unsigned char jump_insn
[] = { 0xe9, 0, 0, 0, 0 };
57 static unsigned char small_jump_insn
[] = { 0x66, 0xe9, 0, 0 };
59 /* Backward compatibility for gdb without XML support. */
61 static const char *xmltarget_i386_linux_no_xml
= "@<target>\
62 <architecture>i386</architecture>\
63 <osabi>GNU/Linux</osabi>\
67 static const char *xmltarget_amd64_linux_no_xml
= "@<target>\
68 <architecture>i386:x86-64</architecture>\
69 <osabi>GNU/Linux</osabi>\
74 #include <sys/procfs.h>
77 #ifndef PTRACE_GET_THREAD_AREA
78 #define PTRACE_GET_THREAD_AREA 25
81 /* This definition comes from prctl.h, but some kernels may not have it. */
82 #ifndef PTRACE_ARCH_PRCTL
83 #define PTRACE_ARCH_PRCTL 30
86 /* The following definitions come from prctl.h, but may be absent
87 for certain configurations. */
89 #define ARCH_SET_GS 0x1001
90 #define ARCH_SET_FS 0x1002
91 #define ARCH_GET_FS 0x1003
92 #define ARCH_GET_GS 0x1004
95 /* Linux target op definitions for the x86 architecture.
96 This is initialized assuming an amd64 target.
97 'low_arch_setup' will correct it for i386 or amd64 targets. */
99 class x86_target
: public linux_process_target
103 /* Update all the target description of all processes; a new GDB
104 connected, and it may or not support xml target descriptions. */
105 void update_xmltarget ();
107 const regs_info
*get_regs_info () override
;
111 void low_arch_setup () override
;
113 bool low_cannot_fetch_register (int regno
) override
;
115 bool low_cannot_store_register (int regno
) override
;
118 /* The singleton target ops object. */
120 static x86_target the_x86_target
;
122 /* Per-process arch-specific data we want to keep. */
124 struct arch_process_info
126 struct x86_debug_reg_state debug_reg_state
;
131 /* Mapping between the general-purpose registers in `struct user'
132 format and GDB's register array layout.
133 Note that the transfer layout uses 64-bit regs. */
134 static /*const*/ int i386_regmap
[] =
136 RAX
* 8, RCX
* 8, RDX
* 8, RBX
* 8,
137 RSP
* 8, RBP
* 8, RSI
* 8, RDI
* 8,
138 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
139 DS
* 8, ES
* 8, FS
* 8, GS
* 8
142 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
144 /* So code below doesn't have to care, i386 or amd64. */
145 #define ORIG_EAX ORIG_RAX
148 static const int x86_64_regmap
[] =
150 RAX
* 8, RBX
* 8, RCX
* 8, RDX
* 8,
151 RSI
* 8, RDI
* 8, RBP
* 8, RSP
* 8,
152 R8
* 8, R9
* 8, R10
* 8, R11
* 8,
153 R12
* 8, R13
* 8, R14
* 8, R15
* 8,
154 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
155 DS
* 8, ES
* 8, FS
* 8, GS
* 8,
156 -1, -1, -1, -1, -1, -1, -1, -1,
157 -1, -1, -1, -1, -1, -1, -1, -1,
158 -1, -1, -1, -1, -1, -1, -1, -1,
160 -1, -1, -1, -1, -1, -1, -1, -1,
162 #ifdef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE
167 -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */
168 -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */
169 -1, -1, -1, -1, -1, -1, -1, -1, /* xmm16 ... xmm31 (AVX512) */
170 -1, -1, -1, -1, -1, -1, -1, -1,
171 -1, -1, -1, -1, -1, -1, -1, -1, /* ymm16 ... ymm31 (AVX512) */
172 -1, -1, -1, -1, -1, -1, -1, -1,
173 -1, -1, -1, -1, -1, -1, -1, -1, /* k0 ... k7 (AVX512) */
174 -1, -1, -1, -1, -1, -1, -1, -1, /* zmm0 ... zmm31 (AVX512) */
175 -1, -1, -1, -1, -1, -1, -1, -1,
176 -1, -1, -1, -1, -1, -1, -1, -1,
177 -1, -1, -1, -1, -1, -1, -1, -1,
181 #define X86_64_NUM_REGS (sizeof (x86_64_regmap) / sizeof (x86_64_regmap[0]))
182 #define X86_64_USER_REGS (GS + 1)
184 #else /* ! __x86_64__ */
186 /* Mapping between the general-purpose registers in `struct user'
187 format and GDB's register array layout. */
188 static /*const*/ int i386_regmap
[] =
190 EAX
* 4, ECX
* 4, EDX
* 4, EBX
* 4,
191 UESP
* 4, EBP
* 4, ESI
* 4, EDI
* 4,
192 EIP
* 4, EFL
* 4, CS
* 4, SS
* 4,
193 DS
* 4, ES
* 4, FS
* 4, GS
* 4
196 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
204 /* Returns true if the current inferior belongs to a x86-64 process,
208 is_64bit_tdesc (void)
210 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
212 return register_size (regcache
->tdesc
, 0) == 8;
218 /* Called by libthread_db. */
221 ps_get_thread_area (struct ps_prochandle
*ph
,
222 lwpid_t lwpid
, int idx
, void **base
)
225 int use_64bit
= is_64bit_tdesc ();
232 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_FS
) == 0)
236 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_GS
) == 0)
247 unsigned int desc
[4];
249 if (ptrace (PTRACE_GET_THREAD_AREA
, lwpid
,
250 (void *) (intptr_t) idx
, (unsigned long) &desc
) < 0)
253 /* Ensure we properly extend the value to 64-bits for x86_64. */
254 *base
= (void *) (uintptr_t) desc
[1];
259 /* Get the thread area address. This is used to recognize which
260 thread is which when tracing with the in-process agent library. We
261 don't read anything from the address, and treat it as opaque; it's
262 the address itself that we assume is unique per-thread. */
265 x86_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
268 int use_64bit
= is_64bit_tdesc ();
273 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_FS
) == 0)
275 *addr
= (CORE_ADDR
) (uintptr_t) base
;
284 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
285 struct thread_info
*thr
= get_lwp_thread (lwp
);
286 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
287 unsigned int desc
[4];
289 const int reg_thread_area
= 3; /* bits to scale down register value. */
292 collect_register_by_name (regcache
, "gs", &gs
);
294 idx
= gs
>> reg_thread_area
;
296 if (ptrace (PTRACE_GET_THREAD_AREA
,
298 (void *) (long) idx
, (unsigned long) &desc
) < 0)
309 x86_target::low_cannot_store_register (int regno
)
312 if (is_64bit_tdesc ())
316 return regno
>= I386_NUM_REGS
;
320 x86_target::low_cannot_fetch_register (int regno
)
323 if (is_64bit_tdesc ())
327 return regno
>= I386_NUM_REGS
;
331 x86_fill_gregset (struct regcache
*regcache
, void *buf
)
336 if (register_size (regcache
->tdesc
, 0) == 8)
338 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
339 if (x86_64_regmap
[i
] != -1)
340 collect_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
342 #ifndef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE
345 int lwpid
= lwpid_of (current_thread
);
347 collect_register_by_name (regcache
, "fs_base", &base
);
348 ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_SET_FS
);
350 collect_register_by_name (regcache
, "gs_base", &base
);
351 ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_SET_GS
);
358 /* 32-bit inferior registers need to be zero-extended.
359 Callers would read uninitialized memory otherwise. */
360 memset (buf
, 0x00, X86_64_USER_REGS
* 8);
363 for (i
= 0; i
< I386_NUM_REGS
; i
++)
364 collect_register (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
366 collect_register_by_name (regcache
, "orig_eax",
367 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
370 /* Sign extend EAX value to avoid potential syscall restart
373 See amd64_linux_collect_native_gregset() in gdb/amd64-linux-nat.c
374 for a detailed explanation. */
375 if (register_size (regcache
->tdesc
, 0) == 4)
377 void *ptr
= ((gdb_byte
*) buf
378 + i386_regmap
[find_regno (regcache
->tdesc
, "eax")]);
380 *(int64_t *) ptr
= *(int32_t *) ptr
;
386 x86_store_gregset (struct regcache
*regcache
, const void *buf
)
391 if (register_size (regcache
->tdesc
, 0) == 8)
393 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
394 if (x86_64_regmap
[i
] != -1)
395 supply_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
397 #ifndef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE
400 int lwpid
= lwpid_of (current_thread
);
402 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_FS
) == 0)
403 supply_register_by_name (regcache
, "fs_base", &base
);
405 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_GS
) == 0)
406 supply_register_by_name (regcache
, "gs_base", &base
);
413 for (i
= 0; i
< I386_NUM_REGS
; i
++)
414 supply_register (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
416 supply_register_by_name (regcache
, "orig_eax",
417 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
421 x86_fill_fpregset (struct regcache
*regcache
, void *buf
)
424 i387_cache_to_fxsave (regcache
, buf
);
426 i387_cache_to_fsave (regcache
, buf
);
431 x86_store_fpregset (struct regcache
*regcache
, const void *buf
)
434 i387_fxsave_to_cache (regcache
, buf
);
436 i387_fsave_to_cache (regcache
, buf
);
443 x86_fill_fpxregset (struct regcache
*regcache
, void *buf
)
445 i387_cache_to_fxsave (regcache
, buf
);
449 x86_store_fpxregset (struct regcache
*regcache
, const void *buf
)
451 i387_fxsave_to_cache (regcache
, buf
);
457 x86_fill_xstateregset (struct regcache
*regcache
, void *buf
)
459 i387_cache_to_xsave (regcache
, buf
);
463 x86_store_xstateregset (struct regcache
*regcache
, const void *buf
)
465 i387_xsave_to_cache (regcache
, buf
);
468 /* ??? The non-biarch i386 case stores all the i387 regs twice.
469 Once in i387_.*fsave.* and once in i387_.*fxsave.*.
470 This is, presumably, to handle the case where PTRACE_[GS]ETFPXREGS
471 doesn't work. IWBN to avoid the duplication in the case where it
472 does work. Maybe the arch_setup routine could check whether it works
473 and update the supported regsets accordingly. */
475 static struct regset_info x86_regsets
[] =
477 #ifdef HAVE_PTRACE_GETREGS
478 { PTRACE_GETREGS
, PTRACE_SETREGS
, 0, sizeof (elf_gregset_t
),
480 x86_fill_gregset
, x86_store_gregset
},
481 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_X86_XSTATE
, 0,
482 EXTENDED_REGS
, x86_fill_xstateregset
, x86_store_xstateregset
},
484 # ifdef HAVE_PTRACE_GETFPXREGS
485 { PTRACE_GETFPXREGS
, PTRACE_SETFPXREGS
, 0, sizeof (elf_fpxregset_t
),
487 x86_fill_fpxregset
, x86_store_fpxregset
},
490 { PTRACE_GETFPREGS
, PTRACE_SETFPREGS
, 0, sizeof (elf_fpregset_t
),
492 x86_fill_fpregset
, x86_store_fpregset
},
493 #endif /* HAVE_PTRACE_GETREGS */
498 x86_get_pc (struct regcache
*regcache
)
500 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
506 collect_register_by_name (regcache
, "rip", &pc
);
507 return (CORE_ADDR
) pc
;
513 collect_register_by_name (regcache
, "eip", &pc
);
514 return (CORE_ADDR
) pc
;
519 x86_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
521 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
527 supply_register_by_name (regcache
, "rip", &newpc
);
533 supply_register_by_name (regcache
, "eip", &newpc
);
537 static const gdb_byte x86_breakpoint
[] = { 0xCC };
538 #define x86_breakpoint_len 1
541 x86_breakpoint_at (CORE_ADDR pc
)
545 the_target
->read_memory (pc
, &c
, 1);
552 /* Low-level function vector. */
553 struct x86_dr_low_type x86_dr_low
=
555 x86_linux_dr_set_control
,
556 x86_linux_dr_set_addr
,
557 x86_linux_dr_get_addr
,
558 x86_linux_dr_get_status
,
559 x86_linux_dr_get_control
,
563 /* Breakpoint/Watchpoint support. */
566 x86_supports_z_point_type (char z_type
)
572 case Z_PACKET_WRITE_WP
:
573 case Z_PACKET_ACCESS_WP
:
581 x86_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
582 int size
, struct raw_breakpoint
*bp
)
584 struct process_info
*proc
= current_process ();
588 case raw_bkpt_type_hw
:
589 case raw_bkpt_type_write_wp
:
590 case raw_bkpt_type_access_wp
:
592 enum target_hw_bp_type hw_type
593 = raw_bkpt_type_to_target_hw_bp_type (type
);
594 struct x86_debug_reg_state
*state
595 = &proc
->priv
->arch_private
->debug_reg_state
;
597 return x86_dr_insert_watchpoint (state
, hw_type
, addr
, size
);
607 x86_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
608 int size
, struct raw_breakpoint
*bp
)
610 struct process_info
*proc
= current_process ();
614 case raw_bkpt_type_hw
:
615 case raw_bkpt_type_write_wp
:
616 case raw_bkpt_type_access_wp
:
618 enum target_hw_bp_type hw_type
619 = raw_bkpt_type_to_target_hw_bp_type (type
);
620 struct x86_debug_reg_state
*state
621 = &proc
->priv
->arch_private
->debug_reg_state
;
623 return x86_dr_remove_watchpoint (state
, hw_type
, addr
, size
);
632 x86_stopped_by_watchpoint (void)
634 struct process_info
*proc
= current_process ();
635 return x86_dr_stopped_by_watchpoint (&proc
->priv
->arch_private
->debug_reg_state
);
639 x86_stopped_data_address (void)
641 struct process_info
*proc
= current_process ();
643 if (x86_dr_stopped_data_address (&proc
->priv
->arch_private
->debug_reg_state
,
649 /* Called when a new process is created. */
651 static struct arch_process_info
*
652 x86_linux_new_process (void)
654 struct arch_process_info
*info
= XCNEW (struct arch_process_info
);
656 x86_low_init_dregs (&info
->debug_reg_state
);
661 /* Called when a process is being deleted. */
664 x86_linux_delete_process (struct arch_process_info
*info
)
669 /* Target routine for linux_new_fork. */
672 x86_linux_new_fork (struct process_info
*parent
, struct process_info
*child
)
674 /* These are allocated by linux_add_process. */
675 gdb_assert (parent
->priv
!= NULL
676 && parent
->priv
->arch_private
!= NULL
);
677 gdb_assert (child
->priv
!= NULL
678 && child
->priv
->arch_private
!= NULL
);
680 /* Linux kernel before 2.6.33 commit
681 72f674d203cd230426437cdcf7dd6f681dad8b0d
682 will inherit hardware debug registers from parent
683 on fork/vfork/clone. Newer Linux kernels create such tasks with
684 zeroed debug registers.
686 GDB core assumes the child inherits the watchpoints/hw
687 breakpoints of the parent, and will remove them all from the
688 forked off process. Copy the debug registers mirrors into the
689 new process so that all breakpoints and watchpoints can be
690 removed together. The debug registers mirror will become zeroed
691 in the end before detaching the forked off process, thus making
692 this compatible with older Linux kernels too. */
694 *child
->priv
->arch_private
= *parent
->priv
->arch_private
;
697 /* See nat/x86-dregs.h. */
699 struct x86_debug_reg_state
*
700 x86_debug_reg_state (pid_t pid
)
702 struct process_info
*proc
= find_process_pid (pid
);
704 return &proc
->priv
->arch_private
->debug_reg_state
;
707 /* When GDBSERVER is built as a 64-bit application on linux, the
708 PTRACE_GETSIGINFO data is always presented in 64-bit layout. Since
709 debugging a 32-bit inferior with a 64-bit GDBSERVER should look the same
710 as debugging it with a 32-bit GDBSERVER, we do the 32-bit <-> 64-bit
711 conversion in-place ourselves. */
713 /* Convert a ptrace/host siginfo object, into/from the siginfo in the
714 layout of the inferiors' architecture. Returns true if any
715 conversion was done; false otherwise. If DIRECTION is 1, then copy
716 from INF to PTRACE. If DIRECTION is 0, copy from PTRACE to
720 x86_siginfo_fixup (siginfo_t
*ptrace
, gdb_byte
*inf
, int direction
)
723 unsigned int machine
;
724 int tid
= lwpid_of (current_thread
);
725 int is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
727 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
728 if (!is_64bit_tdesc ())
729 return amd64_linux_siginfo_fixup_common (ptrace
, inf
, direction
,
731 /* No fixup for native x32 GDB. */
732 else if (!is_elf64
&& sizeof (void *) == 8)
733 return amd64_linux_siginfo_fixup_common (ptrace
, inf
, direction
,
742 /* Format of XSAVE extended state is:
746 sw_usable_bytes[464..511]
747 xstate_hdr_bytes[512..575]
752 Same memory layout will be used for the coredump NT_X86_XSTATE
753 representing the XSAVE extended state registers.
755 The first 8 bytes of the sw_usable_bytes[464..467] is the OS enabled
756 extended state mask, which is the same as the extended control register
757 0 (the XFEATURE_ENABLED_MASK register), XCR0. We can use this mask
758 together with the mask saved in the xstate_hdr_bytes to determine what
759 states the processor/OS supports and what state, used or initialized,
760 the process/thread is in. */
761 #define I386_LINUX_XSAVE_XCR0_OFFSET 464
763 /* Does the current host support the GETFPXREGS request? The header
764 file may or may not define it, and even if it is defined, the
765 kernel will return EIO if it's running on a pre-SSE processor. */
766 int have_ptrace_getfpxregs
=
767 #ifdef HAVE_PTRACE_GETFPXREGS
774 /* Get Linux/x86 target description from running target. */
776 static const struct target_desc
*
777 x86_linux_read_description (void)
779 unsigned int machine
;
783 static uint64_t xcr0
;
784 struct regset_info
*regset
;
786 tid
= lwpid_of (current_thread
);
788 is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
790 if (sizeof (void *) == 4)
793 error (_("Can't debug 64-bit process with 32-bit GDBserver"));
795 else if (machine
== EM_X86_64
)
796 error (_("Can't debug x86-64 process with 32-bit GDBserver"));
800 #if !defined __x86_64__ && defined HAVE_PTRACE_GETFPXREGS
801 if (machine
== EM_386
&& have_ptrace_getfpxregs
== -1)
803 elf_fpxregset_t fpxregs
;
805 if (ptrace (PTRACE_GETFPXREGS
, tid
, 0, (long) &fpxregs
) < 0)
807 have_ptrace_getfpxregs
= 0;
808 have_ptrace_getregset
= 0;
809 return i386_linux_read_description (X86_XSTATE_X87
);
812 have_ptrace_getfpxregs
= 1;
818 x86_xcr0
= X86_XSTATE_SSE_MASK
;
822 if (machine
== EM_X86_64
)
823 return tdesc_amd64_linux_no_xml
;
826 return tdesc_i386_linux_no_xml
;
829 if (have_ptrace_getregset
== -1)
831 uint64_t xstateregs
[(X86_XSTATE_SSE_SIZE
/ sizeof (uint64_t))];
834 iov
.iov_base
= xstateregs
;
835 iov
.iov_len
= sizeof (xstateregs
);
837 /* Check if PTRACE_GETREGSET works. */
838 if (ptrace (PTRACE_GETREGSET
, tid
,
839 (unsigned int) NT_X86_XSTATE
, (long) &iov
) < 0)
840 have_ptrace_getregset
= 0;
843 have_ptrace_getregset
= 1;
845 /* Get XCR0 from XSAVE extended state. */
846 xcr0
= xstateregs
[(I386_LINUX_XSAVE_XCR0_OFFSET
847 / sizeof (uint64_t))];
849 /* Use PTRACE_GETREGSET if it is available. */
850 for (regset
= x86_regsets
;
851 regset
->fill_function
!= NULL
; regset
++)
852 if (regset
->get_request
== PTRACE_GETREGSET
)
853 regset
->size
= X86_XSTATE_SIZE (xcr0
);
854 else if (regset
->type
!= GENERAL_REGS
)
859 /* Check the native XCR0 only if PTRACE_GETREGSET is available. */
860 xcr0_features
= (have_ptrace_getregset
861 && (xcr0
& X86_XSTATE_ALL_MASK
));
866 if (machine
== EM_X86_64
)
869 const target_desc
*tdesc
= NULL
;
873 tdesc
= amd64_linux_read_description (xcr0
& X86_XSTATE_ALL_MASK
,
878 tdesc
= amd64_linux_read_description (X86_XSTATE_SSE_MASK
, !is_elf64
);
884 const target_desc
*tdesc
= NULL
;
887 tdesc
= i386_linux_read_description (xcr0
& X86_XSTATE_ALL_MASK
);
890 tdesc
= i386_linux_read_description (X86_XSTATE_SSE
);
895 gdb_assert_not_reached ("failed to return tdesc");
898 /* Update all the target description of all processes; a new GDB
899 connected, and it may or not support xml target descriptions. */
902 x86_target::update_xmltarget ()
904 struct thread_info
*saved_thread
= current_thread
;
906 /* Before changing the register cache's internal layout, flush the
907 contents of the current valid caches back to the threads, and
908 release the current regcache objects. */
911 for_each_process ([this] (process_info
*proc
) {
914 /* Look up any thread of this process. */
915 current_thread
= find_any_thread_of_pid (pid
);
920 current_thread
= saved_thread
;
923 /* Process qSupported query, "xmlRegisters=". Update the buffer size for
927 x86_linux_process_qsupported (char **features
, int count
)
931 /* Return if gdb doesn't support XML. If gdb sends "xmlRegisters="
932 with "i386" in qSupported query, it supports x86 XML target
935 for (i
= 0; i
< count
; i
++)
937 const char *feature
= features
[i
];
939 if (startswith (feature
, "xmlRegisters="))
941 char *copy
= xstrdup (feature
+ 13);
944 for (char *p
= strtok_r (copy
, ",", &saveptr
);
946 p
= strtok_r (NULL
, ",", &saveptr
))
948 if (strcmp (p
, "i386") == 0)
958 the_x86_target
.update_xmltarget ();
961 /* Common for x86/x86-64. */
963 static struct regsets_info x86_regsets_info
=
965 x86_regsets
, /* regsets */
967 NULL
, /* disabled_regsets */
971 static struct regs_info amd64_linux_regs_info
=
973 NULL
, /* regset_bitmap */
974 NULL
, /* usrregs_info */
978 static struct usrregs_info i386_linux_usrregs_info
=
984 static struct regs_info i386_linux_regs_info
=
986 NULL
, /* regset_bitmap */
987 &i386_linux_usrregs_info
,
992 x86_target::get_regs_info ()
995 if (is_64bit_tdesc ())
996 return &amd64_linux_regs_info
;
999 return &i386_linux_regs_info
;
1002 /* Initialize the target description for the architecture of the
1006 x86_target::low_arch_setup ()
1008 current_process ()->tdesc
= x86_linux_read_description ();
1011 /* Fill *SYSNO and *SYSRET with the syscall nr trapped and the syscall return
1012 code. This should only be called if LWP got a SYSCALL_SIGTRAP. */
1015 x86_get_syscall_trapinfo (struct regcache
*regcache
, int *sysno
)
1017 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
1023 collect_register_by_name (regcache
, "orig_rax", &l_sysno
);
1024 *sysno
= (int) l_sysno
;
1027 collect_register_by_name (regcache
, "orig_eax", sysno
);
1031 x86_supports_tracepoints (void)
1037 append_insns (CORE_ADDR
*to
, size_t len
, const unsigned char *buf
)
1039 target_write_memory (*to
, buf
, len
);
1044 push_opcode (unsigned char *buf
, const char *op
)
1046 unsigned char *buf_org
= buf
;
1051 unsigned long ul
= strtoul (op
, &endptr
, 16);
1060 return buf
- buf_org
;
1065 /* Build a jump pad that saves registers and calls a collection
1066 function. Writes a jump instruction to the jump pad to
1067 JJUMPAD_INSN. The caller is responsible to write it in at the
1068 tracepoint address. */
1071 amd64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1072 CORE_ADDR collector
,
1075 CORE_ADDR
*jump_entry
,
1076 CORE_ADDR
*trampoline
,
1077 ULONGEST
*trampoline_size
,
1078 unsigned char *jjump_pad_insn
,
1079 ULONGEST
*jjump_pad_insn_size
,
1080 CORE_ADDR
*adjusted_insn_addr
,
1081 CORE_ADDR
*adjusted_insn_addr_end
,
1084 unsigned char buf
[40];
1088 CORE_ADDR buildaddr
= *jump_entry
;
1090 /* Build the jump pad. */
1092 /* First, do tracepoint data collection. Save registers. */
1094 /* Need to ensure stack pointer saved first. */
1095 buf
[i
++] = 0x54; /* push %rsp */
1096 buf
[i
++] = 0x55; /* push %rbp */
1097 buf
[i
++] = 0x57; /* push %rdi */
1098 buf
[i
++] = 0x56; /* push %rsi */
1099 buf
[i
++] = 0x52; /* push %rdx */
1100 buf
[i
++] = 0x51; /* push %rcx */
1101 buf
[i
++] = 0x53; /* push %rbx */
1102 buf
[i
++] = 0x50; /* push %rax */
1103 buf
[i
++] = 0x41; buf
[i
++] = 0x57; /* push %r15 */
1104 buf
[i
++] = 0x41; buf
[i
++] = 0x56; /* push %r14 */
1105 buf
[i
++] = 0x41; buf
[i
++] = 0x55; /* push %r13 */
1106 buf
[i
++] = 0x41; buf
[i
++] = 0x54; /* push %r12 */
1107 buf
[i
++] = 0x41; buf
[i
++] = 0x53; /* push %r11 */
1108 buf
[i
++] = 0x41; buf
[i
++] = 0x52; /* push %r10 */
1109 buf
[i
++] = 0x41; buf
[i
++] = 0x51; /* push %r9 */
1110 buf
[i
++] = 0x41; buf
[i
++] = 0x50; /* push %r8 */
1111 buf
[i
++] = 0x9c; /* pushfq */
1112 buf
[i
++] = 0x48; /* movabs <addr>,%rdi */
1114 memcpy (buf
+ i
, &tpaddr
, 8);
1116 buf
[i
++] = 0x57; /* push %rdi */
1117 append_insns (&buildaddr
, i
, buf
);
1119 /* Stack space for the collecting_t object. */
1121 i
+= push_opcode (&buf
[i
], "48 83 ec 18"); /* sub $0x18,%rsp */
1122 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov <tpoint>,%rax */
1123 memcpy (buf
+ i
, &tpoint
, 8);
1125 i
+= push_opcode (&buf
[i
], "48 89 04 24"); /* mov %rax,(%rsp) */
1126 i
+= push_opcode (&buf
[i
],
1127 "64 48 8b 04 25 00 00 00 00"); /* mov %fs:0x0,%rax */
1128 i
+= push_opcode (&buf
[i
], "48 89 44 24 08"); /* mov %rax,0x8(%rsp) */
1129 append_insns (&buildaddr
, i
, buf
);
1133 i
+= push_opcode (&buf
[i
], "48 be"); /* movl <lockaddr>,%rsi */
1134 memcpy (&buf
[i
], (void *) &lockaddr
, 8);
1136 i
+= push_opcode (&buf
[i
], "48 89 e1"); /* mov %rsp,%rcx */
1137 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1138 i
+= push_opcode (&buf
[i
], "f0 48 0f b1 0e"); /* lock cmpxchg %rcx,(%rsi) */
1139 i
+= push_opcode (&buf
[i
], "48 85 c0"); /* test %rax,%rax */
1140 i
+= push_opcode (&buf
[i
], "75 f4"); /* jne <again> */
1141 append_insns (&buildaddr
, i
, buf
);
1143 /* Set up the gdb_collect call. */
1144 /* At this point, (stack pointer + 0x18) is the base of our saved
1148 i
+= push_opcode (&buf
[i
], "48 89 e6"); /* mov %rsp,%rsi */
1149 i
+= push_opcode (&buf
[i
], "48 83 c6 18"); /* add $0x18,%rsi */
1151 /* tpoint address may be 64-bit wide. */
1152 i
+= push_opcode (&buf
[i
], "48 bf"); /* movl <addr>,%rdi */
1153 memcpy (buf
+ i
, &tpoint
, 8);
1155 append_insns (&buildaddr
, i
, buf
);
1157 /* The collector function being in the shared library, may be
1158 >31-bits away off the jump pad. */
1160 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov $collector,%rax */
1161 memcpy (buf
+ i
, &collector
, 8);
1163 i
+= push_opcode (&buf
[i
], "ff d0"); /* callq *%rax */
1164 append_insns (&buildaddr
, i
, buf
);
1166 /* Clear the spin-lock. */
1168 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1169 i
+= push_opcode (&buf
[i
], "48 a3"); /* mov %rax, lockaddr */
1170 memcpy (buf
+ i
, &lockaddr
, 8);
1172 append_insns (&buildaddr
, i
, buf
);
1174 /* Remove stack that had been used for the collect_t object. */
1176 i
+= push_opcode (&buf
[i
], "48 83 c4 18"); /* add $0x18,%rsp */
1177 append_insns (&buildaddr
, i
, buf
);
1179 /* Restore register state. */
1181 buf
[i
++] = 0x48; /* add $0x8,%rsp */
1185 buf
[i
++] = 0x9d; /* popfq */
1186 buf
[i
++] = 0x41; buf
[i
++] = 0x58; /* pop %r8 */
1187 buf
[i
++] = 0x41; buf
[i
++] = 0x59; /* pop %r9 */
1188 buf
[i
++] = 0x41; buf
[i
++] = 0x5a; /* pop %r10 */
1189 buf
[i
++] = 0x41; buf
[i
++] = 0x5b; /* pop %r11 */
1190 buf
[i
++] = 0x41; buf
[i
++] = 0x5c; /* pop %r12 */
1191 buf
[i
++] = 0x41; buf
[i
++] = 0x5d; /* pop %r13 */
1192 buf
[i
++] = 0x41; buf
[i
++] = 0x5e; /* pop %r14 */
1193 buf
[i
++] = 0x41; buf
[i
++] = 0x5f; /* pop %r15 */
1194 buf
[i
++] = 0x58; /* pop %rax */
1195 buf
[i
++] = 0x5b; /* pop %rbx */
1196 buf
[i
++] = 0x59; /* pop %rcx */
1197 buf
[i
++] = 0x5a; /* pop %rdx */
1198 buf
[i
++] = 0x5e; /* pop %rsi */
1199 buf
[i
++] = 0x5f; /* pop %rdi */
1200 buf
[i
++] = 0x5d; /* pop %rbp */
1201 buf
[i
++] = 0x5c; /* pop %rsp */
1202 append_insns (&buildaddr
, i
, buf
);
1204 /* Now, adjust the original instruction to execute in the jump
1206 *adjusted_insn_addr
= buildaddr
;
1207 relocate_instruction (&buildaddr
, tpaddr
);
1208 *adjusted_insn_addr_end
= buildaddr
;
1210 /* Finally, write a jump back to the program. */
1212 loffset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1213 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1216 "E.Jump back from jump pad too far from tracepoint "
1217 "(offset 0x%" PRIx64
" > int32).", loffset
);
1221 offset
= (int) loffset
;
1222 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1223 memcpy (buf
+ 1, &offset
, 4);
1224 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1226 /* The jump pad is now built. Wire in a jump to our jump pad. This
1227 is always done last (by our caller actually), so that we can
1228 install fast tracepoints with threads running. This relies on
1229 the agent's atomic write support. */
1230 loffset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1231 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1234 "E.Jump pad too far from tracepoint "
1235 "(offset 0x%" PRIx64
" > int32).", loffset
);
1239 offset
= (int) loffset
;
1241 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1242 memcpy (buf
+ 1, &offset
, 4);
1243 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1244 *jjump_pad_insn_size
= sizeof (jump_insn
);
1246 /* Return the end address of our pad. */
1247 *jump_entry
= buildaddr
;
1252 #endif /* __x86_64__ */
1254 /* Build a jump pad that saves registers and calls a collection
1255 function. Writes a jump instruction to the jump pad to
1256 JJUMPAD_INSN. The caller is responsible to write it in at the
1257 tracepoint address. */
1260 i386_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1261 CORE_ADDR collector
,
1264 CORE_ADDR
*jump_entry
,
1265 CORE_ADDR
*trampoline
,
1266 ULONGEST
*trampoline_size
,
1267 unsigned char *jjump_pad_insn
,
1268 ULONGEST
*jjump_pad_insn_size
,
1269 CORE_ADDR
*adjusted_insn_addr
,
1270 CORE_ADDR
*adjusted_insn_addr_end
,
1273 unsigned char buf
[0x100];
1275 CORE_ADDR buildaddr
= *jump_entry
;
1277 /* Build the jump pad. */
1279 /* First, do tracepoint data collection. Save registers. */
1281 buf
[i
++] = 0x60; /* pushad */
1282 buf
[i
++] = 0x68; /* push tpaddr aka $pc */
1283 *((int *)(buf
+ i
)) = (int) tpaddr
;
1285 buf
[i
++] = 0x9c; /* pushf */
1286 buf
[i
++] = 0x1e; /* push %ds */
1287 buf
[i
++] = 0x06; /* push %es */
1288 buf
[i
++] = 0x0f; /* push %fs */
1290 buf
[i
++] = 0x0f; /* push %gs */
1292 buf
[i
++] = 0x16; /* push %ss */
1293 buf
[i
++] = 0x0e; /* push %cs */
1294 append_insns (&buildaddr
, i
, buf
);
1296 /* Stack space for the collecting_t object. */
1298 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1300 /* Build the object. */
1301 i
+= push_opcode (&buf
[i
], "b8"); /* mov <tpoint>,%eax */
1302 memcpy (buf
+ i
, &tpoint
, 4);
1304 i
+= push_opcode (&buf
[i
], "89 04 24"); /* mov %eax,(%esp) */
1306 i
+= push_opcode (&buf
[i
], "65 a1 00 00 00 00"); /* mov %gs:0x0,%eax */
1307 i
+= push_opcode (&buf
[i
], "89 44 24 04"); /* mov %eax,0x4(%esp) */
1308 append_insns (&buildaddr
, i
, buf
);
1310 /* spin-lock. Note this is using cmpxchg, which leaves i386 behind.
1311 If we cared for it, this could be using xchg alternatively. */
1314 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1315 i
+= push_opcode (&buf
[i
], "f0 0f b1 25"); /* lock cmpxchg
1317 memcpy (&buf
[i
], (void *) &lockaddr
, 4);
1319 i
+= push_opcode (&buf
[i
], "85 c0"); /* test %eax,%eax */
1320 i
+= push_opcode (&buf
[i
], "75 f2"); /* jne <again> */
1321 append_insns (&buildaddr
, i
, buf
);
1324 /* Set up arguments to the gdb_collect call. */
1326 i
+= push_opcode (&buf
[i
], "89 e0"); /* mov %esp,%eax */
1327 i
+= push_opcode (&buf
[i
], "83 c0 08"); /* add $0x08,%eax */
1328 i
+= push_opcode (&buf
[i
], "89 44 24 fc"); /* mov %eax,-0x4(%esp) */
1329 append_insns (&buildaddr
, i
, buf
);
1332 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1333 append_insns (&buildaddr
, i
, buf
);
1336 i
+= push_opcode (&buf
[i
], "c7 04 24"); /* movl <addr>,(%esp) */
1337 memcpy (&buf
[i
], (void *) &tpoint
, 4);
1339 append_insns (&buildaddr
, i
, buf
);
1341 buf
[0] = 0xe8; /* call <reladdr> */
1342 offset
= collector
- (buildaddr
+ sizeof (jump_insn
));
1343 memcpy (buf
+ 1, &offset
, 4);
1344 append_insns (&buildaddr
, 5, buf
);
1345 /* Clean up after the call. */
1346 buf
[0] = 0x83; /* add $0x8,%esp */
1349 append_insns (&buildaddr
, 3, buf
);
1352 /* Clear the spin-lock. This would need the LOCK prefix on older
1355 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1356 i
+= push_opcode (&buf
[i
], "a3"); /* mov %eax, lockaddr */
1357 memcpy (buf
+ i
, &lockaddr
, 4);
1359 append_insns (&buildaddr
, i
, buf
);
1362 /* Remove stack that had been used for the collect_t object. */
1364 i
+= push_opcode (&buf
[i
], "83 c4 08"); /* add $0x08,%esp */
1365 append_insns (&buildaddr
, i
, buf
);
1368 buf
[i
++] = 0x83; /* add $0x4,%esp (no pop of %cs, assume unchanged) */
1371 buf
[i
++] = 0x17; /* pop %ss */
1372 buf
[i
++] = 0x0f; /* pop %gs */
1374 buf
[i
++] = 0x0f; /* pop %fs */
1376 buf
[i
++] = 0x07; /* pop %es */
1377 buf
[i
++] = 0x1f; /* pop %ds */
1378 buf
[i
++] = 0x9d; /* popf */
1379 buf
[i
++] = 0x83; /* add $0x4,%esp (pop of tpaddr aka $pc) */
1382 buf
[i
++] = 0x61; /* popad */
1383 append_insns (&buildaddr
, i
, buf
);
1385 /* Now, adjust the original instruction to execute in the jump
1387 *adjusted_insn_addr
= buildaddr
;
1388 relocate_instruction (&buildaddr
, tpaddr
);
1389 *adjusted_insn_addr_end
= buildaddr
;
1391 /* Write the jump back to the program. */
1392 offset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1393 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1394 memcpy (buf
+ 1, &offset
, 4);
1395 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1397 /* The jump pad is now built. Wire in a jump to our jump pad. This
1398 is always done last (by our caller actually), so that we can
1399 install fast tracepoints with threads running. This relies on
1400 the agent's atomic write support. */
1403 /* Create a trampoline. */
1404 *trampoline_size
= sizeof (jump_insn
);
1405 if (!claim_trampoline_space (*trampoline_size
, trampoline
))
1407 /* No trampoline space available. */
1409 "E.Cannot allocate trampoline space needed for fast "
1410 "tracepoints on 4-byte instructions.");
1414 offset
= *jump_entry
- (*trampoline
+ sizeof (jump_insn
));
1415 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1416 memcpy (buf
+ 1, &offset
, 4);
1417 target_write_memory (*trampoline
, buf
, sizeof (jump_insn
));
1419 /* Use a 16-bit relative jump instruction to jump to the trampoline. */
1420 offset
= (*trampoline
- (tpaddr
+ sizeof (small_jump_insn
))) & 0xffff;
1421 memcpy (buf
, small_jump_insn
, sizeof (small_jump_insn
));
1422 memcpy (buf
+ 2, &offset
, 2);
1423 memcpy (jjump_pad_insn
, buf
, sizeof (small_jump_insn
));
1424 *jjump_pad_insn_size
= sizeof (small_jump_insn
);
1428 /* Else use a 32-bit relative jump instruction. */
1429 offset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1430 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1431 memcpy (buf
+ 1, &offset
, 4);
1432 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1433 *jjump_pad_insn_size
= sizeof (jump_insn
);
1436 /* Return the end address of our pad. */
1437 *jump_entry
= buildaddr
;
1443 x86_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1444 CORE_ADDR collector
,
1447 CORE_ADDR
*jump_entry
,
1448 CORE_ADDR
*trampoline
,
1449 ULONGEST
*trampoline_size
,
1450 unsigned char *jjump_pad_insn
,
1451 ULONGEST
*jjump_pad_insn_size
,
1452 CORE_ADDR
*adjusted_insn_addr
,
1453 CORE_ADDR
*adjusted_insn_addr_end
,
1457 if (is_64bit_tdesc ())
1458 return amd64_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1459 collector
, lockaddr
,
1460 orig_size
, jump_entry
,
1461 trampoline
, trampoline_size
,
1463 jjump_pad_insn_size
,
1465 adjusted_insn_addr_end
,
1469 return i386_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1470 collector
, lockaddr
,
1471 orig_size
, jump_entry
,
1472 trampoline
, trampoline_size
,
1474 jjump_pad_insn_size
,
1476 adjusted_insn_addr_end
,
1480 /* Return the minimum instruction length for fast tracepoints on x86/x86-64
1484 x86_get_min_fast_tracepoint_insn_len (void)
1486 static int warned_about_fast_tracepoints
= 0;
1489 /* On x86-64, 5-byte jump instructions with a 4-byte offset are always
1490 used for fast tracepoints. */
1491 if (is_64bit_tdesc ())
1495 if (agent_loaded_p ())
1497 char errbuf
[IPA_BUFSIZ
];
1501 /* On x86, if trampolines are available, then 4-byte jump instructions
1502 with a 2-byte offset may be used, otherwise 5-byte jump instructions
1503 with a 4-byte offset are used instead. */
1504 if (have_fast_tracepoint_trampoline_buffer (errbuf
))
1508 /* GDB has no channel to explain to user why a shorter fast
1509 tracepoint is not possible, but at least make GDBserver
1510 mention that something has gone awry. */
1511 if (!warned_about_fast_tracepoints
)
1513 warning ("4-byte fast tracepoints not available; %s", errbuf
);
1514 warned_about_fast_tracepoints
= 1;
1521 /* Indicate that the minimum length is currently unknown since the IPA
1522 has not loaded yet. */
1528 add_insns (unsigned char *start
, int len
)
1530 CORE_ADDR buildaddr
= current_insn_ptr
;
1533 debug_printf ("Adding %d bytes of insn at %s\n",
1534 len
, paddress (buildaddr
));
1536 append_insns (&buildaddr
, len
, start
);
1537 current_insn_ptr
= buildaddr
;
1540 /* Our general strategy for emitting code is to avoid specifying raw
1541 bytes whenever possible, and instead copy a block of inline asm
1542 that is embedded in the function. This is a little messy, because
1543 we need to keep the compiler from discarding what looks like dead
1544 code, plus suppress various warnings. */
1546 #define EMIT_ASM(NAME, INSNS) \
1549 extern unsigned char start_ ## NAME, end_ ## NAME; \
1550 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1551 __asm__ ("jmp end_" #NAME "\n" \
1552 "\t" "start_" #NAME ":" \
1554 "\t" "end_" #NAME ":"); \
1559 #define EMIT_ASM32(NAME,INSNS) \
1562 extern unsigned char start_ ## NAME, end_ ## NAME; \
1563 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1564 __asm__ (".code32\n" \
1565 "\t" "jmp end_" #NAME "\n" \
1566 "\t" "start_" #NAME ":\n" \
1568 "\t" "end_" #NAME ":\n" \
1574 #define EMIT_ASM32(NAME,INSNS) EMIT_ASM(NAME,INSNS)
1581 amd64_emit_prologue (void)
1583 EMIT_ASM (amd64_prologue
,
1585 "movq %rsp,%rbp\n\t"
1586 "sub $0x20,%rsp\n\t"
1587 "movq %rdi,-8(%rbp)\n\t"
1588 "movq %rsi,-16(%rbp)");
1593 amd64_emit_epilogue (void)
1595 EMIT_ASM (amd64_epilogue
,
1596 "movq -16(%rbp),%rdi\n\t"
1597 "movq %rax,(%rdi)\n\t"
1604 amd64_emit_add (void)
1606 EMIT_ASM (amd64_add
,
1607 "add (%rsp),%rax\n\t"
1608 "lea 0x8(%rsp),%rsp");
1612 amd64_emit_sub (void)
1614 EMIT_ASM (amd64_sub
,
1615 "sub %rax,(%rsp)\n\t"
1620 amd64_emit_mul (void)
1626 amd64_emit_lsh (void)
1632 amd64_emit_rsh_signed (void)
1638 amd64_emit_rsh_unsigned (void)
1644 amd64_emit_ext (int arg
)
1649 EMIT_ASM (amd64_ext_8
,
1655 EMIT_ASM (amd64_ext_16
,
1660 EMIT_ASM (amd64_ext_32
,
1669 amd64_emit_log_not (void)
1671 EMIT_ASM (amd64_log_not
,
1672 "test %rax,%rax\n\t"
1678 amd64_emit_bit_and (void)
1680 EMIT_ASM (amd64_and
,
1681 "and (%rsp),%rax\n\t"
1682 "lea 0x8(%rsp),%rsp");
1686 amd64_emit_bit_or (void)
1689 "or (%rsp),%rax\n\t"
1690 "lea 0x8(%rsp),%rsp");
1694 amd64_emit_bit_xor (void)
1696 EMIT_ASM (amd64_xor
,
1697 "xor (%rsp),%rax\n\t"
1698 "lea 0x8(%rsp),%rsp");
1702 amd64_emit_bit_not (void)
1704 EMIT_ASM (amd64_bit_not
,
1705 "xorq $0xffffffffffffffff,%rax");
1709 amd64_emit_equal (void)
1711 EMIT_ASM (amd64_equal
,
1712 "cmp %rax,(%rsp)\n\t"
1713 "je .Lamd64_equal_true\n\t"
1715 "jmp .Lamd64_equal_end\n\t"
1716 ".Lamd64_equal_true:\n\t"
1718 ".Lamd64_equal_end:\n\t"
1719 "lea 0x8(%rsp),%rsp");
1723 amd64_emit_less_signed (void)
1725 EMIT_ASM (amd64_less_signed
,
1726 "cmp %rax,(%rsp)\n\t"
1727 "jl .Lamd64_less_signed_true\n\t"
1729 "jmp .Lamd64_less_signed_end\n\t"
1730 ".Lamd64_less_signed_true:\n\t"
1732 ".Lamd64_less_signed_end:\n\t"
1733 "lea 0x8(%rsp),%rsp");
1737 amd64_emit_less_unsigned (void)
1739 EMIT_ASM (amd64_less_unsigned
,
1740 "cmp %rax,(%rsp)\n\t"
1741 "jb .Lamd64_less_unsigned_true\n\t"
1743 "jmp .Lamd64_less_unsigned_end\n\t"
1744 ".Lamd64_less_unsigned_true:\n\t"
1746 ".Lamd64_less_unsigned_end:\n\t"
1747 "lea 0x8(%rsp),%rsp");
1751 amd64_emit_ref (int size
)
1756 EMIT_ASM (amd64_ref1
,
1760 EMIT_ASM (amd64_ref2
,
1764 EMIT_ASM (amd64_ref4
,
1765 "movl (%rax),%eax");
1768 EMIT_ASM (amd64_ref8
,
1769 "movq (%rax),%rax");
1775 amd64_emit_if_goto (int *offset_p
, int *size_p
)
1777 EMIT_ASM (amd64_if_goto
,
1781 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
1789 amd64_emit_goto (int *offset_p
, int *size_p
)
1791 EMIT_ASM (amd64_goto
,
1792 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
1800 amd64_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
1802 int diff
= (to
- (from
+ size
));
1803 unsigned char buf
[sizeof (int)];
1811 memcpy (buf
, &diff
, sizeof (int));
1812 target_write_memory (from
, buf
, sizeof (int));
1816 amd64_emit_const (LONGEST num
)
1818 unsigned char buf
[16];
1820 CORE_ADDR buildaddr
= current_insn_ptr
;
1823 buf
[i
++] = 0x48; buf
[i
++] = 0xb8; /* mov $<n>,%rax */
1824 memcpy (&buf
[i
], &num
, sizeof (num
));
1826 append_insns (&buildaddr
, i
, buf
);
1827 current_insn_ptr
= buildaddr
;
1831 amd64_emit_call (CORE_ADDR fn
)
1833 unsigned char buf
[16];
1835 CORE_ADDR buildaddr
;
1838 /* The destination function being in the shared library, may be
1839 >31-bits away off the compiled code pad. */
1841 buildaddr
= current_insn_ptr
;
1843 offset64
= fn
- (buildaddr
+ 1 /* call op */ + 4 /* 32-bit offset */);
1847 if (offset64
> INT_MAX
|| offset64
< INT_MIN
)
1849 /* Offset is too large for a call. Use callq, but that requires
1850 a register, so avoid it if possible. Use r10, since it is
1851 call-clobbered, we don't have to push/pop it. */
1852 buf
[i
++] = 0x48; /* mov $fn,%r10 */
1854 memcpy (buf
+ i
, &fn
, 8);
1856 buf
[i
++] = 0xff; /* callq *%r10 */
1861 int offset32
= offset64
; /* we know we can't overflow here. */
1863 buf
[i
++] = 0xe8; /* call <reladdr> */
1864 memcpy (buf
+ i
, &offset32
, 4);
1868 append_insns (&buildaddr
, i
, buf
);
1869 current_insn_ptr
= buildaddr
;
1873 amd64_emit_reg (int reg
)
1875 unsigned char buf
[16];
1877 CORE_ADDR buildaddr
;
1879 /* Assume raw_regs is still in %rdi. */
1880 buildaddr
= current_insn_ptr
;
1882 buf
[i
++] = 0xbe; /* mov $<n>,%esi */
1883 memcpy (&buf
[i
], ®
, sizeof (reg
));
1885 append_insns (&buildaddr
, i
, buf
);
1886 current_insn_ptr
= buildaddr
;
1887 amd64_emit_call (get_raw_reg_func_addr ());
1891 amd64_emit_pop (void)
1893 EMIT_ASM (amd64_pop
,
1898 amd64_emit_stack_flush (void)
1900 EMIT_ASM (amd64_stack_flush
,
1905 amd64_emit_zero_ext (int arg
)
1910 EMIT_ASM (amd64_zero_ext_8
,
1914 EMIT_ASM (amd64_zero_ext_16
,
1915 "and $0xffff,%rax");
1918 EMIT_ASM (amd64_zero_ext_32
,
1919 "mov $0xffffffff,%rcx\n\t"
1928 amd64_emit_swap (void)
1930 EMIT_ASM (amd64_swap
,
1937 amd64_emit_stack_adjust (int n
)
1939 unsigned char buf
[16];
1941 CORE_ADDR buildaddr
= current_insn_ptr
;
1944 buf
[i
++] = 0x48; /* lea $<n>(%rsp),%rsp */
1948 /* This only handles adjustments up to 16, but we don't expect any more. */
1950 append_insns (&buildaddr
, i
, buf
);
1951 current_insn_ptr
= buildaddr
;
1954 /* FN's prototype is `LONGEST(*fn)(int)'. */
1957 amd64_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
1959 unsigned char buf
[16];
1961 CORE_ADDR buildaddr
;
1963 buildaddr
= current_insn_ptr
;
1965 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
1966 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
1968 append_insns (&buildaddr
, i
, buf
);
1969 current_insn_ptr
= buildaddr
;
1970 amd64_emit_call (fn
);
1973 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
1976 amd64_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
1978 unsigned char buf
[16];
1980 CORE_ADDR buildaddr
;
1982 buildaddr
= current_insn_ptr
;
1984 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
1985 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
1987 append_insns (&buildaddr
, i
, buf
);
1988 current_insn_ptr
= buildaddr
;
1989 EMIT_ASM (amd64_void_call_2_a
,
1990 /* Save away a copy of the stack top. */
1992 /* Also pass top as the second argument. */
1994 amd64_emit_call (fn
);
1995 EMIT_ASM (amd64_void_call_2_b
,
1996 /* Restore the stack top, %rax may have been trashed. */
2001 amd64_emit_eq_goto (int *offset_p
, int *size_p
)
2004 "cmp %rax,(%rsp)\n\t"
2005 "jne .Lamd64_eq_fallthru\n\t"
2006 "lea 0x8(%rsp),%rsp\n\t"
2008 /* jmp, but don't trust the assembler to choose the right jump */
2009 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2010 ".Lamd64_eq_fallthru:\n\t"
2011 "lea 0x8(%rsp),%rsp\n\t"
2021 amd64_emit_ne_goto (int *offset_p
, int *size_p
)
2024 "cmp %rax,(%rsp)\n\t"
2025 "je .Lamd64_ne_fallthru\n\t"
2026 "lea 0x8(%rsp),%rsp\n\t"
2028 /* jmp, but don't trust the assembler to choose the right jump */
2029 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2030 ".Lamd64_ne_fallthru:\n\t"
2031 "lea 0x8(%rsp),%rsp\n\t"
2041 amd64_emit_lt_goto (int *offset_p
, int *size_p
)
2044 "cmp %rax,(%rsp)\n\t"
2045 "jnl .Lamd64_lt_fallthru\n\t"
2046 "lea 0x8(%rsp),%rsp\n\t"
2048 /* jmp, but don't trust the assembler to choose the right jump */
2049 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2050 ".Lamd64_lt_fallthru:\n\t"
2051 "lea 0x8(%rsp),%rsp\n\t"
2061 amd64_emit_le_goto (int *offset_p
, int *size_p
)
2064 "cmp %rax,(%rsp)\n\t"
2065 "jnle .Lamd64_le_fallthru\n\t"
2066 "lea 0x8(%rsp),%rsp\n\t"
2068 /* jmp, but don't trust the assembler to choose the right jump */
2069 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2070 ".Lamd64_le_fallthru:\n\t"
2071 "lea 0x8(%rsp),%rsp\n\t"
2081 amd64_emit_gt_goto (int *offset_p
, int *size_p
)
2084 "cmp %rax,(%rsp)\n\t"
2085 "jng .Lamd64_gt_fallthru\n\t"
2086 "lea 0x8(%rsp),%rsp\n\t"
2088 /* jmp, but don't trust the assembler to choose the right jump */
2089 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2090 ".Lamd64_gt_fallthru:\n\t"
2091 "lea 0x8(%rsp),%rsp\n\t"
2101 amd64_emit_ge_goto (int *offset_p
, int *size_p
)
2104 "cmp %rax,(%rsp)\n\t"
2105 "jnge .Lamd64_ge_fallthru\n\t"
2106 ".Lamd64_ge_jump:\n\t"
2107 "lea 0x8(%rsp),%rsp\n\t"
2109 /* jmp, but don't trust the assembler to choose the right jump */
2110 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2111 ".Lamd64_ge_fallthru:\n\t"
2112 "lea 0x8(%rsp),%rsp\n\t"
2121 struct emit_ops amd64_emit_ops
=
2123 amd64_emit_prologue
,
2124 amd64_emit_epilogue
,
2129 amd64_emit_rsh_signed
,
2130 amd64_emit_rsh_unsigned
,
2138 amd64_emit_less_signed
,
2139 amd64_emit_less_unsigned
,
2143 amd64_write_goto_address
,
2148 amd64_emit_stack_flush
,
2149 amd64_emit_zero_ext
,
2151 amd64_emit_stack_adjust
,
2152 amd64_emit_int_call_1
,
2153 amd64_emit_void_call_2
,
2162 #endif /* __x86_64__ */
2165 i386_emit_prologue (void)
2167 EMIT_ASM32 (i386_prologue
,
2171 /* At this point, the raw regs base address is at 8(%ebp), and the
2172 value pointer is at 12(%ebp). */
2176 i386_emit_epilogue (void)
2178 EMIT_ASM32 (i386_epilogue
,
2179 "mov 12(%ebp),%ecx\n\t"
2180 "mov %eax,(%ecx)\n\t"
2181 "mov %ebx,0x4(%ecx)\n\t"
2189 i386_emit_add (void)
2191 EMIT_ASM32 (i386_add
,
2192 "add (%esp),%eax\n\t"
2193 "adc 0x4(%esp),%ebx\n\t"
2194 "lea 0x8(%esp),%esp");
2198 i386_emit_sub (void)
2200 EMIT_ASM32 (i386_sub
,
2201 "subl %eax,(%esp)\n\t"
2202 "sbbl %ebx,4(%esp)\n\t"
2208 i386_emit_mul (void)
2214 i386_emit_lsh (void)
2220 i386_emit_rsh_signed (void)
2226 i386_emit_rsh_unsigned (void)
2232 i386_emit_ext (int arg
)
2237 EMIT_ASM32 (i386_ext_8
,
2240 "movl %eax,%ebx\n\t"
2244 EMIT_ASM32 (i386_ext_16
,
2246 "movl %eax,%ebx\n\t"
2250 EMIT_ASM32 (i386_ext_32
,
2251 "movl %eax,%ebx\n\t"
2260 i386_emit_log_not (void)
2262 EMIT_ASM32 (i386_log_not
,
2264 "test %eax,%eax\n\t"
2271 i386_emit_bit_and (void)
2273 EMIT_ASM32 (i386_and
,
2274 "and (%esp),%eax\n\t"
2275 "and 0x4(%esp),%ebx\n\t"
2276 "lea 0x8(%esp),%esp");
2280 i386_emit_bit_or (void)
2282 EMIT_ASM32 (i386_or
,
2283 "or (%esp),%eax\n\t"
2284 "or 0x4(%esp),%ebx\n\t"
2285 "lea 0x8(%esp),%esp");
2289 i386_emit_bit_xor (void)
2291 EMIT_ASM32 (i386_xor
,
2292 "xor (%esp),%eax\n\t"
2293 "xor 0x4(%esp),%ebx\n\t"
2294 "lea 0x8(%esp),%esp");
2298 i386_emit_bit_not (void)
2300 EMIT_ASM32 (i386_bit_not
,
2301 "xor $0xffffffff,%eax\n\t"
2302 "xor $0xffffffff,%ebx\n\t");
2306 i386_emit_equal (void)
2308 EMIT_ASM32 (i386_equal
,
2309 "cmpl %ebx,4(%esp)\n\t"
2310 "jne .Li386_equal_false\n\t"
2311 "cmpl %eax,(%esp)\n\t"
2312 "je .Li386_equal_true\n\t"
2313 ".Li386_equal_false:\n\t"
2315 "jmp .Li386_equal_end\n\t"
2316 ".Li386_equal_true:\n\t"
2318 ".Li386_equal_end:\n\t"
2320 "lea 0x8(%esp),%esp");
2324 i386_emit_less_signed (void)
2326 EMIT_ASM32 (i386_less_signed
,
2327 "cmpl %ebx,4(%esp)\n\t"
2328 "jl .Li386_less_signed_true\n\t"
2329 "jne .Li386_less_signed_false\n\t"
2330 "cmpl %eax,(%esp)\n\t"
2331 "jl .Li386_less_signed_true\n\t"
2332 ".Li386_less_signed_false:\n\t"
2334 "jmp .Li386_less_signed_end\n\t"
2335 ".Li386_less_signed_true:\n\t"
2337 ".Li386_less_signed_end:\n\t"
2339 "lea 0x8(%esp),%esp");
2343 i386_emit_less_unsigned (void)
2345 EMIT_ASM32 (i386_less_unsigned
,
2346 "cmpl %ebx,4(%esp)\n\t"
2347 "jb .Li386_less_unsigned_true\n\t"
2348 "jne .Li386_less_unsigned_false\n\t"
2349 "cmpl %eax,(%esp)\n\t"
2350 "jb .Li386_less_unsigned_true\n\t"
2351 ".Li386_less_unsigned_false:\n\t"
2353 "jmp .Li386_less_unsigned_end\n\t"
2354 ".Li386_less_unsigned_true:\n\t"
2356 ".Li386_less_unsigned_end:\n\t"
2358 "lea 0x8(%esp),%esp");
2362 i386_emit_ref (int size
)
2367 EMIT_ASM32 (i386_ref1
,
2371 EMIT_ASM32 (i386_ref2
,
2375 EMIT_ASM32 (i386_ref4
,
2376 "movl (%eax),%eax");
2379 EMIT_ASM32 (i386_ref8
,
2380 "movl 4(%eax),%ebx\n\t"
2381 "movl (%eax),%eax");
2387 i386_emit_if_goto (int *offset_p
, int *size_p
)
2389 EMIT_ASM32 (i386_if_goto
,
2395 /* Don't trust the assembler to choose the right jump */
2396 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
2399 *offset_p
= 11; /* be sure that this matches the sequence above */
2405 i386_emit_goto (int *offset_p
, int *size_p
)
2407 EMIT_ASM32 (i386_goto
,
2408 /* Don't trust the assembler to choose the right jump */
2409 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
2417 i386_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2419 int diff
= (to
- (from
+ size
));
2420 unsigned char buf
[sizeof (int)];
2422 /* We're only doing 4-byte sizes at the moment. */
2429 memcpy (buf
, &diff
, sizeof (int));
2430 target_write_memory (from
, buf
, sizeof (int));
2434 i386_emit_const (LONGEST num
)
2436 unsigned char buf
[16];
2438 CORE_ADDR buildaddr
= current_insn_ptr
;
2441 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2442 lo
= num
& 0xffffffff;
2443 memcpy (&buf
[i
], &lo
, sizeof (lo
));
2445 hi
= ((num
>> 32) & 0xffffffff);
2448 buf
[i
++] = 0xbb; /* mov $<n>,%ebx */
2449 memcpy (&buf
[i
], &hi
, sizeof (hi
));
2454 buf
[i
++] = 0x31; buf
[i
++] = 0xdb; /* xor %ebx,%ebx */
2456 append_insns (&buildaddr
, i
, buf
);
2457 current_insn_ptr
= buildaddr
;
2461 i386_emit_call (CORE_ADDR fn
)
2463 unsigned char buf
[16];
2465 CORE_ADDR buildaddr
;
2467 buildaddr
= current_insn_ptr
;
2469 buf
[i
++] = 0xe8; /* call <reladdr> */
2470 offset
= ((int) fn
) - (buildaddr
+ 5);
2471 memcpy (buf
+ 1, &offset
, 4);
2472 append_insns (&buildaddr
, 5, buf
);
2473 current_insn_ptr
= buildaddr
;
2477 i386_emit_reg (int reg
)
2479 unsigned char buf
[16];
2481 CORE_ADDR buildaddr
;
2483 EMIT_ASM32 (i386_reg_a
,
2485 buildaddr
= current_insn_ptr
;
2487 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2488 memcpy (&buf
[i
], ®
, sizeof (reg
));
2490 append_insns (&buildaddr
, i
, buf
);
2491 current_insn_ptr
= buildaddr
;
2492 EMIT_ASM32 (i386_reg_b
,
2493 "mov %eax,4(%esp)\n\t"
2494 "mov 8(%ebp),%eax\n\t"
2496 i386_emit_call (get_raw_reg_func_addr ());
2497 EMIT_ASM32 (i386_reg_c
,
2499 "lea 0x8(%esp),%esp");
2503 i386_emit_pop (void)
2505 EMIT_ASM32 (i386_pop
,
2511 i386_emit_stack_flush (void)
2513 EMIT_ASM32 (i386_stack_flush
,
2519 i386_emit_zero_ext (int arg
)
2524 EMIT_ASM32 (i386_zero_ext_8
,
2525 "and $0xff,%eax\n\t"
2529 EMIT_ASM32 (i386_zero_ext_16
,
2530 "and $0xffff,%eax\n\t"
2534 EMIT_ASM32 (i386_zero_ext_32
,
2543 i386_emit_swap (void)
2545 EMIT_ASM32 (i386_swap
,
2555 i386_emit_stack_adjust (int n
)
2557 unsigned char buf
[16];
2559 CORE_ADDR buildaddr
= current_insn_ptr
;
2562 buf
[i
++] = 0x8d; /* lea $<n>(%esp),%esp */
2566 append_insns (&buildaddr
, i
, buf
);
2567 current_insn_ptr
= buildaddr
;
2570 /* FN's prototype is `LONGEST(*fn)(int)'. */
2573 i386_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2575 unsigned char buf
[16];
2577 CORE_ADDR buildaddr
;
2579 EMIT_ASM32 (i386_int_call_1_a
,
2580 /* Reserve a bit of stack space. */
2582 /* Put the one argument on the stack. */
2583 buildaddr
= current_insn_ptr
;
2585 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2588 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2590 append_insns (&buildaddr
, i
, buf
);
2591 current_insn_ptr
= buildaddr
;
2592 i386_emit_call (fn
);
2593 EMIT_ASM32 (i386_int_call_1_c
,
2595 "lea 0x8(%esp),%esp");
2598 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
2601 i386_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2603 unsigned char buf
[16];
2605 CORE_ADDR buildaddr
;
2607 EMIT_ASM32 (i386_void_call_2_a
,
2608 /* Preserve %eax only; we don't have to worry about %ebx. */
2610 /* Reserve a bit of stack space for arguments. */
2611 "sub $0x10,%esp\n\t"
2612 /* Copy "top" to the second argument position. (Note that
2613 we can't assume function won't scribble on its
2614 arguments, so don't try to restore from this.) */
2615 "mov %eax,4(%esp)\n\t"
2616 "mov %ebx,8(%esp)");
2617 /* Put the first argument on the stack. */
2618 buildaddr
= current_insn_ptr
;
2620 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2623 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2625 append_insns (&buildaddr
, i
, buf
);
2626 current_insn_ptr
= buildaddr
;
2627 i386_emit_call (fn
);
2628 EMIT_ASM32 (i386_void_call_2_b
,
2629 "lea 0x10(%esp),%esp\n\t"
2630 /* Restore original stack top. */
2636 i386_emit_eq_goto (int *offset_p
, int *size_p
)
2639 /* Check low half first, more likely to be decider */
2640 "cmpl %eax,(%esp)\n\t"
2641 "jne .Leq_fallthru\n\t"
2642 "cmpl %ebx,4(%esp)\n\t"
2643 "jne .Leq_fallthru\n\t"
2644 "lea 0x8(%esp),%esp\n\t"
2647 /* jmp, but don't trust the assembler to choose the right jump */
2648 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2649 ".Leq_fallthru:\n\t"
2650 "lea 0x8(%esp),%esp\n\t"
2661 i386_emit_ne_goto (int *offset_p
, int *size_p
)
2664 /* Check low half first, more likely to be decider */
2665 "cmpl %eax,(%esp)\n\t"
2667 "cmpl %ebx,4(%esp)\n\t"
2668 "je .Lne_fallthru\n\t"
2670 "lea 0x8(%esp),%esp\n\t"
2673 /* jmp, but don't trust the assembler to choose the right jump */
2674 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2675 ".Lne_fallthru:\n\t"
2676 "lea 0x8(%esp),%esp\n\t"
2687 i386_emit_lt_goto (int *offset_p
, int *size_p
)
2690 "cmpl %ebx,4(%esp)\n\t"
2692 "jne .Llt_fallthru\n\t"
2693 "cmpl %eax,(%esp)\n\t"
2694 "jnl .Llt_fallthru\n\t"
2696 "lea 0x8(%esp),%esp\n\t"
2699 /* jmp, but don't trust the assembler to choose the right jump */
2700 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2701 ".Llt_fallthru:\n\t"
2702 "lea 0x8(%esp),%esp\n\t"
2713 i386_emit_le_goto (int *offset_p
, int *size_p
)
2716 "cmpl %ebx,4(%esp)\n\t"
2718 "jne .Lle_fallthru\n\t"
2719 "cmpl %eax,(%esp)\n\t"
2720 "jnle .Lle_fallthru\n\t"
2722 "lea 0x8(%esp),%esp\n\t"
2725 /* jmp, but don't trust the assembler to choose the right jump */
2726 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2727 ".Lle_fallthru:\n\t"
2728 "lea 0x8(%esp),%esp\n\t"
2739 i386_emit_gt_goto (int *offset_p
, int *size_p
)
2742 "cmpl %ebx,4(%esp)\n\t"
2744 "jne .Lgt_fallthru\n\t"
2745 "cmpl %eax,(%esp)\n\t"
2746 "jng .Lgt_fallthru\n\t"
2748 "lea 0x8(%esp),%esp\n\t"
2751 /* jmp, but don't trust the assembler to choose the right jump */
2752 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2753 ".Lgt_fallthru:\n\t"
2754 "lea 0x8(%esp),%esp\n\t"
2765 i386_emit_ge_goto (int *offset_p
, int *size_p
)
2768 "cmpl %ebx,4(%esp)\n\t"
2770 "jne .Lge_fallthru\n\t"
2771 "cmpl %eax,(%esp)\n\t"
2772 "jnge .Lge_fallthru\n\t"
2774 "lea 0x8(%esp),%esp\n\t"
2777 /* jmp, but don't trust the assembler to choose the right jump */
2778 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2779 ".Lge_fallthru:\n\t"
2780 "lea 0x8(%esp),%esp\n\t"
2790 struct emit_ops i386_emit_ops
=
2798 i386_emit_rsh_signed
,
2799 i386_emit_rsh_unsigned
,
2807 i386_emit_less_signed
,
2808 i386_emit_less_unsigned
,
2812 i386_write_goto_address
,
2817 i386_emit_stack_flush
,
2820 i386_emit_stack_adjust
,
2821 i386_emit_int_call_1
,
2822 i386_emit_void_call_2
,
2832 static struct emit_ops
*
2836 if (is_64bit_tdesc ())
2837 return &amd64_emit_ops
;
2840 return &i386_emit_ops
;
2843 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
2845 static const gdb_byte
*
2846 x86_sw_breakpoint_from_kind (int kind
, int *size
)
2848 *size
= x86_breakpoint_len
;
2849 return x86_breakpoint
;
2853 x86_supports_range_stepping (void)
2858 /* Implementation of linux_target_ops method "supports_hardware_single_step".
2862 x86_supports_hardware_single_step (void)
2868 x86_get_ipa_tdesc_idx (void)
2870 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
2871 const struct target_desc
*tdesc
= regcache
->tdesc
;
2874 return amd64_get_ipa_tdesc_idx (tdesc
);
2877 if (tdesc
== tdesc_i386_linux_no_xml
)
2878 return X86_TDESC_SSE
;
2880 return i386_get_ipa_tdesc_idx (tdesc
);
2883 /* This is initialized assuming an amd64 target.
2884 x86_arch_setup will correct it for i386 or amd64 targets. */
2886 struct linux_target_ops the_low_target
=
2888 NULL
, /* fetch_register */
2891 NULL
, /* breakpoint_kind_from_pc */
2892 x86_sw_breakpoint_from_kind
,
2896 x86_supports_z_point_type
,
2899 x86_stopped_by_watchpoint
,
2900 x86_stopped_data_address
,
2901 /* collect_ptrace_register/supply_ptrace_register are not needed in the
2902 native i386 case (no registers smaller than an xfer unit), and are not
2903 used in the biarch case (HAVE_LINUX_USRREGS is not defined). */
2906 /* need to fix up i386 siginfo if host is amd64 */
2908 x86_linux_new_process
,
2909 x86_linux_delete_process
,
2910 x86_linux_new_thread
,
2911 x86_linux_delete_thread
,
2913 x86_linux_prepare_to_resume
,
2914 x86_linux_process_qsupported
,
2915 x86_supports_tracepoints
,
2916 x86_get_thread_area
,
2917 x86_install_fast_tracepoint_jump_pad
,
2919 x86_get_min_fast_tracepoint_insn_len
,
2920 x86_supports_range_stepping
,
2921 NULL
, /* breakpoint_kind_from_current_state */
2922 x86_supports_hardware_single_step
,
2923 x86_get_syscall_trapinfo
,
2924 x86_get_ipa_tdesc_idx
,
2927 /* The linux target ops object. */
2929 linux_process_target
*the_linux_target
= &the_x86_target
;
2932 initialize_low_arch (void)
2934 /* Initialize the Linux target descriptions. */
2936 tdesc_amd64_linux_no_xml
= allocate_target_description ();
2937 copy_target_description (tdesc_amd64_linux_no_xml
,
2938 amd64_linux_read_description (X86_XSTATE_SSE_MASK
,
2940 tdesc_amd64_linux_no_xml
->xmltarget
= xmltarget_amd64_linux_no_xml
;
2943 tdesc_i386_linux_no_xml
= allocate_target_description ();
2944 copy_target_description (tdesc_i386_linux_no_xml
,
2945 i386_linux_read_description (X86_XSTATE_SSE_MASK
));
2946 tdesc_i386_linux_no_xml
->xmltarget
= xmltarget_i386_linux_no_xml
;
2948 initialize_regsets_info (&x86_regsets_info
);