1 /* GNU/Linux/x86-64 specific low level interface, for the remote server
3 Copyright (C) 2002-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "linux-low.h"
27 #include "gdbsupport/x86-xstate.h"
28 #include "nat/gdb_ptrace.h"
31 #include "nat/amd64-linux-siginfo.h"
34 #include "gdb_proc_service.h"
35 /* Don't include elf/common.h if linux/elf.h got included by
36 gdb_proc_service.h. */
38 #include "elf/common.h"
41 #include "gdbsupport/agent.h"
43 #include "tracepoint.h"
45 #include "nat/linux-nat.h"
46 #include "nat/x86-linux.h"
47 #include "nat/x86-linux-dregs.h"
48 #include "linux-x86-tdesc.h"
51 static target_desc_up tdesc_amd64_linux_no_xml
;
53 static target_desc_up tdesc_i386_linux_no_xml
;
56 static unsigned char jump_insn
[] = { 0xe9, 0, 0, 0, 0 };
57 static unsigned char small_jump_insn
[] = { 0x66, 0xe9, 0, 0 };
59 /* Backward compatibility for gdb without XML support. */
61 static const char xmltarget_i386_linux_no_xml
[] = "@<target>\
62 <architecture>i386</architecture>\
63 <osabi>GNU/Linux</osabi>\
67 static const char xmltarget_amd64_linux_no_xml
[] = "@<target>\
68 <architecture>i386:x86-64</architecture>\
69 <osabi>GNU/Linux</osabi>\
74 #include <sys/procfs.h>
77 #ifndef PTRACE_GET_THREAD_AREA
78 #define PTRACE_GET_THREAD_AREA 25
81 /* This definition comes from prctl.h, but some kernels may not have it. */
82 #ifndef PTRACE_ARCH_PRCTL
83 #define PTRACE_ARCH_PRCTL 30
86 /* The following definitions come from prctl.h, but may be absent
87 for certain configurations. */
89 #define ARCH_SET_GS 0x1001
90 #define ARCH_SET_FS 0x1002
91 #define ARCH_GET_FS 0x1003
92 #define ARCH_GET_GS 0x1004
95 /* Linux target op definitions for the x86 architecture.
96 This is initialized assuming an amd64 target.
97 'low_arch_setup' will correct it for i386 or amd64 targets. */
99 class x86_target
: public linux_process_target
103 const regs_info
*get_regs_info () override
;
105 const gdb_byte
*sw_breakpoint_from_kind (int kind
, int *size
) override
;
107 bool supports_z_point_type (char z_type
) override
;
109 void process_qsupported (gdb::array_view
<const char * const> features
) override
;
111 bool supports_tracepoints () override
;
113 bool supports_fast_tracepoints () override
;
115 int install_fast_tracepoint_jump_pad
116 (CORE_ADDR tpoint
, CORE_ADDR tpaddr
, CORE_ADDR collector
,
117 CORE_ADDR lockaddr
, ULONGEST orig_size
, CORE_ADDR
*jump_entry
,
118 CORE_ADDR
*trampoline
, ULONGEST
*trampoline_size
,
119 unsigned char *jjump_pad_insn
, ULONGEST
*jjump_pad_insn_size
,
120 CORE_ADDR
*adjusted_insn_addr
, CORE_ADDR
*adjusted_insn_addr_end
,
123 int get_min_fast_tracepoint_insn_len () override
;
125 struct emit_ops
*emit_ops () override
;
127 int get_ipa_tdesc_idx () override
;
131 void low_arch_setup () override
;
133 bool low_cannot_fetch_register (int regno
) override
;
135 bool low_cannot_store_register (int regno
) override
;
137 bool low_supports_breakpoints () override
;
139 CORE_ADDR
low_get_pc (regcache
*regcache
) override
;
141 void low_set_pc (regcache
*regcache
, CORE_ADDR newpc
) override
;
143 int low_decr_pc_after_break () override
;
145 bool low_breakpoint_at (CORE_ADDR pc
) override
;
147 int low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
148 int size
, raw_breakpoint
*bp
) override
;
150 int low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
151 int size
, raw_breakpoint
*bp
) override
;
153 bool low_stopped_by_watchpoint () override
;
155 CORE_ADDR
low_stopped_data_address () override
;
157 /* collect_ptrace_register/supply_ptrace_register are not needed in the
158 native i386 case (no registers smaller than an xfer unit), and are not
159 used in the biarch case (HAVE_LINUX_USRREGS is not defined). */
161 /* Need to fix up i386 siginfo if host is amd64. */
162 bool low_siginfo_fixup (siginfo_t
*native
, gdb_byte
*inf
,
163 int direction
) override
;
165 arch_process_info
*low_new_process () override
;
167 void low_delete_process (arch_process_info
*info
) override
;
169 void low_new_thread (lwp_info
*) override
;
171 void low_delete_thread (arch_lwp_info
*) override
;
173 void low_new_fork (process_info
*parent
, process_info
*child
) override
;
175 void low_prepare_to_resume (lwp_info
*lwp
) override
;
177 int low_get_thread_area (int lwpid
, CORE_ADDR
*addrp
) override
;
179 bool low_supports_range_stepping () override
;
181 bool low_supports_catch_syscall () override
;
183 void low_get_syscall_trapinfo (regcache
*regcache
, int *sysno
) override
;
187 /* Update all the target description of all processes; a new GDB
188 connected, and it may or not support xml target descriptions. */
189 void update_xmltarget ();
192 /* The singleton target ops object. */
194 static x86_target the_x86_target
;
196 /* Per-process arch-specific data we want to keep. */
198 struct arch_process_info
200 struct x86_debug_reg_state debug_reg_state
;
205 /* Mapping between the general-purpose registers in `struct user'
206 format and GDB's register array layout.
207 Note that the transfer layout uses 64-bit regs. */
208 static /*const*/ int i386_regmap
[] =
210 RAX
* 8, RCX
* 8, RDX
* 8, RBX
* 8,
211 RSP
* 8, RBP
* 8, RSI
* 8, RDI
* 8,
212 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
213 DS
* 8, ES
* 8, FS
* 8, GS
* 8
216 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
218 /* So code below doesn't have to care, i386 or amd64. */
219 #define ORIG_EAX ORIG_RAX
222 static const int x86_64_regmap
[] =
224 RAX
* 8, RBX
* 8, RCX
* 8, RDX
* 8,
225 RSI
* 8, RDI
* 8, RBP
* 8, RSP
* 8,
226 R8
* 8, R9
* 8, R10
* 8, R11
* 8,
227 R12
* 8, R13
* 8, R14
* 8, R15
* 8,
228 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
229 DS
* 8, ES
* 8, FS
* 8, GS
* 8,
230 -1, -1, -1, -1, -1, -1, -1, -1,
231 -1, -1, -1, -1, -1, -1, -1, -1,
232 -1, -1, -1, -1, -1, -1, -1, -1,
234 -1, -1, -1, -1, -1, -1, -1, -1,
237 -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */
238 -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */
239 -1, -1, -1, -1, -1, -1, -1, -1, /* xmm16 ... xmm31 (AVX512) */
240 -1, -1, -1, -1, -1, -1, -1, -1,
241 -1, -1, -1, -1, -1, -1, -1, -1, /* ymm16 ... ymm31 (AVX512) */
242 -1, -1, -1, -1, -1, -1, -1, -1,
243 -1, -1, -1, -1, -1, -1, -1, -1, /* k0 ... k7 (AVX512) */
244 -1, -1, -1, -1, -1, -1, -1, -1, /* zmm0 ... zmm31 (AVX512) */
245 -1, -1, -1, -1, -1, -1, -1, -1,
246 -1, -1, -1, -1, -1, -1, -1, -1,
247 -1, -1, -1, -1, -1, -1, -1, -1,
251 #define X86_64_NUM_REGS (sizeof (x86_64_regmap) / sizeof (x86_64_regmap[0]))
252 #define X86_64_USER_REGS (GS + 1)
254 #else /* ! __x86_64__ */
256 /* Mapping between the general-purpose registers in `struct user'
257 format and GDB's register array layout. */
258 static /*const*/ int i386_regmap
[] =
260 EAX
* 4, ECX
* 4, EDX
* 4, EBX
* 4,
261 UESP
* 4, EBP
* 4, ESI
* 4, EDI
* 4,
262 EIP
* 4, EFL
* 4, CS
* 4, SS
* 4,
263 DS
* 4, ES
* 4, FS
* 4, GS
* 4
266 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
274 /* Returns true if the current inferior belongs to a x86-64 process,
278 is_64bit_tdesc (void)
280 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
282 return register_size (regcache
->tdesc
, 0) == 8;
288 /* Called by libthread_db. */
291 ps_get_thread_area (struct ps_prochandle
*ph
,
292 lwpid_t lwpid
, int idx
, void **base
)
295 int use_64bit
= is_64bit_tdesc ();
302 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_FS
) == 0)
306 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_GS
) == 0)
317 unsigned int desc
[4];
319 if (ptrace (PTRACE_GET_THREAD_AREA
, lwpid
,
320 (void *) (intptr_t) idx
, (unsigned long) &desc
) < 0)
323 /* Ensure we properly extend the value to 64-bits for x86_64. */
324 *base
= (void *) (uintptr_t) desc
[1];
329 /* Get the thread area address. This is used to recognize which
330 thread is which when tracing with the in-process agent library. We
331 don't read anything from the address, and treat it as opaque; it's
332 the address itself that we assume is unique per-thread. */
335 x86_target::low_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
338 int use_64bit
= is_64bit_tdesc ();
343 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_FS
) == 0)
345 *addr
= (CORE_ADDR
) (uintptr_t) base
;
354 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
355 struct thread_info
*thr
= get_lwp_thread (lwp
);
356 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
357 unsigned int desc
[4];
359 const int reg_thread_area
= 3; /* bits to scale down register value. */
362 collect_register_by_name (regcache
, "gs", &gs
);
364 idx
= gs
>> reg_thread_area
;
366 if (ptrace (PTRACE_GET_THREAD_AREA
,
368 (void *) (long) idx
, (unsigned long) &desc
) < 0)
379 x86_target::low_cannot_store_register (int regno
)
382 if (is_64bit_tdesc ())
386 return regno
>= I386_NUM_REGS
;
390 x86_target::low_cannot_fetch_register (int regno
)
393 if (is_64bit_tdesc ())
397 return regno
>= I386_NUM_REGS
;
401 x86_fill_gregset (struct regcache
*regcache
, void *buf
)
406 if (register_size (regcache
->tdesc
, 0) == 8)
408 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
409 if (x86_64_regmap
[i
] != -1)
410 collect_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
415 /* 32-bit inferior registers need to be zero-extended.
416 Callers would read uninitialized memory otherwise. */
417 memset (buf
, 0x00, X86_64_USER_REGS
* 8);
420 for (i
= 0; i
< I386_NUM_REGS
; i
++)
421 collect_register (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
423 collect_register_by_name (regcache
, "orig_eax",
424 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
427 /* Sign extend EAX value to avoid potential syscall restart
430 See amd64_linux_collect_native_gregset() in gdb/amd64-linux-nat.c
431 for a detailed explanation. */
432 if (register_size (regcache
->tdesc
, 0) == 4)
434 void *ptr
= ((gdb_byte
*) buf
435 + i386_regmap
[find_regno (regcache
->tdesc
, "eax")]);
437 *(int64_t *) ptr
= *(int32_t *) ptr
;
443 x86_store_gregset (struct regcache
*regcache
, const void *buf
)
448 if (register_size (regcache
->tdesc
, 0) == 8)
450 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
451 if (x86_64_regmap
[i
] != -1)
452 supply_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
458 for (i
= 0; i
< I386_NUM_REGS
; i
++)
459 supply_register (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
461 supply_register_by_name (regcache
, "orig_eax",
462 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
466 x86_fill_fpregset (struct regcache
*regcache
, void *buf
)
469 i387_cache_to_fxsave (regcache
, buf
);
471 i387_cache_to_fsave (regcache
, buf
);
476 x86_store_fpregset (struct regcache
*regcache
, const void *buf
)
479 i387_fxsave_to_cache (regcache
, buf
);
481 i387_fsave_to_cache (regcache
, buf
);
488 x86_fill_fpxregset (struct regcache
*regcache
, void *buf
)
490 i387_cache_to_fxsave (regcache
, buf
);
494 x86_store_fpxregset (struct regcache
*regcache
, const void *buf
)
496 i387_fxsave_to_cache (regcache
, buf
);
502 x86_fill_xstateregset (struct regcache
*regcache
, void *buf
)
504 i387_cache_to_xsave (regcache
, buf
);
508 x86_store_xstateregset (struct regcache
*regcache
, const void *buf
)
510 i387_xsave_to_cache (regcache
, buf
);
513 /* ??? The non-biarch i386 case stores all the i387 regs twice.
514 Once in i387_.*fsave.* and once in i387_.*fxsave.*.
515 This is, presumably, to handle the case where PTRACE_[GS]ETFPXREGS
516 doesn't work. IWBN to avoid the duplication in the case where it
517 does work. Maybe the arch_setup routine could check whether it works
518 and update the supported regsets accordingly. */
520 static struct regset_info x86_regsets
[] =
522 #ifdef HAVE_PTRACE_GETREGS
523 { PTRACE_GETREGS
, PTRACE_SETREGS
, 0, sizeof (elf_gregset_t
),
525 x86_fill_gregset
, x86_store_gregset
},
526 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_X86_XSTATE
, 0,
527 EXTENDED_REGS
, x86_fill_xstateregset
, x86_store_xstateregset
},
529 # ifdef HAVE_PTRACE_GETFPXREGS
530 { PTRACE_GETFPXREGS
, PTRACE_SETFPXREGS
, 0, sizeof (elf_fpxregset_t
),
532 x86_fill_fpxregset
, x86_store_fpxregset
},
535 { PTRACE_GETFPREGS
, PTRACE_SETFPREGS
, 0, sizeof (elf_fpregset_t
),
537 x86_fill_fpregset
, x86_store_fpregset
},
538 #endif /* HAVE_PTRACE_GETREGS */
543 x86_target::low_supports_breakpoints ()
549 x86_target::low_get_pc (regcache
*regcache
)
551 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
557 collect_register_by_name (regcache
, "rip", &pc
);
558 return (CORE_ADDR
) pc
;
564 collect_register_by_name (regcache
, "eip", &pc
);
565 return (CORE_ADDR
) pc
;
570 x86_target::low_set_pc (regcache
*regcache
, CORE_ADDR pc
)
572 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
578 supply_register_by_name (regcache
, "rip", &newpc
);
584 supply_register_by_name (regcache
, "eip", &newpc
);
589 x86_target::low_decr_pc_after_break ()
595 static const gdb_byte x86_breakpoint
[] = { 0xCC };
596 #define x86_breakpoint_len 1
599 x86_target::low_breakpoint_at (CORE_ADDR pc
)
603 read_memory (pc
, &c
, 1);
610 /* Low-level function vector. */
611 struct x86_dr_low_type x86_dr_low
=
613 x86_linux_dr_set_control
,
614 x86_linux_dr_set_addr
,
615 x86_linux_dr_get_addr
,
616 x86_linux_dr_get_status
,
617 x86_linux_dr_get_control
,
621 /* Breakpoint/Watchpoint support. */
624 x86_target::supports_z_point_type (char z_type
)
630 case Z_PACKET_WRITE_WP
:
631 case Z_PACKET_ACCESS_WP
:
639 x86_target::low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
640 int size
, raw_breakpoint
*bp
)
642 struct process_info
*proc
= current_process ();
646 case raw_bkpt_type_hw
:
647 case raw_bkpt_type_write_wp
:
648 case raw_bkpt_type_access_wp
:
650 enum target_hw_bp_type hw_type
651 = raw_bkpt_type_to_target_hw_bp_type (type
);
652 struct x86_debug_reg_state
*state
653 = &proc
->priv
->arch_private
->debug_reg_state
;
655 return x86_dr_insert_watchpoint (state
, hw_type
, addr
, size
);
665 x86_target::low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
666 int size
, raw_breakpoint
*bp
)
668 struct process_info
*proc
= current_process ();
672 case raw_bkpt_type_hw
:
673 case raw_bkpt_type_write_wp
:
674 case raw_bkpt_type_access_wp
:
676 enum target_hw_bp_type hw_type
677 = raw_bkpt_type_to_target_hw_bp_type (type
);
678 struct x86_debug_reg_state
*state
679 = &proc
->priv
->arch_private
->debug_reg_state
;
681 return x86_dr_remove_watchpoint (state
, hw_type
, addr
, size
);
690 x86_target::low_stopped_by_watchpoint ()
692 struct process_info
*proc
= current_process ();
693 return x86_dr_stopped_by_watchpoint (&proc
->priv
->arch_private
->debug_reg_state
);
697 x86_target::low_stopped_data_address ()
699 struct process_info
*proc
= current_process ();
701 if (x86_dr_stopped_data_address (&proc
->priv
->arch_private
->debug_reg_state
,
707 /* Called when a new process is created. */
710 x86_target::low_new_process ()
712 struct arch_process_info
*info
= XCNEW (struct arch_process_info
);
714 x86_low_init_dregs (&info
->debug_reg_state
);
719 /* Called when a process is being deleted. */
722 x86_target::low_delete_process (arch_process_info
*info
)
728 x86_target::low_new_thread (lwp_info
*lwp
)
730 /* This comes from nat/. */
731 x86_linux_new_thread (lwp
);
735 x86_target::low_delete_thread (arch_lwp_info
*alwp
)
737 /* This comes from nat/. */
738 x86_linux_delete_thread (alwp
);
741 /* Target routine for new_fork. */
744 x86_target::low_new_fork (process_info
*parent
, process_info
*child
)
746 /* These are allocated by linux_add_process. */
747 gdb_assert (parent
->priv
!= NULL
748 && parent
->priv
->arch_private
!= NULL
);
749 gdb_assert (child
->priv
!= NULL
750 && child
->priv
->arch_private
!= NULL
);
752 /* Linux kernel before 2.6.33 commit
753 72f674d203cd230426437cdcf7dd6f681dad8b0d
754 will inherit hardware debug registers from parent
755 on fork/vfork/clone. Newer Linux kernels create such tasks with
756 zeroed debug registers.
758 GDB core assumes the child inherits the watchpoints/hw
759 breakpoints of the parent, and will remove them all from the
760 forked off process. Copy the debug registers mirrors into the
761 new process so that all breakpoints and watchpoints can be
762 removed together. The debug registers mirror will become zeroed
763 in the end before detaching the forked off process, thus making
764 this compatible with older Linux kernels too. */
766 *child
->priv
->arch_private
= *parent
->priv
->arch_private
;
770 x86_target::low_prepare_to_resume (lwp_info
*lwp
)
772 /* This comes from nat/. */
773 x86_linux_prepare_to_resume (lwp
);
776 /* See nat/x86-dregs.h. */
778 struct x86_debug_reg_state
*
779 x86_debug_reg_state (pid_t pid
)
781 struct process_info
*proc
= find_process_pid (pid
);
783 return &proc
->priv
->arch_private
->debug_reg_state
;
786 /* When GDBSERVER is built as a 64-bit application on linux, the
787 PTRACE_GETSIGINFO data is always presented in 64-bit layout. Since
788 debugging a 32-bit inferior with a 64-bit GDBSERVER should look the same
789 as debugging it with a 32-bit GDBSERVER, we do the 32-bit <-> 64-bit
790 conversion in-place ourselves. */
792 /* Convert a ptrace/host siginfo object, into/from the siginfo in the
793 layout of the inferiors' architecture. Returns true if any
794 conversion was done; false otherwise. If DIRECTION is 1, then copy
795 from INF to PTRACE. If DIRECTION is 0, copy from PTRACE to
799 x86_target::low_siginfo_fixup (siginfo_t
*ptrace
, gdb_byte
*inf
, int direction
)
802 unsigned int machine
;
803 int tid
= lwpid_of (current_thread
);
804 int is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
806 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
807 if (!is_64bit_tdesc ())
808 return amd64_linux_siginfo_fixup_common (ptrace
, inf
, direction
,
810 /* No fixup for native x32 GDB. */
811 else if (!is_elf64
&& sizeof (void *) == 8)
812 return amd64_linux_siginfo_fixup_common (ptrace
, inf
, direction
,
821 /* Format of XSAVE extended state is:
825 sw_usable_bytes[464..511]
826 xstate_hdr_bytes[512..575]
831 Same memory layout will be used for the coredump NT_X86_XSTATE
832 representing the XSAVE extended state registers.
834 The first 8 bytes of the sw_usable_bytes[464..467] is the OS enabled
835 extended state mask, which is the same as the extended control register
836 0 (the XFEATURE_ENABLED_MASK register), XCR0. We can use this mask
837 together with the mask saved in the xstate_hdr_bytes to determine what
838 states the processor/OS supports and what state, used or initialized,
839 the process/thread is in. */
840 #define I386_LINUX_XSAVE_XCR0_OFFSET 464
842 /* Does the current host support the GETFPXREGS request? The header
843 file may or may not define it, and even if it is defined, the
844 kernel will return EIO if it's running on a pre-SSE processor. */
845 int have_ptrace_getfpxregs
=
846 #ifdef HAVE_PTRACE_GETFPXREGS
853 /* Get Linux/x86 target description from running target. */
855 static const struct target_desc
*
856 x86_linux_read_description (void)
858 unsigned int machine
;
862 static uint64_t xcr0
;
863 struct regset_info
*regset
;
865 tid
= lwpid_of (current_thread
);
867 is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
869 if (sizeof (void *) == 4)
872 error (_("Can't debug 64-bit process with 32-bit GDBserver"));
874 else if (machine
== EM_X86_64
)
875 error (_("Can't debug x86-64 process with 32-bit GDBserver"));
879 #if !defined __x86_64__ && defined HAVE_PTRACE_GETFPXREGS
880 if (machine
== EM_386
&& have_ptrace_getfpxregs
== -1)
882 elf_fpxregset_t fpxregs
;
884 if (ptrace (PTRACE_GETFPXREGS
, tid
, 0, (long) &fpxregs
) < 0)
886 have_ptrace_getfpxregs
= 0;
887 have_ptrace_getregset
= 0;
888 return i386_linux_read_description (X86_XSTATE_X87
);
891 have_ptrace_getfpxregs
= 1;
897 x86_xcr0
= X86_XSTATE_SSE_MASK
;
901 if (machine
== EM_X86_64
)
902 return tdesc_amd64_linux_no_xml
.get ();
905 return tdesc_i386_linux_no_xml
.get ();
908 if (have_ptrace_getregset
== -1)
910 uint64_t xstateregs
[(X86_XSTATE_SSE_SIZE
/ sizeof (uint64_t))];
913 iov
.iov_base
= xstateregs
;
914 iov
.iov_len
= sizeof (xstateregs
);
916 /* Check if PTRACE_GETREGSET works. */
917 if (ptrace (PTRACE_GETREGSET
, tid
,
918 (unsigned int) NT_X86_XSTATE
, (long) &iov
) < 0)
919 have_ptrace_getregset
= 0;
922 have_ptrace_getregset
= 1;
924 /* Get XCR0 from XSAVE extended state. */
925 xcr0
= xstateregs
[(I386_LINUX_XSAVE_XCR0_OFFSET
926 / sizeof (uint64_t))];
928 /* Use PTRACE_GETREGSET if it is available. */
929 for (regset
= x86_regsets
;
930 regset
->fill_function
!= NULL
; regset
++)
931 if (regset
->get_request
== PTRACE_GETREGSET
)
932 regset
->size
= X86_XSTATE_SIZE (xcr0
);
933 else if (regset
->type
!= GENERAL_REGS
)
938 /* Check the native XCR0 only if PTRACE_GETREGSET is available. */
939 xcr0_features
= (have_ptrace_getregset
940 && (xcr0
& X86_XSTATE_ALL_MASK
));
945 if (machine
== EM_X86_64
)
948 const target_desc
*tdesc
= NULL
;
952 tdesc
= amd64_linux_read_description (xcr0
& X86_XSTATE_ALL_MASK
,
957 tdesc
= amd64_linux_read_description (X86_XSTATE_SSE_MASK
, !is_elf64
);
963 const target_desc
*tdesc
= NULL
;
966 tdesc
= i386_linux_read_description (xcr0
& X86_XSTATE_ALL_MASK
);
969 tdesc
= i386_linux_read_description (X86_XSTATE_SSE
);
974 gdb_assert_not_reached ("failed to return tdesc");
977 /* Update all the target description of all processes; a new GDB
978 connected, and it may or not support xml target descriptions. */
981 x86_target::update_xmltarget ()
983 struct thread_info
*saved_thread
= current_thread
;
985 /* Before changing the register cache's internal layout, flush the
986 contents of the current valid caches back to the threads, and
987 release the current regcache objects. */
990 for_each_process ([this] (process_info
*proc
) {
993 /* Look up any thread of this process. */
994 current_thread
= find_any_thread_of_pid (pid
);
999 current_thread
= saved_thread
;
1002 /* Process qSupported query, "xmlRegisters=". Update the buffer size for
1003 PTRACE_GETREGSET. */
1006 x86_target::process_qsupported (gdb::array_view
<const char * const> features
)
1008 /* Return if gdb doesn't support XML. If gdb sends "xmlRegisters="
1009 with "i386" in qSupported query, it supports x86 XML target
1013 for (const char *feature
: features
)
1015 if (startswith (feature
, "xmlRegisters="))
1017 char *copy
= xstrdup (feature
+ 13);
1020 for (char *p
= strtok_r (copy
, ",", &saveptr
);
1022 p
= strtok_r (NULL
, ",", &saveptr
))
1024 if (strcmp (p
, "i386") == 0)
1035 update_xmltarget ();
1038 /* Common for x86/x86-64. */
1040 static struct regsets_info x86_regsets_info
=
1042 x86_regsets
, /* regsets */
1043 0, /* num_regsets */
1044 NULL
, /* disabled_regsets */
1048 static struct regs_info amd64_linux_regs_info
=
1050 NULL
, /* regset_bitmap */
1051 NULL
, /* usrregs_info */
1055 static struct usrregs_info i386_linux_usrregs_info
=
1061 static struct regs_info i386_linux_regs_info
=
1063 NULL
, /* regset_bitmap */
1064 &i386_linux_usrregs_info
,
1069 x86_target::get_regs_info ()
1072 if (is_64bit_tdesc ())
1073 return &amd64_linux_regs_info
;
1076 return &i386_linux_regs_info
;
1079 /* Initialize the target description for the architecture of the
1083 x86_target::low_arch_setup ()
1085 current_process ()->tdesc
= x86_linux_read_description ();
1089 x86_target::low_supports_catch_syscall ()
1094 /* Fill *SYSNO and *SYSRET with the syscall nr trapped and the syscall return
1095 code. This should only be called if LWP got a SYSCALL_SIGTRAP. */
1098 x86_target::low_get_syscall_trapinfo (regcache
*regcache
, int *sysno
)
1100 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
1106 collect_register_by_name (regcache
, "orig_rax", &l_sysno
);
1107 *sysno
= (int) l_sysno
;
1110 collect_register_by_name (regcache
, "orig_eax", sysno
);
1114 x86_target::supports_tracepoints ()
1120 append_insns (CORE_ADDR
*to
, size_t len
, const unsigned char *buf
)
1122 target_write_memory (*to
, buf
, len
);
1127 push_opcode (unsigned char *buf
, const char *op
)
1129 unsigned char *buf_org
= buf
;
1134 unsigned long ul
= strtoul (op
, &endptr
, 16);
1143 return buf
- buf_org
;
1148 /* Build a jump pad that saves registers and calls a collection
1149 function. Writes a jump instruction to the jump pad to
1150 JJUMPAD_INSN. The caller is responsible to write it in at the
1151 tracepoint address. */
1154 amd64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1155 CORE_ADDR collector
,
1158 CORE_ADDR
*jump_entry
,
1159 CORE_ADDR
*trampoline
,
1160 ULONGEST
*trampoline_size
,
1161 unsigned char *jjump_pad_insn
,
1162 ULONGEST
*jjump_pad_insn_size
,
1163 CORE_ADDR
*adjusted_insn_addr
,
1164 CORE_ADDR
*adjusted_insn_addr_end
,
1167 unsigned char buf
[40];
1171 CORE_ADDR buildaddr
= *jump_entry
;
1173 /* Build the jump pad. */
1175 /* First, do tracepoint data collection. Save registers. */
1177 /* Need to ensure stack pointer saved first. */
1178 buf
[i
++] = 0x54; /* push %rsp */
1179 buf
[i
++] = 0x55; /* push %rbp */
1180 buf
[i
++] = 0x57; /* push %rdi */
1181 buf
[i
++] = 0x56; /* push %rsi */
1182 buf
[i
++] = 0x52; /* push %rdx */
1183 buf
[i
++] = 0x51; /* push %rcx */
1184 buf
[i
++] = 0x53; /* push %rbx */
1185 buf
[i
++] = 0x50; /* push %rax */
1186 buf
[i
++] = 0x41; buf
[i
++] = 0x57; /* push %r15 */
1187 buf
[i
++] = 0x41; buf
[i
++] = 0x56; /* push %r14 */
1188 buf
[i
++] = 0x41; buf
[i
++] = 0x55; /* push %r13 */
1189 buf
[i
++] = 0x41; buf
[i
++] = 0x54; /* push %r12 */
1190 buf
[i
++] = 0x41; buf
[i
++] = 0x53; /* push %r11 */
1191 buf
[i
++] = 0x41; buf
[i
++] = 0x52; /* push %r10 */
1192 buf
[i
++] = 0x41; buf
[i
++] = 0x51; /* push %r9 */
1193 buf
[i
++] = 0x41; buf
[i
++] = 0x50; /* push %r8 */
1194 buf
[i
++] = 0x9c; /* pushfq */
1195 buf
[i
++] = 0x48; /* movabs <addr>,%rdi */
1197 memcpy (buf
+ i
, &tpaddr
, 8);
1199 buf
[i
++] = 0x57; /* push %rdi */
1200 append_insns (&buildaddr
, i
, buf
);
1202 /* Stack space for the collecting_t object. */
1204 i
+= push_opcode (&buf
[i
], "48 83 ec 18"); /* sub $0x18,%rsp */
1205 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov <tpoint>,%rax */
1206 memcpy (buf
+ i
, &tpoint
, 8);
1208 i
+= push_opcode (&buf
[i
], "48 89 04 24"); /* mov %rax,(%rsp) */
1209 i
+= push_opcode (&buf
[i
],
1210 "64 48 8b 04 25 00 00 00 00"); /* mov %fs:0x0,%rax */
1211 i
+= push_opcode (&buf
[i
], "48 89 44 24 08"); /* mov %rax,0x8(%rsp) */
1212 append_insns (&buildaddr
, i
, buf
);
1216 i
+= push_opcode (&buf
[i
], "48 be"); /* movl <lockaddr>,%rsi */
1217 memcpy (&buf
[i
], (void *) &lockaddr
, 8);
1219 i
+= push_opcode (&buf
[i
], "48 89 e1"); /* mov %rsp,%rcx */
1220 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1221 i
+= push_opcode (&buf
[i
], "f0 48 0f b1 0e"); /* lock cmpxchg %rcx,(%rsi) */
1222 i
+= push_opcode (&buf
[i
], "48 85 c0"); /* test %rax,%rax */
1223 i
+= push_opcode (&buf
[i
], "75 f4"); /* jne <again> */
1224 append_insns (&buildaddr
, i
, buf
);
1226 /* Set up the gdb_collect call. */
1227 /* At this point, (stack pointer + 0x18) is the base of our saved
1231 i
+= push_opcode (&buf
[i
], "48 89 e6"); /* mov %rsp,%rsi */
1232 i
+= push_opcode (&buf
[i
], "48 83 c6 18"); /* add $0x18,%rsi */
1234 /* tpoint address may be 64-bit wide. */
1235 i
+= push_opcode (&buf
[i
], "48 bf"); /* movl <addr>,%rdi */
1236 memcpy (buf
+ i
, &tpoint
, 8);
1238 append_insns (&buildaddr
, i
, buf
);
1240 /* The collector function being in the shared library, may be
1241 >31-bits away off the jump pad. */
1243 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov $collector,%rax */
1244 memcpy (buf
+ i
, &collector
, 8);
1246 i
+= push_opcode (&buf
[i
], "ff d0"); /* callq *%rax */
1247 append_insns (&buildaddr
, i
, buf
);
1249 /* Clear the spin-lock. */
1251 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1252 i
+= push_opcode (&buf
[i
], "48 a3"); /* mov %rax, lockaddr */
1253 memcpy (buf
+ i
, &lockaddr
, 8);
1255 append_insns (&buildaddr
, i
, buf
);
1257 /* Remove stack that had been used for the collect_t object. */
1259 i
+= push_opcode (&buf
[i
], "48 83 c4 18"); /* add $0x18,%rsp */
1260 append_insns (&buildaddr
, i
, buf
);
1262 /* Restore register state. */
1264 buf
[i
++] = 0x48; /* add $0x8,%rsp */
1268 buf
[i
++] = 0x9d; /* popfq */
1269 buf
[i
++] = 0x41; buf
[i
++] = 0x58; /* pop %r8 */
1270 buf
[i
++] = 0x41; buf
[i
++] = 0x59; /* pop %r9 */
1271 buf
[i
++] = 0x41; buf
[i
++] = 0x5a; /* pop %r10 */
1272 buf
[i
++] = 0x41; buf
[i
++] = 0x5b; /* pop %r11 */
1273 buf
[i
++] = 0x41; buf
[i
++] = 0x5c; /* pop %r12 */
1274 buf
[i
++] = 0x41; buf
[i
++] = 0x5d; /* pop %r13 */
1275 buf
[i
++] = 0x41; buf
[i
++] = 0x5e; /* pop %r14 */
1276 buf
[i
++] = 0x41; buf
[i
++] = 0x5f; /* pop %r15 */
1277 buf
[i
++] = 0x58; /* pop %rax */
1278 buf
[i
++] = 0x5b; /* pop %rbx */
1279 buf
[i
++] = 0x59; /* pop %rcx */
1280 buf
[i
++] = 0x5a; /* pop %rdx */
1281 buf
[i
++] = 0x5e; /* pop %rsi */
1282 buf
[i
++] = 0x5f; /* pop %rdi */
1283 buf
[i
++] = 0x5d; /* pop %rbp */
1284 buf
[i
++] = 0x5c; /* pop %rsp */
1285 append_insns (&buildaddr
, i
, buf
);
1287 /* Now, adjust the original instruction to execute in the jump
1289 *adjusted_insn_addr
= buildaddr
;
1290 relocate_instruction (&buildaddr
, tpaddr
);
1291 *adjusted_insn_addr_end
= buildaddr
;
1293 /* Finally, write a jump back to the program. */
1295 loffset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1296 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1299 "E.Jump back from jump pad too far from tracepoint "
1300 "(offset 0x%" PRIx64
" > int32).", loffset
);
1304 offset
= (int) loffset
;
1305 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1306 memcpy (buf
+ 1, &offset
, 4);
1307 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1309 /* The jump pad is now built. Wire in a jump to our jump pad. This
1310 is always done last (by our caller actually), so that we can
1311 install fast tracepoints with threads running. This relies on
1312 the agent's atomic write support. */
1313 loffset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1314 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1317 "E.Jump pad too far from tracepoint "
1318 "(offset 0x%" PRIx64
" > int32).", loffset
);
1322 offset
= (int) loffset
;
1324 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1325 memcpy (buf
+ 1, &offset
, 4);
1326 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1327 *jjump_pad_insn_size
= sizeof (jump_insn
);
1329 /* Return the end address of our pad. */
1330 *jump_entry
= buildaddr
;
1335 #endif /* __x86_64__ */
1337 /* Build a jump pad that saves registers and calls a collection
1338 function. Writes a jump instruction to the jump pad to
1339 JJUMPAD_INSN. The caller is responsible to write it in at the
1340 tracepoint address. */
1343 i386_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1344 CORE_ADDR collector
,
1347 CORE_ADDR
*jump_entry
,
1348 CORE_ADDR
*trampoline
,
1349 ULONGEST
*trampoline_size
,
1350 unsigned char *jjump_pad_insn
,
1351 ULONGEST
*jjump_pad_insn_size
,
1352 CORE_ADDR
*adjusted_insn_addr
,
1353 CORE_ADDR
*adjusted_insn_addr_end
,
1356 unsigned char buf
[0x100];
1358 CORE_ADDR buildaddr
= *jump_entry
;
1360 /* Build the jump pad. */
1362 /* First, do tracepoint data collection. Save registers. */
1364 buf
[i
++] = 0x60; /* pushad */
1365 buf
[i
++] = 0x68; /* push tpaddr aka $pc */
1366 *((int *)(buf
+ i
)) = (int) tpaddr
;
1368 buf
[i
++] = 0x9c; /* pushf */
1369 buf
[i
++] = 0x1e; /* push %ds */
1370 buf
[i
++] = 0x06; /* push %es */
1371 buf
[i
++] = 0x0f; /* push %fs */
1373 buf
[i
++] = 0x0f; /* push %gs */
1375 buf
[i
++] = 0x16; /* push %ss */
1376 buf
[i
++] = 0x0e; /* push %cs */
1377 append_insns (&buildaddr
, i
, buf
);
1379 /* Stack space for the collecting_t object. */
1381 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1383 /* Build the object. */
1384 i
+= push_opcode (&buf
[i
], "b8"); /* mov <tpoint>,%eax */
1385 memcpy (buf
+ i
, &tpoint
, 4);
1387 i
+= push_opcode (&buf
[i
], "89 04 24"); /* mov %eax,(%esp) */
1389 i
+= push_opcode (&buf
[i
], "65 a1 00 00 00 00"); /* mov %gs:0x0,%eax */
1390 i
+= push_opcode (&buf
[i
], "89 44 24 04"); /* mov %eax,0x4(%esp) */
1391 append_insns (&buildaddr
, i
, buf
);
1393 /* spin-lock. Note this is using cmpxchg, which leaves i386 behind.
1394 If we cared for it, this could be using xchg alternatively. */
1397 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1398 i
+= push_opcode (&buf
[i
], "f0 0f b1 25"); /* lock cmpxchg
1400 memcpy (&buf
[i
], (void *) &lockaddr
, 4);
1402 i
+= push_opcode (&buf
[i
], "85 c0"); /* test %eax,%eax */
1403 i
+= push_opcode (&buf
[i
], "75 f2"); /* jne <again> */
1404 append_insns (&buildaddr
, i
, buf
);
1407 /* Set up arguments to the gdb_collect call. */
1409 i
+= push_opcode (&buf
[i
], "89 e0"); /* mov %esp,%eax */
1410 i
+= push_opcode (&buf
[i
], "83 c0 08"); /* add $0x08,%eax */
1411 i
+= push_opcode (&buf
[i
], "89 44 24 fc"); /* mov %eax,-0x4(%esp) */
1412 append_insns (&buildaddr
, i
, buf
);
1415 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1416 append_insns (&buildaddr
, i
, buf
);
1419 i
+= push_opcode (&buf
[i
], "c7 04 24"); /* movl <addr>,(%esp) */
1420 memcpy (&buf
[i
], (void *) &tpoint
, 4);
1422 append_insns (&buildaddr
, i
, buf
);
1424 buf
[0] = 0xe8; /* call <reladdr> */
1425 offset
= collector
- (buildaddr
+ sizeof (jump_insn
));
1426 memcpy (buf
+ 1, &offset
, 4);
1427 append_insns (&buildaddr
, 5, buf
);
1428 /* Clean up after the call. */
1429 buf
[0] = 0x83; /* add $0x8,%esp */
1432 append_insns (&buildaddr
, 3, buf
);
1435 /* Clear the spin-lock. This would need the LOCK prefix on older
1438 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1439 i
+= push_opcode (&buf
[i
], "a3"); /* mov %eax, lockaddr */
1440 memcpy (buf
+ i
, &lockaddr
, 4);
1442 append_insns (&buildaddr
, i
, buf
);
1445 /* Remove stack that had been used for the collect_t object. */
1447 i
+= push_opcode (&buf
[i
], "83 c4 08"); /* add $0x08,%esp */
1448 append_insns (&buildaddr
, i
, buf
);
1451 buf
[i
++] = 0x83; /* add $0x4,%esp (no pop of %cs, assume unchanged) */
1454 buf
[i
++] = 0x17; /* pop %ss */
1455 buf
[i
++] = 0x0f; /* pop %gs */
1457 buf
[i
++] = 0x0f; /* pop %fs */
1459 buf
[i
++] = 0x07; /* pop %es */
1460 buf
[i
++] = 0x1f; /* pop %ds */
1461 buf
[i
++] = 0x9d; /* popf */
1462 buf
[i
++] = 0x83; /* add $0x4,%esp (pop of tpaddr aka $pc) */
1465 buf
[i
++] = 0x61; /* popad */
1466 append_insns (&buildaddr
, i
, buf
);
1468 /* Now, adjust the original instruction to execute in the jump
1470 *adjusted_insn_addr
= buildaddr
;
1471 relocate_instruction (&buildaddr
, tpaddr
);
1472 *adjusted_insn_addr_end
= buildaddr
;
1474 /* Write the jump back to the program. */
1475 offset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1476 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1477 memcpy (buf
+ 1, &offset
, 4);
1478 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1480 /* The jump pad is now built. Wire in a jump to our jump pad. This
1481 is always done last (by our caller actually), so that we can
1482 install fast tracepoints with threads running. This relies on
1483 the agent's atomic write support. */
1486 /* Create a trampoline. */
1487 *trampoline_size
= sizeof (jump_insn
);
1488 if (!claim_trampoline_space (*trampoline_size
, trampoline
))
1490 /* No trampoline space available. */
1492 "E.Cannot allocate trampoline space needed for fast "
1493 "tracepoints on 4-byte instructions.");
1497 offset
= *jump_entry
- (*trampoline
+ sizeof (jump_insn
));
1498 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1499 memcpy (buf
+ 1, &offset
, 4);
1500 target_write_memory (*trampoline
, buf
, sizeof (jump_insn
));
1502 /* Use a 16-bit relative jump instruction to jump to the trampoline. */
1503 offset
= (*trampoline
- (tpaddr
+ sizeof (small_jump_insn
))) & 0xffff;
1504 memcpy (buf
, small_jump_insn
, sizeof (small_jump_insn
));
1505 memcpy (buf
+ 2, &offset
, 2);
1506 memcpy (jjump_pad_insn
, buf
, sizeof (small_jump_insn
));
1507 *jjump_pad_insn_size
= sizeof (small_jump_insn
);
1511 /* Else use a 32-bit relative jump instruction. */
1512 offset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1513 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1514 memcpy (buf
+ 1, &offset
, 4);
1515 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1516 *jjump_pad_insn_size
= sizeof (jump_insn
);
1519 /* Return the end address of our pad. */
1520 *jump_entry
= buildaddr
;
1526 x86_target::supports_fast_tracepoints ()
1532 x86_target::install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
,
1534 CORE_ADDR collector
,
1537 CORE_ADDR
*jump_entry
,
1538 CORE_ADDR
*trampoline
,
1539 ULONGEST
*trampoline_size
,
1540 unsigned char *jjump_pad_insn
,
1541 ULONGEST
*jjump_pad_insn_size
,
1542 CORE_ADDR
*adjusted_insn_addr
,
1543 CORE_ADDR
*adjusted_insn_addr_end
,
1547 if (is_64bit_tdesc ())
1548 return amd64_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1549 collector
, lockaddr
,
1550 orig_size
, jump_entry
,
1551 trampoline
, trampoline_size
,
1553 jjump_pad_insn_size
,
1555 adjusted_insn_addr_end
,
1559 return i386_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1560 collector
, lockaddr
,
1561 orig_size
, jump_entry
,
1562 trampoline
, trampoline_size
,
1564 jjump_pad_insn_size
,
1566 adjusted_insn_addr_end
,
1570 /* Return the minimum instruction length for fast tracepoints on x86/x86-64
1574 x86_target::get_min_fast_tracepoint_insn_len ()
1576 static int warned_about_fast_tracepoints
= 0;
1579 /* On x86-64, 5-byte jump instructions with a 4-byte offset are always
1580 used for fast tracepoints. */
1581 if (is_64bit_tdesc ())
1585 if (agent_loaded_p ())
1587 char errbuf
[IPA_BUFSIZ
];
1591 /* On x86, if trampolines are available, then 4-byte jump instructions
1592 with a 2-byte offset may be used, otherwise 5-byte jump instructions
1593 with a 4-byte offset are used instead. */
1594 if (have_fast_tracepoint_trampoline_buffer (errbuf
))
1598 /* GDB has no channel to explain to user why a shorter fast
1599 tracepoint is not possible, but at least make GDBserver
1600 mention that something has gone awry. */
1601 if (!warned_about_fast_tracepoints
)
1603 warning ("4-byte fast tracepoints not available; %s", errbuf
);
1604 warned_about_fast_tracepoints
= 1;
1611 /* Indicate that the minimum length is currently unknown since the IPA
1612 has not loaded yet. */
1618 add_insns (unsigned char *start
, int len
)
1620 CORE_ADDR buildaddr
= current_insn_ptr
;
1623 debug_printf ("Adding %d bytes of insn at %s\n",
1624 len
, paddress (buildaddr
));
1626 append_insns (&buildaddr
, len
, start
);
1627 current_insn_ptr
= buildaddr
;
1630 /* Our general strategy for emitting code is to avoid specifying raw
1631 bytes whenever possible, and instead copy a block of inline asm
1632 that is embedded in the function. This is a little messy, because
1633 we need to keep the compiler from discarding what looks like dead
1634 code, plus suppress various warnings. */
1636 #define EMIT_ASM(NAME, INSNS) \
1639 extern unsigned char start_ ## NAME, end_ ## NAME; \
1640 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1641 __asm__ ("jmp end_" #NAME "\n" \
1642 "\t" "start_" #NAME ":" \
1644 "\t" "end_" #NAME ":"); \
1649 #define EMIT_ASM32(NAME,INSNS) \
1652 extern unsigned char start_ ## NAME, end_ ## NAME; \
1653 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1654 __asm__ (".code32\n" \
1655 "\t" "jmp end_" #NAME "\n" \
1656 "\t" "start_" #NAME ":\n" \
1658 "\t" "end_" #NAME ":\n" \
1664 #define EMIT_ASM32(NAME,INSNS) EMIT_ASM(NAME,INSNS)
1671 amd64_emit_prologue (void)
1673 EMIT_ASM (amd64_prologue
,
1675 "movq %rsp,%rbp\n\t"
1676 "sub $0x20,%rsp\n\t"
1677 "movq %rdi,-8(%rbp)\n\t"
1678 "movq %rsi,-16(%rbp)");
1683 amd64_emit_epilogue (void)
1685 EMIT_ASM (amd64_epilogue
,
1686 "movq -16(%rbp),%rdi\n\t"
1687 "movq %rax,(%rdi)\n\t"
1694 amd64_emit_add (void)
1696 EMIT_ASM (amd64_add
,
1697 "add (%rsp),%rax\n\t"
1698 "lea 0x8(%rsp),%rsp");
1702 amd64_emit_sub (void)
1704 EMIT_ASM (amd64_sub
,
1705 "sub %rax,(%rsp)\n\t"
1710 amd64_emit_mul (void)
1716 amd64_emit_lsh (void)
1722 amd64_emit_rsh_signed (void)
1728 amd64_emit_rsh_unsigned (void)
1734 amd64_emit_ext (int arg
)
1739 EMIT_ASM (amd64_ext_8
,
1745 EMIT_ASM (amd64_ext_16
,
1750 EMIT_ASM (amd64_ext_32
,
1759 amd64_emit_log_not (void)
1761 EMIT_ASM (amd64_log_not
,
1762 "test %rax,%rax\n\t"
1768 amd64_emit_bit_and (void)
1770 EMIT_ASM (amd64_and
,
1771 "and (%rsp),%rax\n\t"
1772 "lea 0x8(%rsp),%rsp");
1776 amd64_emit_bit_or (void)
1779 "or (%rsp),%rax\n\t"
1780 "lea 0x8(%rsp),%rsp");
1784 amd64_emit_bit_xor (void)
1786 EMIT_ASM (amd64_xor
,
1787 "xor (%rsp),%rax\n\t"
1788 "lea 0x8(%rsp),%rsp");
1792 amd64_emit_bit_not (void)
1794 EMIT_ASM (amd64_bit_not
,
1795 "xorq $0xffffffffffffffff,%rax");
1799 amd64_emit_equal (void)
1801 EMIT_ASM (amd64_equal
,
1802 "cmp %rax,(%rsp)\n\t"
1803 "je .Lamd64_equal_true\n\t"
1805 "jmp .Lamd64_equal_end\n\t"
1806 ".Lamd64_equal_true:\n\t"
1808 ".Lamd64_equal_end:\n\t"
1809 "lea 0x8(%rsp),%rsp");
1813 amd64_emit_less_signed (void)
1815 EMIT_ASM (amd64_less_signed
,
1816 "cmp %rax,(%rsp)\n\t"
1817 "jl .Lamd64_less_signed_true\n\t"
1819 "jmp .Lamd64_less_signed_end\n\t"
1820 ".Lamd64_less_signed_true:\n\t"
1822 ".Lamd64_less_signed_end:\n\t"
1823 "lea 0x8(%rsp),%rsp");
1827 amd64_emit_less_unsigned (void)
1829 EMIT_ASM (amd64_less_unsigned
,
1830 "cmp %rax,(%rsp)\n\t"
1831 "jb .Lamd64_less_unsigned_true\n\t"
1833 "jmp .Lamd64_less_unsigned_end\n\t"
1834 ".Lamd64_less_unsigned_true:\n\t"
1836 ".Lamd64_less_unsigned_end:\n\t"
1837 "lea 0x8(%rsp),%rsp");
1841 amd64_emit_ref (int size
)
1846 EMIT_ASM (amd64_ref1
,
1850 EMIT_ASM (amd64_ref2
,
1854 EMIT_ASM (amd64_ref4
,
1855 "movl (%rax),%eax");
1858 EMIT_ASM (amd64_ref8
,
1859 "movq (%rax),%rax");
1865 amd64_emit_if_goto (int *offset_p
, int *size_p
)
1867 EMIT_ASM (amd64_if_goto
,
1871 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
1879 amd64_emit_goto (int *offset_p
, int *size_p
)
1881 EMIT_ASM (amd64_goto
,
1882 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
1890 amd64_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
1892 int diff
= (to
- (from
+ size
));
1893 unsigned char buf
[sizeof (int)];
1901 memcpy (buf
, &diff
, sizeof (int));
1902 target_write_memory (from
, buf
, sizeof (int));
1906 amd64_emit_const (LONGEST num
)
1908 unsigned char buf
[16];
1910 CORE_ADDR buildaddr
= current_insn_ptr
;
1913 buf
[i
++] = 0x48; buf
[i
++] = 0xb8; /* mov $<n>,%rax */
1914 memcpy (&buf
[i
], &num
, sizeof (num
));
1916 append_insns (&buildaddr
, i
, buf
);
1917 current_insn_ptr
= buildaddr
;
1921 amd64_emit_call (CORE_ADDR fn
)
1923 unsigned char buf
[16];
1925 CORE_ADDR buildaddr
;
1928 /* The destination function being in the shared library, may be
1929 >31-bits away off the compiled code pad. */
1931 buildaddr
= current_insn_ptr
;
1933 offset64
= fn
- (buildaddr
+ 1 /* call op */ + 4 /* 32-bit offset */);
1937 if (offset64
> INT_MAX
|| offset64
< INT_MIN
)
1939 /* Offset is too large for a call. Use callq, but that requires
1940 a register, so avoid it if possible. Use r10, since it is
1941 call-clobbered, we don't have to push/pop it. */
1942 buf
[i
++] = 0x48; /* mov $fn,%r10 */
1944 memcpy (buf
+ i
, &fn
, 8);
1946 buf
[i
++] = 0xff; /* callq *%r10 */
1951 int offset32
= offset64
; /* we know we can't overflow here. */
1953 buf
[i
++] = 0xe8; /* call <reladdr> */
1954 memcpy (buf
+ i
, &offset32
, 4);
1958 append_insns (&buildaddr
, i
, buf
);
1959 current_insn_ptr
= buildaddr
;
1963 amd64_emit_reg (int reg
)
1965 unsigned char buf
[16];
1967 CORE_ADDR buildaddr
;
1969 /* Assume raw_regs is still in %rdi. */
1970 buildaddr
= current_insn_ptr
;
1972 buf
[i
++] = 0xbe; /* mov $<n>,%esi */
1973 memcpy (&buf
[i
], ®
, sizeof (reg
));
1975 append_insns (&buildaddr
, i
, buf
);
1976 current_insn_ptr
= buildaddr
;
1977 amd64_emit_call (get_raw_reg_func_addr ());
1981 amd64_emit_pop (void)
1983 EMIT_ASM (amd64_pop
,
1988 amd64_emit_stack_flush (void)
1990 EMIT_ASM (amd64_stack_flush
,
1995 amd64_emit_zero_ext (int arg
)
2000 EMIT_ASM (amd64_zero_ext_8
,
2004 EMIT_ASM (amd64_zero_ext_16
,
2005 "and $0xffff,%rax");
2008 EMIT_ASM (amd64_zero_ext_32
,
2009 "mov $0xffffffff,%rcx\n\t"
2018 amd64_emit_swap (void)
2020 EMIT_ASM (amd64_swap
,
2027 amd64_emit_stack_adjust (int n
)
2029 unsigned char buf
[16];
2031 CORE_ADDR buildaddr
= current_insn_ptr
;
2034 buf
[i
++] = 0x48; /* lea $<n>(%rsp),%rsp */
2038 /* This only handles adjustments up to 16, but we don't expect any more. */
2040 append_insns (&buildaddr
, i
, buf
);
2041 current_insn_ptr
= buildaddr
;
2044 /* FN's prototype is `LONGEST(*fn)(int)'. */
2047 amd64_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2049 unsigned char buf
[16];
2051 CORE_ADDR buildaddr
;
2053 buildaddr
= current_insn_ptr
;
2055 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
2056 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2058 append_insns (&buildaddr
, i
, buf
);
2059 current_insn_ptr
= buildaddr
;
2060 amd64_emit_call (fn
);
2063 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
2066 amd64_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2068 unsigned char buf
[16];
2070 CORE_ADDR buildaddr
;
2072 buildaddr
= current_insn_ptr
;
2074 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
2075 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2077 append_insns (&buildaddr
, i
, buf
);
2078 current_insn_ptr
= buildaddr
;
2079 EMIT_ASM (amd64_void_call_2_a
,
2080 /* Save away a copy of the stack top. */
2082 /* Also pass top as the second argument. */
2084 amd64_emit_call (fn
);
2085 EMIT_ASM (amd64_void_call_2_b
,
2086 /* Restore the stack top, %rax may have been trashed. */
2091 amd64_emit_eq_goto (int *offset_p
, int *size_p
)
2094 "cmp %rax,(%rsp)\n\t"
2095 "jne .Lamd64_eq_fallthru\n\t"
2096 "lea 0x8(%rsp),%rsp\n\t"
2098 /* jmp, but don't trust the assembler to choose the right jump */
2099 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2100 ".Lamd64_eq_fallthru:\n\t"
2101 "lea 0x8(%rsp),%rsp\n\t"
2111 amd64_emit_ne_goto (int *offset_p
, int *size_p
)
2114 "cmp %rax,(%rsp)\n\t"
2115 "je .Lamd64_ne_fallthru\n\t"
2116 "lea 0x8(%rsp),%rsp\n\t"
2118 /* jmp, but don't trust the assembler to choose the right jump */
2119 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2120 ".Lamd64_ne_fallthru:\n\t"
2121 "lea 0x8(%rsp),%rsp\n\t"
2131 amd64_emit_lt_goto (int *offset_p
, int *size_p
)
2134 "cmp %rax,(%rsp)\n\t"
2135 "jnl .Lamd64_lt_fallthru\n\t"
2136 "lea 0x8(%rsp),%rsp\n\t"
2138 /* jmp, but don't trust the assembler to choose the right jump */
2139 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2140 ".Lamd64_lt_fallthru:\n\t"
2141 "lea 0x8(%rsp),%rsp\n\t"
2151 amd64_emit_le_goto (int *offset_p
, int *size_p
)
2154 "cmp %rax,(%rsp)\n\t"
2155 "jnle .Lamd64_le_fallthru\n\t"
2156 "lea 0x8(%rsp),%rsp\n\t"
2158 /* jmp, but don't trust the assembler to choose the right jump */
2159 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2160 ".Lamd64_le_fallthru:\n\t"
2161 "lea 0x8(%rsp),%rsp\n\t"
2171 amd64_emit_gt_goto (int *offset_p
, int *size_p
)
2174 "cmp %rax,(%rsp)\n\t"
2175 "jng .Lamd64_gt_fallthru\n\t"
2176 "lea 0x8(%rsp),%rsp\n\t"
2178 /* jmp, but don't trust the assembler to choose the right jump */
2179 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2180 ".Lamd64_gt_fallthru:\n\t"
2181 "lea 0x8(%rsp),%rsp\n\t"
2191 amd64_emit_ge_goto (int *offset_p
, int *size_p
)
2194 "cmp %rax,(%rsp)\n\t"
2195 "jnge .Lamd64_ge_fallthru\n\t"
2196 ".Lamd64_ge_jump:\n\t"
2197 "lea 0x8(%rsp),%rsp\n\t"
2199 /* jmp, but don't trust the assembler to choose the right jump */
2200 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2201 ".Lamd64_ge_fallthru:\n\t"
2202 "lea 0x8(%rsp),%rsp\n\t"
2211 struct emit_ops amd64_emit_ops
=
2213 amd64_emit_prologue
,
2214 amd64_emit_epilogue
,
2219 amd64_emit_rsh_signed
,
2220 amd64_emit_rsh_unsigned
,
2228 amd64_emit_less_signed
,
2229 amd64_emit_less_unsigned
,
2233 amd64_write_goto_address
,
2238 amd64_emit_stack_flush
,
2239 amd64_emit_zero_ext
,
2241 amd64_emit_stack_adjust
,
2242 amd64_emit_int_call_1
,
2243 amd64_emit_void_call_2
,
2252 #endif /* __x86_64__ */
2255 i386_emit_prologue (void)
2257 EMIT_ASM32 (i386_prologue
,
2261 /* At this point, the raw regs base address is at 8(%ebp), and the
2262 value pointer is at 12(%ebp). */
2266 i386_emit_epilogue (void)
2268 EMIT_ASM32 (i386_epilogue
,
2269 "mov 12(%ebp),%ecx\n\t"
2270 "mov %eax,(%ecx)\n\t"
2271 "mov %ebx,0x4(%ecx)\n\t"
2279 i386_emit_add (void)
2281 EMIT_ASM32 (i386_add
,
2282 "add (%esp),%eax\n\t"
2283 "adc 0x4(%esp),%ebx\n\t"
2284 "lea 0x8(%esp),%esp");
2288 i386_emit_sub (void)
2290 EMIT_ASM32 (i386_sub
,
2291 "subl %eax,(%esp)\n\t"
2292 "sbbl %ebx,4(%esp)\n\t"
2298 i386_emit_mul (void)
2304 i386_emit_lsh (void)
2310 i386_emit_rsh_signed (void)
2316 i386_emit_rsh_unsigned (void)
2322 i386_emit_ext (int arg
)
2327 EMIT_ASM32 (i386_ext_8
,
2330 "movl %eax,%ebx\n\t"
2334 EMIT_ASM32 (i386_ext_16
,
2336 "movl %eax,%ebx\n\t"
2340 EMIT_ASM32 (i386_ext_32
,
2341 "movl %eax,%ebx\n\t"
2350 i386_emit_log_not (void)
2352 EMIT_ASM32 (i386_log_not
,
2354 "test %eax,%eax\n\t"
2361 i386_emit_bit_and (void)
2363 EMIT_ASM32 (i386_and
,
2364 "and (%esp),%eax\n\t"
2365 "and 0x4(%esp),%ebx\n\t"
2366 "lea 0x8(%esp),%esp");
2370 i386_emit_bit_or (void)
2372 EMIT_ASM32 (i386_or
,
2373 "or (%esp),%eax\n\t"
2374 "or 0x4(%esp),%ebx\n\t"
2375 "lea 0x8(%esp),%esp");
2379 i386_emit_bit_xor (void)
2381 EMIT_ASM32 (i386_xor
,
2382 "xor (%esp),%eax\n\t"
2383 "xor 0x4(%esp),%ebx\n\t"
2384 "lea 0x8(%esp),%esp");
2388 i386_emit_bit_not (void)
2390 EMIT_ASM32 (i386_bit_not
,
2391 "xor $0xffffffff,%eax\n\t"
2392 "xor $0xffffffff,%ebx\n\t");
2396 i386_emit_equal (void)
2398 EMIT_ASM32 (i386_equal
,
2399 "cmpl %ebx,4(%esp)\n\t"
2400 "jne .Li386_equal_false\n\t"
2401 "cmpl %eax,(%esp)\n\t"
2402 "je .Li386_equal_true\n\t"
2403 ".Li386_equal_false:\n\t"
2405 "jmp .Li386_equal_end\n\t"
2406 ".Li386_equal_true:\n\t"
2408 ".Li386_equal_end:\n\t"
2410 "lea 0x8(%esp),%esp");
2414 i386_emit_less_signed (void)
2416 EMIT_ASM32 (i386_less_signed
,
2417 "cmpl %ebx,4(%esp)\n\t"
2418 "jl .Li386_less_signed_true\n\t"
2419 "jne .Li386_less_signed_false\n\t"
2420 "cmpl %eax,(%esp)\n\t"
2421 "jl .Li386_less_signed_true\n\t"
2422 ".Li386_less_signed_false:\n\t"
2424 "jmp .Li386_less_signed_end\n\t"
2425 ".Li386_less_signed_true:\n\t"
2427 ".Li386_less_signed_end:\n\t"
2429 "lea 0x8(%esp),%esp");
2433 i386_emit_less_unsigned (void)
2435 EMIT_ASM32 (i386_less_unsigned
,
2436 "cmpl %ebx,4(%esp)\n\t"
2437 "jb .Li386_less_unsigned_true\n\t"
2438 "jne .Li386_less_unsigned_false\n\t"
2439 "cmpl %eax,(%esp)\n\t"
2440 "jb .Li386_less_unsigned_true\n\t"
2441 ".Li386_less_unsigned_false:\n\t"
2443 "jmp .Li386_less_unsigned_end\n\t"
2444 ".Li386_less_unsigned_true:\n\t"
2446 ".Li386_less_unsigned_end:\n\t"
2448 "lea 0x8(%esp),%esp");
2452 i386_emit_ref (int size
)
2457 EMIT_ASM32 (i386_ref1
,
2461 EMIT_ASM32 (i386_ref2
,
2465 EMIT_ASM32 (i386_ref4
,
2466 "movl (%eax),%eax");
2469 EMIT_ASM32 (i386_ref8
,
2470 "movl 4(%eax),%ebx\n\t"
2471 "movl (%eax),%eax");
2477 i386_emit_if_goto (int *offset_p
, int *size_p
)
2479 EMIT_ASM32 (i386_if_goto
,
2485 /* Don't trust the assembler to choose the right jump */
2486 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
2489 *offset_p
= 11; /* be sure that this matches the sequence above */
2495 i386_emit_goto (int *offset_p
, int *size_p
)
2497 EMIT_ASM32 (i386_goto
,
2498 /* Don't trust the assembler to choose the right jump */
2499 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
2507 i386_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2509 int diff
= (to
- (from
+ size
));
2510 unsigned char buf
[sizeof (int)];
2512 /* We're only doing 4-byte sizes at the moment. */
2519 memcpy (buf
, &diff
, sizeof (int));
2520 target_write_memory (from
, buf
, sizeof (int));
2524 i386_emit_const (LONGEST num
)
2526 unsigned char buf
[16];
2528 CORE_ADDR buildaddr
= current_insn_ptr
;
2531 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2532 lo
= num
& 0xffffffff;
2533 memcpy (&buf
[i
], &lo
, sizeof (lo
));
2535 hi
= ((num
>> 32) & 0xffffffff);
2538 buf
[i
++] = 0xbb; /* mov $<n>,%ebx */
2539 memcpy (&buf
[i
], &hi
, sizeof (hi
));
2544 buf
[i
++] = 0x31; buf
[i
++] = 0xdb; /* xor %ebx,%ebx */
2546 append_insns (&buildaddr
, i
, buf
);
2547 current_insn_ptr
= buildaddr
;
2551 i386_emit_call (CORE_ADDR fn
)
2553 unsigned char buf
[16];
2555 CORE_ADDR buildaddr
;
2557 buildaddr
= current_insn_ptr
;
2559 buf
[i
++] = 0xe8; /* call <reladdr> */
2560 offset
= ((int) fn
) - (buildaddr
+ 5);
2561 memcpy (buf
+ 1, &offset
, 4);
2562 append_insns (&buildaddr
, 5, buf
);
2563 current_insn_ptr
= buildaddr
;
2567 i386_emit_reg (int reg
)
2569 unsigned char buf
[16];
2571 CORE_ADDR buildaddr
;
2573 EMIT_ASM32 (i386_reg_a
,
2575 buildaddr
= current_insn_ptr
;
2577 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2578 memcpy (&buf
[i
], ®
, sizeof (reg
));
2580 append_insns (&buildaddr
, i
, buf
);
2581 current_insn_ptr
= buildaddr
;
2582 EMIT_ASM32 (i386_reg_b
,
2583 "mov %eax,4(%esp)\n\t"
2584 "mov 8(%ebp),%eax\n\t"
2586 i386_emit_call (get_raw_reg_func_addr ());
2587 EMIT_ASM32 (i386_reg_c
,
2589 "lea 0x8(%esp),%esp");
2593 i386_emit_pop (void)
2595 EMIT_ASM32 (i386_pop
,
2601 i386_emit_stack_flush (void)
2603 EMIT_ASM32 (i386_stack_flush
,
2609 i386_emit_zero_ext (int arg
)
2614 EMIT_ASM32 (i386_zero_ext_8
,
2615 "and $0xff,%eax\n\t"
2619 EMIT_ASM32 (i386_zero_ext_16
,
2620 "and $0xffff,%eax\n\t"
2624 EMIT_ASM32 (i386_zero_ext_32
,
2633 i386_emit_swap (void)
2635 EMIT_ASM32 (i386_swap
,
2645 i386_emit_stack_adjust (int n
)
2647 unsigned char buf
[16];
2649 CORE_ADDR buildaddr
= current_insn_ptr
;
2652 buf
[i
++] = 0x8d; /* lea $<n>(%esp),%esp */
2656 append_insns (&buildaddr
, i
, buf
);
2657 current_insn_ptr
= buildaddr
;
2660 /* FN's prototype is `LONGEST(*fn)(int)'. */
2663 i386_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2665 unsigned char buf
[16];
2667 CORE_ADDR buildaddr
;
2669 EMIT_ASM32 (i386_int_call_1_a
,
2670 /* Reserve a bit of stack space. */
2672 /* Put the one argument on the stack. */
2673 buildaddr
= current_insn_ptr
;
2675 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2678 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2680 append_insns (&buildaddr
, i
, buf
);
2681 current_insn_ptr
= buildaddr
;
2682 i386_emit_call (fn
);
2683 EMIT_ASM32 (i386_int_call_1_c
,
2685 "lea 0x8(%esp),%esp");
2688 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
2691 i386_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2693 unsigned char buf
[16];
2695 CORE_ADDR buildaddr
;
2697 EMIT_ASM32 (i386_void_call_2_a
,
2698 /* Preserve %eax only; we don't have to worry about %ebx. */
2700 /* Reserve a bit of stack space for arguments. */
2701 "sub $0x10,%esp\n\t"
2702 /* Copy "top" to the second argument position. (Note that
2703 we can't assume function won't scribble on its
2704 arguments, so don't try to restore from this.) */
2705 "mov %eax,4(%esp)\n\t"
2706 "mov %ebx,8(%esp)");
2707 /* Put the first argument on the stack. */
2708 buildaddr
= current_insn_ptr
;
2710 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2713 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2715 append_insns (&buildaddr
, i
, buf
);
2716 current_insn_ptr
= buildaddr
;
2717 i386_emit_call (fn
);
2718 EMIT_ASM32 (i386_void_call_2_b
,
2719 "lea 0x10(%esp),%esp\n\t"
2720 /* Restore original stack top. */
2726 i386_emit_eq_goto (int *offset_p
, int *size_p
)
2729 /* Check low half first, more likely to be decider */
2730 "cmpl %eax,(%esp)\n\t"
2731 "jne .Leq_fallthru\n\t"
2732 "cmpl %ebx,4(%esp)\n\t"
2733 "jne .Leq_fallthru\n\t"
2734 "lea 0x8(%esp),%esp\n\t"
2737 /* jmp, but don't trust the assembler to choose the right jump */
2738 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2739 ".Leq_fallthru:\n\t"
2740 "lea 0x8(%esp),%esp\n\t"
2751 i386_emit_ne_goto (int *offset_p
, int *size_p
)
2754 /* Check low half first, more likely to be decider */
2755 "cmpl %eax,(%esp)\n\t"
2757 "cmpl %ebx,4(%esp)\n\t"
2758 "je .Lne_fallthru\n\t"
2760 "lea 0x8(%esp),%esp\n\t"
2763 /* jmp, but don't trust the assembler to choose the right jump */
2764 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2765 ".Lne_fallthru:\n\t"
2766 "lea 0x8(%esp),%esp\n\t"
2777 i386_emit_lt_goto (int *offset_p
, int *size_p
)
2780 "cmpl %ebx,4(%esp)\n\t"
2782 "jne .Llt_fallthru\n\t"
2783 "cmpl %eax,(%esp)\n\t"
2784 "jnl .Llt_fallthru\n\t"
2786 "lea 0x8(%esp),%esp\n\t"
2789 /* jmp, but don't trust the assembler to choose the right jump */
2790 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2791 ".Llt_fallthru:\n\t"
2792 "lea 0x8(%esp),%esp\n\t"
2803 i386_emit_le_goto (int *offset_p
, int *size_p
)
2806 "cmpl %ebx,4(%esp)\n\t"
2808 "jne .Lle_fallthru\n\t"
2809 "cmpl %eax,(%esp)\n\t"
2810 "jnle .Lle_fallthru\n\t"
2812 "lea 0x8(%esp),%esp\n\t"
2815 /* jmp, but don't trust the assembler to choose the right jump */
2816 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2817 ".Lle_fallthru:\n\t"
2818 "lea 0x8(%esp),%esp\n\t"
2829 i386_emit_gt_goto (int *offset_p
, int *size_p
)
2832 "cmpl %ebx,4(%esp)\n\t"
2834 "jne .Lgt_fallthru\n\t"
2835 "cmpl %eax,(%esp)\n\t"
2836 "jng .Lgt_fallthru\n\t"
2838 "lea 0x8(%esp),%esp\n\t"
2841 /* jmp, but don't trust the assembler to choose the right jump */
2842 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2843 ".Lgt_fallthru:\n\t"
2844 "lea 0x8(%esp),%esp\n\t"
2855 i386_emit_ge_goto (int *offset_p
, int *size_p
)
2858 "cmpl %ebx,4(%esp)\n\t"
2860 "jne .Lge_fallthru\n\t"
2861 "cmpl %eax,(%esp)\n\t"
2862 "jnge .Lge_fallthru\n\t"
2864 "lea 0x8(%esp),%esp\n\t"
2867 /* jmp, but don't trust the assembler to choose the right jump */
2868 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2869 ".Lge_fallthru:\n\t"
2870 "lea 0x8(%esp),%esp\n\t"
2880 struct emit_ops i386_emit_ops
=
2888 i386_emit_rsh_signed
,
2889 i386_emit_rsh_unsigned
,
2897 i386_emit_less_signed
,
2898 i386_emit_less_unsigned
,
2902 i386_write_goto_address
,
2907 i386_emit_stack_flush
,
2910 i386_emit_stack_adjust
,
2911 i386_emit_int_call_1
,
2912 i386_emit_void_call_2
,
2923 x86_target::emit_ops ()
2926 if (is_64bit_tdesc ())
2927 return &amd64_emit_ops
;
2930 return &i386_emit_ops
;
2933 /* Implementation of target ops method "sw_breakpoint_from_kind". */
2936 x86_target::sw_breakpoint_from_kind (int kind
, int *size
)
2938 *size
= x86_breakpoint_len
;
2939 return x86_breakpoint
;
2943 x86_target::low_supports_range_stepping ()
2949 x86_target::get_ipa_tdesc_idx ()
2951 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
2952 const struct target_desc
*tdesc
= regcache
->tdesc
;
2955 return amd64_get_ipa_tdesc_idx (tdesc
);
2958 if (tdesc
== tdesc_i386_linux_no_xml
.get ())
2959 return X86_TDESC_SSE
;
2961 return i386_get_ipa_tdesc_idx (tdesc
);
2964 /* The linux target ops object. */
2966 linux_process_target
*the_linux_target
= &the_x86_target
;
2969 initialize_low_arch (void)
2971 /* Initialize the Linux target descriptions. */
2973 tdesc_amd64_linux_no_xml
= allocate_target_description ();
2974 copy_target_description (tdesc_amd64_linux_no_xml
.get (),
2975 amd64_linux_read_description (X86_XSTATE_SSE_MASK
,
2977 tdesc_amd64_linux_no_xml
->xmltarget
= xmltarget_amd64_linux_no_xml
;
2980 tdesc_i386_linux_no_xml
= allocate_target_description ();
2981 copy_target_description (tdesc_i386_linux_no_xml
.get (),
2982 i386_linux_read_description (X86_XSTATE_SSE_MASK
));
2983 tdesc_i386_linux_no_xml
->xmltarget
= xmltarget_i386_linux_no_xml
;
2985 initialize_regsets_info (&x86_regsets_info
);