1 /* GNU/Linux/x86-64 specific low level interface, for the remote server
3 Copyright (C) 2002-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "linux-low.h"
27 #include "gdbsupport/x86-xstate.h"
28 #include "nat/gdb_ptrace.h"
31 #include "nat/amd64-linux-siginfo.h"
34 #include "gdb_proc_service.h"
35 /* Don't include elf/common.h if linux/elf.h got included by
36 gdb_proc_service.h. */
38 #include "elf/common.h"
41 #include "gdbsupport/agent.h"
43 #include "tracepoint.h"
45 #include "nat/linux-nat.h"
46 #include "nat/x86-linux.h"
47 #include "nat/x86-linux-dregs.h"
48 #include "linux-x86-tdesc.h"
51 static struct target_desc
*tdesc_amd64_linux_no_xml
;
53 static struct target_desc
*tdesc_i386_linux_no_xml
;
56 static unsigned char jump_insn
[] = { 0xe9, 0, 0, 0, 0 };
57 static unsigned char small_jump_insn
[] = { 0x66, 0xe9, 0, 0 };
59 /* Backward compatibility for gdb without XML support. */
61 static const char *xmltarget_i386_linux_no_xml
= "@<target>\
62 <architecture>i386</architecture>\
63 <osabi>GNU/Linux</osabi>\
67 static const char *xmltarget_amd64_linux_no_xml
= "@<target>\
68 <architecture>i386:x86-64</architecture>\
69 <osabi>GNU/Linux</osabi>\
74 #include <sys/procfs.h>
77 #ifndef PTRACE_GET_THREAD_AREA
78 #define PTRACE_GET_THREAD_AREA 25
81 /* This definition comes from prctl.h, but some kernels may not have it. */
82 #ifndef PTRACE_ARCH_PRCTL
83 #define PTRACE_ARCH_PRCTL 30
86 /* The following definitions come from prctl.h, but may be absent
87 for certain configurations. */
89 #define ARCH_SET_GS 0x1001
90 #define ARCH_SET_FS 0x1002
91 #define ARCH_GET_FS 0x1003
92 #define ARCH_GET_GS 0x1004
95 /* Linux target op definitions for the x86 architecture.
96 This is initialized assuming an amd64 target.
97 'low_arch_setup' will correct it for i386 or amd64 targets. */
99 class x86_target
: public linux_process_target
103 const regs_info
*get_regs_info () override
;
105 const gdb_byte
*sw_breakpoint_from_kind (int kind
, int *size
) override
;
107 bool supports_z_point_type (char z_type
) override
;
109 void process_qsupported (char **features
, int count
) override
;
111 bool supports_tracepoints () override
;
113 bool supports_fast_tracepoints () override
;
115 int install_fast_tracepoint_jump_pad
116 (CORE_ADDR tpoint
, CORE_ADDR tpaddr
, CORE_ADDR collector
,
117 CORE_ADDR lockaddr
, ULONGEST orig_size
, CORE_ADDR
*jump_entry
,
118 CORE_ADDR
*trampoline
, ULONGEST
*trampoline_size
,
119 unsigned char *jjump_pad_insn
, ULONGEST
*jjump_pad_insn_size
,
120 CORE_ADDR
*adjusted_insn_addr
, CORE_ADDR
*adjusted_insn_addr_end
,
123 int get_min_fast_tracepoint_insn_len () override
;
125 struct emit_ops
*emit_ops () override
;
129 void low_arch_setup () override
;
131 bool low_cannot_fetch_register (int regno
) override
;
133 bool low_cannot_store_register (int regno
) override
;
135 bool low_supports_breakpoints () override
;
137 CORE_ADDR
low_get_pc (regcache
*regcache
) override
;
139 void low_set_pc (regcache
*regcache
, CORE_ADDR newpc
) override
;
141 int low_decr_pc_after_break () override
;
143 bool low_breakpoint_at (CORE_ADDR pc
) override
;
145 int low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
146 int size
, raw_breakpoint
*bp
) override
;
148 int low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
149 int size
, raw_breakpoint
*bp
) override
;
151 bool low_stopped_by_watchpoint () override
;
153 CORE_ADDR
low_stopped_data_address () override
;
155 /* collect_ptrace_register/supply_ptrace_register are not needed in the
156 native i386 case (no registers smaller than an xfer unit), and are not
157 used in the biarch case (HAVE_LINUX_USRREGS is not defined). */
159 /* Need to fix up i386 siginfo if host is amd64. */
160 bool low_siginfo_fixup (siginfo_t
*native
, gdb_byte
*inf
,
161 int direction
) override
;
163 arch_process_info
*low_new_process () override
;
165 void low_delete_process (arch_process_info
*info
) override
;
167 void low_new_thread (lwp_info
*) override
;
169 void low_delete_thread (arch_lwp_info
*) override
;
171 void low_new_fork (process_info
*parent
, process_info
*child
) override
;
173 void low_prepare_to_resume (lwp_info
*lwp
) override
;
175 int low_get_thread_area (int lwpid
, CORE_ADDR
*addrp
) override
;
179 /* Update all the target description of all processes; a new GDB
180 connected, and it may or not support xml target descriptions. */
181 void update_xmltarget ();
184 /* The singleton target ops object. */
186 static x86_target the_x86_target
;
188 /* Per-process arch-specific data we want to keep. */
190 struct arch_process_info
192 struct x86_debug_reg_state debug_reg_state
;
197 /* Mapping between the general-purpose registers in `struct user'
198 format and GDB's register array layout.
199 Note that the transfer layout uses 64-bit regs. */
200 static /*const*/ int i386_regmap
[] =
202 RAX
* 8, RCX
* 8, RDX
* 8, RBX
* 8,
203 RSP
* 8, RBP
* 8, RSI
* 8, RDI
* 8,
204 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
205 DS
* 8, ES
* 8, FS
* 8, GS
* 8
208 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
210 /* So code below doesn't have to care, i386 or amd64. */
211 #define ORIG_EAX ORIG_RAX
214 static const int x86_64_regmap
[] =
216 RAX
* 8, RBX
* 8, RCX
* 8, RDX
* 8,
217 RSI
* 8, RDI
* 8, RBP
* 8, RSP
* 8,
218 R8
* 8, R9
* 8, R10
* 8, R11
* 8,
219 R12
* 8, R13
* 8, R14
* 8, R15
* 8,
220 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
221 DS
* 8, ES
* 8, FS
* 8, GS
* 8,
222 -1, -1, -1, -1, -1, -1, -1, -1,
223 -1, -1, -1, -1, -1, -1, -1, -1,
224 -1, -1, -1, -1, -1, -1, -1, -1,
226 -1, -1, -1, -1, -1, -1, -1, -1,
228 #ifdef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE
233 -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */
234 -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */
235 -1, -1, -1, -1, -1, -1, -1, -1, /* xmm16 ... xmm31 (AVX512) */
236 -1, -1, -1, -1, -1, -1, -1, -1,
237 -1, -1, -1, -1, -1, -1, -1, -1, /* ymm16 ... ymm31 (AVX512) */
238 -1, -1, -1, -1, -1, -1, -1, -1,
239 -1, -1, -1, -1, -1, -1, -1, -1, /* k0 ... k7 (AVX512) */
240 -1, -1, -1, -1, -1, -1, -1, -1, /* zmm0 ... zmm31 (AVX512) */
241 -1, -1, -1, -1, -1, -1, -1, -1,
242 -1, -1, -1, -1, -1, -1, -1, -1,
243 -1, -1, -1, -1, -1, -1, -1, -1,
247 #define X86_64_NUM_REGS (sizeof (x86_64_regmap) / sizeof (x86_64_regmap[0]))
248 #define X86_64_USER_REGS (GS + 1)
250 #else /* ! __x86_64__ */
252 /* Mapping between the general-purpose registers in `struct user'
253 format and GDB's register array layout. */
254 static /*const*/ int i386_regmap
[] =
256 EAX
* 4, ECX
* 4, EDX
* 4, EBX
* 4,
257 UESP
* 4, EBP
* 4, ESI
* 4, EDI
* 4,
258 EIP
* 4, EFL
* 4, CS
* 4, SS
* 4,
259 DS
* 4, ES
* 4, FS
* 4, GS
* 4
262 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
270 /* Returns true if the current inferior belongs to a x86-64 process,
274 is_64bit_tdesc (void)
276 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
278 return register_size (regcache
->tdesc
, 0) == 8;
284 /* Called by libthread_db. */
287 ps_get_thread_area (struct ps_prochandle
*ph
,
288 lwpid_t lwpid
, int idx
, void **base
)
291 int use_64bit
= is_64bit_tdesc ();
298 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_FS
) == 0)
302 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_GS
) == 0)
313 unsigned int desc
[4];
315 if (ptrace (PTRACE_GET_THREAD_AREA
, lwpid
,
316 (void *) (intptr_t) idx
, (unsigned long) &desc
) < 0)
319 /* Ensure we properly extend the value to 64-bits for x86_64. */
320 *base
= (void *) (uintptr_t) desc
[1];
325 /* Get the thread area address. This is used to recognize which
326 thread is which when tracing with the in-process agent library. We
327 don't read anything from the address, and treat it as opaque; it's
328 the address itself that we assume is unique per-thread. */
331 x86_target::low_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
334 int use_64bit
= is_64bit_tdesc ();
339 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_FS
) == 0)
341 *addr
= (CORE_ADDR
) (uintptr_t) base
;
350 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
351 struct thread_info
*thr
= get_lwp_thread (lwp
);
352 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
353 unsigned int desc
[4];
355 const int reg_thread_area
= 3; /* bits to scale down register value. */
358 collect_register_by_name (regcache
, "gs", &gs
);
360 idx
= gs
>> reg_thread_area
;
362 if (ptrace (PTRACE_GET_THREAD_AREA
,
364 (void *) (long) idx
, (unsigned long) &desc
) < 0)
375 x86_target::low_cannot_store_register (int regno
)
378 if (is_64bit_tdesc ())
382 return regno
>= I386_NUM_REGS
;
386 x86_target::low_cannot_fetch_register (int regno
)
389 if (is_64bit_tdesc ())
393 return regno
>= I386_NUM_REGS
;
397 x86_fill_gregset (struct regcache
*regcache
, void *buf
)
402 if (register_size (regcache
->tdesc
, 0) == 8)
404 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
405 if (x86_64_regmap
[i
] != -1)
406 collect_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
408 #ifndef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE
411 int lwpid
= lwpid_of (current_thread
);
413 collect_register_by_name (regcache
, "fs_base", &base
);
414 ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_SET_FS
);
416 collect_register_by_name (regcache
, "gs_base", &base
);
417 ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_SET_GS
);
424 /* 32-bit inferior registers need to be zero-extended.
425 Callers would read uninitialized memory otherwise. */
426 memset (buf
, 0x00, X86_64_USER_REGS
* 8);
429 for (i
= 0; i
< I386_NUM_REGS
; i
++)
430 collect_register (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
432 collect_register_by_name (regcache
, "orig_eax",
433 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
436 /* Sign extend EAX value to avoid potential syscall restart
439 See amd64_linux_collect_native_gregset() in gdb/amd64-linux-nat.c
440 for a detailed explanation. */
441 if (register_size (regcache
->tdesc
, 0) == 4)
443 void *ptr
= ((gdb_byte
*) buf
444 + i386_regmap
[find_regno (regcache
->tdesc
, "eax")]);
446 *(int64_t *) ptr
= *(int32_t *) ptr
;
452 x86_store_gregset (struct regcache
*regcache
, const void *buf
)
457 if (register_size (regcache
->tdesc
, 0) == 8)
459 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
460 if (x86_64_regmap
[i
] != -1)
461 supply_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
463 #ifndef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE
466 int lwpid
= lwpid_of (current_thread
);
468 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_FS
) == 0)
469 supply_register_by_name (regcache
, "fs_base", &base
);
471 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_GS
) == 0)
472 supply_register_by_name (regcache
, "gs_base", &base
);
479 for (i
= 0; i
< I386_NUM_REGS
; i
++)
480 supply_register (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
482 supply_register_by_name (regcache
, "orig_eax",
483 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
487 x86_fill_fpregset (struct regcache
*regcache
, void *buf
)
490 i387_cache_to_fxsave (regcache
, buf
);
492 i387_cache_to_fsave (regcache
, buf
);
497 x86_store_fpregset (struct regcache
*regcache
, const void *buf
)
500 i387_fxsave_to_cache (regcache
, buf
);
502 i387_fsave_to_cache (regcache
, buf
);
509 x86_fill_fpxregset (struct regcache
*regcache
, void *buf
)
511 i387_cache_to_fxsave (regcache
, buf
);
515 x86_store_fpxregset (struct regcache
*regcache
, const void *buf
)
517 i387_fxsave_to_cache (regcache
, buf
);
523 x86_fill_xstateregset (struct regcache
*regcache
, void *buf
)
525 i387_cache_to_xsave (regcache
, buf
);
529 x86_store_xstateregset (struct regcache
*regcache
, const void *buf
)
531 i387_xsave_to_cache (regcache
, buf
);
534 /* ??? The non-biarch i386 case stores all the i387 regs twice.
535 Once in i387_.*fsave.* and once in i387_.*fxsave.*.
536 This is, presumably, to handle the case where PTRACE_[GS]ETFPXREGS
537 doesn't work. IWBN to avoid the duplication in the case where it
538 does work. Maybe the arch_setup routine could check whether it works
539 and update the supported regsets accordingly. */
541 static struct regset_info x86_regsets
[] =
543 #ifdef HAVE_PTRACE_GETREGS
544 { PTRACE_GETREGS
, PTRACE_SETREGS
, 0, sizeof (elf_gregset_t
),
546 x86_fill_gregset
, x86_store_gregset
},
547 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_X86_XSTATE
, 0,
548 EXTENDED_REGS
, x86_fill_xstateregset
, x86_store_xstateregset
},
550 # ifdef HAVE_PTRACE_GETFPXREGS
551 { PTRACE_GETFPXREGS
, PTRACE_SETFPXREGS
, 0, sizeof (elf_fpxregset_t
),
553 x86_fill_fpxregset
, x86_store_fpxregset
},
556 { PTRACE_GETFPREGS
, PTRACE_SETFPREGS
, 0, sizeof (elf_fpregset_t
),
558 x86_fill_fpregset
, x86_store_fpregset
},
559 #endif /* HAVE_PTRACE_GETREGS */
564 x86_target::low_supports_breakpoints ()
570 x86_target::low_get_pc (regcache
*regcache
)
572 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
578 collect_register_by_name (regcache
, "rip", &pc
);
579 return (CORE_ADDR
) pc
;
585 collect_register_by_name (regcache
, "eip", &pc
);
586 return (CORE_ADDR
) pc
;
591 x86_target::low_set_pc (regcache
*regcache
, CORE_ADDR pc
)
593 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
599 supply_register_by_name (regcache
, "rip", &newpc
);
605 supply_register_by_name (regcache
, "eip", &newpc
);
610 x86_target::low_decr_pc_after_break ()
616 static const gdb_byte x86_breakpoint
[] = { 0xCC };
617 #define x86_breakpoint_len 1
620 x86_target::low_breakpoint_at (CORE_ADDR pc
)
624 read_memory (pc
, &c
, 1);
631 /* Low-level function vector. */
632 struct x86_dr_low_type x86_dr_low
=
634 x86_linux_dr_set_control
,
635 x86_linux_dr_set_addr
,
636 x86_linux_dr_get_addr
,
637 x86_linux_dr_get_status
,
638 x86_linux_dr_get_control
,
642 /* Breakpoint/Watchpoint support. */
645 x86_target::supports_z_point_type (char z_type
)
651 case Z_PACKET_WRITE_WP
:
652 case Z_PACKET_ACCESS_WP
:
660 x86_target::low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
661 int size
, raw_breakpoint
*bp
)
663 struct process_info
*proc
= current_process ();
667 case raw_bkpt_type_hw
:
668 case raw_bkpt_type_write_wp
:
669 case raw_bkpt_type_access_wp
:
671 enum target_hw_bp_type hw_type
672 = raw_bkpt_type_to_target_hw_bp_type (type
);
673 struct x86_debug_reg_state
*state
674 = &proc
->priv
->arch_private
->debug_reg_state
;
676 return x86_dr_insert_watchpoint (state
, hw_type
, addr
, size
);
686 x86_target::low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
687 int size
, raw_breakpoint
*bp
)
689 struct process_info
*proc
= current_process ();
693 case raw_bkpt_type_hw
:
694 case raw_bkpt_type_write_wp
:
695 case raw_bkpt_type_access_wp
:
697 enum target_hw_bp_type hw_type
698 = raw_bkpt_type_to_target_hw_bp_type (type
);
699 struct x86_debug_reg_state
*state
700 = &proc
->priv
->arch_private
->debug_reg_state
;
702 return x86_dr_remove_watchpoint (state
, hw_type
, addr
, size
);
711 x86_target::low_stopped_by_watchpoint ()
713 struct process_info
*proc
= current_process ();
714 return x86_dr_stopped_by_watchpoint (&proc
->priv
->arch_private
->debug_reg_state
);
718 x86_target::low_stopped_data_address ()
720 struct process_info
*proc
= current_process ();
722 if (x86_dr_stopped_data_address (&proc
->priv
->arch_private
->debug_reg_state
,
728 /* Called when a new process is created. */
731 x86_target::low_new_process ()
733 struct arch_process_info
*info
= XCNEW (struct arch_process_info
);
735 x86_low_init_dregs (&info
->debug_reg_state
);
740 /* Called when a process is being deleted. */
743 x86_target::low_delete_process (arch_process_info
*info
)
749 x86_target::low_new_thread (lwp_info
*lwp
)
751 /* This comes from nat/. */
752 x86_linux_new_thread (lwp
);
756 x86_target::low_delete_thread (arch_lwp_info
*alwp
)
758 /* This comes from nat/. */
759 x86_linux_delete_thread (alwp
);
762 /* Target routine for new_fork. */
765 x86_target::low_new_fork (process_info
*parent
, process_info
*child
)
767 /* These are allocated by linux_add_process. */
768 gdb_assert (parent
->priv
!= NULL
769 && parent
->priv
->arch_private
!= NULL
);
770 gdb_assert (child
->priv
!= NULL
771 && child
->priv
->arch_private
!= NULL
);
773 /* Linux kernel before 2.6.33 commit
774 72f674d203cd230426437cdcf7dd6f681dad8b0d
775 will inherit hardware debug registers from parent
776 on fork/vfork/clone. Newer Linux kernels create such tasks with
777 zeroed debug registers.
779 GDB core assumes the child inherits the watchpoints/hw
780 breakpoints of the parent, and will remove them all from the
781 forked off process. Copy the debug registers mirrors into the
782 new process so that all breakpoints and watchpoints can be
783 removed together. The debug registers mirror will become zeroed
784 in the end before detaching the forked off process, thus making
785 this compatible with older Linux kernels too. */
787 *child
->priv
->arch_private
= *parent
->priv
->arch_private
;
791 x86_target::low_prepare_to_resume (lwp_info
*lwp
)
793 /* This comes from nat/. */
794 x86_linux_prepare_to_resume (lwp
);
797 /* See nat/x86-dregs.h. */
799 struct x86_debug_reg_state
*
800 x86_debug_reg_state (pid_t pid
)
802 struct process_info
*proc
= find_process_pid (pid
);
804 return &proc
->priv
->arch_private
->debug_reg_state
;
807 /* When GDBSERVER is built as a 64-bit application on linux, the
808 PTRACE_GETSIGINFO data is always presented in 64-bit layout. Since
809 debugging a 32-bit inferior with a 64-bit GDBSERVER should look the same
810 as debugging it with a 32-bit GDBSERVER, we do the 32-bit <-> 64-bit
811 conversion in-place ourselves. */
813 /* Convert a ptrace/host siginfo object, into/from the siginfo in the
814 layout of the inferiors' architecture. Returns true if any
815 conversion was done; false otherwise. If DIRECTION is 1, then copy
816 from INF to PTRACE. If DIRECTION is 0, copy from PTRACE to
820 x86_target::low_siginfo_fixup (siginfo_t
*ptrace
, gdb_byte
*inf
, int direction
)
823 unsigned int machine
;
824 int tid
= lwpid_of (current_thread
);
825 int is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
827 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
828 if (!is_64bit_tdesc ())
829 return amd64_linux_siginfo_fixup_common (ptrace
, inf
, direction
,
831 /* No fixup for native x32 GDB. */
832 else if (!is_elf64
&& sizeof (void *) == 8)
833 return amd64_linux_siginfo_fixup_common (ptrace
, inf
, direction
,
842 /* Format of XSAVE extended state is:
846 sw_usable_bytes[464..511]
847 xstate_hdr_bytes[512..575]
852 Same memory layout will be used for the coredump NT_X86_XSTATE
853 representing the XSAVE extended state registers.
855 The first 8 bytes of the sw_usable_bytes[464..467] is the OS enabled
856 extended state mask, which is the same as the extended control register
857 0 (the XFEATURE_ENABLED_MASK register), XCR0. We can use this mask
858 together with the mask saved in the xstate_hdr_bytes to determine what
859 states the processor/OS supports and what state, used or initialized,
860 the process/thread is in. */
861 #define I386_LINUX_XSAVE_XCR0_OFFSET 464
863 /* Does the current host support the GETFPXREGS request? The header
864 file may or may not define it, and even if it is defined, the
865 kernel will return EIO if it's running on a pre-SSE processor. */
866 int have_ptrace_getfpxregs
=
867 #ifdef HAVE_PTRACE_GETFPXREGS
874 /* Get Linux/x86 target description from running target. */
876 static const struct target_desc
*
877 x86_linux_read_description (void)
879 unsigned int machine
;
883 static uint64_t xcr0
;
884 struct regset_info
*regset
;
886 tid
= lwpid_of (current_thread
);
888 is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
890 if (sizeof (void *) == 4)
893 error (_("Can't debug 64-bit process with 32-bit GDBserver"));
895 else if (machine
== EM_X86_64
)
896 error (_("Can't debug x86-64 process with 32-bit GDBserver"));
900 #if !defined __x86_64__ && defined HAVE_PTRACE_GETFPXREGS
901 if (machine
== EM_386
&& have_ptrace_getfpxregs
== -1)
903 elf_fpxregset_t fpxregs
;
905 if (ptrace (PTRACE_GETFPXREGS
, tid
, 0, (long) &fpxregs
) < 0)
907 have_ptrace_getfpxregs
= 0;
908 have_ptrace_getregset
= 0;
909 return i386_linux_read_description (X86_XSTATE_X87
);
912 have_ptrace_getfpxregs
= 1;
918 x86_xcr0
= X86_XSTATE_SSE_MASK
;
922 if (machine
== EM_X86_64
)
923 return tdesc_amd64_linux_no_xml
;
926 return tdesc_i386_linux_no_xml
;
929 if (have_ptrace_getregset
== -1)
931 uint64_t xstateregs
[(X86_XSTATE_SSE_SIZE
/ sizeof (uint64_t))];
934 iov
.iov_base
= xstateregs
;
935 iov
.iov_len
= sizeof (xstateregs
);
937 /* Check if PTRACE_GETREGSET works. */
938 if (ptrace (PTRACE_GETREGSET
, tid
,
939 (unsigned int) NT_X86_XSTATE
, (long) &iov
) < 0)
940 have_ptrace_getregset
= 0;
943 have_ptrace_getregset
= 1;
945 /* Get XCR0 from XSAVE extended state. */
946 xcr0
= xstateregs
[(I386_LINUX_XSAVE_XCR0_OFFSET
947 / sizeof (uint64_t))];
949 /* Use PTRACE_GETREGSET if it is available. */
950 for (regset
= x86_regsets
;
951 regset
->fill_function
!= NULL
; regset
++)
952 if (regset
->get_request
== PTRACE_GETREGSET
)
953 regset
->size
= X86_XSTATE_SIZE (xcr0
);
954 else if (regset
->type
!= GENERAL_REGS
)
959 /* Check the native XCR0 only if PTRACE_GETREGSET is available. */
960 xcr0_features
= (have_ptrace_getregset
961 && (xcr0
& X86_XSTATE_ALL_MASK
));
966 if (machine
== EM_X86_64
)
969 const target_desc
*tdesc
= NULL
;
973 tdesc
= amd64_linux_read_description (xcr0
& X86_XSTATE_ALL_MASK
,
978 tdesc
= amd64_linux_read_description (X86_XSTATE_SSE_MASK
, !is_elf64
);
984 const target_desc
*tdesc
= NULL
;
987 tdesc
= i386_linux_read_description (xcr0
& X86_XSTATE_ALL_MASK
);
990 tdesc
= i386_linux_read_description (X86_XSTATE_SSE
);
995 gdb_assert_not_reached ("failed to return tdesc");
998 /* Update all the target description of all processes; a new GDB
999 connected, and it may or not support xml target descriptions. */
1002 x86_target::update_xmltarget ()
1004 struct thread_info
*saved_thread
= current_thread
;
1006 /* Before changing the register cache's internal layout, flush the
1007 contents of the current valid caches back to the threads, and
1008 release the current regcache objects. */
1009 regcache_release ();
1011 for_each_process ([this] (process_info
*proc
) {
1012 int pid
= proc
->pid
;
1014 /* Look up any thread of this process. */
1015 current_thread
= find_any_thread_of_pid (pid
);
1020 current_thread
= saved_thread
;
1023 /* Process qSupported query, "xmlRegisters=". Update the buffer size for
1024 PTRACE_GETREGSET. */
1027 x86_target::process_qsupported (char **features
, int count
)
1031 /* Return if gdb doesn't support XML. If gdb sends "xmlRegisters="
1032 with "i386" in qSupported query, it supports x86 XML target
1035 for (i
= 0; i
< count
; i
++)
1037 const char *feature
= features
[i
];
1039 if (startswith (feature
, "xmlRegisters="))
1041 char *copy
= xstrdup (feature
+ 13);
1044 for (char *p
= strtok_r (copy
, ",", &saveptr
);
1046 p
= strtok_r (NULL
, ",", &saveptr
))
1048 if (strcmp (p
, "i386") == 0)
1058 update_xmltarget ();
1061 /* Common for x86/x86-64. */
1063 static struct regsets_info x86_regsets_info
=
1065 x86_regsets
, /* regsets */
1066 0, /* num_regsets */
1067 NULL
, /* disabled_regsets */
1071 static struct regs_info amd64_linux_regs_info
=
1073 NULL
, /* regset_bitmap */
1074 NULL
, /* usrregs_info */
1078 static struct usrregs_info i386_linux_usrregs_info
=
1084 static struct regs_info i386_linux_regs_info
=
1086 NULL
, /* regset_bitmap */
1087 &i386_linux_usrregs_info
,
1092 x86_target::get_regs_info ()
1095 if (is_64bit_tdesc ())
1096 return &amd64_linux_regs_info
;
1099 return &i386_linux_regs_info
;
1102 /* Initialize the target description for the architecture of the
1106 x86_target::low_arch_setup ()
1108 current_process ()->tdesc
= x86_linux_read_description ();
1111 /* Fill *SYSNO and *SYSRET with the syscall nr trapped and the syscall return
1112 code. This should only be called if LWP got a SYSCALL_SIGTRAP. */
1115 x86_get_syscall_trapinfo (struct regcache
*regcache
, int *sysno
)
1117 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
1123 collect_register_by_name (regcache
, "orig_rax", &l_sysno
);
1124 *sysno
= (int) l_sysno
;
1127 collect_register_by_name (regcache
, "orig_eax", sysno
);
1131 x86_target::supports_tracepoints ()
1137 append_insns (CORE_ADDR
*to
, size_t len
, const unsigned char *buf
)
1139 target_write_memory (*to
, buf
, len
);
1144 push_opcode (unsigned char *buf
, const char *op
)
1146 unsigned char *buf_org
= buf
;
1151 unsigned long ul
= strtoul (op
, &endptr
, 16);
1160 return buf
- buf_org
;
1165 /* Build a jump pad that saves registers and calls a collection
1166 function. Writes a jump instruction to the jump pad to
1167 JJUMPAD_INSN. The caller is responsible to write it in at the
1168 tracepoint address. */
1171 amd64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1172 CORE_ADDR collector
,
1175 CORE_ADDR
*jump_entry
,
1176 CORE_ADDR
*trampoline
,
1177 ULONGEST
*trampoline_size
,
1178 unsigned char *jjump_pad_insn
,
1179 ULONGEST
*jjump_pad_insn_size
,
1180 CORE_ADDR
*adjusted_insn_addr
,
1181 CORE_ADDR
*adjusted_insn_addr_end
,
1184 unsigned char buf
[40];
1188 CORE_ADDR buildaddr
= *jump_entry
;
1190 /* Build the jump pad. */
1192 /* First, do tracepoint data collection. Save registers. */
1194 /* Need to ensure stack pointer saved first. */
1195 buf
[i
++] = 0x54; /* push %rsp */
1196 buf
[i
++] = 0x55; /* push %rbp */
1197 buf
[i
++] = 0x57; /* push %rdi */
1198 buf
[i
++] = 0x56; /* push %rsi */
1199 buf
[i
++] = 0x52; /* push %rdx */
1200 buf
[i
++] = 0x51; /* push %rcx */
1201 buf
[i
++] = 0x53; /* push %rbx */
1202 buf
[i
++] = 0x50; /* push %rax */
1203 buf
[i
++] = 0x41; buf
[i
++] = 0x57; /* push %r15 */
1204 buf
[i
++] = 0x41; buf
[i
++] = 0x56; /* push %r14 */
1205 buf
[i
++] = 0x41; buf
[i
++] = 0x55; /* push %r13 */
1206 buf
[i
++] = 0x41; buf
[i
++] = 0x54; /* push %r12 */
1207 buf
[i
++] = 0x41; buf
[i
++] = 0x53; /* push %r11 */
1208 buf
[i
++] = 0x41; buf
[i
++] = 0x52; /* push %r10 */
1209 buf
[i
++] = 0x41; buf
[i
++] = 0x51; /* push %r9 */
1210 buf
[i
++] = 0x41; buf
[i
++] = 0x50; /* push %r8 */
1211 buf
[i
++] = 0x9c; /* pushfq */
1212 buf
[i
++] = 0x48; /* movabs <addr>,%rdi */
1214 memcpy (buf
+ i
, &tpaddr
, 8);
1216 buf
[i
++] = 0x57; /* push %rdi */
1217 append_insns (&buildaddr
, i
, buf
);
1219 /* Stack space for the collecting_t object. */
1221 i
+= push_opcode (&buf
[i
], "48 83 ec 18"); /* sub $0x18,%rsp */
1222 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov <tpoint>,%rax */
1223 memcpy (buf
+ i
, &tpoint
, 8);
1225 i
+= push_opcode (&buf
[i
], "48 89 04 24"); /* mov %rax,(%rsp) */
1226 i
+= push_opcode (&buf
[i
],
1227 "64 48 8b 04 25 00 00 00 00"); /* mov %fs:0x0,%rax */
1228 i
+= push_opcode (&buf
[i
], "48 89 44 24 08"); /* mov %rax,0x8(%rsp) */
1229 append_insns (&buildaddr
, i
, buf
);
1233 i
+= push_opcode (&buf
[i
], "48 be"); /* movl <lockaddr>,%rsi */
1234 memcpy (&buf
[i
], (void *) &lockaddr
, 8);
1236 i
+= push_opcode (&buf
[i
], "48 89 e1"); /* mov %rsp,%rcx */
1237 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1238 i
+= push_opcode (&buf
[i
], "f0 48 0f b1 0e"); /* lock cmpxchg %rcx,(%rsi) */
1239 i
+= push_opcode (&buf
[i
], "48 85 c0"); /* test %rax,%rax */
1240 i
+= push_opcode (&buf
[i
], "75 f4"); /* jne <again> */
1241 append_insns (&buildaddr
, i
, buf
);
1243 /* Set up the gdb_collect call. */
1244 /* At this point, (stack pointer + 0x18) is the base of our saved
1248 i
+= push_opcode (&buf
[i
], "48 89 e6"); /* mov %rsp,%rsi */
1249 i
+= push_opcode (&buf
[i
], "48 83 c6 18"); /* add $0x18,%rsi */
1251 /* tpoint address may be 64-bit wide. */
1252 i
+= push_opcode (&buf
[i
], "48 bf"); /* movl <addr>,%rdi */
1253 memcpy (buf
+ i
, &tpoint
, 8);
1255 append_insns (&buildaddr
, i
, buf
);
1257 /* The collector function being in the shared library, may be
1258 >31-bits away off the jump pad. */
1260 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov $collector,%rax */
1261 memcpy (buf
+ i
, &collector
, 8);
1263 i
+= push_opcode (&buf
[i
], "ff d0"); /* callq *%rax */
1264 append_insns (&buildaddr
, i
, buf
);
1266 /* Clear the spin-lock. */
1268 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1269 i
+= push_opcode (&buf
[i
], "48 a3"); /* mov %rax, lockaddr */
1270 memcpy (buf
+ i
, &lockaddr
, 8);
1272 append_insns (&buildaddr
, i
, buf
);
1274 /* Remove stack that had been used for the collect_t object. */
1276 i
+= push_opcode (&buf
[i
], "48 83 c4 18"); /* add $0x18,%rsp */
1277 append_insns (&buildaddr
, i
, buf
);
1279 /* Restore register state. */
1281 buf
[i
++] = 0x48; /* add $0x8,%rsp */
1285 buf
[i
++] = 0x9d; /* popfq */
1286 buf
[i
++] = 0x41; buf
[i
++] = 0x58; /* pop %r8 */
1287 buf
[i
++] = 0x41; buf
[i
++] = 0x59; /* pop %r9 */
1288 buf
[i
++] = 0x41; buf
[i
++] = 0x5a; /* pop %r10 */
1289 buf
[i
++] = 0x41; buf
[i
++] = 0x5b; /* pop %r11 */
1290 buf
[i
++] = 0x41; buf
[i
++] = 0x5c; /* pop %r12 */
1291 buf
[i
++] = 0x41; buf
[i
++] = 0x5d; /* pop %r13 */
1292 buf
[i
++] = 0x41; buf
[i
++] = 0x5e; /* pop %r14 */
1293 buf
[i
++] = 0x41; buf
[i
++] = 0x5f; /* pop %r15 */
1294 buf
[i
++] = 0x58; /* pop %rax */
1295 buf
[i
++] = 0x5b; /* pop %rbx */
1296 buf
[i
++] = 0x59; /* pop %rcx */
1297 buf
[i
++] = 0x5a; /* pop %rdx */
1298 buf
[i
++] = 0x5e; /* pop %rsi */
1299 buf
[i
++] = 0x5f; /* pop %rdi */
1300 buf
[i
++] = 0x5d; /* pop %rbp */
1301 buf
[i
++] = 0x5c; /* pop %rsp */
1302 append_insns (&buildaddr
, i
, buf
);
1304 /* Now, adjust the original instruction to execute in the jump
1306 *adjusted_insn_addr
= buildaddr
;
1307 relocate_instruction (&buildaddr
, tpaddr
);
1308 *adjusted_insn_addr_end
= buildaddr
;
1310 /* Finally, write a jump back to the program. */
1312 loffset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1313 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1316 "E.Jump back from jump pad too far from tracepoint "
1317 "(offset 0x%" PRIx64
" > int32).", loffset
);
1321 offset
= (int) loffset
;
1322 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1323 memcpy (buf
+ 1, &offset
, 4);
1324 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1326 /* The jump pad is now built. Wire in a jump to our jump pad. This
1327 is always done last (by our caller actually), so that we can
1328 install fast tracepoints with threads running. This relies on
1329 the agent's atomic write support. */
1330 loffset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1331 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1334 "E.Jump pad too far from tracepoint "
1335 "(offset 0x%" PRIx64
" > int32).", loffset
);
1339 offset
= (int) loffset
;
1341 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1342 memcpy (buf
+ 1, &offset
, 4);
1343 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1344 *jjump_pad_insn_size
= sizeof (jump_insn
);
1346 /* Return the end address of our pad. */
1347 *jump_entry
= buildaddr
;
1352 #endif /* __x86_64__ */
1354 /* Build a jump pad that saves registers and calls a collection
1355 function. Writes a jump instruction to the jump pad to
1356 JJUMPAD_INSN. The caller is responsible to write it in at the
1357 tracepoint address. */
1360 i386_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1361 CORE_ADDR collector
,
1364 CORE_ADDR
*jump_entry
,
1365 CORE_ADDR
*trampoline
,
1366 ULONGEST
*trampoline_size
,
1367 unsigned char *jjump_pad_insn
,
1368 ULONGEST
*jjump_pad_insn_size
,
1369 CORE_ADDR
*adjusted_insn_addr
,
1370 CORE_ADDR
*adjusted_insn_addr_end
,
1373 unsigned char buf
[0x100];
1375 CORE_ADDR buildaddr
= *jump_entry
;
1377 /* Build the jump pad. */
1379 /* First, do tracepoint data collection. Save registers. */
1381 buf
[i
++] = 0x60; /* pushad */
1382 buf
[i
++] = 0x68; /* push tpaddr aka $pc */
1383 *((int *)(buf
+ i
)) = (int) tpaddr
;
1385 buf
[i
++] = 0x9c; /* pushf */
1386 buf
[i
++] = 0x1e; /* push %ds */
1387 buf
[i
++] = 0x06; /* push %es */
1388 buf
[i
++] = 0x0f; /* push %fs */
1390 buf
[i
++] = 0x0f; /* push %gs */
1392 buf
[i
++] = 0x16; /* push %ss */
1393 buf
[i
++] = 0x0e; /* push %cs */
1394 append_insns (&buildaddr
, i
, buf
);
1396 /* Stack space for the collecting_t object. */
1398 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1400 /* Build the object. */
1401 i
+= push_opcode (&buf
[i
], "b8"); /* mov <tpoint>,%eax */
1402 memcpy (buf
+ i
, &tpoint
, 4);
1404 i
+= push_opcode (&buf
[i
], "89 04 24"); /* mov %eax,(%esp) */
1406 i
+= push_opcode (&buf
[i
], "65 a1 00 00 00 00"); /* mov %gs:0x0,%eax */
1407 i
+= push_opcode (&buf
[i
], "89 44 24 04"); /* mov %eax,0x4(%esp) */
1408 append_insns (&buildaddr
, i
, buf
);
1410 /* spin-lock. Note this is using cmpxchg, which leaves i386 behind.
1411 If we cared for it, this could be using xchg alternatively. */
1414 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1415 i
+= push_opcode (&buf
[i
], "f0 0f b1 25"); /* lock cmpxchg
1417 memcpy (&buf
[i
], (void *) &lockaddr
, 4);
1419 i
+= push_opcode (&buf
[i
], "85 c0"); /* test %eax,%eax */
1420 i
+= push_opcode (&buf
[i
], "75 f2"); /* jne <again> */
1421 append_insns (&buildaddr
, i
, buf
);
1424 /* Set up arguments to the gdb_collect call. */
1426 i
+= push_opcode (&buf
[i
], "89 e0"); /* mov %esp,%eax */
1427 i
+= push_opcode (&buf
[i
], "83 c0 08"); /* add $0x08,%eax */
1428 i
+= push_opcode (&buf
[i
], "89 44 24 fc"); /* mov %eax,-0x4(%esp) */
1429 append_insns (&buildaddr
, i
, buf
);
1432 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1433 append_insns (&buildaddr
, i
, buf
);
1436 i
+= push_opcode (&buf
[i
], "c7 04 24"); /* movl <addr>,(%esp) */
1437 memcpy (&buf
[i
], (void *) &tpoint
, 4);
1439 append_insns (&buildaddr
, i
, buf
);
1441 buf
[0] = 0xe8; /* call <reladdr> */
1442 offset
= collector
- (buildaddr
+ sizeof (jump_insn
));
1443 memcpy (buf
+ 1, &offset
, 4);
1444 append_insns (&buildaddr
, 5, buf
);
1445 /* Clean up after the call. */
1446 buf
[0] = 0x83; /* add $0x8,%esp */
1449 append_insns (&buildaddr
, 3, buf
);
1452 /* Clear the spin-lock. This would need the LOCK prefix on older
1455 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1456 i
+= push_opcode (&buf
[i
], "a3"); /* mov %eax, lockaddr */
1457 memcpy (buf
+ i
, &lockaddr
, 4);
1459 append_insns (&buildaddr
, i
, buf
);
1462 /* Remove stack that had been used for the collect_t object. */
1464 i
+= push_opcode (&buf
[i
], "83 c4 08"); /* add $0x08,%esp */
1465 append_insns (&buildaddr
, i
, buf
);
1468 buf
[i
++] = 0x83; /* add $0x4,%esp (no pop of %cs, assume unchanged) */
1471 buf
[i
++] = 0x17; /* pop %ss */
1472 buf
[i
++] = 0x0f; /* pop %gs */
1474 buf
[i
++] = 0x0f; /* pop %fs */
1476 buf
[i
++] = 0x07; /* pop %es */
1477 buf
[i
++] = 0x1f; /* pop %ds */
1478 buf
[i
++] = 0x9d; /* popf */
1479 buf
[i
++] = 0x83; /* add $0x4,%esp (pop of tpaddr aka $pc) */
1482 buf
[i
++] = 0x61; /* popad */
1483 append_insns (&buildaddr
, i
, buf
);
1485 /* Now, adjust the original instruction to execute in the jump
1487 *adjusted_insn_addr
= buildaddr
;
1488 relocate_instruction (&buildaddr
, tpaddr
);
1489 *adjusted_insn_addr_end
= buildaddr
;
1491 /* Write the jump back to the program. */
1492 offset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1493 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1494 memcpy (buf
+ 1, &offset
, 4);
1495 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1497 /* The jump pad is now built. Wire in a jump to our jump pad. This
1498 is always done last (by our caller actually), so that we can
1499 install fast tracepoints with threads running. This relies on
1500 the agent's atomic write support. */
1503 /* Create a trampoline. */
1504 *trampoline_size
= sizeof (jump_insn
);
1505 if (!claim_trampoline_space (*trampoline_size
, trampoline
))
1507 /* No trampoline space available. */
1509 "E.Cannot allocate trampoline space needed for fast "
1510 "tracepoints on 4-byte instructions.");
1514 offset
= *jump_entry
- (*trampoline
+ sizeof (jump_insn
));
1515 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1516 memcpy (buf
+ 1, &offset
, 4);
1517 target_write_memory (*trampoline
, buf
, sizeof (jump_insn
));
1519 /* Use a 16-bit relative jump instruction to jump to the trampoline. */
1520 offset
= (*trampoline
- (tpaddr
+ sizeof (small_jump_insn
))) & 0xffff;
1521 memcpy (buf
, small_jump_insn
, sizeof (small_jump_insn
));
1522 memcpy (buf
+ 2, &offset
, 2);
1523 memcpy (jjump_pad_insn
, buf
, sizeof (small_jump_insn
));
1524 *jjump_pad_insn_size
= sizeof (small_jump_insn
);
1528 /* Else use a 32-bit relative jump instruction. */
1529 offset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1530 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1531 memcpy (buf
+ 1, &offset
, 4);
1532 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1533 *jjump_pad_insn_size
= sizeof (jump_insn
);
1536 /* Return the end address of our pad. */
1537 *jump_entry
= buildaddr
;
1543 x86_target::supports_fast_tracepoints ()
1549 x86_target::install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
,
1551 CORE_ADDR collector
,
1554 CORE_ADDR
*jump_entry
,
1555 CORE_ADDR
*trampoline
,
1556 ULONGEST
*trampoline_size
,
1557 unsigned char *jjump_pad_insn
,
1558 ULONGEST
*jjump_pad_insn_size
,
1559 CORE_ADDR
*adjusted_insn_addr
,
1560 CORE_ADDR
*adjusted_insn_addr_end
,
1564 if (is_64bit_tdesc ())
1565 return amd64_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1566 collector
, lockaddr
,
1567 orig_size
, jump_entry
,
1568 trampoline
, trampoline_size
,
1570 jjump_pad_insn_size
,
1572 adjusted_insn_addr_end
,
1576 return i386_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1577 collector
, lockaddr
,
1578 orig_size
, jump_entry
,
1579 trampoline
, trampoline_size
,
1581 jjump_pad_insn_size
,
1583 adjusted_insn_addr_end
,
1587 /* Return the minimum instruction length for fast tracepoints on x86/x86-64
1591 x86_target::get_min_fast_tracepoint_insn_len ()
1593 static int warned_about_fast_tracepoints
= 0;
1596 /* On x86-64, 5-byte jump instructions with a 4-byte offset are always
1597 used for fast tracepoints. */
1598 if (is_64bit_tdesc ())
1602 if (agent_loaded_p ())
1604 char errbuf
[IPA_BUFSIZ
];
1608 /* On x86, if trampolines are available, then 4-byte jump instructions
1609 with a 2-byte offset may be used, otherwise 5-byte jump instructions
1610 with a 4-byte offset are used instead. */
1611 if (have_fast_tracepoint_trampoline_buffer (errbuf
))
1615 /* GDB has no channel to explain to user why a shorter fast
1616 tracepoint is not possible, but at least make GDBserver
1617 mention that something has gone awry. */
1618 if (!warned_about_fast_tracepoints
)
1620 warning ("4-byte fast tracepoints not available; %s", errbuf
);
1621 warned_about_fast_tracepoints
= 1;
1628 /* Indicate that the minimum length is currently unknown since the IPA
1629 has not loaded yet. */
1635 add_insns (unsigned char *start
, int len
)
1637 CORE_ADDR buildaddr
= current_insn_ptr
;
1640 debug_printf ("Adding %d bytes of insn at %s\n",
1641 len
, paddress (buildaddr
));
1643 append_insns (&buildaddr
, len
, start
);
1644 current_insn_ptr
= buildaddr
;
1647 /* Our general strategy for emitting code is to avoid specifying raw
1648 bytes whenever possible, and instead copy a block of inline asm
1649 that is embedded in the function. This is a little messy, because
1650 we need to keep the compiler from discarding what looks like dead
1651 code, plus suppress various warnings. */
1653 #define EMIT_ASM(NAME, INSNS) \
1656 extern unsigned char start_ ## NAME, end_ ## NAME; \
1657 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1658 __asm__ ("jmp end_" #NAME "\n" \
1659 "\t" "start_" #NAME ":" \
1661 "\t" "end_" #NAME ":"); \
1666 #define EMIT_ASM32(NAME,INSNS) \
1669 extern unsigned char start_ ## NAME, end_ ## NAME; \
1670 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1671 __asm__ (".code32\n" \
1672 "\t" "jmp end_" #NAME "\n" \
1673 "\t" "start_" #NAME ":\n" \
1675 "\t" "end_" #NAME ":\n" \
1681 #define EMIT_ASM32(NAME,INSNS) EMIT_ASM(NAME,INSNS)
1688 amd64_emit_prologue (void)
1690 EMIT_ASM (amd64_prologue
,
1692 "movq %rsp,%rbp\n\t"
1693 "sub $0x20,%rsp\n\t"
1694 "movq %rdi,-8(%rbp)\n\t"
1695 "movq %rsi,-16(%rbp)");
1700 amd64_emit_epilogue (void)
1702 EMIT_ASM (amd64_epilogue
,
1703 "movq -16(%rbp),%rdi\n\t"
1704 "movq %rax,(%rdi)\n\t"
1711 amd64_emit_add (void)
1713 EMIT_ASM (amd64_add
,
1714 "add (%rsp),%rax\n\t"
1715 "lea 0x8(%rsp),%rsp");
1719 amd64_emit_sub (void)
1721 EMIT_ASM (amd64_sub
,
1722 "sub %rax,(%rsp)\n\t"
1727 amd64_emit_mul (void)
1733 amd64_emit_lsh (void)
1739 amd64_emit_rsh_signed (void)
1745 amd64_emit_rsh_unsigned (void)
1751 amd64_emit_ext (int arg
)
1756 EMIT_ASM (amd64_ext_8
,
1762 EMIT_ASM (amd64_ext_16
,
1767 EMIT_ASM (amd64_ext_32
,
1776 amd64_emit_log_not (void)
1778 EMIT_ASM (amd64_log_not
,
1779 "test %rax,%rax\n\t"
1785 amd64_emit_bit_and (void)
1787 EMIT_ASM (amd64_and
,
1788 "and (%rsp),%rax\n\t"
1789 "lea 0x8(%rsp),%rsp");
1793 amd64_emit_bit_or (void)
1796 "or (%rsp),%rax\n\t"
1797 "lea 0x8(%rsp),%rsp");
1801 amd64_emit_bit_xor (void)
1803 EMIT_ASM (amd64_xor
,
1804 "xor (%rsp),%rax\n\t"
1805 "lea 0x8(%rsp),%rsp");
1809 amd64_emit_bit_not (void)
1811 EMIT_ASM (amd64_bit_not
,
1812 "xorq $0xffffffffffffffff,%rax");
1816 amd64_emit_equal (void)
1818 EMIT_ASM (amd64_equal
,
1819 "cmp %rax,(%rsp)\n\t"
1820 "je .Lamd64_equal_true\n\t"
1822 "jmp .Lamd64_equal_end\n\t"
1823 ".Lamd64_equal_true:\n\t"
1825 ".Lamd64_equal_end:\n\t"
1826 "lea 0x8(%rsp),%rsp");
1830 amd64_emit_less_signed (void)
1832 EMIT_ASM (amd64_less_signed
,
1833 "cmp %rax,(%rsp)\n\t"
1834 "jl .Lamd64_less_signed_true\n\t"
1836 "jmp .Lamd64_less_signed_end\n\t"
1837 ".Lamd64_less_signed_true:\n\t"
1839 ".Lamd64_less_signed_end:\n\t"
1840 "lea 0x8(%rsp),%rsp");
1844 amd64_emit_less_unsigned (void)
1846 EMIT_ASM (amd64_less_unsigned
,
1847 "cmp %rax,(%rsp)\n\t"
1848 "jb .Lamd64_less_unsigned_true\n\t"
1850 "jmp .Lamd64_less_unsigned_end\n\t"
1851 ".Lamd64_less_unsigned_true:\n\t"
1853 ".Lamd64_less_unsigned_end:\n\t"
1854 "lea 0x8(%rsp),%rsp");
1858 amd64_emit_ref (int size
)
1863 EMIT_ASM (amd64_ref1
,
1867 EMIT_ASM (amd64_ref2
,
1871 EMIT_ASM (amd64_ref4
,
1872 "movl (%rax),%eax");
1875 EMIT_ASM (amd64_ref8
,
1876 "movq (%rax),%rax");
1882 amd64_emit_if_goto (int *offset_p
, int *size_p
)
1884 EMIT_ASM (amd64_if_goto
,
1888 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
1896 amd64_emit_goto (int *offset_p
, int *size_p
)
1898 EMIT_ASM (amd64_goto
,
1899 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
1907 amd64_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
1909 int diff
= (to
- (from
+ size
));
1910 unsigned char buf
[sizeof (int)];
1918 memcpy (buf
, &diff
, sizeof (int));
1919 target_write_memory (from
, buf
, sizeof (int));
1923 amd64_emit_const (LONGEST num
)
1925 unsigned char buf
[16];
1927 CORE_ADDR buildaddr
= current_insn_ptr
;
1930 buf
[i
++] = 0x48; buf
[i
++] = 0xb8; /* mov $<n>,%rax */
1931 memcpy (&buf
[i
], &num
, sizeof (num
));
1933 append_insns (&buildaddr
, i
, buf
);
1934 current_insn_ptr
= buildaddr
;
1938 amd64_emit_call (CORE_ADDR fn
)
1940 unsigned char buf
[16];
1942 CORE_ADDR buildaddr
;
1945 /* The destination function being in the shared library, may be
1946 >31-bits away off the compiled code pad. */
1948 buildaddr
= current_insn_ptr
;
1950 offset64
= fn
- (buildaddr
+ 1 /* call op */ + 4 /* 32-bit offset */);
1954 if (offset64
> INT_MAX
|| offset64
< INT_MIN
)
1956 /* Offset is too large for a call. Use callq, but that requires
1957 a register, so avoid it if possible. Use r10, since it is
1958 call-clobbered, we don't have to push/pop it. */
1959 buf
[i
++] = 0x48; /* mov $fn,%r10 */
1961 memcpy (buf
+ i
, &fn
, 8);
1963 buf
[i
++] = 0xff; /* callq *%r10 */
1968 int offset32
= offset64
; /* we know we can't overflow here. */
1970 buf
[i
++] = 0xe8; /* call <reladdr> */
1971 memcpy (buf
+ i
, &offset32
, 4);
1975 append_insns (&buildaddr
, i
, buf
);
1976 current_insn_ptr
= buildaddr
;
1980 amd64_emit_reg (int reg
)
1982 unsigned char buf
[16];
1984 CORE_ADDR buildaddr
;
1986 /* Assume raw_regs is still in %rdi. */
1987 buildaddr
= current_insn_ptr
;
1989 buf
[i
++] = 0xbe; /* mov $<n>,%esi */
1990 memcpy (&buf
[i
], ®
, sizeof (reg
));
1992 append_insns (&buildaddr
, i
, buf
);
1993 current_insn_ptr
= buildaddr
;
1994 amd64_emit_call (get_raw_reg_func_addr ());
1998 amd64_emit_pop (void)
2000 EMIT_ASM (amd64_pop
,
2005 amd64_emit_stack_flush (void)
2007 EMIT_ASM (amd64_stack_flush
,
2012 amd64_emit_zero_ext (int arg
)
2017 EMIT_ASM (amd64_zero_ext_8
,
2021 EMIT_ASM (amd64_zero_ext_16
,
2022 "and $0xffff,%rax");
2025 EMIT_ASM (amd64_zero_ext_32
,
2026 "mov $0xffffffff,%rcx\n\t"
2035 amd64_emit_swap (void)
2037 EMIT_ASM (amd64_swap
,
2044 amd64_emit_stack_adjust (int n
)
2046 unsigned char buf
[16];
2048 CORE_ADDR buildaddr
= current_insn_ptr
;
2051 buf
[i
++] = 0x48; /* lea $<n>(%rsp),%rsp */
2055 /* This only handles adjustments up to 16, but we don't expect any more. */
2057 append_insns (&buildaddr
, i
, buf
);
2058 current_insn_ptr
= buildaddr
;
2061 /* FN's prototype is `LONGEST(*fn)(int)'. */
2064 amd64_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2066 unsigned char buf
[16];
2068 CORE_ADDR buildaddr
;
2070 buildaddr
= current_insn_ptr
;
2072 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
2073 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2075 append_insns (&buildaddr
, i
, buf
);
2076 current_insn_ptr
= buildaddr
;
2077 amd64_emit_call (fn
);
2080 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
2083 amd64_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2085 unsigned char buf
[16];
2087 CORE_ADDR buildaddr
;
2089 buildaddr
= current_insn_ptr
;
2091 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
2092 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2094 append_insns (&buildaddr
, i
, buf
);
2095 current_insn_ptr
= buildaddr
;
2096 EMIT_ASM (amd64_void_call_2_a
,
2097 /* Save away a copy of the stack top. */
2099 /* Also pass top as the second argument. */
2101 amd64_emit_call (fn
);
2102 EMIT_ASM (amd64_void_call_2_b
,
2103 /* Restore the stack top, %rax may have been trashed. */
2108 amd64_emit_eq_goto (int *offset_p
, int *size_p
)
2111 "cmp %rax,(%rsp)\n\t"
2112 "jne .Lamd64_eq_fallthru\n\t"
2113 "lea 0x8(%rsp),%rsp\n\t"
2115 /* jmp, but don't trust the assembler to choose the right jump */
2116 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2117 ".Lamd64_eq_fallthru:\n\t"
2118 "lea 0x8(%rsp),%rsp\n\t"
2128 amd64_emit_ne_goto (int *offset_p
, int *size_p
)
2131 "cmp %rax,(%rsp)\n\t"
2132 "je .Lamd64_ne_fallthru\n\t"
2133 "lea 0x8(%rsp),%rsp\n\t"
2135 /* jmp, but don't trust the assembler to choose the right jump */
2136 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2137 ".Lamd64_ne_fallthru:\n\t"
2138 "lea 0x8(%rsp),%rsp\n\t"
2148 amd64_emit_lt_goto (int *offset_p
, int *size_p
)
2151 "cmp %rax,(%rsp)\n\t"
2152 "jnl .Lamd64_lt_fallthru\n\t"
2153 "lea 0x8(%rsp),%rsp\n\t"
2155 /* jmp, but don't trust the assembler to choose the right jump */
2156 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2157 ".Lamd64_lt_fallthru:\n\t"
2158 "lea 0x8(%rsp),%rsp\n\t"
2168 amd64_emit_le_goto (int *offset_p
, int *size_p
)
2171 "cmp %rax,(%rsp)\n\t"
2172 "jnle .Lamd64_le_fallthru\n\t"
2173 "lea 0x8(%rsp),%rsp\n\t"
2175 /* jmp, but don't trust the assembler to choose the right jump */
2176 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2177 ".Lamd64_le_fallthru:\n\t"
2178 "lea 0x8(%rsp),%rsp\n\t"
2188 amd64_emit_gt_goto (int *offset_p
, int *size_p
)
2191 "cmp %rax,(%rsp)\n\t"
2192 "jng .Lamd64_gt_fallthru\n\t"
2193 "lea 0x8(%rsp),%rsp\n\t"
2195 /* jmp, but don't trust the assembler to choose the right jump */
2196 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2197 ".Lamd64_gt_fallthru:\n\t"
2198 "lea 0x8(%rsp),%rsp\n\t"
2208 amd64_emit_ge_goto (int *offset_p
, int *size_p
)
2211 "cmp %rax,(%rsp)\n\t"
2212 "jnge .Lamd64_ge_fallthru\n\t"
2213 ".Lamd64_ge_jump:\n\t"
2214 "lea 0x8(%rsp),%rsp\n\t"
2216 /* jmp, but don't trust the assembler to choose the right jump */
2217 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2218 ".Lamd64_ge_fallthru:\n\t"
2219 "lea 0x8(%rsp),%rsp\n\t"
2228 struct emit_ops amd64_emit_ops
=
2230 amd64_emit_prologue
,
2231 amd64_emit_epilogue
,
2236 amd64_emit_rsh_signed
,
2237 amd64_emit_rsh_unsigned
,
2245 amd64_emit_less_signed
,
2246 amd64_emit_less_unsigned
,
2250 amd64_write_goto_address
,
2255 amd64_emit_stack_flush
,
2256 amd64_emit_zero_ext
,
2258 amd64_emit_stack_adjust
,
2259 amd64_emit_int_call_1
,
2260 amd64_emit_void_call_2
,
2269 #endif /* __x86_64__ */
2272 i386_emit_prologue (void)
2274 EMIT_ASM32 (i386_prologue
,
2278 /* At this point, the raw regs base address is at 8(%ebp), and the
2279 value pointer is at 12(%ebp). */
2283 i386_emit_epilogue (void)
2285 EMIT_ASM32 (i386_epilogue
,
2286 "mov 12(%ebp),%ecx\n\t"
2287 "mov %eax,(%ecx)\n\t"
2288 "mov %ebx,0x4(%ecx)\n\t"
2296 i386_emit_add (void)
2298 EMIT_ASM32 (i386_add
,
2299 "add (%esp),%eax\n\t"
2300 "adc 0x4(%esp),%ebx\n\t"
2301 "lea 0x8(%esp),%esp");
2305 i386_emit_sub (void)
2307 EMIT_ASM32 (i386_sub
,
2308 "subl %eax,(%esp)\n\t"
2309 "sbbl %ebx,4(%esp)\n\t"
2315 i386_emit_mul (void)
2321 i386_emit_lsh (void)
2327 i386_emit_rsh_signed (void)
2333 i386_emit_rsh_unsigned (void)
2339 i386_emit_ext (int arg
)
2344 EMIT_ASM32 (i386_ext_8
,
2347 "movl %eax,%ebx\n\t"
2351 EMIT_ASM32 (i386_ext_16
,
2353 "movl %eax,%ebx\n\t"
2357 EMIT_ASM32 (i386_ext_32
,
2358 "movl %eax,%ebx\n\t"
2367 i386_emit_log_not (void)
2369 EMIT_ASM32 (i386_log_not
,
2371 "test %eax,%eax\n\t"
2378 i386_emit_bit_and (void)
2380 EMIT_ASM32 (i386_and
,
2381 "and (%esp),%eax\n\t"
2382 "and 0x4(%esp),%ebx\n\t"
2383 "lea 0x8(%esp),%esp");
2387 i386_emit_bit_or (void)
2389 EMIT_ASM32 (i386_or
,
2390 "or (%esp),%eax\n\t"
2391 "or 0x4(%esp),%ebx\n\t"
2392 "lea 0x8(%esp),%esp");
2396 i386_emit_bit_xor (void)
2398 EMIT_ASM32 (i386_xor
,
2399 "xor (%esp),%eax\n\t"
2400 "xor 0x4(%esp),%ebx\n\t"
2401 "lea 0x8(%esp),%esp");
2405 i386_emit_bit_not (void)
2407 EMIT_ASM32 (i386_bit_not
,
2408 "xor $0xffffffff,%eax\n\t"
2409 "xor $0xffffffff,%ebx\n\t");
2413 i386_emit_equal (void)
2415 EMIT_ASM32 (i386_equal
,
2416 "cmpl %ebx,4(%esp)\n\t"
2417 "jne .Li386_equal_false\n\t"
2418 "cmpl %eax,(%esp)\n\t"
2419 "je .Li386_equal_true\n\t"
2420 ".Li386_equal_false:\n\t"
2422 "jmp .Li386_equal_end\n\t"
2423 ".Li386_equal_true:\n\t"
2425 ".Li386_equal_end:\n\t"
2427 "lea 0x8(%esp),%esp");
2431 i386_emit_less_signed (void)
2433 EMIT_ASM32 (i386_less_signed
,
2434 "cmpl %ebx,4(%esp)\n\t"
2435 "jl .Li386_less_signed_true\n\t"
2436 "jne .Li386_less_signed_false\n\t"
2437 "cmpl %eax,(%esp)\n\t"
2438 "jl .Li386_less_signed_true\n\t"
2439 ".Li386_less_signed_false:\n\t"
2441 "jmp .Li386_less_signed_end\n\t"
2442 ".Li386_less_signed_true:\n\t"
2444 ".Li386_less_signed_end:\n\t"
2446 "lea 0x8(%esp),%esp");
2450 i386_emit_less_unsigned (void)
2452 EMIT_ASM32 (i386_less_unsigned
,
2453 "cmpl %ebx,4(%esp)\n\t"
2454 "jb .Li386_less_unsigned_true\n\t"
2455 "jne .Li386_less_unsigned_false\n\t"
2456 "cmpl %eax,(%esp)\n\t"
2457 "jb .Li386_less_unsigned_true\n\t"
2458 ".Li386_less_unsigned_false:\n\t"
2460 "jmp .Li386_less_unsigned_end\n\t"
2461 ".Li386_less_unsigned_true:\n\t"
2463 ".Li386_less_unsigned_end:\n\t"
2465 "lea 0x8(%esp),%esp");
2469 i386_emit_ref (int size
)
2474 EMIT_ASM32 (i386_ref1
,
2478 EMIT_ASM32 (i386_ref2
,
2482 EMIT_ASM32 (i386_ref4
,
2483 "movl (%eax),%eax");
2486 EMIT_ASM32 (i386_ref8
,
2487 "movl 4(%eax),%ebx\n\t"
2488 "movl (%eax),%eax");
2494 i386_emit_if_goto (int *offset_p
, int *size_p
)
2496 EMIT_ASM32 (i386_if_goto
,
2502 /* Don't trust the assembler to choose the right jump */
2503 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
2506 *offset_p
= 11; /* be sure that this matches the sequence above */
2512 i386_emit_goto (int *offset_p
, int *size_p
)
2514 EMIT_ASM32 (i386_goto
,
2515 /* Don't trust the assembler to choose the right jump */
2516 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
2524 i386_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2526 int diff
= (to
- (from
+ size
));
2527 unsigned char buf
[sizeof (int)];
2529 /* We're only doing 4-byte sizes at the moment. */
2536 memcpy (buf
, &diff
, sizeof (int));
2537 target_write_memory (from
, buf
, sizeof (int));
2541 i386_emit_const (LONGEST num
)
2543 unsigned char buf
[16];
2545 CORE_ADDR buildaddr
= current_insn_ptr
;
2548 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2549 lo
= num
& 0xffffffff;
2550 memcpy (&buf
[i
], &lo
, sizeof (lo
));
2552 hi
= ((num
>> 32) & 0xffffffff);
2555 buf
[i
++] = 0xbb; /* mov $<n>,%ebx */
2556 memcpy (&buf
[i
], &hi
, sizeof (hi
));
2561 buf
[i
++] = 0x31; buf
[i
++] = 0xdb; /* xor %ebx,%ebx */
2563 append_insns (&buildaddr
, i
, buf
);
2564 current_insn_ptr
= buildaddr
;
2568 i386_emit_call (CORE_ADDR fn
)
2570 unsigned char buf
[16];
2572 CORE_ADDR buildaddr
;
2574 buildaddr
= current_insn_ptr
;
2576 buf
[i
++] = 0xe8; /* call <reladdr> */
2577 offset
= ((int) fn
) - (buildaddr
+ 5);
2578 memcpy (buf
+ 1, &offset
, 4);
2579 append_insns (&buildaddr
, 5, buf
);
2580 current_insn_ptr
= buildaddr
;
2584 i386_emit_reg (int reg
)
2586 unsigned char buf
[16];
2588 CORE_ADDR buildaddr
;
2590 EMIT_ASM32 (i386_reg_a
,
2592 buildaddr
= current_insn_ptr
;
2594 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2595 memcpy (&buf
[i
], ®
, sizeof (reg
));
2597 append_insns (&buildaddr
, i
, buf
);
2598 current_insn_ptr
= buildaddr
;
2599 EMIT_ASM32 (i386_reg_b
,
2600 "mov %eax,4(%esp)\n\t"
2601 "mov 8(%ebp),%eax\n\t"
2603 i386_emit_call (get_raw_reg_func_addr ());
2604 EMIT_ASM32 (i386_reg_c
,
2606 "lea 0x8(%esp),%esp");
2610 i386_emit_pop (void)
2612 EMIT_ASM32 (i386_pop
,
2618 i386_emit_stack_flush (void)
2620 EMIT_ASM32 (i386_stack_flush
,
2626 i386_emit_zero_ext (int arg
)
2631 EMIT_ASM32 (i386_zero_ext_8
,
2632 "and $0xff,%eax\n\t"
2636 EMIT_ASM32 (i386_zero_ext_16
,
2637 "and $0xffff,%eax\n\t"
2641 EMIT_ASM32 (i386_zero_ext_32
,
2650 i386_emit_swap (void)
2652 EMIT_ASM32 (i386_swap
,
2662 i386_emit_stack_adjust (int n
)
2664 unsigned char buf
[16];
2666 CORE_ADDR buildaddr
= current_insn_ptr
;
2669 buf
[i
++] = 0x8d; /* lea $<n>(%esp),%esp */
2673 append_insns (&buildaddr
, i
, buf
);
2674 current_insn_ptr
= buildaddr
;
2677 /* FN's prototype is `LONGEST(*fn)(int)'. */
2680 i386_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2682 unsigned char buf
[16];
2684 CORE_ADDR buildaddr
;
2686 EMIT_ASM32 (i386_int_call_1_a
,
2687 /* Reserve a bit of stack space. */
2689 /* Put the one argument on the stack. */
2690 buildaddr
= current_insn_ptr
;
2692 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2695 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2697 append_insns (&buildaddr
, i
, buf
);
2698 current_insn_ptr
= buildaddr
;
2699 i386_emit_call (fn
);
2700 EMIT_ASM32 (i386_int_call_1_c
,
2702 "lea 0x8(%esp),%esp");
2705 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
2708 i386_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2710 unsigned char buf
[16];
2712 CORE_ADDR buildaddr
;
2714 EMIT_ASM32 (i386_void_call_2_a
,
2715 /* Preserve %eax only; we don't have to worry about %ebx. */
2717 /* Reserve a bit of stack space for arguments. */
2718 "sub $0x10,%esp\n\t"
2719 /* Copy "top" to the second argument position. (Note that
2720 we can't assume function won't scribble on its
2721 arguments, so don't try to restore from this.) */
2722 "mov %eax,4(%esp)\n\t"
2723 "mov %ebx,8(%esp)");
2724 /* Put the first argument on the stack. */
2725 buildaddr
= current_insn_ptr
;
2727 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2730 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2732 append_insns (&buildaddr
, i
, buf
);
2733 current_insn_ptr
= buildaddr
;
2734 i386_emit_call (fn
);
2735 EMIT_ASM32 (i386_void_call_2_b
,
2736 "lea 0x10(%esp),%esp\n\t"
2737 /* Restore original stack top. */
2743 i386_emit_eq_goto (int *offset_p
, int *size_p
)
2746 /* Check low half first, more likely to be decider */
2747 "cmpl %eax,(%esp)\n\t"
2748 "jne .Leq_fallthru\n\t"
2749 "cmpl %ebx,4(%esp)\n\t"
2750 "jne .Leq_fallthru\n\t"
2751 "lea 0x8(%esp),%esp\n\t"
2754 /* jmp, but don't trust the assembler to choose the right jump */
2755 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2756 ".Leq_fallthru:\n\t"
2757 "lea 0x8(%esp),%esp\n\t"
2768 i386_emit_ne_goto (int *offset_p
, int *size_p
)
2771 /* Check low half first, more likely to be decider */
2772 "cmpl %eax,(%esp)\n\t"
2774 "cmpl %ebx,4(%esp)\n\t"
2775 "je .Lne_fallthru\n\t"
2777 "lea 0x8(%esp),%esp\n\t"
2780 /* jmp, but don't trust the assembler to choose the right jump */
2781 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2782 ".Lne_fallthru:\n\t"
2783 "lea 0x8(%esp),%esp\n\t"
2794 i386_emit_lt_goto (int *offset_p
, int *size_p
)
2797 "cmpl %ebx,4(%esp)\n\t"
2799 "jne .Llt_fallthru\n\t"
2800 "cmpl %eax,(%esp)\n\t"
2801 "jnl .Llt_fallthru\n\t"
2803 "lea 0x8(%esp),%esp\n\t"
2806 /* jmp, but don't trust the assembler to choose the right jump */
2807 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2808 ".Llt_fallthru:\n\t"
2809 "lea 0x8(%esp),%esp\n\t"
2820 i386_emit_le_goto (int *offset_p
, int *size_p
)
2823 "cmpl %ebx,4(%esp)\n\t"
2825 "jne .Lle_fallthru\n\t"
2826 "cmpl %eax,(%esp)\n\t"
2827 "jnle .Lle_fallthru\n\t"
2829 "lea 0x8(%esp),%esp\n\t"
2832 /* jmp, but don't trust the assembler to choose the right jump */
2833 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2834 ".Lle_fallthru:\n\t"
2835 "lea 0x8(%esp),%esp\n\t"
2846 i386_emit_gt_goto (int *offset_p
, int *size_p
)
2849 "cmpl %ebx,4(%esp)\n\t"
2851 "jne .Lgt_fallthru\n\t"
2852 "cmpl %eax,(%esp)\n\t"
2853 "jng .Lgt_fallthru\n\t"
2855 "lea 0x8(%esp),%esp\n\t"
2858 /* jmp, but don't trust the assembler to choose the right jump */
2859 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2860 ".Lgt_fallthru:\n\t"
2861 "lea 0x8(%esp),%esp\n\t"
2872 i386_emit_ge_goto (int *offset_p
, int *size_p
)
2875 "cmpl %ebx,4(%esp)\n\t"
2877 "jne .Lge_fallthru\n\t"
2878 "cmpl %eax,(%esp)\n\t"
2879 "jnge .Lge_fallthru\n\t"
2881 "lea 0x8(%esp),%esp\n\t"
2884 /* jmp, but don't trust the assembler to choose the right jump */
2885 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2886 ".Lge_fallthru:\n\t"
2887 "lea 0x8(%esp),%esp\n\t"
2897 struct emit_ops i386_emit_ops
=
2905 i386_emit_rsh_signed
,
2906 i386_emit_rsh_unsigned
,
2914 i386_emit_less_signed
,
2915 i386_emit_less_unsigned
,
2919 i386_write_goto_address
,
2924 i386_emit_stack_flush
,
2927 i386_emit_stack_adjust
,
2928 i386_emit_int_call_1
,
2929 i386_emit_void_call_2
,
2940 x86_target::emit_ops ()
2943 if (is_64bit_tdesc ())
2944 return &amd64_emit_ops
;
2947 return &i386_emit_ops
;
2950 /* Implementation of target ops method "sw_breakpoint_from_kind". */
2953 x86_target::sw_breakpoint_from_kind (int kind
, int *size
)
2955 *size
= x86_breakpoint_len
;
2956 return x86_breakpoint
;
2960 x86_supports_range_stepping (void)
2965 /* Implementation of linux_target_ops method "supports_hardware_single_step".
2969 x86_supports_hardware_single_step (void)
2975 x86_get_ipa_tdesc_idx (void)
2977 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
2978 const struct target_desc
*tdesc
= regcache
->tdesc
;
2981 return amd64_get_ipa_tdesc_idx (tdesc
);
2984 if (tdesc
== tdesc_i386_linux_no_xml
)
2985 return X86_TDESC_SSE
;
2987 return i386_get_ipa_tdesc_idx (tdesc
);
2990 /* This is initialized assuming an amd64 target.
2991 x86_arch_setup will correct it for i386 or amd64 targets. */
2993 struct linux_target_ops the_low_target
=
2995 x86_supports_range_stepping
,
2996 x86_supports_hardware_single_step
,
2997 x86_get_syscall_trapinfo
,
2998 x86_get_ipa_tdesc_idx
,
3001 /* The linux target ops object. */
3003 linux_process_target
*the_linux_target
= &the_x86_target
;
3006 initialize_low_arch (void)
3008 /* Initialize the Linux target descriptions. */
3010 tdesc_amd64_linux_no_xml
= allocate_target_description ();
3011 copy_target_description (tdesc_amd64_linux_no_xml
,
3012 amd64_linux_read_description (X86_XSTATE_SSE_MASK
,
3014 tdesc_amd64_linux_no_xml
->xmltarget
= xmltarget_amd64_linux_no_xml
;
3017 tdesc_i386_linux_no_xml
= allocate_target_description ();
3018 copy_target_description (tdesc_i386_linux_no_xml
,
3019 i386_linux_read_description (X86_XSTATE_SSE_MASK
));
3020 tdesc_i386_linux_no_xml
->xmltarget
= xmltarget_i386_linux_no_xml
;
3022 initialize_regsets_info (&x86_regsets_info
);