1 /* GNU/Linux/x86-64 specific low level interface, for the remote server
3 Copyright (C) 2002-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "linux-low.h"
27 #include "gdbsupport/x86-xstate.h"
28 #include "nat/gdb_ptrace.h"
31 #include "nat/amd64-linux-siginfo.h"
34 #include "gdb_proc_service.h"
35 /* Don't include elf/common.h if linux/elf.h got included by
36 gdb_proc_service.h. */
38 #include "elf/common.h"
41 #include "gdbsupport/agent.h"
43 #include "tracepoint.h"
45 #include "nat/linux-nat.h"
46 #include "nat/x86-linux.h"
47 #include "nat/x86-linux-dregs.h"
48 #include "linux-x86-tdesc.h"
51 static struct target_desc
*tdesc_amd64_linux_no_xml
;
53 static struct target_desc
*tdesc_i386_linux_no_xml
;
56 static unsigned char jump_insn
[] = { 0xe9, 0, 0, 0, 0 };
57 static unsigned char small_jump_insn
[] = { 0x66, 0xe9, 0, 0 };
59 /* Backward compatibility for gdb without XML support. */
61 static const char *xmltarget_i386_linux_no_xml
= "@<target>\
62 <architecture>i386</architecture>\
63 <osabi>GNU/Linux</osabi>\
67 static const char *xmltarget_amd64_linux_no_xml
= "@<target>\
68 <architecture>i386:x86-64</architecture>\
69 <osabi>GNU/Linux</osabi>\
74 #include <sys/procfs.h>
77 #ifndef PTRACE_GET_THREAD_AREA
78 #define PTRACE_GET_THREAD_AREA 25
81 /* This definition comes from prctl.h, but some kernels may not have it. */
82 #ifndef PTRACE_ARCH_PRCTL
83 #define PTRACE_ARCH_PRCTL 30
86 /* The following definitions come from prctl.h, but may be absent
87 for certain configurations. */
89 #define ARCH_SET_GS 0x1001
90 #define ARCH_SET_FS 0x1002
91 #define ARCH_GET_FS 0x1003
92 #define ARCH_GET_GS 0x1004
95 /* Linux target op definitions for the x86 architecture.
96 This is initialized assuming an amd64 target.
97 'low_arch_setup' will correct it for i386 or amd64 targets. */
99 class x86_target
: public linux_process_target
103 /* Update all the target description of all processes; a new GDB
104 connected, and it may or not support xml target descriptions. */
105 void update_xmltarget ();
107 const regs_info
*get_regs_info () override
;
109 const gdb_byte
*sw_breakpoint_from_kind (int kind
, int *size
) override
;
113 void low_arch_setup () override
;
115 bool low_cannot_fetch_register (int regno
) override
;
117 bool low_cannot_store_register (int regno
) override
;
119 bool low_supports_breakpoints () override
;
121 CORE_ADDR
low_get_pc (regcache
*regcache
) override
;
123 void low_set_pc (regcache
*regcache
, CORE_ADDR newpc
) override
;
125 int low_decr_pc_after_break () override
;
127 bool low_breakpoint_at (CORE_ADDR pc
) override
;
130 /* The singleton target ops object. */
132 static x86_target the_x86_target
;
134 /* Per-process arch-specific data we want to keep. */
136 struct arch_process_info
138 struct x86_debug_reg_state debug_reg_state
;
143 /* Mapping between the general-purpose registers in `struct user'
144 format and GDB's register array layout.
145 Note that the transfer layout uses 64-bit regs. */
146 static /*const*/ int i386_regmap
[] =
148 RAX
* 8, RCX
* 8, RDX
* 8, RBX
* 8,
149 RSP
* 8, RBP
* 8, RSI
* 8, RDI
* 8,
150 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
151 DS
* 8, ES
* 8, FS
* 8, GS
* 8
154 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
156 /* So code below doesn't have to care, i386 or amd64. */
157 #define ORIG_EAX ORIG_RAX
160 static const int x86_64_regmap
[] =
162 RAX
* 8, RBX
* 8, RCX
* 8, RDX
* 8,
163 RSI
* 8, RDI
* 8, RBP
* 8, RSP
* 8,
164 R8
* 8, R9
* 8, R10
* 8, R11
* 8,
165 R12
* 8, R13
* 8, R14
* 8, R15
* 8,
166 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
167 DS
* 8, ES
* 8, FS
* 8, GS
* 8,
168 -1, -1, -1, -1, -1, -1, -1, -1,
169 -1, -1, -1, -1, -1, -1, -1, -1,
170 -1, -1, -1, -1, -1, -1, -1, -1,
172 -1, -1, -1, -1, -1, -1, -1, -1,
174 #ifdef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE
179 -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */
180 -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */
181 -1, -1, -1, -1, -1, -1, -1, -1, /* xmm16 ... xmm31 (AVX512) */
182 -1, -1, -1, -1, -1, -1, -1, -1,
183 -1, -1, -1, -1, -1, -1, -1, -1, /* ymm16 ... ymm31 (AVX512) */
184 -1, -1, -1, -1, -1, -1, -1, -1,
185 -1, -1, -1, -1, -1, -1, -1, -1, /* k0 ... k7 (AVX512) */
186 -1, -1, -1, -1, -1, -1, -1, -1, /* zmm0 ... zmm31 (AVX512) */
187 -1, -1, -1, -1, -1, -1, -1, -1,
188 -1, -1, -1, -1, -1, -1, -1, -1,
189 -1, -1, -1, -1, -1, -1, -1, -1,
193 #define X86_64_NUM_REGS (sizeof (x86_64_regmap) / sizeof (x86_64_regmap[0]))
194 #define X86_64_USER_REGS (GS + 1)
196 #else /* ! __x86_64__ */
198 /* Mapping between the general-purpose registers in `struct user'
199 format and GDB's register array layout. */
200 static /*const*/ int i386_regmap
[] =
202 EAX
* 4, ECX
* 4, EDX
* 4, EBX
* 4,
203 UESP
* 4, EBP
* 4, ESI
* 4, EDI
* 4,
204 EIP
* 4, EFL
* 4, CS
* 4, SS
* 4,
205 DS
* 4, ES
* 4, FS
* 4, GS
* 4
208 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
216 /* Returns true if the current inferior belongs to a x86-64 process,
220 is_64bit_tdesc (void)
222 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
224 return register_size (regcache
->tdesc
, 0) == 8;
230 /* Called by libthread_db. */
233 ps_get_thread_area (struct ps_prochandle
*ph
,
234 lwpid_t lwpid
, int idx
, void **base
)
237 int use_64bit
= is_64bit_tdesc ();
244 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_FS
) == 0)
248 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_GS
) == 0)
259 unsigned int desc
[4];
261 if (ptrace (PTRACE_GET_THREAD_AREA
, lwpid
,
262 (void *) (intptr_t) idx
, (unsigned long) &desc
) < 0)
265 /* Ensure we properly extend the value to 64-bits for x86_64. */
266 *base
= (void *) (uintptr_t) desc
[1];
271 /* Get the thread area address. This is used to recognize which
272 thread is which when tracing with the in-process agent library. We
273 don't read anything from the address, and treat it as opaque; it's
274 the address itself that we assume is unique per-thread. */
277 x86_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
280 int use_64bit
= is_64bit_tdesc ();
285 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_FS
) == 0)
287 *addr
= (CORE_ADDR
) (uintptr_t) base
;
296 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
297 struct thread_info
*thr
= get_lwp_thread (lwp
);
298 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
299 unsigned int desc
[4];
301 const int reg_thread_area
= 3; /* bits to scale down register value. */
304 collect_register_by_name (regcache
, "gs", &gs
);
306 idx
= gs
>> reg_thread_area
;
308 if (ptrace (PTRACE_GET_THREAD_AREA
,
310 (void *) (long) idx
, (unsigned long) &desc
) < 0)
321 x86_target::low_cannot_store_register (int regno
)
324 if (is_64bit_tdesc ())
328 return regno
>= I386_NUM_REGS
;
332 x86_target::low_cannot_fetch_register (int regno
)
335 if (is_64bit_tdesc ())
339 return regno
>= I386_NUM_REGS
;
343 x86_fill_gregset (struct regcache
*regcache
, void *buf
)
348 if (register_size (regcache
->tdesc
, 0) == 8)
350 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
351 if (x86_64_regmap
[i
] != -1)
352 collect_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
354 #ifndef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE
357 int lwpid
= lwpid_of (current_thread
);
359 collect_register_by_name (regcache
, "fs_base", &base
);
360 ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_SET_FS
);
362 collect_register_by_name (regcache
, "gs_base", &base
);
363 ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_SET_GS
);
370 /* 32-bit inferior registers need to be zero-extended.
371 Callers would read uninitialized memory otherwise. */
372 memset (buf
, 0x00, X86_64_USER_REGS
* 8);
375 for (i
= 0; i
< I386_NUM_REGS
; i
++)
376 collect_register (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
378 collect_register_by_name (regcache
, "orig_eax",
379 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
382 /* Sign extend EAX value to avoid potential syscall restart
385 See amd64_linux_collect_native_gregset() in gdb/amd64-linux-nat.c
386 for a detailed explanation. */
387 if (register_size (regcache
->tdesc
, 0) == 4)
389 void *ptr
= ((gdb_byte
*) buf
390 + i386_regmap
[find_regno (regcache
->tdesc
, "eax")]);
392 *(int64_t *) ptr
= *(int32_t *) ptr
;
398 x86_store_gregset (struct regcache
*regcache
, const void *buf
)
403 if (register_size (regcache
->tdesc
, 0) == 8)
405 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
406 if (x86_64_regmap
[i
] != -1)
407 supply_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
409 #ifndef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE
412 int lwpid
= lwpid_of (current_thread
);
414 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_FS
) == 0)
415 supply_register_by_name (regcache
, "fs_base", &base
);
417 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_GS
) == 0)
418 supply_register_by_name (regcache
, "gs_base", &base
);
425 for (i
= 0; i
< I386_NUM_REGS
; i
++)
426 supply_register (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
428 supply_register_by_name (regcache
, "orig_eax",
429 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
433 x86_fill_fpregset (struct regcache
*regcache
, void *buf
)
436 i387_cache_to_fxsave (regcache
, buf
);
438 i387_cache_to_fsave (regcache
, buf
);
443 x86_store_fpregset (struct regcache
*regcache
, const void *buf
)
446 i387_fxsave_to_cache (regcache
, buf
);
448 i387_fsave_to_cache (regcache
, buf
);
455 x86_fill_fpxregset (struct regcache
*regcache
, void *buf
)
457 i387_cache_to_fxsave (regcache
, buf
);
461 x86_store_fpxregset (struct regcache
*regcache
, const void *buf
)
463 i387_fxsave_to_cache (regcache
, buf
);
469 x86_fill_xstateregset (struct regcache
*regcache
, void *buf
)
471 i387_cache_to_xsave (regcache
, buf
);
475 x86_store_xstateregset (struct regcache
*regcache
, const void *buf
)
477 i387_xsave_to_cache (regcache
, buf
);
480 /* ??? The non-biarch i386 case stores all the i387 regs twice.
481 Once in i387_.*fsave.* and once in i387_.*fxsave.*.
482 This is, presumably, to handle the case where PTRACE_[GS]ETFPXREGS
483 doesn't work. IWBN to avoid the duplication in the case where it
484 does work. Maybe the arch_setup routine could check whether it works
485 and update the supported regsets accordingly. */
487 static struct regset_info x86_regsets
[] =
489 #ifdef HAVE_PTRACE_GETREGS
490 { PTRACE_GETREGS
, PTRACE_SETREGS
, 0, sizeof (elf_gregset_t
),
492 x86_fill_gregset
, x86_store_gregset
},
493 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_X86_XSTATE
, 0,
494 EXTENDED_REGS
, x86_fill_xstateregset
, x86_store_xstateregset
},
496 # ifdef HAVE_PTRACE_GETFPXREGS
497 { PTRACE_GETFPXREGS
, PTRACE_SETFPXREGS
, 0, sizeof (elf_fpxregset_t
),
499 x86_fill_fpxregset
, x86_store_fpxregset
},
502 { PTRACE_GETFPREGS
, PTRACE_SETFPREGS
, 0, sizeof (elf_fpregset_t
),
504 x86_fill_fpregset
, x86_store_fpregset
},
505 #endif /* HAVE_PTRACE_GETREGS */
510 x86_target::low_supports_breakpoints ()
516 x86_target::low_get_pc (regcache
*regcache
)
518 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
524 collect_register_by_name (regcache
, "rip", &pc
);
525 return (CORE_ADDR
) pc
;
531 collect_register_by_name (regcache
, "eip", &pc
);
532 return (CORE_ADDR
) pc
;
537 x86_target::low_set_pc (regcache
*regcache
, CORE_ADDR pc
)
539 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
545 supply_register_by_name (regcache
, "rip", &newpc
);
551 supply_register_by_name (regcache
, "eip", &newpc
);
556 x86_target::low_decr_pc_after_break ()
562 static const gdb_byte x86_breakpoint
[] = { 0xCC };
563 #define x86_breakpoint_len 1
566 x86_target::low_breakpoint_at (CORE_ADDR pc
)
570 read_memory (pc
, &c
, 1);
577 /* Low-level function vector. */
578 struct x86_dr_low_type x86_dr_low
=
580 x86_linux_dr_set_control
,
581 x86_linux_dr_set_addr
,
582 x86_linux_dr_get_addr
,
583 x86_linux_dr_get_status
,
584 x86_linux_dr_get_control
,
588 /* Breakpoint/Watchpoint support. */
591 x86_supports_z_point_type (char z_type
)
597 case Z_PACKET_WRITE_WP
:
598 case Z_PACKET_ACCESS_WP
:
606 x86_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
607 int size
, struct raw_breakpoint
*bp
)
609 struct process_info
*proc
= current_process ();
613 case raw_bkpt_type_hw
:
614 case raw_bkpt_type_write_wp
:
615 case raw_bkpt_type_access_wp
:
617 enum target_hw_bp_type hw_type
618 = raw_bkpt_type_to_target_hw_bp_type (type
);
619 struct x86_debug_reg_state
*state
620 = &proc
->priv
->arch_private
->debug_reg_state
;
622 return x86_dr_insert_watchpoint (state
, hw_type
, addr
, size
);
632 x86_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
633 int size
, struct raw_breakpoint
*bp
)
635 struct process_info
*proc
= current_process ();
639 case raw_bkpt_type_hw
:
640 case raw_bkpt_type_write_wp
:
641 case raw_bkpt_type_access_wp
:
643 enum target_hw_bp_type hw_type
644 = raw_bkpt_type_to_target_hw_bp_type (type
);
645 struct x86_debug_reg_state
*state
646 = &proc
->priv
->arch_private
->debug_reg_state
;
648 return x86_dr_remove_watchpoint (state
, hw_type
, addr
, size
);
657 x86_stopped_by_watchpoint (void)
659 struct process_info
*proc
= current_process ();
660 return x86_dr_stopped_by_watchpoint (&proc
->priv
->arch_private
->debug_reg_state
);
664 x86_stopped_data_address (void)
666 struct process_info
*proc
= current_process ();
668 if (x86_dr_stopped_data_address (&proc
->priv
->arch_private
->debug_reg_state
,
674 /* Called when a new process is created. */
676 static struct arch_process_info
*
677 x86_linux_new_process (void)
679 struct arch_process_info
*info
= XCNEW (struct arch_process_info
);
681 x86_low_init_dregs (&info
->debug_reg_state
);
686 /* Called when a process is being deleted. */
689 x86_linux_delete_process (struct arch_process_info
*info
)
694 /* Target routine for linux_new_fork. */
697 x86_linux_new_fork (struct process_info
*parent
, struct process_info
*child
)
699 /* These are allocated by linux_add_process. */
700 gdb_assert (parent
->priv
!= NULL
701 && parent
->priv
->arch_private
!= NULL
);
702 gdb_assert (child
->priv
!= NULL
703 && child
->priv
->arch_private
!= NULL
);
705 /* Linux kernel before 2.6.33 commit
706 72f674d203cd230426437cdcf7dd6f681dad8b0d
707 will inherit hardware debug registers from parent
708 on fork/vfork/clone. Newer Linux kernels create such tasks with
709 zeroed debug registers.
711 GDB core assumes the child inherits the watchpoints/hw
712 breakpoints of the parent, and will remove them all from the
713 forked off process. Copy the debug registers mirrors into the
714 new process so that all breakpoints and watchpoints can be
715 removed together. The debug registers mirror will become zeroed
716 in the end before detaching the forked off process, thus making
717 this compatible with older Linux kernels too. */
719 *child
->priv
->arch_private
= *parent
->priv
->arch_private
;
722 /* See nat/x86-dregs.h. */
724 struct x86_debug_reg_state
*
725 x86_debug_reg_state (pid_t pid
)
727 struct process_info
*proc
= find_process_pid (pid
);
729 return &proc
->priv
->arch_private
->debug_reg_state
;
732 /* When GDBSERVER is built as a 64-bit application on linux, the
733 PTRACE_GETSIGINFO data is always presented in 64-bit layout. Since
734 debugging a 32-bit inferior with a 64-bit GDBSERVER should look the same
735 as debugging it with a 32-bit GDBSERVER, we do the 32-bit <-> 64-bit
736 conversion in-place ourselves. */
738 /* Convert a ptrace/host siginfo object, into/from the siginfo in the
739 layout of the inferiors' architecture. Returns true if any
740 conversion was done; false otherwise. If DIRECTION is 1, then copy
741 from INF to PTRACE. If DIRECTION is 0, copy from PTRACE to
745 x86_siginfo_fixup (siginfo_t
*ptrace
, gdb_byte
*inf
, int direction
)
748 unsigned int machine
;
749 int tid
= lwpid_of (current_thread
);
750 int is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
752 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
753 if (!is_64bit_tdesc ())
754 return amd64_linux_siginfo_fixup_common (ptrace
, inf
, direction
,
756 /* No fixup for native x32 GDB. */
757 else if (!is_elf64
&& sizeof (void *) == 8)
758 return amd64_linux_siginfo_fixup_common (ptrace
, inf
, direction
,
767 /* Format of XSAVE extended state is:
771 sw_usable_bytes[464..511]
772 xstate_hdr_bytes[512..575]
777 Same memory layout will be used for the coredump NT_X86_XSTATE
778 representing the XSAVE extended state registers.
780 The first 8 bytes of the sw_usable_bytes[464..467] is the OS enabled
781 extended state mask, which is the same as the extended control register
782 0 (the XFEATURE_ENABLED_MASK register), XCR0. We can use this mask
783 together with the mask saved in the xstate_hdr_bytes to determine what
784 states the processor/OS supports and what state, used or initialized,
785 the process/thread is in. */
786 #define I386_LINUX_XSAVE_XCR0_OFFSET 464
788 /* Does the current host support the GETFPXREGS request? The header
789 file may or may not define it, and even if it is defined, the
790 kernel will return EIO if it's running on a pre-SSE processor. */
791 int have_ptrace_getfpxregs
=
792 #ifdef HAVE_PTRACE_GETFPXREGS
799 /* Get Linux/x86 target description from running target. */
801 static const struct target_desc
*
802 x86_linux_read_description (void)
804 unsigned int machine
;
808 static uint64_t xcr0
;
809 struct regset_info
*regset
;
811 tid
= lwpid_of (current_thread
);
813 is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
815 if (sizeof (void *) == 4)
818 error (_("Can't debug 64-bit process with 32-bit GDBserver"));
820 else if (machine
== EM_X86_64
)
821 error (_("Can't debug x86-64 process with 32-bit GDBserver"));
825 #if !defined __x86_64__ && defined HAVE_PTRACE_GETFPXREGS
826 if (machine
== EM_386
&& have_ptrace_getfpxregs
== -1)
828 elf_fpxregset_t fpxregs
;
830 if (ptrace (PTRACE_GETFPXREGS
, tid
, 0, (long) &fpxregs
) < 0)
832 have_ptrace_getfpxregs
= 0;
833 have_ptrace_getregset
= 0;
834 return i386_linux_read_description (X86_XSTATE_X87
);
837 have_ptrace_getfpxregs
= 1;
843 x86_xcr0
= X86_XSTATE_SSE_MASK
;
847 if (machine
== EM_X86_64
)
848 return tdesc_amd64_linux_no_xml
;
851 return tdesc_i386_linux_no_xml
;
854 if (have_ptrace_getregset
== -1)
856 uint64_t xstateregs
[(X86_XSTATE_SSE_SIZE
/ sizeof (uint64_t))];
859 iov
.iov_base
= xstateregs
;
860 iov
.iov_len
= sizeof (xstateregs
);
862 /* Check if PTRACE_GETREGSET works. */
863 if (ptrace (PTRACE_GETREGSET
, tid
,
864 (unsigned int) NT_X86_XSTATE
, (long) &iov
) < 0)
865 have_ptrace_getregset
= 0;
868 have_ptrace_getregset
= 1;
870 /* Get XCR0 from XSAVE extended state. */
871 xcr0
= xstateregs
[(I386_LINUX_XSAVE_XCR0_OFFSET
872 / sizeof (uint64_t))];
874 /* Use PTRACE_GETREGSET if it is available. */
875 for (regset
= x86_regsets
;
876 regset
->fill_function
!= NULL
; regset
++)
877 if (regset
->get_request
== PTRACE_GETREGSET
)
878 regset
->size
= X86_XSTATE_SIZE (xcr0
);
879 else if (regset
->type
!= GENERAL_REGS
)
884 /* Check the native XCR0 only if PTRACE_GETREGSET is available. */
885 xcr0_features
= (have_ptrace_getregset
886 && (xcr0
& X86_XSTATE_ALL_MASK
));
891 if (machine
== EM_X86_64
)
894 const target_desc
*tdesc
= NULL
;
898 tdesc
= amd64_linux_read_description (xcr0
& X86_XSTATE_ALL_MASK
,
903 tdesc
= amd64_linux_read_description (X86_XSTATE_SSE_MASK
, !is_elf64
);
909 const target_desc
*tdesc
= NULL
;
912 tdesc
= i386_linux_read_description (xcr0
& X86_XSTATE_ALL_MASK
);
915 tdesc
= i386_linux_read_description (X86_XSTATE_SSE
);
920 gdb_assert_not_reached ("failed to return tdesc");
923 /* Update all the target description of all processes; a new GDB
924 connected, and it may or not support xml target descriptions. */
927 x86_target::update_xmltarget ()
929 struct thread_info
*saved_thread
= current_thread
;
931 /* Before changing the register cache's internal layout, flush the
932 contents of the current valid caches back to the threads, and
933 release the current regcache objects. */
936 for_each_process ([this] (process_info
*proc
) {
939 /* Look up any thread of this process. */
940 current_thread
= find_any_thread_of_pid (pid
);
945 current_thread
= saved_thread
;
948 /* Process qSupported query, "xmlRegisters=". Update the buffer size for
952 x86_linux_process_qsupported (char **features
, int count
)
956 /* Return if gdb doesn't support XML. If gdb sends "xmlRegisters="
957 with "i386" in qSupported query, it supports x86 XML target
960 for (i
= 0; i
< count
; i
++)
962 const char *feature
= features
[i
];
964 if (startswith (feature
, "xmlRegisters="))
966 char *copy
= xstrdup (feature
+ 13);
969 for (char *p
= strtok_r (copy
, ",", &saveptr
);
971 p
= strtok_r (NULL
, ",", &saveptr
))
973 if (strcmp (p
, "i386") == 0)
983 the_x86_target
.update_xmltarget ();
986 /* Common for x86/x86-64. */
988 static struct regsets_info x86_regsets_info
=
990 x86_regsets
, /* regsets */
992 NULL
, /* disabled_regsets */
996 static struct regs_info amd64_linux_regs_info
=
998 NULL
, /* regset_bitmap */
999 NULL
, /* usrregs_info */
1003 static struct usrregs_info i386_linux_usrregs_info
=
1009 static struct regs_info i386_linux_regs_info
=
1011 NULL
, /* regset_bitmap */
1012 &i386_linux_usrregs_info
,
1017 x86_target::get_regs_info ()
1020 if (is_64bit_tdesc ())
1021 return &amd64_linux_regs_info
;
1024 return &i386_linux_regs_info
;
1027 /* Initialize the target description for the architecture of the
1031 x86_target::low_arch_setup ()
1033 current_process ()->tdesc
= x86_linux_read_description ();
1036 /* Fill *SYSNO and *SYSRET with the syscall nr trapped and the syscall return
1037 code. This should only be called if LWP got a SYSCALL_SIGTRAP. */
1040 x86_get_syscall_trapinfo (struct regcache
*regcache
, int *sysno
)
1042 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
1048 collect_register_by_name (regcache
, "orig_rax", &l_sysno
);
1049 *sysno
= (int) l_sysno
;
1052 collect_register_by_name (regcache
, "orig_eax", sysno
);
1056 x86_supports_tracepoints (void)
1062 append_insns (CORE_ADDR
*to
, size_t len
, const unsigned char *buf
)
1064 target_write_memory (*to
, buf
, len
);
1069 push_opcode (unsigned char *buf
, const char *op
)
1071 unsigned char *buf_org
= buf
;
1076 unsigned long ul
= strtoul (op
, &endptr
, 16);
1085 return buf
- buf_org
;
1090 /* Build a jump pad that saves registers and calls a collection
1091 function. Writes a jump instruction to the jump pad to
1092 JJUMPAD_INSN. The caller is responsible to write it in at the
1093 tracepoint address. */
1096 amd64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1097 CORE_ADDR collector
,
1100 CORE_ADDR
*jump_entry
,
1101 CORE_ADDR
*trampoline
,
1102 ULONGEST
*trampoline_size
,
1103 unsigned char *jjump_pad_insn
,
1104 ULONGEST
*jjump_pad_insn_size
,
1105 CORE_ADDR
*adjusted_insn_addr
,
1106 CORE_ADDR
*adjusted_insn_addr_end
,
1109 unsigned char buf
[40];
1113 CORE_ADDR buildaddr
= *jump_entry
;
1115 /* Build the jump pad. */
1117 /* First, do tracepoint data collection. Save registers. */
1119 /* Need to ensure stack pointer saved first. */
1120 buf
[i
++] = 0x54; /* push %rsp */
1121 buf
[i
++] = 0x55; /* push %rbp */
1122 buf
[i
++] = 0x57; /* push %rdi */
1123 buf
[i
++] = 0x56; /* push %rsi */
1124 buf
[i
++] = 0x52; /* push %rdx */
1125 buf
[i
++] = 0x51; /* push %rcx */
1126 buf
[i
++] = 0x53; /* push %rbx */
1127 buf
[i
++] = 0x50; /* push %rax */
1128 buf
[i
++] = 0x41; buf
[i
++] = 0x57; /* push %r15 */
1129 buf
[i
++] = 0x41; buf
[i
++] = 0x56; /* push %r14 */
1130 buf
[i
++] = 0x41; buf
[i
++] = 0x55; /* push %r13 */
1131 buf
[i
++] = 0x41; buf
[i
++] = 0x54; /* push %r12 */
1132 buf
[i
++] = 0x41; buf
[i
++] = 0x53; /* push %r11 */
1133 buf
[i
++] = 0x41; buf
[i
++] = 0x52; /* push %r10 */
1134 buf
[i
++] = 0x41; buf
[i
++] = 0x51; /* push %r9 */
1135 buf
[i
++] = 0x41; buf
[i
++] = 0x50; /* push %r8 */
1136 buf
[i
++] = 0x9c; /* pushfq */
1137 buf
[i
++] = 0x48; /* movabs <addr>,%rdi */
1139 memcpy (buf
+ i
, &tpaddr
, 8);
1141 buf
[i
++] = 0x57; /* push %rdi */
1142 append_insns (&buildaddr
, i
, buf
);
1144 /* Stack space for the collecting_t object. */
1146 i
+= push_opcode (&buf
[i
], "48 83 ec 18"); /* sub $0x18,%rsp */
1147 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov <tpoint>,%rax */
1148 memcpy (buf
+ i
, &tpoint
, 8);
1150 i
+= push_opcode (&buf
[i
], "48 89 04 24"); /* mov %rax,(%rsp) */
1151 i
+= push_opcode (&buf
[i
],
1152 "64 48 8b 04 25 00 00 00 00"); /* mov %fs:0x0,%rax */
1153 i
+= push_opcode (&buf
[i
], "48 89 44 24 08"); /* mov %rax,0x8(%rsp) */
1154 append_insns (&buildaddr
, i
, buf
);
1158 i
+= push_opcode (&buf
[i
], "48 be"); /* movl <lockaddr>,%rsi */
1159 memcpy (&buf
[i
], (void *) &lockaddr
, 8);
1161 i
+= push_opcode (&buf
[i
], "48 89 e1"); /* mov %rsp,%rcx */
1162 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1163 i
+= push_opcode (&buf
[i
], "f0 48 0f b1 0e"); /* lock cmpxchg %rcx,(%rsi) */
1164 i
+= push_opcode (&buf
[i
], "48 85 c0"); /* test %rax,%rax */
1165 i
+= push_opcode (&buf
[i
], "75 f4"); /* jne <again> */
1166 append_insns (&buildaddr
, i
, buf
);
1168 /* Set up the gdb_collect call. */
1169 /* At this point, (stack pointer + 0x18) is the base of our saved
1173 i
+= push_opcode (&buf
[i
], "48 89 e6"); /* mov %rsp,%rsi */
1174 i
+= push_opcode (&buf
[i
], "48 83 c6 18"); /* add $0x18,%rsi */
1176 /* tpoint address may be 64-bit wide. */
1177 i
+= push_opcode (&buf
[i
], "48 bf"); /* movl <addr>,%rdi */
1178 memcpy (buf
+ i
, &tpoint
, 8);
1180 append_insns (&buildaddr
, i
, buf
);
1182 /* The collector function being in the shared library, may be
1183 >31-bits away off the jump pad. */
1185 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov $collector,%rax */
1186 memcpy (buf
+ i
, &collector
, 8);
1188 i
+= push_opcode (&buf
[i
], "ff d0"); /* callq *%rax */
1189 append_insns (&buildaddr
, i
, buf
);
1191 /* Clear the spin-lock. */
1193 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1194 i
+= push_opcode (&buf
[i
], "48 a3"); /* mov %rax, lockaddr */
1195 memcpy (buf
+ i
, &lockaddr
, 8);
1197 append_insns (&buildaddr
, i
, buf
);
1199 /* Remove stack that had been used for the collect_t object. */
1201 i
+= push_opcode (&buf
[i
], "48 83 c4 18"); /* add $0x18,%rsp */
1202 append_insns (&buildaddr
, i
, buf
);
1204 /* Restore register state. */
1206 buf
[i
++] = 0x48; /* add $0x8,%rsp */
1210 buf
[i
++] = 0x9d; /* popfq */
1211 buf
[i
++] = 0x41; buf
[i
++] = 0x58; /* pop %r8 */
1212 buf
[i
++] = 0x41; buf
[i
++] = 0x59; /* pop %r9 */
1213 buf
[i
++] = 0x41; buf
[i
++] = 0x5a; /* pop %r10 */
1214 buf
[i
++] = 0x41; buf
[i
++] = 0x5b; /* pop %r11 */
1215 buf
[i
++] = 0x41; buf
[i
++] = 0x5c; /* pop %r12 */
1216 buf
[i
++] = 0x41; buf
[i
++] = 0x5d; /* pop %r13 */
1217 buf
[i
++] = 0x41; buf
[i
++] = 0x5e; /* pop %r14 */
1218 buf
[i
++] = 0x41; buf
[i
++] = 0x5f; /* pop %r15 */
1219 buf
[i
++] = 0x58; /* pop %rax */
1220 buf
[i
++] = 0x5b; /* pop %rbx */
1221 buf
[i
++] = 0x59; /* pop %rcx */
1222 buf
[i
++] = 0x5a; /* pop %rdx */
1223 buf
[i
++] = 0x5e; /* pop %rsi */
1224 buf
[i
++] = 0x5f; /* pop %rdi */
1225 buf
[i
++] = 0x5d; /* pop %rbp */
1226 buf
[i
++] = 0x5c; /* pop %rsp */
1227 append_insns (&buildaddr
, i
, buf
);
1229 /* Now, adjust the original instruction to execute in the jump
1231 *adjusted_insn_addr
= buildaddr
;
1232 relocate_instruction (&buildaddr
, tpaddr
);
1233 *adjusted_insn_addr_end
= buildaddr
;
1235 /* Finally, write a jump back to the program. */
1237 loffset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1238 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1241 "E.Jump back from jump pad too far from tracepoint "
1242 "(offset 0x%" PRIx64
" > int32).", loffset
);
1246 offset
= (int) loffset
;
1247 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1248 memcpy (buf
+ 1, &offset
, 4);
1249 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1251 /* The jump pad is now built. Wire in a jump to our jump pad. This
1252 is always done last (by our caller actually), so that we can
1253 install fast tracepoints with threads running. This relies on
1254 the agent's atomic write support. */
1255 loffset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1256 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1259 "E.Jump pad too far from tracepoint "
1260 "(offset 0x%" PRIx64
" > int32).", loffset
);
1264 offset
= (int) loffset
;
1266 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1267 memcpy (buf
+ 1, &offset
, 4);
1268 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1269 *jjump_pad_insn_size
= sizeof (jump_insn
);
1271 /* Return the end address of our pad. */
1272 *jump_entry
= buildaddr
;
1277 #endif /* __x86_64__ */
1279 /* Build a jump pad that saves registers and calls a collection
1280 function. Writes a jump instruction to the jump pad to
1281 JJUMPAD_INSN. The caller is responsible to write it in at the
1282 tracepoint address. */
1285 i386_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1286 CORE_ADDR collector
,
1289 CORE_ADDR
*jump_entry
,
1290 CORE_ADDR
*trampoline
,
1291 ULONGEST
*trampoline_size
,
1292 unsigned char *jjump_pad_insn
,
1293 ULONGEST
*jjump_pad_insn_size
,
1294 CORE_ADDR
*adjusted_insn_addr
,
1295 CORE_ADDR
*adjusted_insn_addr_end
,
1298 unsigned char buf
[0x100];
1300 CORE_ADDR buildaddr
= *jump_entry
;
1302 /* Build the jump pad. */
1304 /* First, do tracepoint data collection. Save registers. */
1306 buf
[i
++] = 0x60; /* pushad */
1307 buf
[i
++] = 0x68; /* push tpaddr aka $pc */
1308 *((int *)(buf
+ i
)) = (int) tpaddr
;
1310 buf
[i
++] = 0x9c; /* pushf */
1311 buf
[i
++] = 0x1e; /* push %ds */
1312 buf
[i
++] = 0x06; /* push %es */
1313 buf
[i
++] = 0x0f; /* push %fs */
1315 buf
[i
++] = 0x0f; /* push %gs */
1317 buf
[i
++] = 0x16; /* push %ss */
1318 buf
[i
++] = 0x0e; /* push %cs */
1319 append_insns (&buildaddr
, i
, buf
);
1321 /* Stack space for the collecting_t object. */
1323 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1325 /* Build the object. */
1326 i
+= push_opcode (&buf
[i
], "b8"); /* mov <tpoint>,%eax */
1327 memcpy (buf
+ i
, &tpoint
, 4);
1329 i
+= push_opcode (&buf
[i
], "89 04 24"); /* mov %eax,(%esp) */
1331 i
+= push_opcode (&buf
[i
], "65 a1 00 00 00 00"); /* mov %gs:0x0,%eax */
1332 i
+= push_opcode (&buf
[i
], "89 44 24 04"); /* mov %eax,0x4(%esp) */
1333 append_insns (&buildaddr
, i
, buf
);
1335 /* spin-lock. Note this is using cmpxchg, which leaves i386 behind.
1336 If we cared for it, this could be using xchg alternatively. */
1339 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1340 i
+= push_opcode (&buf
[i
], "f0 0f b1 25"); /* lock cmpxchg
1342 memcpy (&buf
[i
], (void *) &lockaddr
, 4);
1344 i
+= push_opcode (&buf
[i
], "85 c0"); /* test %eax,%eax */
1345 i
+= push_opcode (&buf
[i
], "75 f2"); /* jne <again> */
1346 append_insns (&buildaddr
, i
, buf
);
1349 /* Set up arguments to the gdb_collect call. */
1351 i
+= push_opcode (&buf
[i
], "89 e0"); /* mov %esp,%eax */
1352 i
+= push_opcode (&buf
[i
], "83 c0 08"); /* add $0x08,%eax */
1353 i
+= push_opcode (&buf
[i
], "89 44 24 fc"); /* mov %eax,-0x4(%esp) */
1354 append_insns (&buildaddr
, i
, buf
);
1357 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1358 append_insns (&buildaddr
, i
, buf
);
1361 i
+= push_opcode (&buf
[i
], "c7 04 24"); /* movl <addr>,(%esp) */
1362 memcpy (&buf
[i
], (void *) &tpoint
, 4);
1364 append_insns (&buildaddr
, i
, buf
);
1366 buf
[0] = 0xe8; /* call <reladdr> */
1367 offset
= collector
- (buildaddr
+ sizeof (jump_insn
));
1368 memcpy (buf
+ 1, &offset
, 4);
1369 append_insns (&buildaddr
, 5, buf
);
1370 /* Clean up after the call. */
1371 buf
[0] = 0x83; /* add $0x8,%esp */
1374 append_insns (&buildaddr
, 3, buf
);
1377 /* Clear the spin-lock. This would need the LOCK prefix on older
1380 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1381 i
+= push_opcode (&buf
[i
], "a3"); /* mov %eax, lockaddr */
1382 memcpy (buf
+ i
, &lockaddr
, 4);
1384 append_insns (&buildaddr
, i
, buf
);
1387 /* Remove stack that had been used for the collect_t object. */
1389 i
+= push_opcode (&buf
[i
], "83 c4 08"); /* add $0x08,%esp */
1390 append_insns (&buildaddr
, i
, buf
);
1393 buf
[i
++] = 0x83; /* add $0x4,%esp (no pop of %cs, assume unchanged) */
1396 buf
[i
++] = 0x17; /* pop %ss */
1397 buf
[i
++] = 0x0f; /* pop %gs */
1399 buf
[i
++] = 0x0f; /* pop %fs */
1401 buf
[i
++] = 0x07; /* pop %es */
1402 buf
[i
++] = 0x1f; /* pop %ds */
1403 buf
[i
++] = 0x9d; /* popf */
1404 buf
[i
++] = 0x83; /* add $0x4,%esp (pop of tpaddr aka $pc) */
1407 buf
[i
++] = 0x61; /* popad */
1408 append_insns (&buildaddr
, i
, buf
);
1410 /* Now, adjust the original instruction to execute in the jump
1412 *adjusted_insn_addr
= buildaddr
;
1413 relocate_instruction (&buildaddr
, tpaddr
);
1414 *adjusted_insn_addr_end
= buildaddr
;
1416 /* Write the jump back to the program. */
1417 offset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1418 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1419 memcpy (buf
+ 1, &offset
, 4);
1420 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1422 /* The jump pad is now built. Wire in a jump to our jump pad. This
1423 is always done last (by our caller actually), so that we can
1424 install fast tracepoints with threads running. This relies on
1425 the agent's atomic write support. */
1428 /* Create a trampoline. */
1429 *trampoline_size
= sizeof (jump_insn
);
1430 if (!claim_trampoline_space (*trampoline_size
, trampoline
))
1432 /* No trampoline space available. */
1434 "E.Cannot allocate trampoline space needed for fast "
1435 "tracepoints on 4-byte instructions.");
1439 offset
= *jump_entry
- (*trampoline
+ sizeof (jump_insn
));
1440 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1441 memcpy (buf
+ 1, &offset
, 4);
1442 target_write_memory (*trampoline
, buf
, sizeof (jump_insn
));
1444 /* Use a 16-bit relative jump instruction to jump to the trampoline. */
1445 offset
= (*trampoline
- (tpaddr
+ sizeof (small_jump_insn
))) & 0xffff;
1446 memcpy (buf
, small_jump_insn
, sizeof (small_jump_insn
));
1447 memcpy (buf
+ 2, &offset
, 2);
1448 memcpy (jjump_pad_insn
, buf
, sizeof (small_jump_insn
));
1449 *jjump_pad_insn_size
= sizeof (small_jump_insn
);
1453 /* Else use a 32-bit relative jump instruction. */
1454 offset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1455 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1456 memcpy (buf
+ 1, &offset
, 4);
1457 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1458 *jjump_pad_insn_size
= sizeof (jump_insn
);
1461 /* Return the end address of our pad. */
1462 *jump_entry
= buildaddr
;
1468 x86_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1469 CORE_ADDR collector
,
1472 CORE_ADDR
*jump_entry
,
1473 CORE_ADDR
*trampoline
,
1474 ULONGEST
*trampoline_size
,
1475 unsigned char *jjump_pad_insn
,
1476 ULONGEST
*jjump_pad_insn_size
,
1477 CORE_ADDR
*adjusted_insn_addr
,
1478 CORE_ADDR
*adjusted_insn_addr_end
,
1482 if (is_64bit_tdesc ())
1483 return amd64_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1484 collector
, lockaddr
,
1485 orig_size
, jump_entry
,
1486 trampoline
, trampoline_size
,
1488 jjump_pad_insn_size
,
1490 adjusted_insn_addr_end
,
1494 return i386_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1495 collector
, lockaddr
,
1496 orig_size
, jump_entry
,
1497 trampoline
, trampoline_size
,
1499 jjump_pad_insn_size
,
1501 adjusted_insn_addr_end
,
1505 /* Return the minimum instruction length for fast tracepoints on x86/x86-64
1509 x86_get_min_fast_tracepoint_insn_len (void)
1511 static int warned_about_fast_tracepoints
= 0;
1514 /* On x86-64, 5-byte jump instructions with a 4-byte offset are always
1515 used for fast tracepoints. */
1516 if (is_64bit_tdesc ())
1520 if (agent_loaded_p ())
1522 char errbuf
[IPA_BUFSIZ
];
1526 /* On x86, if trampolines are available, then 4-byte jump instructions
1527 with a 2-byte offset may be used, otherwise 5-byte jump instructions
1528 with a 4-byte offset are used instead. */
1529 if (have_fast_tracepoint_trampoline_buffer (errbuf
))
1533 /* GDB has no channel to explain to user why a shorter fast
1534 tracepoint is not possible, but at least make GDBserver
1535 mention that something has gone awry. */
1536 if (!warned_about_fast_tracepoints
)
1538 warning ("4-byte fast tracepoints not available; %s", errbuf
);
1539 warned_about_fast_tracepoints
= 1;
1546 /* Indicate that the minimum length is currently unknown since the IPA
1547 has not loaded yet. */
1553 add_insns (unsigned char *start
, int len
)
1555 CORE_ADDR buildaddr
= current_insn_ptr
;
1558 debug_printf ("Adding %d bytes of insn at %s\n",
1559 len
, paddress (buildaddr
));
1561 append_insns (&buildaddr
, len
, start
);
1562 current_insn_ptr
= buildaddr
;
1565 /* Our general strategy for emitting code is to avoid specifying raw
1566 bytes whenever possible, and instead copy a block of inline asm
1567 that is embedded in the function. This is a little messy, because
1568 we need to keep the compiler from discarding what looks like dead
1569 code, plus suppress various warnings. */
1571 #define EMIT_ASM(NAME, INSNS) \
1574 extern unsigned char start_ ## NAME, end_ ## NAME; \
1575 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1576 __asm__ ("jmp end_" #NAME "\n" \
1577 "\t" "start_" #NAME ":" \
1579 "\t" "end_" #NAME ":"); \
1584 #define EMIT_ASM32(NAME,INSNS) \
1587 extern unsigned char start_ ## NAME, end_ ## NAME; \
1588 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1589 __asm__ (".code32\n" \
1590 "\t" "jmp end_" #NAME "\n" \
1591 "\t" "start_" #NAME ":\n" \
1593 "\t" "end_" #NAME ":\n" \
1599 #define EMIT_ASM32(NAME,INSNS) EMIT_ASM(NAME,INSNS)
1606 amd64_emit_prologue (void)
1608 EMIT_ASM (amd64_prologue
,
1610 "movq %rsp,%rbp\n\t"
1611 "sub $0x20,%rsp\n\t"
1612 "movq %rdi,-8(%rbp)\n\t"
1613 "movq %rsi,-16(%rbp)");
1618 amd64_emit_epilogue (void)
1620 EMIT_ASM (amd64_epilogue
,
1621 "movq -16(%rbp),%rdi\n\t"
1622 "movq %rax,(%rdi)\n\t"
1629 amd64_emit_add (void)
1631 EMIT_ASM (amd64_add
,
1632 "add (%rsp),%rax\n\t"
1633 "lea 0x8(%rsp),%rsp");
1637 amd64_emit_sub (void)
1639 EMIT_ASM (amd64_sub
,
1640 "sub %rax,(%rsp)\n\t"
1645 amd64_emit_mul (void)
1651 amd64_emit_lsh (void)
1657 amd64_emit_rsh_signed (void)
1663 amd64_emit_rsh_unsigned (void)
1669 amd64_emit_ext (int arg
)
1674 EMIT_ASM (amd64_ext_8
,
1680 EMIT_ASM (amd64_ext_16
,
1685 EMIT_ASM (amd64_ext_32
,
1694 amd64_emit_log_not (void)
1696 EMIT_ASM (amd64_log_not
,
1697 "test %rax,%rax\n\t"
1703 amd64_emit_bit_and (void)
1705 EMIT_ASM (amd64_and
,
1706 "and (%rsp),%rax\n\t"
1707 "lea 0x8(%rsp),%rsp");
1711 amd64_emit_bit_or (void)
1714 "or (%rsp),%rax\n\t"
1715 "lea 0x8(%rsp),%rsp");
1719 amd64_emit_bit_xor (void)
1721 EMIT_ASM (amd64_xor
,
1722 "xor (%rsp),%rax\n\t"
1723 "lea 0x8(%rsp),%rsp");
1727 amd64_emit_bit_not (void)
1729 EMIT_ASM (amd64_bit_not
,
1730 "xorq $0xffffffffffffffff,%rax");
1734 amd64_emit_equal (void)
1736 EMIT_ASM (amd64_equal
,
1737 "cmp %rax,(%rsp)\n\t"
1738 "je .Lamd64_equal_true\n\t"
1740 "jmp .Lamd64_equal_end\n\t"
1741 ".Lamd64_equal_true:\n\t"
1743 ".Lamd64_equal_end:\n\t"
1744 "lea 0x8(%rsp),%rsp");
1748 amd64_emit_less_signed (void)
1750 EMIT_ASM (amd64_less_signed
,
1751 "cmp %rax,(%rsp)\n\t"
1752 "jl .Lamd64_less_signed_true\n\t"
1754 "jmp .Lamd64_less_signed_end\n\t"
1755 ".Lamd64_less_signed_true:\n\t"
1757 ".Lamd64_less_signed_end:\n\t"
1758 "lea 0x8(%rsp),%rsp");
1762 amd64_emit_less_unsigned (void)
1764 EMIT_ASM (amd64_less_unsigned
,
1765 "cmp %rax,(%rsp)\n\t"
1766 "jb .Lamd64_less_unsigned_true\n\t"
1768 "jmp .Lamd64_less_unsigned_end\n\t"
1769 ".Lamd64_less_unsigned_true:\n\t"
1771 ".Lamd64_less_unsigned_end:\n\t"
1772 "lea 0x8(%rsp),%rsp");
1776 amd64_emit_ref (int size
)
1781 EMIT_ASM (amd64_ref1
,
1785 EMIT_ASM (amd64_ref2
,
1789 EMIT_ASM (amd64_ref4
,
1790 "movl (%rax),%eax");
1793 EMIT_ASM (amd64_ref8
,
1794 "movq (%rax),%rax");
1800 amd64_emit_if_goto (int *offset_p
, int *size_p
)
1802 EMIT_ASM (amd64_if_goto
,
1806 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
1814 amd64_emit_goto (int *offset_p
, int *size_p
)
1816 EMIT_ASM (amd64_goto
,
1817 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
1825 amd64_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
1827 int diff
= (to
- (from
+ size
));
1828 unsigned char buf
[sizeof (int)];
1836 memcpy (buf
, &diff
, sizeof (int));
1837 target_write_memory (from
, buf
, sizeof (int));
1841 amd64_emit_const (LONGEST num
)
1843 unsigned char buf
[16];
1845 CORE_ADDR buildaddr
= current_insn_ptr
;
1848 buf
[i
++] = 0x48; buf
[i
++] = 0xb8; /* mov $<n>,%rax */
1849 memcpy (&buf
[i
], &num
, sizeof (num
));
1851 append_insns (&buildaddr
, i
, buf
);
1852 current_insn_ptr
= buildaddr
;
1856 amd64_emit_call (CORE_ADDR fn
)
1858 unsigned char buf
[16];
1860 CORE_ADDR buildaddr
;
1863 /* The destination function being in the shared library, may be
1864 >31-bits away off the compiled code pad. */
1866 buildaddr
= current_insn_ptr
;
1868 offset64
= fn
- (buildaddr
+ 1 /* call op */ + 4 /* 32-bit offset */);
1872 if (offset64
> INT_MAX
|| offset64
< INT_MIN
)
1874 /* Offset is too large for a call. Use callq, but that requires
1875 a register, so avoid it if possible. Use r10, since it is
1876 call-clobbered, we don't have to push/pop it. */
1877 buf
[i
++] = 0x48; /* mov $fn,%r10 */
1879 memcpy (buf
+ i
, &fn
, 8);
1881 buf
[i
++] = 0xff; /* callq *%r10 */
1886 int offset32
= offset64
; /* we know we can't overflow here. */
1888 buf
[i
++] = 0xe8; /* call <reladdr> */
1889 memcpy (buf
+ i
, &offset32
, 4);
1893 append_insns (&buildaddr
, i
, buf
);
1894 current_insn_ptr
= buildaddr
;
1898 amd64_emit_reg (int reg
)
1900 unsigned char buf
[16];
1902 CORE_ADDR buildaddr
;
1904 /* Assume raw_regs is still in %rdi. */
1905 buildaddr
= current_insn_ptr
;
1907 buf
[i
++] = 0xbe; /* mov $<n>,%esi */
1908 memcpy (&buf
[i
], ®
, sizeof (reg
));
1910 append_insns (&buildaddr
, i
, buf
);
1911 current_insn_ptr
= buildaddr
;
1912 amd64_emit_call (get_raw_reg_func_addr ());
1916 amd64_emit_pop (void)
1918 EMIT_ASM (amd64_pop
,
1923 amd64_emit_stack_flush (void)
1925 EMIT_ASM (amd64_stack_flush
,
1930 amd64_emit_zero_ext (int arg
)
1935 EMIT_ASM (amd64_zero_ext_8
,
1939 EMIT_ASM (amd64_zero_ext_16
,
1940 "and $0xffff,%rax");
1943 EMIT_ASM (amd64_zero_ext_32
,
1944 "mov $0xffffffff,%rcx\n\t"
1953 amd64_emit_swap (void)
1955 EMIT_ASM (amd64_swap
,
1962 amd64_emit_stack_adjust (int n
)
1964 unsigned char buf
[16];
1966 CORE_ADDR buildaddr
= current_insn_ptr
;
1969 buf
[i
++] = 0x48; /* lea $<n>(%rsp),%rsp */
1973 /* This only handles adjustments up to 16, but we don't expect any more. */
1975 append_insns (&buildaddr
, i
, buf
);
1976 current_insn_ptr
= buildaddr
;
1979 /* FN's prototype is `LONGEST(*fn)(int)'. */
1982 amd64_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
1984 unsigned char buf
[16];
1986 CORE_ADDR buildaddr
;
1988 buildaddr
= current_insn_ptr
;
1990 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
1991 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
1993 append_insns (&buildaddr
, i
, buf
);
1994 current_insn_ptr
= buildaddr
;
1995 amd64_emit_call (fn
);
1998 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
2001 amd64_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2003 unsigned char buf
[16];
2005 CORE_ADDR buildaddr
;
2007 buildaddr
= current_insn_ptr
;
2009 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
2010 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2012 append_insns (&buildaddr
, i
, buf
);
2013 current_insn_ptr
= buildaddr
;
2014 EMIT_ASM (amd64_void_call_2_a
,
2015 /* Save away a copy of the stack top. */
2017 /* Also pass top as the second argument. */
2019 amd64_emit_call (fn
);
2020 EMIT_ASM (amd64_void_call_2_b
,
2021 /* Restore the stack top, %rax may have been trashed. */
2026 amd64_emit_eq_goto (int *offset_p
, int *size_p
)
2029 "cmp %rax,(%rsp)\n\t"
2030 "jne .Lamd64_eq_fallthru\n\t"
2031 "lea 0x8(%rsp),%rsp\n\t"
2033 /* jmp, but don't trust the assembler to choose the right jump */
2034 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2035 ".Lamd64_eq_fallthru:\n\t"
2036 "lea 0x8(%rsp),%rsp\n\t"
2046 amd64_emit_ne_goto (int *offset_p
, int *size_p
)
2049 "cmp %rax,(%rsp)\n\t"
2050 "je .Lamd64_ne_fallthru\n\t"
2051 "lea 0x8(%rsp),%rsp\n\t"
2053 /* jmp, but don't trust the assembler to choose the right jump */
2054 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2055 ".Lamd64_ne_fallthru:\n\t"
2056 "lea 0x8(%rsp),%rsp\n\t"
2066 amd64_emit_lt_goto (int *offset_p
, int *size_p
)
2069 "cmp %rax,(%rsp)\n\t"
2070 "jnl .Lamd64_lt_fallthru\n\t"
2071 "lea 0x8(%rsp),%rsp\n\t"
2073 /* jmp, but don't trust the assembler to choose the right jump */
2074 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2075 ".Lamd64_lt_fallthru:\n\t"
2076 "lea 0x8(%rsp),%rsp\n\t"
2086 amd64_emit_le_goto (int *offset_p
, int *size_p
)
2089 "cmp %rax,(%rsp)\n\t"
2090 "jnle .Lamd64_le_fallthru\n\t"
2091 "lea 0x8(%rsp),%rsp\n\t"
2093 /* jmp, but don't trust the assembler to choose the right jump */
2094 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2095 ".Lamd64_le_fallthru:\n\t"
2096 "lea 0x8(%rsp),%rsp\n\t"
2106 amd64_emit_gt_goto (int *offset_p
, int *size_p
)
2109 "cmp %rax,(%rsp)\n\t"
2110 "jng .Lamd64_gt_fallthru\n\t"
2111 "lea 0x8(%rsp),%rsp\n\t"
2113 /* jmp, but don't trust the assembler to choose the right jump */
2114 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2115 ".Lamd64_gt_fallthru:\n\t"
2116 "lea 0x8(%rsp),%rsp\n\t"
2126 amd64_emit_ge_goto (int *offset_p
, int *size_p
)
2129 "cmp %rax,(%rsp)\n\t"
2130 "jnge .Lamd64_ge_fallthru\n\t"
2131 ".Lamd64_ge_jump:\n\t"
2132 "lea 0x8(%rsp),%rsp\n\t"
2134 /* jmp, but don't trust the assembler to choose the right jump */
2135 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2136 ".Lamd64_ge_fallthru:\n\t"
2137 "lea 0x8(%rsp),%rsp\n\t"
2146 struct emit_ops amd64_emit_ops
=
2148 amd64_emit_prologue
,
2149 amd64_emit_epilogue
,
2154 amd64_emit_rsh_signed
,
2155 amd64_emit_rsh_unsigned
,
2163 amd64_emit_less_signed
,
2164 amd64_emit_less_unsigned
,
2168 amd64_write_goto_address
,
2173 amd64_emit_stack_flush
,
2174 amd64_emit_zero_ext
,
2176 amd64_emit_stack_adjust
,
2177 amd64_emit_int_call_1
,
2178 amd64_emit_void_call_2
,
2187 #endif /* __x86_64__ */
2190 i386_emit_prologue (void)
2192 EMIT_ASM32 (i386_prologue
,
2196 /* At this point, the raw regs base address is at 8(%ebp), and the
2197 value pointer is at 12(%ebp). */
2201 i386_emit_epilogue (void)
2203 EMIT_ASM32 (i386_epilogue
,
2204 "mov 12(%ebp),%ecx\n\t"
2205 "mov %eax,(%ecx)\n\t"
2206 "mov %ebx,0x4(%ecx)\n\t"
2214 i386_emit_add (void)
2216 EMIT_ASM32 (i386_add
,
2217 "add (%esp),%eax\n\t"
2218 "adc 0x4(%esp),%ebx\n\t"
2219 "lea 0x8(%esp),%esp");
2223 i386_emit_sub (void)
2225 EMIT_ASM32 (i386_sub
,
2226 "subl %eax,(%esp)\n\t"
2227 "sbbl %ebx,4(%esp)\n\t"
2233 i386_emit_mul (void)
2239 i386_emit_lsh (void)
2245 i386_emit_rsh_signed (void)
2251 i386_emit_rsh_unsigned (void)
2257 i386_emit_ext (int arg
)
2262 EMIT_ASM32 (i386_ext_8
,
2265 "movl %eax,%ebx\n\t"
2269 EMIT_ASM32 (i386_ext_16
,
2271 "movl %eax,%ebx\n\t"
2275 EMIT_ASM32 (i386_ext_32
,
2276 "movl %eax,%ebx\n\t"
2285 i386_emit_log_not (void)
2287 EMIT_ASM32 (i386_log_not
,
2289 "test %eax,%eax\n\t"
2296 i386_emit_bit_and (void)
2298 EMIT_ASM32 (i386_and
,
2299 "and (%esp),%eax\n\t"
2300 "and 0x4(%esp),%ebx\n\t"
2301 "lea 0x8(%esp),%esp");
2305 i386_emit_bit_or (void)
2307 EMIT_ASM32 (i386_or
,
2308 "or (%esp),%eax\n\t"
2309 "or 0x4(%esp),%ebx\n\t"
2310 "lea 0x8(%esp),%esp");
2314 i386_emit_bit_xor (void)
2316 EMIT_ASM32 (i386_xor
,
2317 "xor (%esp),%eax\n\t"
2318 "xor 0x4(%esp),%ebx\n\t"
2319 "lea 0x8(%esp),%esp");
2323 i386_emit_bit_not (void)
2325 EMIT_ASM32 (i386_bit_not
,
2326 "xor $0xffffffff,%eax\n\t"
2327 "xor $0xffffffff,%ebx\n\t");
2331 i386_emit_equal (void)
2333 EMIT_ASM32 (i386_equal
,
2334 "cmpl %ebx,4(%esp)\n\t"
2335 "jne .Li386_equal_false\n\t"
2336 "cmpl %eax,(%esp)\n\t"
2337 "je .Li386_equal_true\n\t"
2338 ".Li386_equal_false:\n\t"
2340 "jmp .Li386_equal_end\n\t"
2341 ".Li386_equal_true:\n\t"
2343 ".Li386_equal_end:\n\t"
2345 "lea 0x8(%esp),%esp");
2349 i386_emit_less_signed (void)
2351 EMIT_ASM32 (i386_less_signed
,
2352 "cmpl %ebx,4(%esp)\n\t"
2353 "jl .Li386_less_signed_true\n\t"
2354 "jne .Li386_less_signed_false\n\t"
2355 "cmpl %eax,(%esp)\n\t"
2356 "jl .Li386_less_signed_true\n\t"
2357 ".Li386_less_signed_false:\n\t"
2359 "jmp .Li386_less_signed_end\n\t"
2360 ".Li386_less_signed_true:\n\t"
2362 ".Li386_less_signed_end:\n\t"
2364 "lea 0x8(%esp),%esp");
2368 i386_emit_less_unsigned (void)
2370 EMIT_ASM32 (i386_less_unsigned
,
2371 "cmpl %ebx,4(%esp)\n\t"
2372 "jb .Li386_less_unsigned_true\n\t"
2373 "jne .Li386_less_unsigned_false\n\t"
2374 "cmpl %eax,(%esp)\n\t"
2375 "jb .Li386_less_unsigned_true\n\t"
2376 ".Li386_less_unsigned_false:\n\t"
2378 "jmp .Li386_less_unsigned_end\n\t"
2379 ".Li386_less_unsigned_true:\n\t"
2381 ".Li386_less_unsigned_end:\n\t"
2383 "lea 0x8(%esp),%esp");
2387 i386_emit_ref (int size
)
2392 EMIT_ASM32 (i386_ref1
,
2396 EMIT_ASM32 (i386_ref2
,
2400 EMIT_ASM32 (i386_ref4
,
2401 "movl (%eax),%eax");
2404 EMIT_ASM32 (i386_ref8
,
2405 "movl 4(%eax),%ebx\n\t"
2406 "movl (%eax),%eax");
2412 i386_emit_if_goto (int *offset_p
, int *size_p
)
2414 EMIT_ASM32 (i386_if_goto
,
2420 /* Don't trust the assembler to choose the right jump */
2421 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
2424 *offset_p
= 11; /* be sure that this matches the sequence above */
2430 i386_emit_goto (int *offset_p
, int *size_p
)
2432 EMIT_ASM32 (i386_goto
,
2433 /* Don't trust the assembler to choose the right jump */
2434 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
2442 i386_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2444 int diff
= (to
- (from
+ size
));
2445 unsigned char buf
[sizeof (int)];
2447 /* We're only doing 4-byte sizes at the moment. */
2454 memcpy (buf
, &diff
, sizeof (int));
2455 target_write_memory (from
, buf
, sizeof (int));
2459 i386_emit_const (LONGEST num
)
2461 unsigned char buf
[16];
2463 CORE_ADDR buildaddr
= current_insn_ptr
;
2466 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2467 lo
= num
& 0xffffffff;
2468 memcpy (&buf
[i
], &lo
, sizeof (lo
));
2470 hi
= ((num
>> 32) & 0xffffffff);
2473 buf
[i
++] = 0xbb; /* mov $<n>,%ebx */
2474 memcpy (&buf
[i
], &hi
, sizeof (hi
));
2479 buf
[i
++] = 0x31; buf
[i
++] = 0xdb; /* xor %ebx,%ebx */
2481 append_insns (&buildaddr
, i
, buf
);
2482 current_insn_ptr
= buildaddr
;
2486 i386_emit_call (CORE_ADDR fn
)
2488 unsigned char buf
[16];
2490 CORE_ADDR buildaddr
;
2492 buildaddr
= current_insn_ptr
;
2494 buf
[i
++] = 0xe8; /* call <reladdr> */
2495 offset
= ((int) fn
) - (buildaddr
+ 5);
2496 memcpy (buf
+ 1, &offset
, 4);
2497 append_insns (&buildaddr
, 5, buf
);
2498 current_insn_ptr
= buildaddr
;
2502 i386_emit_reg (int reg
)
2504 unsigned char buf
[16];
2506 CORE_ADDR buildaddr
;
2508 EMIT_ASM32 (i386_reg_a
,
2510 buildaddr
= current_insn_ptr
;
2512 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2513 memcpy (&buf
[i
], ®
, sizeof (reg
));
2515 append_insns (&buildaddr
, i
, buf
);
2516 current_insn_ptr
= buildaddr
;
2517 EMIT_ASM32 (i386_reg_b
,
2518 "mov %eax,4(%esp)\n\t"
2519 "mov 8(%ebp),%eax\n\t"
2521 i386_emit_call (get_raw_reg_func_addr ());
2522 EMIT_ASM32 (i386_reg_c
,
2524 "lea 0x8(%esp),%esp");
2528 i386_emit_pop (void)
2530 EMIT_ASM32 (i386_pop
,
2536 i386_emit_stack_flush (void)
2538 EMIT_ASM32 (i386_stack_flush
,
2544 i386_emit_zero_ext (int arg
)
2549 EMIT_ASM32 (i386_zero_ext_8
,
2550 "and $0xff,%eax\n\t"
2554 EMIT_ASM32 (i386_zero_ext_16
,
2555 "and $0xffff,%eax\n\t"
2559 EMIT_ASM32 (i386_zero_ext_32
,
2568 i386_emit_swap (void)
2570 EMIT_ASM32 (i386_swap
,
2580 i386_emit_stack_adjust (int n
)
2582 unsigned char buf
[16];
2584 CORE_ADDR buildaddr
= current_insn_ptr
;
2587 buf
[i
++] = 0x8d; /* lea $<n>(%esp),%esp */
2591 append_insns (&buildaddr
, i
, buf
);
2592 current_insn_ptr
= buildaddr
;
2595 /* FN's prototype is `LONGEST(*fn)(int)'. */
2598 i386_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2600 unsigned char buf
[16];
2602 CORE_ADDR buildaddr
;
2604 EMIT_ASM32 (i386_int_call_1_a
,
2605 /* Reserve a bit of stack space. */
2607 /* Put the one argument on the stack. */
2608 buildaddr
= current_insn_ptr
;
2610 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2613 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2615 append_insns (&buildaddr
, i
, buf
);
2616 current_insn_ptr
= buildaddr
;
2617 i386_emit_call (fn
);
2618 EMIT_ASM32 (i386_int_call_1_c
,
2620 "lea 0x8(%esp),%esp");
2623 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
2626 i386_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2628 unsigned char buf
[16];
2630 CORE_ADDR buildaddr
;
2632 EMIT_ASM32 (i386_void_call_2_a
,
2633 /* Preserve %eax only; we don't have to worry about %ebx. */
2635 /* Reserve a bit of stack space for arguments. */
2636 "sub $0x10,%esp\n\t"
2637 /* Copy "top" to the second argument position. (Note that
2638 we can't assume function won't scribble on its
2639 arguments, so don't try to restore from this.) */
2640 "mov %eax,4(%esp)\n\t"
2641 "mov %ebx,8(%esp)");
2642 /* Put the first argument on the stack. */
2643 buildaddr
= current_insn_ptr
;
2645 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2648 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2650 append_insns (&buildaddr
, i
, buf
);
2651 current_insn_ptr
= buildaddr
;
2652 i386_emit_call (fn
);
2653 EMIT_ASM32 (i386_void_call_2_b
,
2654 "lea 0x10(%esp),%esp\n\t"
2655 /* Restore original stack top. */
2661 i386_emit_eq_goto (int *offset_p
, int *size_p
)
2664 /* Check low half first, more likely to be decider */
2665 "cmpl %eax,(%esp)\n\t"
2666 "jne .Leq_fallthru\n\t"
2667 "cmpl %ebx,4(%esp)\n\t"
2668 "jne .Leq_fallthru\n\t"
2669 "lea 0x8(%esp),%esp\n\t"
2672 /* jmp, but don't trust the assembler to choose the right jump */
2673 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2674 ".Leq_fallthru:\n\t"
2675 "lea 0x8(%esp),%esp\n\t"
2686 i386_emit_ne_goto (int *offset_p
, int *size_p
)
2689 /* Check low half first, more likely to be decider */
2690 "cmpl %eax,(%esp)\n\t"
2692 "cmpl %ebx,4(%esp)\n\t"
2693 "je .Lne_fallthru\n\t"
2695 "lea 0x8(%esp),%esp\n\t"
2698 /* jmp, but don't trust the assembler to choose the right jump */
2699 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2700 ".Lne_fallthru:\n\t"
2701 "lea 0x8(%esp),%esp\n\t"
2712 i386_emit_lt_goto (int *offset_p
, int *size_p
)
2715 "cmpl %ebx,4(%esp)\n\t"
2717 "jne .Llt_fallthru\n\t"
2718 "cmpl %eax,(%esp)\n\t"
2719 "jnl .Llt_fallthru\n\t"
2721 "lea 0x8(%esp),%esp\n\t"
2724 /* jmp, but don't trust the assembler to choose the right jump */
2725 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2726 ".Llt_fallthru:\n\t"
2727 "lea 0x8(%esp),%esp\n\t"
2738 i386_emit_le_goto (int *offset_p
, int *size_p
)
2741 "cmpl %ebx,4(%esp)\n\t"
2743 "jne .Lle_fallthru\n\t"
2744 "cmpl %eax,(%esp)\n\t"
2745 "jnle .Lle_fallthru\n\t"
2747 "lea 0x8(%esp),%esp\n\t"
2750 /* jmp, but don't trust the assembler to choose the right jump */
2751 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2752 ".Lle_fallthru:\n\t"
2753 "lea 0x8(%esp),%esp\n\t"
2764 i386_emit_gt_goto (int *offset_p
, int *size_p
)
2767 "cmpl %ebx,4(%esp)\n\t"
2769 "jne .Lgt_fallthru\n\t"
2770 "cmpl %eax,(%esp)\n\t"
2771 "jng .Lgt_fallthru\n\t"
2773 "lea 0x8(%esp),%esp\n\t"
2776 /* jmp, but don't trust the assembler to choose the right jump */
2777 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2778 ".Lgt_fallthru:\n\t"
2779 "lea 0x8(%esp),%esp\n\t"
2790 i386_emit_ge_goto (int *offset_p
, int *size_p
)
2793 "cmpl %ebx,4(%esp)\n\t"
2795 "jne .Lge_fallthru\n\t"
2796 "cmpl %eax,(%esp)\n\t"
2797 "jnge .Lge_fallthru\n\t"
2799 "lea 0x8(%esp),%esp\n\t"
2802 /* jmp, but don't trust the assembler to choose the right jump */
2803 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2804 ".Lge_fallthru:\n\t"
2805 "lea 0x8(%esp),%esp\n\t"
2815 struct emit_ops i386_emit_ops
=
2823 i386_emit_rsh_signed
,
2824 i386_emit_rsh_unsigned
,
2832 i386_emit_less_signed
,
2833 i386_emit_less_unsigned
,
2837 i386_write_goto_address
,
2842 i386_emit_stack_flush
,
2845 i386_emit_stack_adjust
,
2846 i386_emit_int_call_1
,
2847 i386_emit_void_call_2
,
2857 static struct emit_ops
*
2861 if (is_64bit_tdesc ())
2862 return &amd64_emit_ops
;
2865 return &i386_emit_ops
;
2868 /* Implementation of target ops method "sw_breakpoint_from_kind". */
2871 x86_target::sw_breakpoint_from_kind (int kind
, int *size
)
2873 *size
= x86_breakpoint_len
;
2874 return x86_breakpoint
;
2878 x86_supports_range_stepping (void)
2883 /* Implementation of linux_target_ops method "supports_hardware_single_step".
2887 x86_supports_hardware_single_step (void)
2893 x86_get_ipa_tdesc_idx (void)
2895 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
2896 const struct target_desc
*tdesc
= regcache
->tdesc
;
2899 return amd64_get_ipa_tdesc_idx (tdesc
);
2902 if (tdesc
== tdesc_i386_linux_no_xml
)
2903 return X86_TDESC_SSE
;
2905 return i386_get_ipa_tdesc_idx (tdesc
);
2908 /* This is initialized assuming an amd64 target.
2909 x86_arch_setup will correct it for i386 or amd64 targets. */
2911 struct linux_target_ops the_low_target
=
2913 x86_supports_z_point_type
,
2916 x86_stopped_by_watchpoint
,
2917 x86_stopped_data_address
,
2918 /* collect_ptrace_register/supply_ptrace_register are not needed in the
2919 native i386 case (no registers smaller than an xfer unit), and are not
2920 used in the biarch case (HAVE_LINUX_USRREGS is not defined). */
2923 /* need to fix up i386 siginfo if host is amd64 */
2925 x86_linux_new_process
,
2926 x86_linux_delete_process
,
2927 x86_linux_new_thread
,
2928 x86_linux_delete_thread
,
2930 x86_linux_prepare_to_resume
,
2931 x86_linux_process_qsupported
,
2932 x86_supports_tracepoints
,
2933 x86_get_thread_area
,
2934 x86_install_fast_tracepoint_jump_pad
,
2936 x86_get_min_fast_tracepoint_insn_len
,
2937 x86_supports_range_stepping
,
2938 x86_supports_hardware_single_step
,
2939 x86_get_syscall_trapinfo
,
2940 x86_get_ipa_tdesc_idx
,
2943 /* The linux target ops object. */
2945 linux_process_target
*the_linux_target
= &the_x86_target
;
2948 initialize_low_arch (void)
2950 /* Initialize the Linux target descriptions. */
2952 tdesc_amd64_linux_no_xml
= allocate_target_description ();
2953 copy_target_description (tdesc_amd64_linux_no_xml
,
2954 amd64_linux_read_description (X86_XSTATE_SSE_MASK
,
2956 tdesc_amd64_linux_no_xml
->xmltarget
= xmltarget_amd64_linux_no_xml
;
2959 tdesc_i386_linux_no_xml
= allocate_target_description ();
2960 copy_target_description (tdesc_i386_linux_no_xml
,
2961 i386_linux_read_description (X86_XSTATE_SSE_MASK
));
2962 tdesc_i386_linux_no_xml
->xmltarget
= xmltarget_i386_linux_no_xml
;
2964 initialize_regsets_info (&x86_regsets_info
);