7375bacc414d5047ae43dad476a65349c4ee51ea
[deliverable/binutils-gdb.git] / include / ChangeLog
1 2018-12-03 Kito Cheng <kito@andestech.com>
2
3 * opcode/riscv.h (riscv_opcode): Change type of xlen_requirement to
4 unsigned.
5
6 2018-11-27 Jim Wilson <jimw@sifive.com>
7
8 * opcode/riscv.h (OP_MASK_CFUNCT6, OP_SH_CFUNCT6): New.
9 (OP_MASK_CFUNCT2, OP_SH_CFUNCT2): New.
10
11 2018-11-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
12
13 * opcode/arm.h (ARM_AEXT_V6M_ONLY): Merge into its use in ARM_AEXT_V6M.
14 (ARM_ARCH_V6M_ONLY): Remove.
15 (ARM_EXT_V1, ARM_EXT_V2, ARM_EXT_V2S, ARM_EXT_V3, ARM_EXT_V3M,
16 ARM_EXT_V4, ARM_EXT_V4T, ARM_EXT_V5, ARM_EXT_V5T, ARM_EXT_V5ExP,
17 ARM_EXT_V5E, ARM_EXT_V5J, ARM_EXT_V6, ARM_EXT_V6K, ARM_EXT_V8,
18 ARM_EXT_V6T2, ARM_EXT_DIV, ARM_EXT_V5E_NOTM, ARM_EXT_V6_NOTM,
19 ARM_EXT_V7, ARM_EXT_V7A, ARM_EXT_V7R, ARM_EXT_V7M, ARM_EXT_V6M,
20 ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR, ARM_EXT_V6_DSP, ARM_EXT_MP,
21 ARM_EXT_SEC, ARM_EXT_OS, ARM_EXT_ADIV, ARM_EXT_VIRT, ARM_EXT2_PAN,
22 ARM_EXT2_V8_2A, ARM_EXT2_V8M, ARM_EXT2_ATOMICS, ARM_EXT2_V6T2_V8M,
23 ARM_EXT2_FP16_INST, ARM_EXT2_V8M_MAIN, ARM_EXT2_RAS, ARM_EXT2_V8_3A,
24 ARM_EXT2_V8A, ARM_EXT2_V8_4A, ARM_EXT2_FP16_FML, ARM_EXT2_V8_5A,
25 ARM_EXT2_SB, ARM_EXT2_PREDRES, ARM_CEXT_XSCALE, ARM_CEXT_MAVERICK,
26 ARM_CEXT_IWMMXT, ARM_CEXT_IWMMXT2, FPU_ENDIAN_PURE, FPU_ENDIAN_BIG,
27 FPU_FPA_EXT_V1, FPU_FPA_EXT_V2, FPU_MAVERICK, FPU_VFP_EXT_V1xD,
28 FPU_VFP_EXT_V1, FPU_VFP_EXT_V2, FPU_VFP_EXT_V3xD, FPU_VFP_EXT_V3,
29 FPU_NEON_EXT_V1, FPU_VFP_EXT_D32, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
30 FPU_VFP_EXT_FMA, FPU_VFP_EXT_ARMV8, FPU_NEON_EXT_ARMV8,
31 FPU_CRYPTO_EXT_ARMV8, CRC_EXT_ARMV8, FPU_VFP_EXT_ARMV8xD,
32 FPU_NEON_EXT_RDMA, FPU_NEON_EXT_DOTPROD, ARM_AEXT_V1, ARM_AEXT_V2,
33 ARM_AEXT_V2S, ARM_AEXT_V3, ARM_AEXT_V3M, ARM_AEXT_V4xM, ARM_AEXT_V4,
34 ARM_AEXT_V4TxM, ARM_AEXT_V4T, ARM_AEXT_V5xM, ARM_AEXT_V5,
35 ARM_AEXT_V5TxM, ARM_AEXT_V5T, ARM_AEXT_V5TExP, ARM_AEXT_V5TE,
36 ARM_AEXT_V5TEJ, ARM_AEXT_V6, ARM_AEXT_V6K, ARM_AEXT_V6Z, ARM_AEXT_V6KZ,
37 ARM_AEXT_V6T2, ARM_AEXT_V6KT2, ARM_AEXT_V6ZT2, ARM_AEXT_V6KZT2,
38 ARM_AEXT_V7_ARM, ARM_AEXT_V7A, ARM_AEXT_V7VE, ARM_AEXT_V7R,
39 ARM_AEXT_NOTM, ARM_AEXT_V6M_ONLY, ARM_AEXT_V6M, ARM_AEXT_V6SM,
40 ARM_AEXT_V7M, ARM_AEXT_V7, ARM_AEXT_V7EM, ARM_AEXT_V8A, ARM_AEXT2_V8A,
41 ARM_AEXT2_V8_1A, ARM_AEXT2_V8_2A, ARM_AEXT2_V8_3A, ARM_AEXT2_V8_4A,
42 ARM_AEXT2_V8_5A, ARM_AEXT_V8M_BASE, ARM_AEXT_V8M_MAIN,
43 ARM_AEXT_V8M_MAIN_DSP, ARM_AEXT2_V8M, ARM_AEXT2_V8M_BASE,
44 ARM_AEXT2_V8M_MAIN, ARM_AEXT2_V8M_MAIN_DSP, ARM_AEXT_V8R,
45 ARM_AEXT2_V8R, FPU_VFP_V1xD, FPU_VFP_V1, FPU_VFP_V2, FPU_VFP_V3D16,
46 FPU_VFP_V3, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4, FPU_VFP_V4_SP_D16,
47 FPU_VFP_V5D16, FPU_VFP_ARMV8, FPU_NEON_ARMV8, FPU_CRYPTO_ARMV8,
48 FPU_VFP_HARD, FPU_FPA, FPU_ARCH_VFP, FPU_ARCH_FPE, FPU_ARCH_FPA,
49 FPU_ARCH_VFP_V1xD, FPU_ARCH_VFP_V1, FPU_ARCH_VFP_V2,
50 FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_FP16,
51 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_NEON_V1, FPU_ARCH_VFP_V3_PLUS_NEON_V1,
52 FPU_ARCH_NEON_FP16, FPU_ARCH_VFP_HARD, FPU_ARCH_VFP_V4,
53 FPU_ARCH_VFP_V4D16, FPU_ARCH_VFP_V4_SP_D16, FPU_ARCH_VFP_V5D16,
54 FPU_ARCH_VFP_V5_SP_D16, FPU_ARCH_NEON_VFP_V4, FPU_ARCH_VFP_ARMV8,
55 FPU_ARCH_NEON_VFP_ARMV8, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
56 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD, ARCH_CRC_ARMV8,
57 FPU_ARCH_NEON_VFP_ARMV8_1, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
58 FPU_ARCH_DOTPROD_NEON_VFP_ARMV8, ARM_ARCH_V1, ARM_ARCH_V2,
59 ARM_ARCH_V2S, ARM_ARCH_V3, ARM_ARCH_V3M, ARM_ARCH_V4xM, ARM_ARCH_V4,
60 ARM_ARCH_V4TxM, ARM_ARCH_V4T, ARM_ARCH_V5xM, ARM_ARCH_V5,
61 ARM_ARCH_V5TxM, ARM_ARCH_V5T, ARM_ARCH_V5TExP, ARM_ARCH_V5TE,
62 ARM_ARCH_V5TEJ, ARM_ARCH_V6, ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6KZ,
63 ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, ARM_ARCH_V6KZT2,
64 ARM_ARCH_V6M, ARM_ARCH_V6SM, ARM_ARCH_V7, ARM_ARCH_V7A, ARM_ARCH_V7VE,
65 ARM_ARCH_V7R, ARM_ARCH_V7M, ARM_ARCH_V7EM, ARM_ARCH_V8A,
66 ARM_ARCH_V8A_CRC, ARM_ARCH_V8_1A, ARM_ARCH_V8_2A, ARM_ARCH_V8_3A,
67 ARM_ARCH_V8_4A, ARM_ARCH_V8_5A, ARM_ARCH_V8M_BASE, ARM_ARCH_V8M_MAIN,
68 ARM_ARCH_V8M_MAIN_DSP, ARM_ARCH_V8R): Reindent.
69
70 2018-11-12 Sudakshina Das <sudi.das@arm.com>
71
72 * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2.
73 (aarch64_insn_class): Add ldstgv_indexed.
74
75 2018-11-12 Sudakshina Das <sudi.das@arm.com>
76
77 * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
78 and AARCH64_OPND_ADDR_SIMM13.
79 (aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.
80
81 2018-11-12 Sudakshina Das <sudi.das@arm.com>
82
83 * opcode/aarch64.h (aarch64_opnd): Add
84 AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums.
85
86 2018-11-12 Sudakshina Das <sudi.das@arm.com>
87
88 * opcode/aarch64.h (AARCH64_FEATURE_MEMTAG): New.
89
90 2018-11-07 Roman Bolshakov <r.bolshakov@yadro.com>
91 Saagar Jha <saagar@saagarjha.com>
92
93 * mach-o/external.h (mach_o_nversion_min_command_external): Rename
94 reserved to sdk.
95 (mach_o_note_command_external): New.
96 (mach_o_build_version_command_external): New.
97 * mach-o/loader.h (BFD_MACH_O_LC_VERSION_MIN_TVOS): Define.
98 (BFD_MACH_O_LC_NOTE): Define.
99
100 2018-11-06 Romain Margheriti <lilrom13@gmail.com>
101
102 PR 23742
103 * mach-o/loader.h: Add BFD_MACH_O_LC_BUILD_VERSION.
104
105 2018-11-06 Sudakshina Das <sudi.das@arm.com>
106
107 * opcode/arm.h (ARM_ARCH_V8_5A): Move ARM_EXT2_PREDRES and
108 ARM_EXT2_SB to ...
109 (ARM_AEXT2_V8_5A): Here.
110
111 2018-10-26 John Baldwin <jhb@FreeBSD.org>
112
113 * elf/common.h (AT_FREEBSD_HWCAP2): Define.
114
115 2018-10-09 Sudakshina Das <sudi.das@arm.com>
116
117 * opcode/aarch64.h (AARCH64_FEATURE_SSBS): New.
118 (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SSBS by default.
119
120 2018-10-09 Sudakshina Das <sudi.das@arm.com>
121
122 * opcode/aarch64.h (AARCH64_FEATURE_SCXTNUM): New.
123 (AARCH64_FEATURE_ID_PFR2): New.
124 (AARCH64_ARCH_V8_5): Add both by default.
125
126 2018-10-09 Sudakshina Das <sudi.das@arm.com>
127
128 * opcode/aarch64.h (AARCH64_FEATURE_BTI): New.
129 (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default.
130 (aarch64_opnd): Add AARCH64_OPND_BTI_TARGET.
131 (HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to
132 define HINT #imm values.
133 (HINT_OPD_JC, HINT_OPD_NULL): Likewise.
134
135 2018-10-09 Sudakshina Das <sudi.das@arm.com>
136
137 * opcode/aarch64.h (AARCH64_FEATURE_RNG): New.
138
139 2018-10-09 Sudakshina Das <sudi.das@arm.com>
140
141 * opcode/aarch64.h (AARCH64_FEATURE_CVADP): New.
142
143 2018-10-09 Sudakshina Das <sudi.das@arm.com>
144
145 * opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New.
146 (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default.
147 (aarch64_opnd): Add AARCH64_OPND_SYSREG_SR.
148 (aarch64_sys_regs_sr): Declare new table.
149
150 2018-10-09 Sudakshina Das <sudi.das@arm.com>
151
152 * opcode/aarch64.h (AARCH64_FEATURE_SB): New.
153 (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SB by default.
154
155 2018-10-09 Sudakshina Das <sudi.das@arm.com>
156
157 * opcode/aarch64.h (AARCH64_FEATURE_FLAGMANIP): New.
158 (AARCH64_FEATURE_FRINTTS): New.
159 (AARCH64_ARCH_V8_5): Add both by default.
160
161 2018-10-09 Sudakshina Das <sudi.das@arm.com>
162
163 * opcode/aarch64.h (AARCH64_FEATURE_V8_5): New.
164 (AARCH64_ARCH_V8_5): New.
165
166 2018-10-08 Alan Modra <amodra@gmail.com>
167
168 * bfdlink.h (struct bfd_link_info): Add load_phdrs field.
169
170 2018-10-05 Sudakshina Das <sudi.das@arm.com>
171
172 * opcode/arm.h (ARM_EXT2_PREDRES): New.
173 (ARM_ARCH_V8_5A): Add ARM_EXT2_PREDRES by default.
174
175 2018-10-05 Sudakshina Das <sudi.das@arm.com>
176
177 * opcode/arm.h (ARM_EXT2_SB): New.
178 (ARM_ARCH_V8_5A): Add ARM_EXT2_SB by default.
179
180 2018-10-05 Sudakshina Das <sudi.das@arm.com>
181
182 * opcode/arm.h (ARM_EXT2_V8_5A): New.
183 (ARM_AEXT2_V8_5A, ARM_ARCH_V8_5A): New.
184
185 2018-10-05 Richard Henderson <rth@twiddle.net>
186
187 * elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_PCREL_PG21,
188 R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
189 R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13,
190 R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13,
191 R_OR1K_SLO13, R_OR1K_PLTA26.
192
193 2018-10-05 Richard Henderson <rth@twiddle.net>
194
195 * elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_AHI16,
196 R_OR1K_GOTOFF_AHI16, R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16,
197 R_OR1K_SLO16, R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.
198
199 2018-10-03 Tamar Christina <tamar.christina@arm.com>
200
201 * opcode/aarch64.h (aarch64_inst): Remove.
202 (enum err_type): Add ERR_VFI.
203 (aarch64_is_destructive_by_operands): New.
204 (init_insn_sequence): New.
205 (aarch64_decode_insn): Remove param name.
206
207 2018-10-03 Tamar Christina <tamar.christina@arm.com>
208
209 * opcode/aarch64.h (struct aarch64_opcode): Expand verifiers to take
210 more arguments.
211
212 2018-10-03 Tamar Christina <tamar.christina@arm.com>
213
214 * opcode/aarch64.h (enum err_type): New.
215 (aarch64_decode_insn): Use it.
216
217 2018-10-03 Tamar Christina <tamar.christina@arm.com>
218
219 * opcode/aarch64.h (struct aarch64_instr_sequence): New.
220 (aarch64_opcode_encode): Use it.
221
222 2018-10-03 Tamar Christina <tamar.christina@arm.com>
223
224 * opcode/aarch64.h (struct aarch64_opcode): Add constraints,
225 extend flags field size.
226 (F_SCAN, C_SCAN_MOVPRFX, C_MAX_ELEM): New.
227
228 2018-10-03 John Darrington <john@darrington.wattle.id.au>
229
230 * dis-asm.h (print_insn_s12z): New declaration.
231
232 2018-10-02 Palmer Dabbelt <palmer@sifive.com>
233
234 * opcode/riscv-opc.h (MATCH_FENCE_TSO): New define.
235 (MASK_FENCE_TSO): Likewise.
236
237 2018-10-01 Cupertino Miranda <cmiranda@synopsys.com>
238
239 * arc-reloc.def (ARC_TLS_LE_32): Updated reloc formula.
240
241 2018-09-21 H.J. Lu <hongjiu.lu@intel.com>
242
243 PR binutils/23694
244 * include/elf/internal.h (ELF_SECTION_IN_SEGMENT_1): Don't
245 include zero size sections at start of PT_NOTE segment.
246
247 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
248
249 * elf/nds32.h: Remove the unused target features.
250 * dis-asm.h (disassemble_init_nds32): Declared.
251 * elf/nds32.h (E_NDS32_NULL): Removed.
252 (E_NDS32_HAS_DSP_INST, E_NDS32_HAS_ZOL): New.
253 * opcode/nds32.h: Ident.
254 (N32_SUB6, INSN_LW): New macros.
255 (enum n32_opcodes): Updated.
256 * elf/nds32.h: Doc fixes.
257 * elf/nds32.h: Add R_NDS32_LSI.
258 * elf/nds32.h: Add new relocations for TLS.
259
260 2018-09-20 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
261
262 * elf/common.h (AT_SUN_HWCAP): Rename to ...
263 (AT_SUN_CAP_HW1): ... this. Retain old name for backward
264 compatibility.
265 (AT_SUN_EMULATOR, AT_SUN_BRANDNAME, AT_SUN_BRAND_AUX1)
266 (AT_SUN_BRAND_AUX2, AT_SUN_BRAND_AUX3, AT_SUN_CAP_HW2): Define.
267
268 2018-09-05 Simon Marchi <simon.marchi@ericsson.com>
269
270 * diagnostics.h (DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL): New macro.
271
272 2018-08-31 Alan Modra <amodra@gmail.com>
273
274 * elf/ppc64.h (R_PPC64_REL16_HIGH, R_PPC64_REL16_HIGHA),
275 (R_PPC64_REL16_HIGHER, R_PPC64_REL16_HIGHERA),
276 (R_PPC64_REL16_HIGHEST, R_PPC64_REL16_HIGHESTA): Define.
277 (R_PPC64_LO_DS_OPT, R_PPC64_16DX_HA): Bump value.
278
279 2018-08-30 Kito Cheng <kito@andestech.com>
280
281 * opcode/riscv.h (MAX_SUBSET_NUM): New.
282 (riscv_opcode): Add xlen_requirement field and change type of
283 subset.
284
285 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
286
287 * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E.
288 * opcode/mips.h (CPU_XXX): New CPU_GS264E.
289
290 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
291
292 * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E.
293 * opcode/mips.h (CPU_XXX): New CPU_GS464E.
294
295 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
296
297 * elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to
298 E_MIPS_MACH_GS464.
299 (AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A.
300 * opcode/mips.h (INSN_XXX): Delete INSN_LOONGSON_3A.
301 (CPU_XXX): Rename CPU_LOONGSON_3A to CPU_GS464.
302 * opcode/mips.h (mips_isa_table): Delete CPU_LOONGSON_3A case.
303
304 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
305
306 * elf/mips.h (AFL_ASE_LOONGSON_EXT2): New macro.
307 (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT2.
308 * opcode/mips.h (ASE_LOONGSON_EXT2): New macro.
309
310 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
311
312 * elf/mips.h (AFL_ASE_LOONGSON_EXT): New macro.
313 (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT.
314 * opcode/mips.h (ASE_LOONGSON_EXT): New macro.
315
316 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
317
318 * elf/mips.h (AFL_ASE_LOONGSON_CAM): New macro.
319 (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_CAM.
320 * opcode/mips.h (ASE_LOONGSON_CAM): New macro.
321
322 2018-08-24 H.J. Lu <hongjiu.lu@intel.com>
323
324 * elf/common.h (GNU_PROPERTY_X86_ISA_1_USED): Renamed to ...
325 (GNU_PROPERTY_X86_COMPAT_ISA_1_USED): This.
326 (GNU_PROPERTY_X86_ISA_1_NEEDED): Renamed to ...
327 (GNU_PROPERTY_X86_COMPAT_ISA_1_NEEDED): This.
328 (GNU_PROPERTY_X86_ISA_1_XXX): Renamed to ...
329 (GNU_PROPERTY_X86_COMPAT_ISA_1_XXX): This.
330 (GNU_PROPERTY_X86_UINT32_AND_LO): New.
331 (GNU_PROPERTY_X86_UINT32_AND_HI): Likewise.
332 (GNU_PROPERTY_X86_UINT32_OR_LO): Likewise.
333 (GNU_PROPERTY_X86_UINT32_OR_HI): Likewise.
334 (GNU_PROPERTY_X86_UINT32_OR_AND_LO): Likewise.
335 (GNU_PROPERTY_X86_UINT32_OR_AND_HI): Likewise.
336 (GNU_PROPERTY_X86_ISA_1_CMOV): Likewise.
337 (GNU_PROPERTY_X86_ISA_1_SSE): Likewise.
338 (GNU_PROPERTY_X86_ISA_1_SSE2): Likewise.
339 (GNU_PROPERTY_X86_ISA_1_SSE3): Likewise.
340 (GNU_PROPERTY_X86_ISA_1_SSSE3): Likewise.
341 (GNU_PROPERTY_X86_ISA_1_SSE4_1): Likewise.
342 (GNU_PROPERTY_X86_ISA_1_SSE4_2): Likewise.
343 (GNU_PROPERTY_X86_ISA_1_AVX): Likewise.
344 (GNU_PROPERTY_X86_ISA_1_AVX2): Likewise.
345 (GNU_PROPERTY_X86_ISA_1_FMA): Likewise.
346 (GNU_PROPERTY_X86_ISA_1_AVX512F): Likewise.
347 (GNU_PROPERTY_X86_ISA_1_AVX512CD): Likewise.
348 (GNU_PROPERTY_X86_ISA_1_AVX512ER): Likewise.
349 (GNU_PROPERTY_X86_ISA_1_AVX512PF): Likewise.
350 (GNU_PROPERTY_X86_ISA_1_AVX512VL): Likewise.
351 (GNU_PROPERTY_X86_ISA_1_AVX512DQ): Likewise.
352 (GNU_PROPERTY_X86_ISA_1_AVX512BW): Likewise.
353 (GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS): Likewise.
354 (GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW): Likewise.
355 (GNU_PROPERTY_X86_ISA_1_AVX512_BITALG): Likewise.
356 (GNU_PROPERTY_X86_ISA_1_AVX512_IFMA): Likewise.
357 (GNU_PROPERTY_X86_ISA_1_AVX512_VBMI): Likewise.
358 (GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2): Likewise.
359 (GNU_PROPERTY_X86_ISA_1_AVX512_VNNI): Likewise.
360 (GNU_PROPERTY_X86_FEATURE_2_X86): Likewise.
361 (GNU_PROPERTY_X86_FEATURE_2_X87): Likewise.
362 (GNU_PROPERTY_X86_FEATURE_2_MMX): Likewise.
363 (GNU_PROPERTY_X86_FEATURE_2_XMM): Likewise.
364 (GNU_PROPERTY_X86_FEATURE_2_YMM): Likewise.
365 (GNU_PROPERTY_X86_FEATURE_2_ZMM): Likewise.
366 (GNU_PROPERTY_X86_FEATURE_2_FXSR): Likewise.
367 (GNU_PROPERTY_X86_FEATURE_2_XSAVE): Likewise.
368 (GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT): Likewise.
369 (GNU_PROPERTY_X86_FEATURE_2_XSAVEC): Likewise.
370 (GNU_PROPERTY_X86_FEATURE_1_AND): Updated to
371 (GNU_PROPERTY_X86_UINT32_AND_LO + 0).
372 (GNU_PROPERTY_X86_ISA_1_NEEDED): Defined to
373 (GNU_PROPERTY_X86_UINT32_OR_LO + 0).
374 (GNU_PROPERTY_X86_FEATURE_2_NEEDED): New. Defined to
375 (GNU_PROPERTY_X86_UINT32_OR_LO + 1).
376 (GNU_PROPERTY_X86_ISA_1_USED): Defined to
377 (GNU_PROPERTY_X86_UINT32_OR_AND_LO + 0).
378 (GNU_PROPERTY_X86_FEATURE_2_USED): New. Defined to
379 (GNU_PROPERTY_X86_UINT32_OR_AND_LO + 1).
380
381 2018-08-24 H.J. Lu <hongjiu.lu@intel.com>
382
383 * elf/common.h (GNU_PROPERTY_X86_UINT32_VALID): New.
384
385 2018-08-21 John Darrington <john@darrington.wattle.id.au>
386
387 * elf/s12z.h: Rename R_S12Z_UKNWN_3 to R_S12Z_EXT18.
388
389 2018-08-21 Alan Modra <amodra@gmail.com>
390
391 * opcode/ppc.h (struct powerpc_operand): Correct "insert" comment.
392 Mention use of "extract" function to provide default value.
393 (PPC_OPERAND_OPTIONAL_VALUE): Delete.
394 (ppc_optional_operand_value): Rewrite to use extract function.
395
396 2018-08-18 John Darrington <john@darrington.wattle.id.au>
397
398 * opcode/s12z.h: New file.
399
400 2018-08-09 Richard Earnshaw <rearnsha@arm.com>
401
402 * elf/arm.h: Updated comments for e_flags definitions.
403
404 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
405
406 * elf/arc.h (Tag_ARC_ATR_version): New tag.
407
408 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
409
410 * opcode/arc.h (ARC_OPCODE_ARCV1): Define.
411
412 2018-08-01 Richard Earnshaw <rearnsha@arm.com>
413
414 Copy over from GCC
415 2018-07-26 Martin Liska <mliska@suse.cz>
416
417 PR lto/86548
418 * libiberty.h (make_temp_file_with_prefix): New function.
419
420 2018-07-30 Jim Wilson <jimw@sifive.com>
421
422 * opcode/riscv.h (INSN_TYPE, INSN_BRANCH, INSN_CONDBRANCH, INSN_JSR)
423 (INSN_DREF, INSN_DATA_SIZE, INSN_DATA_SIZE_SHIFT, INSN_1_BYTE)
424 (INSN_2_BYTE, INSN_4_BYTE, INSN_8_BYTE, INSN_16_BYTE): New.
425
426 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
427
428 * elf/common.h (EM_CSKY, EM_CSKY_OLD): Define.
429 * elf/csky.h: New file.
430
431 2018-07-27 Chenghua Xu <paul.hua.gm@gmail.com>
432 Maciej W. Rozycki <macro@linux-mips.org>
433
434 * elf/mips.h (AFL_ASE_MASK): Correct typo.
435
436 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
437
438 * opcode/ppc.h (PPC_OPCODE_750): Adjust comment.
439
440 2018-07-26 Alan Modra <amodra@gmail.com>
441
442 * elf/ppc64.h: Specify byte offset to local entry for values
443 of two to six in STO_PPC64_LOCAL_MASK. Clarify r2 return
444 value for such functions when entering via global entry point.
445 Specify meaning of a value of one in STO_PPC64_LOCAL_MASK.
446
447 2018-07-24 Alan Modra <amodra@gmail.com>
448
449 PR 23430
450 * elf/common.h (SHT_SYMTAB_SHNDX): Fix comment typo.
451
452 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
453 Maciej W. Rozycki <macro@mips.com>
454
455 * elf/mips.h (AFL_ASE_MMI): New macro.
456 (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_MMI.
457 * opcode/mips.h (ASE_LOONGSON_MMI): New macro.
458
459 2018-07-17 Maciej W. Rozycki <macro@mips.com>
460
461 * bfdlink.h (bfd_link_hash_entry): Add `rel_from_abs' member.
462
463 2018-07-06 Alan Modra <amodra@gmail.com>
464
465 * diagnostics.h: Comment on macro usage.
466
467 2018-07-05 Simon Marchi <simon.marchi@polymtl.ca>
468
469 * diagnostics.h (DIAGNOSTIC_IGNORE_DEPRECATED_DECLARATIONS):
470 Define for clang.
471
472 2018-07-02 Maciej W. Rozycki <macro@mips.com>
473
474 PR tdep/8282
475 * dis-asm.h (disasm_option_arg_t): New typedef.
476 (disasm_options_and_args_t): Likewise.
477 (disasm_options_t): Add `arg' member, document members.
478 (disassembler_options_mips): New prototype.
479 (disassembler_options_arm, disassembler_options_powerpc)
480 (disassembler_options_s390): Update prototypes.
481
482 2018-06-29 Tamar Christina <tamar.christina@arm.com>
483
484 PR binutils/23192
485 *opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16.
486
487 2018-06-26 Alan Modra <amodra@gmail.com>
488
489 * elf/internal.h (ELF_SECTION_IN_SEGMENT): Revert last change.
490
491 2018-06-24 Nick Clifton <nickc@redhat.com>
492
493 2.31 branch created.
494
495 2018-06-21 Alan Hayward <alan.hayward@arm.com>
496
497 * elf/internal.h (ELF_SECTION_IN_SEGMENT): Don’t check addresses
498 for non SHT_NOBITS.
499
500 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
501
502 Sync with GCC
503
504 2018-05-24 Tom Rix <trix@juniper.net>
505
506 * dwarf2.def (DW_FORM_strx*, DW_FORM_addrx*): New.
507
508 2017-11-20 Kito Cheng <kito.cheng@gmail.com>
509
510 * longlong.h [__riscv] (__umulsidi3): Define.
511 [__riscv] (umul_ppmm): Likewise.
512 [__riscv] (__muluw3): Likewise.
513
514 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
515
516 * elf/mips.h (AFL_ASE_GINV, AFL_ASE_RESERVED1): New macros.
517 (AFL_ASE_MASK): Update to include AFL_ASE_GINV.
518 * opcode/mips.h: Document "+\" operand format.
519 (ASE_GINV): New macro.
520
521 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
522 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
523
524 * elf/mips.h (AFL_ASE_CRC): New macro.
525 (AFL_ASE_MASK): Update to include AFL_ASE_CRC.
526 * opcode/mips.h (ASE_CRC): New macro.
527 * opcode/mips.h (ASE_CRC64): Likewise.
528
529 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
530
531 * elf/xtensa.h (xtensa_read_table_entries)
532 (xtensa_compute_fill_extra_space): New declarations.
533
534 2018-06-04 H.J. Lu <hongjiu.lu@intel.com>
535
536 * diagnostics.h (DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION): Always
537 define for GCC.
538
539 2018-06-04 H.J. Lu <hongjiu.lu@intel.com>
540
541 * diagnostics.h (DIAGNOSTIC_STRINGIFY_1): New.
542 (DIAGNOSTIC_STRINGIFY): Likewise.
543 (DIAGNOSTIC_IGNORE): Replace STRINGIFY with DIAGNOSTIC_STRINGIFY.
544 (DIAGNOSTIC_IGNORE_SELF_MOVE): Define empty if not defined.
545 (DIAGNOSTIC_IGNORE_DEPRECATED_REGISTER): Likewise.
546 (DIAGNOSTIC_IGNORE_UNUSED_FUNCTION): Likewise.
547 (DIAGNOSTIC_IGNORE_SWITCH_DIFFERENT_ENUM_TYPES): Likewise.
548 (DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION): New.
549
550 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
551
552 * diagnostics.h: Moved from ../gdb/common/diagnostics.h.
553
554 2018-05-28 Bernd Edlinger <bernd.edlinger@hotmail.de>
555
556 * splay-tree.h (splay_tree_compare_strings,
557 splay_tree_delete_pointers): Declare new utility functions.
558
559 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
560
561 * opcode/ppc.h (PPC_OPERAND_FAKE): Delete macro.
562
563 2018-05-18 Kito Cheng <kito.cheng@gmail.com>
564
565 * elf/riscv.h (EF_RISCV_RVE): New define.
566
567 2018-05-18 John Darrington <john@darrington.wattle.id.au>
568
569 * elf/s12z.h: New header.
570
571 2018-05-15 Tamar Christina <tamar.christina@arm.com>
572
573 PR binutils/21446
574 * opcode/aarch64.h (F_SYS_READ, F_SYS_WRITE): New.
575
576 2018-05-15 Tamar Christina <tamar.christina@arm.com>
577
578 PR binutils/21446
579 * opcode/aarch64.h (aarch64_operand_error): Add non_fatal.
580 (aarch64_print_operand): Support notes.
581
582 2018-05-15 Tamar Christina <tamar.christina@arm.com>
583
584 PR binutils/21446
585 * opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
586 (aarch64_decode_insn): Accept error struct.
587
588 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
589
590 * opcode/nfp.h: Use uint64_t instead of bfd_vma.
591
592 2018-05-10 John Darrington <john@darrington.wattle.id.au>
593
594 * elf/common.h (EM_S12Z): New macro.
595
596 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
597
598 * mach-o/unwind.h (MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS):
599 Rename from MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS.
600 (MACH_O_UNWIND_X86_EBP_FRAME_REGISTERS): Rename from
601 MACH_O_UNWIND_X86_EBP_FRAME_REGSITERS.
602
603 2018-05-08 Jim Wilson <jimw@sifive.com>
604
605 * opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New.
606 (MATCH_C_SRAI64, MASK_C_SRAI64): New.
607 (MATCH_C_SLLI64, MASK_C_SLLI64): New.
608
609 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
610
611 * opcode/ppc.h (powerpc_num_opcodes): Change type to unsigned.
612 (vle_num_opcodes): Likewise.
613 (spe2_num_opcodes): Likewise.
614
615 2018-05-04 Alan Modra <amodra@gmail.com>
616
617 * ansidecl.h: Import from gcc.
618 * coff/internal.h (struct internal_scnhdr): Add ATTRIBUTE_NONSTRING
619 to s_name.
620 (struct internal_syment): Add ATTRIBUTE_NONSTRING to _n_name.
621
622 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
623
624 * dis-asm.h: Added print_nfp_disassembler_options prototype.
625 * elf/common.h: Added EM_NFP, officially assigned. See Google Group
626 Generic System V Application Binary Interface.
627 * elf/nfp.h: New, for NFP support.
628 * opcode/nfp.h: New, for NFP support.
629
630 2018-04-25 Christophe Lyon <christophe.lyon@st.com>
631 Mickaël Guêné <mickael.guene@st.com>
632
633 * elf/arm.h: Add R_ARM_TLS_GD32_FDPIC, R_ARM_TLS_LDM32_FDPIC,
634 R_ARM_TLS_IE32_FDPIC.
635
636 2018-04-25 Christophe Lyon <christophe.lyon@st.com>
637 Mickaël Guêné <mickael.guene@st.com>
638
639 * elf/arm.h (R_ARM_GOTFUNCDESC, R_ARM_GOTOFFFUNCDESC)
640 (R_ARM_FUNCDESC)
641 (R_ARM_FUNCDESC_VALUE): Define new relocations.
642
643 2018-04-25 Christophe Lyon <christophe.lyon@st.com>
644 Mickaël Guêné <mickael.guene@st.com>
645
646 * elf/arm.h (EF_ARM_FDPIC): New.
647
648 2018-04-18 Alan Modra <amodra@gmail.com>
649
650 * coff/mipspe.h: Delete.
651
652 2018-04-18 Alan Modra <amodra@gmail.com>
653
654 * aout/dynix3.h: Delete.
655
656 2018-04-17 Andrew Sadek <andrew.sadek.se@gmail.com>
657
658 Microblaze Target: PIC data text relative
659
660 * bfdlink.h (Add flag): Add new flag @ 'bfd_link_info' struct.
661 * elf/microblaze.h (Add 3 new relocations):
662 R_MICROBLAZE_TEXTPCREL_64, R_MICROBLAZE_TEXTREL_64
663 and R_MICROBLAZE_TEXTREL_32_LO for relax function.
664
665 2018-04-17 Alan Modra <amodra@gmail.com>
666
667 * elf/i370.h: Revert removal.
668 * elf/i860.h: Likewise.
669 * elf/i960.h: Likewise.
670
671 2018-04-16 Alan Modra <amodra@gmail.com>
672
673 * coff/sparc.h: Delete.
674
675 2018-04-16 Alan Modra <amodra@gmail.com>
676
677 * aout/host.h: Remove m68k-aout and m68k-coff support.
678 * aout/hp300hpux.h: Delete.
679 * coff/apollo.h: Delete.
680 * coff/aux-coff.h: Delete.
681 * coff/m68k.h: Delete.
682
683 2018-04-16 Alan Modra <amodra@gmail.com>
684
685 * dis-asm.h: Remove sh5 and sh64 support.
686
687 2018-04-16 Alan Modra <amodra@gmail.com>
688
689 * coff/internal.h: Remove w65 support.
690 * coff/w65.h: Delete.
691
692 2018-04-16 Alan Modra <amodra@gmail.com>
693
694 * coff/we32k.h: Delete.
695
696 2018-04-16 Alan Modra <amodra@gmail.com>
697
698 * coff/internal.h: Remove m88k support.
699 * coff/m88k.h: Delete.
700 * opcode/m88k.h: Delete.
701
702 2018-04-16 Alan Modra <amodra@gmail.com>
703
704 * elf/i370.h: Delete.
705 * opcode/i370.h: Delete.
706
707 2018-04-16 Alan Modra <amodra@gmail.com>
708
709 * coff/h8500.h: Delete.
710 * coff/internal.h: Remove h8500 support.
711
712 2018-04-16 Alan Modra <amodra@gmail.com>
713
714 * coff/h8300.h: Delete.
715
716 2018-04-16 Alan Modra <amodra@gmail.com>
717
718 * ieee.h: Delete.
719
720 2018-04-16 Alan Modra <amodra@gmail.com>
721
722 * aout/host.h: Remove newsos3 support.
723
724 2018-04-16 Alan Modra <amodra@gmail.com>
725
726 * nlm/ChangeLog-9315: Delete.
727 * nlm/alpha-ext.h: Delete.
728 * nlm/common.h: Delete.
729 * nlm/external.h: Delete.
730 * nlm/i386-ext.h: Delete.
731 * nlm/internal.h: Delete.
732 * nlm/ppc-ext.h: Delete.
733 * nlm/sparc32-ext.h: Delete.
734
735 2018-04-16 Alan Modra <amodra@gmail.com>
736
737 * opcode/tahoe.h: Delete.
738
739 2018-04-11 Alan Modra <amodra@gmail.com>
740
741 * aout/adobe.h: Delete.
742 * aout/reloc.h: Delete.
743 * coff/i860.h: Delete.
744 * coff/i960.h: Delete.
745 * elf/i860.h: Delete.
746 * elf/i960.h: Delete.
747 * opcode/i860.h: Delete.
748 * opcode/i960.h: Delete.
749 * aout/aout64.h (enum reloc_type): Trim off 29k and other unused values.
750 * aout/ar.h (ARMAGB): Remove.
751 * coff/internal.h (struct internal_aouthdr, struct internal_scnhdr,
752 union internal_auxent): Remove i960 support.
753
754 2018-04-09 Alan Modra <amodra@gmail.com>
755
756 * elf/ppc.h (R_PPC_PLTSEQ, R_PPC_PLTCALL): Define.
757 * elf/ppc64.h (R_PPC64_PLTSEQ, R_PPC64_PLTCALL): Define.
758
759 2018-03-28 Renlin Li <renlin.li@arm.com>
760
761 PR ld/22970
762 * elf/aarch64.h: Add relocation number for
763 R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12,
764 R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC,
765 R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12,
766 R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC,
767 R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12,
768 R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC,
769 R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12,
770 R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC.
771
772 2018-03-28 Nick Clifton <nickc@redhat.com>
773
774 PR 22988
775 * opcode/aarch64.h (enum aarch64_opnd): Add
776 AARCH64_OPND_SVE_ADDR_R.
777
778 2018-03-21 H.J. Lu <hongjiu.lu@intel.com>
779
780 * elf/common.h (DF_1_KMOD): New.
781 (DF_1_WEAKFILTER): Likewise.
782 (DF_1_NOCOMMON): Likewise.
783
784 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
785
786 * opcode/riscv.h (OP_MASK_FUNCT3): New.
787 (OP_SH_FUNCT3): Likewise.
788 (OP_MASK_FUNCT7): Likewise.
789 (OP_SH_FUNCT7): Likewise.
790 (OP_MASK_OP2): Likewise.
791 (OP_SH_OP2): Likewise.
792 (OP_MASK_CFUNCT4): Likewise.
793 (OP_SH_CFUNCT4): Likewise.
794 (OP_MASK_CFUNCT3): Likewise.
795 (OP_SH_CFUNCT3): Likewise.
796 (riscv_insn_types): Likewise.
797
798 2018-03-13 Nick Clifton <nickc@redhat.com>
799
800 PR 22113
801 * coff/pe.h (struct pex64_unwind_info): Add a rawUnwindCodesEnd
802 field.
803
804 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
805
806 * opcode/i386 (OLDGCC_COMPAT): Removed.
807
808 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
809
810 * opcode/arm.h (ARM_FEATURE_COPY): Remove macro definition.
811
812 2018-02-20 Maciej W. Rozycki <macro@mips.com>
813
814 * opcode/mips.h: Remove `M' operand code.
815
816 2018-02-12 Zebediah Figura <z.figura12@gmail.com>
817
818 * coff/msdos.h: New header.
819 * coff/pe.h: Move common defines to msdos.h.
820 * coff/powerpc.h: Likewise.
821
822 2018-01-13 Nick Clifton <nickc@redhat.com>
823
824 2.30 branch created.
825
826 2018-01-11 H.J. Lu <hongjiu.lu@intel.com>
827
828 PR ld/22393
829 * bfdlink.h (bfd_link_info): Add separate_code.
830
831 2018-01-04 Jim Wilson <jimw@sifive.com>
832
833 * opcode/riscv-opc.h (CSR_SBADADDR): Rename to CSR_STVAL. Rename
834 DECLARE_CSR entry. Add alias to map sbadaddr to CSR_STVAL.
835 (CSR_MBADADDR): Rename to CSR_MTVAL. Rename DECLARE_CSR entry.
836 Add alias to map mbadaddr to CSR_MTVAL.
837
838 2018-01-03 Alan Modra <amodra@gmail.com>
839
840 Update year range in copyright notice of all files.
841
842 For older changes see ChangeLog-2017
843 \f
844 Copyright (C) 2018 Free Software Foundation, Inc.
845
846 Copying and distribution of this file, with or without modification,
847 are permitted in any medium without royalty provided the copyright
848 notice and this notice are preserved.
849
850 Local Variables:
851 mode: change-log
852 left-margin: 8
853 fill-column: 74
854 version-control: never
855 End:
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