1 /* Table of opcodes for the AMD 29000
2 Copyright (C) 1990, 1991 Free Software Foundation, Inc.
4 This file is part of GDB and GAS.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 1, or (at your option)
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
23 /* Name of the instruction. */
29 /* A string of characters which describe the operands.
31 , Itself. The character appears in the assembly code.
32 a RA. The register number is in bits 8-15 of the instruction.
33 b RB. The register number is in bits 0-7 of the instruction.
34 c RC. The register number is in bits 16-23 of the instruction.
35 i An immediate operand is in bits 0-7 of the instruction.
36 x Bits 0-7 and 16-23 of the instruction are bits 0-7 and 8-15
37 (respectively) of the immediate operand.
38 h Same as x but the instruction contains bits 16-31 of the
40 X Same as x but bits 16-31 of the signed immediate operand
41 are set to 1 (thus the operand is always negative).
42 P,A Bits 0-7 and 16-23 of the instruction are bits 2-9 and 10-17
43 (respectively) of the immediate operand.
44 P=PC-relative, sign-extended to 32 bits.
45 A=Absolute, zero-extended to 32 bits.
46 e CE bit (bit 23) for a load/store instruction.
47 n Control field (bits 16-22) for a load/store instruction.
48 v Immediate operand in bits 16-23 of the instruction.
49 (used for trap numbers).
50 s SA. Special-purpose register number in bits 8-15
52 u UI--bit 7 of the instruction.
53 r RND--bits 4-6 of the instruction.
54 d FD--bits 2-3 of the instruction.
55 f FS--bits 0-1 of the instruction.
59 d FMT--bits 2-3 of the instruction (not really new).
60 f ACN--bits 0-1 of the instruction (not really new).
61 F FUNC--Special function in bits 18-21 of the instruction.
62 C ACN--bits 16-17 specifying the accumlator register. */
70 static CONST
struct a29k_opcode a29k_opcodes
[] =
73 { "add", 0x14000000, "c,a,b" },
74 { "add", 0x15000000, "c,a,i" },
75 { "addc", 0x1c000000, "c,a,b" },
76 { "addc", 0x1d000000, "c,a,i" },
77 { "addcs", 0x18000000, "c,a,b" },
78 { "addcs", 0x19000000, "c,a,i" },
79 { "addcu", 0x1a000000, "c,a,b" },
80 { "addcu", 0x1b000000, "c,a,i" },
81 { "adds", 0x10000000, "c,a,b" },
82 { "adds", 0x11000000, "c,a,i" },
83 { "addu", 0x12000000, "c,a,b" },
84 { "addu", 0x13000000, "c,a,i" },
85 { "and", 0x90000000, "c,a,b" },
86 { "and", 0x91000000, "c,a,i" },
87 { "andn", 0x9c000000, "c,a,b" },
88 { "andn", 0x9d000000, "c,a,i" },
89 { "aseq", 0x70000000, "v,a,b" },
90 { "aseq", 0x71000000, "v,a,i" },
91 { "asge", 0x5c000000, "v,a,b" },
92 { "asge", 0x5d000000, "v,a,i" },
93 { "asgeu", 0x5e000000, "v,a,b" },
94 { "asgeu", 0x5f000000, "v,a,i" },
95 { "asgt", 0x58000000, "v,a,b" },
96 { "asgt", 0x59000000, "v,a,i" },
97 { "asgtu", 0x5a000000, "v,a,b" },
98 { "asgtu", 0x5b000000, "v,a,i" },
99 { "asle", 0x54000000, "v,a,b" },
100 { "asle", 0x55000000, "v,a,i" },
101 { "asleu", 0x56000000, "v,a,b" },
102 { "asleu", 0x57000000, "v,a,i" },
103 { "aslt", 0x50000000, "v,a,b" },
104 { "aslt", 0x51000000, "v,a,i" },
105 { "asltu", 0x52000000, "v,a,b" },
106 { "asltu", 0x53000000, "v,a,i" },
107 { "asneq", 0x72000000, "v,a,b" },
108 { "asneq", 0x73000000, "v,a,i" },
109 { "call", 0xa8000000, "a,P" },
110 { "call", 0xa9000000, "a,A" },
111 { "calli", 0xc8000000, "a,b" },
112 { "class", 0xe6000000, "c,a,f" },
113 { "clz", 0x08000000, "c,b" },
114 { "clz", 0x09000000, "c,i" },
115 { "const", 0x03000000, "a,x" },
116 { "consth", 0x02000000, "a,h" },
117 { "consthz", 0x05000000, "a,h" },
118 { "constn", 0x01000000, "a,X" },
119 { "convert", 0xe4000000, "c,a,u,r,d,f" },
120 { "cpbyte", 0x2e000000, "c,a,b" },
121 { "cpbyte", 0x2f000000, "c,a,i" },
122 { "cpeq", 0x60000000, "c,a,b" },
123 { "cpeq", 0x61000000, "c,a,i" },
124 { "cpge", 0x4c000000, "c,a,b" },
125 { "cpge", 0x4d000000, "c,a,i" },
126 { "cpgeu", 0x4e000000, "c,a,b" },
127 { "cpgeu", 0x4f000000, "c,a,i" },
128 { "cpgt", 0x48000000, "c,a,b" },
129 { "cpgt", 0x49000000, "c,a,i" },
130 { "cpgtu", 0x4a000000, "c,a,b" },
131 { "cpgtu", 0x4b000000, "c,a,i" },
132 { "cple", 0x44000000, "c,a,b" },
133 { "cple", 0x45000000, "c,a,i" },
134 { "cpleu", 0x46000000, "c,a,b" },
135 { "cpleu", 0x47000000, "c,a,i" },
136 { "cplt", 0x40000000, "c,a,b" },
137 { "cplt", 0x41000000, "c,a,i" },
138 { "cpltu", 0x42000000, "c,a,b" },
139 { "cpltu", 0x43000000, "c,a,i" },
140 { "cpneq", 0x62000000, "c,a,b" },
141 { "cpneq", 0x63000000, "c,a,i" },
142 { "dadd", 0xf1000000, "c,a,b" },
143 { "ddiv", 0xf7000000, "c,a,b" },
144 { "deq", 0xeb000000, "c,a,b" },
145 { "dge", 0xef000000, "c,a,b" },
146 { "dgt", 0xed000000, "c,a,b" },
147 { "div", 0x6a000000, "c,a,b" },
148 { "div", 0x6b000000, "c,a,i" },
149 { "div0", 0x68000000, "c,b" },
150 { "div0", 0x69000000, "c,i" },
151 { "divide", 0xe1000000, "c,a,b" },
152 { "dividu", 0xe3000000, "c,a,b" },
153 { "divl", 0x6c000000, "c,a,b" },
154 { "divl", 0x6d000000, "c,a,i" },
155 { "divrem", 0x6e000000, "c,a,b" },
156 { "divrem", 0x6f000000, "c,a,i" },
157 { "dmac", 0xd9000000, "F,C,a,b" },
158 { "dmsm", 0xdb000000, "c,a,b" },
159 { "dmul", 0xf5000000, "c,a,b" },
160 { "dsub", 0xf3000000, "c,a,b" },
161 { "emulate", 0xd7000000, "v,a,b" },
162 { "exbyte", 0x0a000000, "c,a,b" },
163 { "exbyte", 0x0b000000, "c,a,i" },
164 { "exhw", 0x7c000000, "c,a,b" },
165 { "exhw", 0x7d000000, "c,a,i" },
166 { "exhws", 0x7e000000, "c,a" },
167 { "extract", 0x7a000000, "c,a,b" },
168 { "extract", 0x7b000000, "c,a,i" },
169 { "fadd", 0xf0000000, "c,a,b" },
170 { "fdiv", 0xf6000000, "c,a,b" },
171 { "fdmul", 0xf9000000, "c,a,b" },
172 { "feq", 0xea000000, "c,a,b" },
173 { "fge", 0xee000000, "c,a,b" },
174 { "fgt", 0xec000000, "c,a,b" },
175 { "fmac", 0xd8000000, "F,C,a,b" },
176 { "fmsm", 0xda000000, "c,a,b" },
177 { "fmul", 0xf4000000, "c,a,b" },
178 { "fsub", 0xf2000000, "c,a,b" },
179 { "halt", 0x89000000, "" },
180 { "inbyte", 0x0c000000, "c,a,b" },
181 { "inbyte", 0x0d000000, "c,a,i" },
182 { "inhw", 0x78000000, "c,a,b" },
183 { "inhw", 0x79000000, "c,a,i" },
184 { "inv", 0x9f000000, "" },
185 { "iret", 0x88000000, "" },
186 { "iretinv", 0x8c000000, "" },
187 { "jmp", 0xa0000000, "P" },
188 { "jmp", 0xa1000000, "A" },
189 { "jmpf", 0xa4000000, "a,P" },
190 { "jmpf", 0xa5000000, "a,A" },
191 { "jmpfdec", 0xb4000000, "a,P" },
192 { "jmpfdec", 0xb5000000, "a,A" },
193 { "jmpfi", 0xc4000000, "a,b" },
194 { "jmpi", 0xc0000000, "b" },
195 { "jmpt", 0xac000000, "a,P" },
196 { "jmpt", 0xad000000, "a,A" },
197 { "jmpti", 0xcc000000, "a,b" },
198 { "load", 0x16000000, "e,n,a,b" },
199 { "load", 0x17000000, "e,n,a,i" },
200 { "loadl", 0x06000000, "e,n,a,b" },
201 { "loadl", 0x07000000, "e,n,a,i" },
202 { "loadm", 0x36000000, "e,n,a,b" },
203 { "loadm", 0x37000000, "e,n,a,i" },
204 { "loadset", 0x26000000, "e,n,a,b" },
205 { "loadset", 0x27000000, "e,n,a,i" },
206 { "mfacc", 0xe9000100, "c,d,f" },
207 { "mfsr", 0xc6000000, "c,s" },
208 { "mftlb", 0xb6000000, "c,a" },
209 { "mtacc", 0xe8010000, "a,d,f" },
210 { "mtsr", 0xce000000, "s,b" },
211 { "mtsrim", 0x04000000, "s,x" },
212 { "mttlb", 0xbe000000, "a,b" },
213 { "mul", 0x64000000, "c,a,b" },
214 { "mul", 0x65000000, "c,a,i" },
215 { "mull", 0x66000000, "c,a,b" },
216 { "mull", 0x67000000, "c,a,i" },
217 { "multiplu", 0xe2000000, "c,a,b" },
218 { "multiply", 0xe0000000, "c,a,b" },
219 { "multm", 0xde000000, "c,a,b" },
220 { "multmu", 0xdf000000, "c,a,b" },
221 { "mulu", 0x74000000, "c,a,b" },
222 { "mulu", 0x75000000, "c,a,i" },
223 { "nand", 0x9a000000, "c,a,b" },
224 { "nand", 0x9b000000, "c,a,i" },
225 { "nop", 0x70400101, "" },
226 { "nor", 0x98000000, "c,a,b" },
227 { "nor", 0x99000000, "c,a,i" },
228 { "or", 0x92000000, "c,a,b" },
229 { "or", 0x93000000, "c,a,i" },
230 { "orn", 0xaa000000, "c,a,b" },
231 { "orn", 0xab000000, "c,a,i" },
233 /* The description of "setip" in Chapter 8 ("instruction set") of the user's
234 manual claims that these are absolute register numbers. But section
235 7.2.1 explains that they are not. The latter is correct, so print
236 these normally ("lr0", "lr5", etc.). */
237 { "setip", 0x9e000000, "c,a,b" },
239 { "sll", 0x80000000, "c,a,b" },
240 { "sll", 0x81000000, "c,a,i" },
241 { "sqrt", 0xe5000000, "c,a,f" },
242 { "sra", 0x86000000, "c,a,b" },
243 { "sra", 0x87000000, "c,a,i" },
244 { "srl", 0x82000000, "c,a,b" },
245 { "srl", 0x83000000, "c,a,i" },
246 { "store", 0x1e000000, "e,n,a,b" },
247 { "store", 0x1f000000, "e,n,a,i" },
248 { "storel", 0x0e000000, "e,n,a,b" },
249 { "storel", 0x0f000000, "e,n,a,i" },
250 { "storem", 0x3e000000, "e,n,a,b" },
251 { "storem", 0x3f000000, "e,n,a,i" },
252 { "sub", 0x24000000, "c,a,b" },
253 { "sub", 0x25000000, "c,a,i" },
254 { "subc", 0x2c000000, "c,a,b" },
255 { "subc", 0x2d000000, "c,a,i" },
256 { "subcs", 0x28000000, "c,a,b" },
257 { "subcs", 0x29000000, "c,a,i" },
258 { "subcu", 0x2a000000, "c,a,b" },
259 { "subcu", 0x2b000000, "c,a,i" },
260 { "subr", 0x34000000, "c,a,b" },
261 { "subr", 0x35000000, "c,a,i" },
262 { "subrc", 0x3c000000, "c,a,b" },
263 { "subrc", 0x3d000000, "c,a,i" },
264 { "subrcs", 0x38000000, "c,a,b" },
265 { "subrcs", 0x39000000, "c,a,i" },
266 { "subrcu", 0x3a000000, "c,a,b" },
267 { "subrcu", 0x3b000000, "c,a,i" },
268 { "subrs", 0x30000000, "c,a,b" },
269 { "subrs", 0x31000000, "c,a,i" },
270 { "subru", 0x32000000, "c,a,b" },
271 { "subru", 0x33000000, "c,a,i" },
272 { "subs", 0x20000000, "c,a,b" },
273 { "subs", 0x21000000, "c,a,i" },
274 { "subu", 0x22000000, "c,a,b" },
275 { "subu", 0x23000000, "c,a,i" },
276 { "xnor", 0x96000000, "c,a,b" },
277 { "xnor", 0x97000000, "c,a,i" },
278 { "xor", 0x94000000, "c,a,b" },
279 { "xor", 0x95000000, "c,a,i" },
281 { "", 0x0, "" } /* Dummy entry, not included in NUM_OPCODES. This
282 lets code examine entry i+1 without checking
283 if we've run off the end of the table. */
286 CONST
unsigned int num_opcodes
= (((sizeof a29k_opcodes
) / (sizeof a29k_opcodes
[0])) - 1);
290 * Revision 1.5 1991/11/07 16:59:19 sac
291 * Fixed encoding of mtacc instruction.
293 * Revision 1.4 1991/08/06 07:20:27 rich
294 * Fixing CONST declarations.
296 * Revision 1.3 1991/08/05 22:31:05 rich
297 * *** empty log message ***
299 * Revision 1.2 1991/07/15 23:34:04 steve
300 * *** empty log message ***
302 * Revision 1.1 1991/05/19 00:19:33 rich
305 * Revision 1.1.1.1 1991/04/04 18:15:23 rich
308 * Revision 1.1 1991/04/04 18:15:23 rich
311 * Revision 1.2 1991/03/30 17:13:19 rich
312 * num_opcodes now unsigned. Also, added rcsid and log.
317 /* end of a29k-opcode.h */
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