2 * linux/include/asm-arm/arch-pxa/pxa-regs.h
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
16 #include <linux/config.h>
22 #define PXA_CS0_PHYS 0x00000000
23 #define PXA_CS1_PHYS 0x04000000
24 #define PXA_CS2_PHYS 0x08000000
25 #define PXA_CS3_PHYS 0x0C000000
26 #define PXA_CS4_PHYS 0x10000000
27 #define PXA_CS5_PHYS 0x14000000
31 * Personal Computer Memory Card International Association (PCMCIA) sockets
34 #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
35 #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
36 #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
37 #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
38 #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
40 #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
41 #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
42 #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
43 #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
45 #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
46 #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
47 #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
48 #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
50 #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
51 (0x20000000 + (Nb)*PCMCIASp)
52 #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
53 #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
54 (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
55 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
56 (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
58 #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
59 #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
60 #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
61 #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
63 #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
64 #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
65 #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
66 #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
74 #define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */
75 #define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */
76 #define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */
77 #define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */
78 #define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */
79 #define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */
80 #define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */
81 #define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */
82 #define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */
83 #define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */
84 #define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */
85 #define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */
86 #define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */
87 #define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */
88 #define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */
89 #define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */
91 #define DCSR(x) __REG2(0x40000000, (x) << 2)
93 #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
94 #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
95 #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
97 #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
98 #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
99 #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
100 #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
101 #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
102 #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
103 #define DCSR_ENRINTR (1 << 9) /* The end of Receive */
105 #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
106 #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
107 #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
108 #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
109 #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
111 #define DINT __REG(0x400000f0) /* DMA Interrupt Register */
113 #define DRCMR(n) __REG2(0x40000100, (n)<<2)
114 #define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */
115 #define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */
116 #define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */
117 #define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */
118 #define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */
119 #define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */
120 #define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */
121 #define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */
122 #define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */
123 #define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */
124 #define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */
125 #define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */
126 #define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */
127 #define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */
128 #define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */
129 #define DRCMR15 __REG(0x4000013c) /* Request to Channel Map Register for SSP2 receive Request */
130 #define DRCMR16 __REG(0x40000140) /* Request to Channel Map Register for SSP2 transmit Request */
131 #define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */
132 #define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */
133 #define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */
134 #define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */
135 #define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */
136 #define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */
137 #define DRCMR23 __REG(0x4000015c) /* Reserved */
138 #define DRCMR24 __REG(0x40000160) /* Reserved */
139 #define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */
140 #define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */
141 #define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */
142 #define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */
143 #define DRCMR29 __REG(0x40000174) /* Reserved */
144 #define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */
145 #define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */
146 #define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */
147 #define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */
148 #define DRCMR34 __REG(0x40000188) /* Reserved */
149 #define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */
150 #define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */
151 #define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */
152 #define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */
153 #define DRCMR39 __REG(0x4000019C) /* Reserved */
154 #define DRCMR66 __REG(0x40001108) /* Request to Channel Map Register for SSP3 receive Request */
155 #define DRCMR67 __REG(0x4000110C) /* Request to Channel Map Register for SSP3 transmit Request */
156 #define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */
157 #define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */
158 #define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */
160 #define DRCMRRXSADR DRCMR2
161 #define DRCMRTXSADR DRCMR3
162 #define DRCMRRXBTRBR DRCMR4
163 #define DRCMRTXBTTHR DRCMR5
164 #define DRCMRRXFFRBR DRCMR6
165 #define DRCMRTXFFTHR DRCMR7
166 #define DRCMRRXMCDR DRCMR8
167 #define DRCMRRXMODR DRCMR9
168 #define DRCMRTXMODR DRCMR10
169 #define DRCMRRXPCDR DRCMR11
170 #define DRCMRTXPCDR DRCMR12
171 #define DRCMRRXSSDR DRCMR13
172 #define DRCMRTXSSDR DRCMR14
173 #define DRCMRRXSS2DR DRCMR15
174 #define DRCMRTXSS2DR DRCMR16
175 #define DRCMRRXICDR DRCMR17
176 #define DRCMRTXICDR DRCMR18
177 #define DRCMRRXSTRBR DRCMR19
178 #define DRCMRTXSTTHR DRCMR20
179 #define DRCMRRXMMC DRCMR21
180 #define DRCMRTXMMC DRCMR22
181 #define DRCMRRXSS3DR DRCMR66
182 #define DRCMRTXSS3DR DRCMR67
183 #define DRCMRUDC(x) DRCMR((x) + 24)
185 #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
186 #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
188 #define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */
189 #define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */
190 #define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */
191 #define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */
192 #define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */
193 #define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */
194 #define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */
195 #define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */
196 #define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */
197 #define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */
198 #define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */
199 #define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */
200 #define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */
201 #define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */
202 #define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */
203 #define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */
204 #define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */
205 #define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */
206 #define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */
207 #define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */
208 #define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */
209 #define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */
210 #define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */
211 #define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */
212 #define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */
213 #define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */
214 #define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */
215 #define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */
216 #define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */
217 #define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */
218 #define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */
219 #define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */
220 #define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */
221 #define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */
222 #define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */
223 #define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */
224 #define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */
225 #define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */
226 #define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */
227 #define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */
228 #define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */
229 #define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */
230 #define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */
231 #define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */
232 #define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */
233 #define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */
234 #define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */
235 #define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */
236 #define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */
237 #define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */
238 #define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */
239 #define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */
240 #define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */
241 #define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */
242 #define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */
243 #define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */
244 #define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */
245 #define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */
246 #define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */
247 #define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */
248 #define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */
249 #define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */
250 #define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */
251 #define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */
253 #define DDADR(x) __REG2(0x40000200, (x) << 4)
254 #define DSADR(x) __REG2(0x40000204, (x) << 4)
255 #define DTADR(x) __REG2(0x40000208, (x) << 4)
256 #define DCMD(x) __REG2(0x4000020c, (x) << 4)
258 #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
259 #define DDADR_STOP (1 << 0) /* Stop (read / write) */
261 #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
262 #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
263 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
264 #define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
265 #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
266 #define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
267 #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
268 #define DCMD_BURST8 (1 << 16) /* 8 byte burst */
269 #define DCMD_BURST16 (2 << 16) /* 16 byte burst */
270 #define DCMD_BURST32 (3 << 16) /* 32 byte burst */
271 #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
272 #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
273 #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
274 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
281 /* Full Function UART (FFUART) */
283 #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
284 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
285 #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
286 #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
287 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
288 #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
289 #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
290 #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
291 #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
292 #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
293 #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
294 #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
295 #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
297 /* Bluetooth UART (BTUART) */
299 #define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
300 #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
301 #define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
302 #define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
303 #define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
304 #define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
305 #define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
306 #define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
307 #define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
308 #define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
309 #define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
310 #define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
311 #define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
313 /* Standard UART (STUART) */
315 #define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
316 #define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
317 #define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
318 #define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
319 #define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
320 #define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
321 #define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
322 #define STLSR __REG(0x40700014) /* Line Status Register (read only) */
323 #define STMSR __REG(0x40700018) /* Reserved */
324 #define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
325 #define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
326 #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
327 #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
329 #define IER_DMAE (1 << 7) /* DMA Requests Enable */
330 #define IER_UUE (1 << 6) /* UART Unit Enable */
331 #define IER_NRZE (1 << 5) /* NRZ coding Enable */
332 #define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
333 #define IER_MIE (1 << 3) /* Modem Interrupt Enable */
334 #define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
335 #define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
336 #define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
338 #define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
339 #define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
340 #define IIR_TOD (1 << 3) /* Time Out Detected */
341 #define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
342 #define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
343 #define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
345 #define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
346 #define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
347 #define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
348 #define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
349 #define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
350 #define FCR_ITL_1 (0)
351 #define FCR_ITL_8 (FCR_ITL1)
352 #define FCR_ITL_16 (FCR_ITL2)
353 #define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
355 #define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
356 #define LCR_SB (1 << 6) /* Set Break */
357 #define LCR_STKYP (1 << 5) /* Sticky Parity */
358 #define LCR_EPS (1 << 4) /* Even Parity Select */
359 #define LCR_PEN (1 << 3) /* Parity Enable */
360 #define LCR_STB (1 << 2) /* Stop Bit */
361 #define LCR_WLS1 (1 << 1) /* Word Length Select */
362 #define LCR_WLS0 (1 << 0) /* Word Length Select */
364 #define LSR_FIFOE (1 << 7) /* FIFO Error Status */
365 #define LSR_TEMT (1 << 6) /* Transmitter Empty */
366 #define LSR_TDRQ (1 << 5) /* Transmit Data Request */
367 #define LSR_BI (1 << 4) /* Break Interrupt */
368 #define LSR_FE (1 << 3) /* Framing Error */
369 #define LSR_PE (1 << 2) /* Parity Error */
370 #define LSR_OE (1 << 1) /* Overrun Error */
371 #define LSR_DR (1 << 0) /* Data Ready */
373 #define MCR_LOOP (1 << 4)
374 #define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
375 #define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
376 #define MCR_RTS (1 << 1) /* Request to Send */
377 #define MCR_DTR (1 << 0) /* Data Terminal Ready */
379 #define MSR_DCD (1 << 7) /* Data Carrier Detect */
380 #define MSR_RI (1 << 6) /* Ring Indicator */
381 #define MSR_DSR (1 << 5) /* Data Set Ready */
382 #define MSR_CTS (1 << 4) /* Clear To Send */
383 #define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
384 #define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
385 #define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
386 #define MSR_DCTS (1 << 0) /* Delta Clear To Send */
389 * IrSR (Infrared Selection Register)
391 #define STISR_RXPL (1 << 4) /* Receive Data Polarity */
392 #define STISR_TXPL (1 << 3) /* Transmit Data Polarity */
393 #define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */
394 #define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */
395 #define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */
402 #define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */
403 #define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */
404 #define ICR __REG(0x40301690) /* I2C Control Register - ICR */
405 #define ISR __REG(0x40301698) /* I2C Status Register - ISR */
406 #define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
408 #define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */
409 #define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */
410 #define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */
411 #define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */
412 #define PWRISAR __REG(0x40f001A0) /*Power I2C Slave Address Register-ISAR */
414 #define ICR_START (1 << 0) /* start bit */
415 #define ICR_STOP (1 << 1) /* stop bit */
416 #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
417 #define ICR_TB (1 << 3) /* transfer byte bit */
418 #define ICR_MA (1 << 4) /* master abort */
419 #define ICR_SCLE (1 << 5) /* master clock enable */
420 #define ICR_IUE (1 << 6) /* unit enable */
421 #define ICR_GCD (1 << 7) /* general call disable */
422 #define ICR_ITEIE (1 << 8) /* enable tx interrupts */
423 #define ICR_IRFIE (1 << 9) /* enable rx interrupts */
424 #define ICR_BEIE (1 << 10) /* enable bus error ints */
425 #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
426 #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
427 #define ICR_SADIE (1 << 13) /* slave address detected int enable */
428 #define ICR_UR (1 << 14) /* unit reset */
430 #define ISR_RWM (1 << 0) /* read/write mode */
431 #define ISR_ACKNAK (1 << 1) /* ack/nak status */
432 #define ISR_UB (1 << 2) /* unit busy */
433 #define ISR_IBB (1 << 3) /* bus busy */
434 #define ISR_SSD (1 << 4) /* slave stop detected */
435 #define ISR_ALD (1 << 5) /* arbitration loss detected */
436 #define ISR_ITE (1 << 6) /* tx buffer empty */
437 #define ISR_IRF (1 << 7) /* rx buffer full */
438 #define ISR_GCAD (1 << 8) /* general call address detected */
439 #define ISR_SAD (1 << 9) /* slave address detected */
440 #define ISR_BED (1 << 10) /* bus error no ACK/NAK */
444 * Serial Audio Controller
447 /* FIXME: This clash with SA1111 defines */
448 #ifndef _ASM_ARCH_SA1111
450 #define SACR0 __REG(0x40400000) /* Global Control Register */
451 #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
452 #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
453 #define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */
454 #define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */
455 #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
456 #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
458 #define SACR0_RFTH(x) (x << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */
459 #define SACR0_TFTH(x) (x << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */
460 #define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */
461 #define SACR0_EFWR (1 << 4) /* Enable EFWR Function */
462 #define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */
463 #define SACR0_BCKD (1 << 2) /* Bit Clock Direction */
464 #define SACR0_ENB (1 << 0) /* Enable I2S Link */
465 #define SACR1_ENLBF (1 << 5) /* Enable Loopback */
466 #define SACR1_DRPL (1 << 4) /* Disable Replaying Function */
467 #define SACR1_DREC (1 << 3) /* Disable Recording Function */
468 #define SACR1_AMSL (1 << 1) /* Specify Alternate Mode */
470 #define SASR0_I2SOFF (1 << 7) /* Controller Status */
471 #define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */
472 #define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */
473 #define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */
474 #define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */
475 #define SASR0_BSY (1 << 2) /* I2S Busy */
476 #define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */
477 #define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */
479 #define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */
480 #define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */
482 #define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */
483 #define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */
484 #define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */
485 #define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */
490 * AC97 Controller registers
493 #define POCR __REG(0x40500000) /* PCM Out Control Register */
494 #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
495 #define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
497 #define PICR __REG(0x40500004) /* PCM In Control Register */
498 #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
499 #define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
501 #define MCCR __REG(0x40500008) /* Mic In Control Register */
502 #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
503 #define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
505 #define GCR __REG(0x4050000C) /* Global Control Register */
506 #define GCR_nDMAEN (1 << 24) /* non DMA Enable */
507 #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
508 #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
509 #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
510 #define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
511 #define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
512 #define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
513 #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
514 #define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
515 #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
516 #define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
518 #define POSR __REG(0x40500010) /* PCM Out Status Register */
519 #define POSR_FIFOE (1 << 4) /* FIFO error */
520 #define POSR_FSR (1 << 2) /* FIFO Service Request */
522 #define PISR __REG(0x40500014) /* PCM In Status Register */
523 #define PISR_FIFOE (1 << 4) /* FIFO error */
524 #define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
525 #define PISR_FSR (1 << 2) /* FIFO Service Request */
527 #define MCSR __REG(0x40500018) /* Mic In Status Register */
528 #define MCSR_FIFOE (1 << 4) /* FIFO error */
529 #define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
530 #define MCSR_FSR (1 << 2) /* FIFO Service Request */
532 #define GSR __REG(0x4050001C) /* Global Status Register */
533 #define GSR_CDONE (1 << 19) /* Command Done */
534 #define GSR_SDONE (1 << 18) /* Status Done */
535 #define GSR_RDCS (1 << 15) /* Read Completion Status */
536 #define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
537 #define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
538 #define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
539 #define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
540 #define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
541 #define GSR_SCR (1 << 9) /* Secondary Codec Ready */
542 #define GSR_PCR (1 << 8) /* Primary Codec Ready */
543 #define GSR_MCINT (1 << 7) /* Mic In Interrupt */
544 #define GSR_POINT (1 << 6) /* PCM Out Interrupt */
545 #define GSR_PIINT (1 << 5) /* PCM In Interrupt */
546 #define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */
547 #define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
548 #define GSR_MIINT (1 << 1) /* Modem In Interrupt */
549 #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
551 #define CAR __REG(0x40500020) /* CODEC Access Register */
552 #define CAR_CAIP (1 << 0) /* Codec Access In Progress */
554 #define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
555 #define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
557 #define MOCR __REG(0x40500100) /* Modem Out Control Register */
558 #define MOCR_FEIE (1 << 3) /* FIFO Error */
559 #define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
561 #define MICR __REG(0x40500108) /* Modem In Control Register */
562 #define MICR_FEIE (1 << 3) /* FIFO Error */
563 #define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
565 #define MOSR __REG(0x40500110) /* Modem Out Status Register */
566 #define MOSR_FIFOE (1 << 4) /* FIFO error */
567 #define MOSR_FSR (1 << 2) /* FIFO Service Request */
569 #define MISR __REG(0x40500118) /* Modem In Status Register */
570 #define MISR_FIFOE (1 << 4) /* FIFO error */
571 #define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
572 #define MISR_FSR (1 << 2) /* FIFO Service Request */
574 #define MODR __REG(0x40500140) /* Modem FIFO Data Register */
576 #define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
577 #define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
578 #define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
579 #define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
583 * USB Device Controller
584 * PXA25x and PXA27x USB device controller registers are different.
586 #if defined(CONFIG_PXA25x)
588 #define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
589 #define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
590 #define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
592 #define UDCCR __REG(0x40600000) /* UDC Control Register */
593 #define UDCCR_UDE (1 << 0) /* UDC enable */
594 #define UDCCR_UDA (1 << 1) /* UDC active */
595 #define UDCCR_RSM (1 << 2) /* Device resume */
596 #define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
597 #define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
598 #define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
599 #define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
600 #define UDCCR_REM (1 << 7) /* Reset interrupt mask */
602 #define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
603 #define UDCCS0_OPR (1 << 0) /* OUT packet ready */
604 #define UDCCS0_IPR (1 << 1) /* IN packet ready */
605 #define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
606 #define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
607 #define UDCCS0_SST (1 << 4) /* Sent stall */
608 #define UDCCS0_FST (1 << 5) /* Force stall */
609 #define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
610 #define UDCCS0_SA (1 << 7) /* Setup active */
612 /* Bulk IN - Endpoint 1,6,11 */
613 #define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
614 #define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
615 #define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
617 #define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
618 #define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
619 #define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
620 #define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
621 #define UDCCS_BI_SST (1 << 4) /* Sent stall */
622 #define UDCCS_BI_FST (1 << 5) /* Force stall */
623 #define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
625 /* Bulk OUT - Endpoint 2,7,12 */
626 #define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
627 #define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
628 #define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
630 #define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
631 #define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
632 #define UDCCS_BO_DME (1 << 3) /* DMA enable */
633 #define UDCCS_BO_SST (1 << 4) /* Sent stall */
634 #define UDCCS_BO_FST (1 << 5) /* Force stall */
635 #define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
636 #define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
638 /* Isochronous IN - Endpoint 3,8,13 */
639 #define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
640 #define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
641 #define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
643 #define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
644 #define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
645 #define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
646 #define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
647 #define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
649 /* Isochronous OUT - Endpoint 4,9,14 */
650 #define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
651 #define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
652 #define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
654 #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
655 #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
656 #define UDCCS_IO_ROF (1 << 2) /* Receive overflow */
657 #define UDCCS_IO_DME (1 << 3) /* DMA enable */
658 #define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
659 #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
661 /* Interrupt IN - Endpoint 5,10,15 */
662 #define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
663 #define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
664 #define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
666 #define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
667 #define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
668 #define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
669 #define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
670 #define UDCCS_INT_SST (1 << 4) /* Sent stall */
671 #define UDCCS_INT_FST (1 << 5) /* Force stall */
672 #define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
674 #define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
675 #define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
676 #define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
677 #define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
678 #define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
679 #define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
680 #define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
681 #define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
682 #define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
683 #define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
684 #define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
685 #define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
686 #define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
687 #define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
688 #define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
689 #define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
690 #define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
691 #define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
692 #define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
693 #define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
694 #define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
695 #define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
696 #define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
697 #define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
699 #define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
701 #define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
702 #define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
703 #define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
704 #define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
705 #define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
706 #define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
707 #define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
708 #define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
710 #define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
712 #define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
713 #define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
714 #define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
715 #define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
716 #define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
717 #define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
718 #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
719 #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
721 #define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
723 #define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */
724 #define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */
725 #define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */
726 #define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */
727 #define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */
728 #define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */
729 #define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */
730 #define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */
732 #define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
734 #define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */
735 #define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */
736 #define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */
737 #define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */
738 #define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */
739 #define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */
740 #define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */
741 #define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
743 #elif defined(CONFIG_PXA27x)
745 #define UDCCR __REG(0x40600000) /* UDC Control Register */
746 #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
747 #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
748 Protocol Port Support */
749 #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
751 #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
753 #define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
754 #define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
755 #define UDCCR_ACN_S 11
756 #define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
757 #define UDCCR_AIN_S 8
758 #define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
760 #define UDCCR_AAISN_S 5
761 #define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
763 #define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
765 #define UDCCR_UDR (1 << 2) /* UDC Resume */
766 #define UDCCR_UDA (1 << 1) /* UDC Active */
767 #define UDCCR_UDE (1 << 0) /* UDC Enable */
769 #define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
770 #define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
771 #define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
772 #define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
774 #define UDC_INT_FIFOERROR (0x2)
775 #define UDC_INT_PACKETCMP (0x1)
777 #define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
778 #define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
779 #define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
780 #define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
781 #define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
782 #define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
784 #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
785 #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
786 #define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
787 #define UDCISR1_IECC (1 << 31) /* IntEn - Configuration Change */
788 #define UDCISR1_IESOF (1 << 30) /* IntEn - Start of Frame */
789 #define UDCISR1_IERU (1 << 29) /* IntEn - Resume */
790 #define UDCISR1_IESU (1 << 28) /* IntEn - Suspend */
791 #define UDCISR1_IERS (1 << 27) /* IntEn - Reset */
794 #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
795 #define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
796 #define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
797 #define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt
798 Rising Edge Interrupt Enable */
799 #define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt
800 Falling Edge Interrupt Enable */
801 #define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
803 #define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
805 #define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
807 #define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
809 #define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
811 #define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
813 #define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
814 Edge Interrupt Enable */
815 #define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
816 Edge Interrupt Enable */
817 #define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
819 #define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
822 #define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
824 #define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
825 #define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
826 #define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */
827 #define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */
828 #define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */
829 #define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */
830 #define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
831 #define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
832 #define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
833 #define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
834 #define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
835 #define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */
836 #define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
837 #define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
839 #define UDCCSN(x) __REG2(0x40600100, (x) << 2)
840 #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
841 #define UDCCSR0_SA (1 << 7) /* Setup Active */
842 #define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
843 #define UDCCSR0_FST (1 << 5) /* Force Stall */
844 #define UDCCSR0_SST (1 << 4) /* Sent Stall */
845 #define UDCCSR0_DME (1 << 3) /* DMA Enable */
846 #define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
847 #define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
848 #define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
850 #define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
851 #define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
852 #define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
853 #define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
854 #define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
855 #define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
856 #define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
857 #define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
858 #define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
859 #define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
860 #define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
861 #define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
862 #define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
863 #define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
864 #define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
865 #define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
866 #define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
867 #define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
868 #define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
869 #define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
870 #define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
871 #define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
872 #define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
874 #define UDCCSR_DPE (1 << 9) /* Data Packet Error */
875 #define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
876 #define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
877 #define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
878 #define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
879 #define UDCCSR_FST (1 << 5) /* Force STALL */
880 #define UDCCSR_SST (1 << 4) /* Sent STALL */
881 #define UDCCSR_DME (1 << 3) /* DMA Enable */
882 #define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
883 #define UDCCSR_PC (1 << 1) /* Packet Complete */
884 #define UDCCSR_FS (1 << 0) /* FIFO needs service */
886 #define UDCBCN(x) __REG2(0x40600200, (x)<<2)
887 #define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
888 #define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
889 #define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
890 #define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
891 #define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
892 #define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
893 #define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
894 #define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
895 #define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
896 #define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
897 #define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
898 #define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
899 #define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
900 #define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
901 #define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
902 #define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
903 #define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
904 #define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
905 #define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
906 #define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
907 #define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
908 #define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
909 #define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
910 #define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
912 #define UDCDN(x) __REG2(0x40600300, (x)<<2)
913 #define PHYS_UDCDN(x) (0x40600300 + ((x)<<2))
914 #define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
915 #define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
916 #define UDCDRA __REG(0x40600304) /* Data Register - EPA */
917 #define UDCDRB __REG(0x40600308) /* Data Register - EPB */
918 #define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
919 #define UDCDRD __REG(0x40600310) /* Data Register - EPD */
920 #define UDCDRE __REG(0x40600314) /* Data Register - EPE */
921 #define UDCDRF __REG(0x40600318) /* Data Register - EPF */
922 #define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
923 #define UDCDRH __REG(0x40600320) /* Data Register - EPH */
924 #define UDCDRI __REG(0x40600324) /* Data Register - EPI */
925 #define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
926 #define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
927 #define UDCDRL __REG(0x40600330) /* Data Register - EPL */
928 #define UDCDRM __REG(0x40600334) /* Data Register - EPM */
929 #define UDCDRN __REG(0x40600338) /* Data Register - EPN */
930 #define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
931 #define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
932 #define UDCDRR __REG(0x40600344) /* Data Register - EPR */
933 #define UDCDRS __REG(0x40600348) /* Data Register - EPS */
934 #define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
935 #define UDCDRU __REG(0x40600350) /* Data Register - EPU */
936 #define UDCDRV __REG(0x40600354) /* Data Register - EPV */
937 #define UDCDRW __REG(0x40600358) /* Data Register - EPW */
938 #define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
940 #define UDCCN(x) __REG2(0x40600400, (x)<<2)
941 #define UDCCRA __REG(0x40600404) /* Configuration register EPA */
942 #define UDCCRB __REG(0x40600408) /* Configuration register EPB */
943 #define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
944 #define UDCCRD __REG(0x40600410) /* Configuration register EPD */
945 #define UDCCRE __REG(0x40600414) /* Configuration register EPE */
946 #define UDCCRF __REG(0x40600418) /* Configuration register EPF */
947 #define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
948 #define UDCCRH __REG(0x40600420) /* Configuration register EPH */
949 #define UDCCRI __REG(0x40600424) /* Configuration register EPI */
950 #define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
951 #define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
952 #define UDCCRL __REG(0x40600430) /* Configuration register EPL */
953 #define UDCCRM __REG(0x40600434) /* Configuration register EPM */
954 #define UDCCRN __REG(0x40600438) /* Configuration register EPN */
955 #define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
956 #define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
957 #define UDCCRR __REG(0x40600444) /* Configuration register EPR */
958 #define UDCCRS __REG(0x40600448) /* Configuration register EPS */
959 #define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
960 #define UDCCRU __REG(0x40600450) /* Configuration register EPU */
961 #define UDCCRV __REG(0x40600454) /* Configuration register EPV */
962 #define UDCCRW __REG(0x40600458) /* Configuration register EPW */
963 #define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
965 #define UDCCONR_CN (0x03 << 25) /* Configuration Number */
966 #define UDCCONR_CN_S (25)
967 #define UDCCONR_IN (0x07 << 22) /* Interface Number */
968 #define UDCCONR_IN_S (22)
969 #define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
970 #define UDCCONR_AISN_S (19)
971 #define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
972 #define UDCCONR_EN_S (15)
973 #define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
974 #define UDCCONR_ET_S (13)
975 #define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
976 #define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
977 #define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
978 #define UDCCONR_ET_NU (0x00 << 13) /* Not used */
979 #define UDCCONR_ED (1 << 12) /* Endpoint Direction */
980 #define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
981 #define UDCCONR_MPS_S (2)
982 #define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
983 #define UDCCONR_EE (1 << 0) /* Endpoint Enable */
986 #define UDC_INT_FIFOERROR (0x2)
987 #define UDC_INT_PACKETCMP (0x1)
989 #define UDC_FNR_MASK (0x7ff)
991 #define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
992 #define UDC_BCR_MASK (0x3ff)
996 * Fast Infrared Communication Port
999 #define FICP __REG(0x40800000) /* Start of FICP area */
1000 #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
1001 #define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
1002 #define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
1003 #define ICDR __REG(0x4080000c) /* ICP Data Register */
1004 #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
1005 #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
1007 #define ICCR0_AME (1 << 7) /* Adress match enable */
1008 #define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */
1009 #define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */
1010 #define ICCR0_RXE (1 << 4) /* Receive enable */
1011 #define ICCR0_TXE (1 << 3) /* Transmit enable */
1012 #define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */
1013 #define ICCR0_LBM (1 << 1) /* Loopback mode */
1014 #define ICCR0_ITR (1 << 0) /* IrDA transmission */
1016 #ifdef CONFIG_PXA27x
1017 #define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */
1018 #define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */
1019 #define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */
1020 #define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */
1021 #define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */
1022 #define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */
1025 #ifdef CONFIG_PXA27x
1026 #define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */
1028 #define ICSR0_FRE (1 << 5) /* Framing error */
1029 #define ICSR0_RFS (1 << 4) /* Receive FIFO service request */
1030 #define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */
1031 #define ICSR0_RAB (1 << 2) /* Receiver abort */
1032 #define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */
1033 #define ICSR0_EIF (1 << 0) /* End/Error in FIFO */
1035 #define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */
1036 #define ICSR1_CRE (1 << 5) /* CRC error */
1037 #define ICSR1_EOF (1 << 4) /* End of frame */
1038 #define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */
1039 #define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */
1040 #define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */
1041 #define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */
1048 #define RCNR __REG(0x40900000) /* RTC Count Register */
1049 #define RTAR __REG(0x40900004) /* RTC Alarm Register */
1050 #define RTSR __REG(0x40900008) /* RTC Status Register */
1051 #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
1052 #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
1054 #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
1055 #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
1056 #define RTSR_HZE (1 << 3) /* HZ interrupt enable */
1057 #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
1058 #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
1059 #define RTSR_AL (1 << 0) /* RTC alarm detected */
1063 * OS Timer & Match Registers
1066 #define OSMR0 __REG(0x40A00000) /* */
1067 #define OSMR1 __REG(0x40A00004) /* */
1068 #define OSMR2 __REG(0x40A00008) /* */
1069 #define OSMR3 __REG(0x40A0000C) /* */
1070 #define OSMR4 __REG(0x40A00080) /* */
1071 #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
1072 #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
1073 #define OMCR4 __REG(0x40A000C0) /* */
1074 #define OSSR __REG(0x40A00014) /* OS Timer Status Register */
1075 #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
1076 #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
1078 #define OSSR_M3 (1 << 3) /* Match status channel 3 */
1079 #define OSSR_M2 (1 << 2) /* Match status channel 2 */
1080 #define OSSR_M1 (1 << 1) /* Match status channel 1 */
1081 #define OSSR_M0 (1 << 0) /* Match status channel 0 */
1083 #define OWER_WME (1 << 0) /* Watchdog Match Enable */
1085 #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
1086 #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
1087 #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
1088 #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
1092 * Pulse Width Modulator
1095 #define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */
1096 #define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */
1097 #define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */
1099 #define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */
1100 #define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */
1101 #define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */
1105 * Interrupt Controller
1108 #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
1109 #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
1110 #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
1111 #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
1112 #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
1113 #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
1117 * General Purpose I/O
1120 #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */
1121 #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */
1122 #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */
1124 #define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */
1125 #define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */
1126 #define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */
1128 #define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */
1129 #define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */
1130 #define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */
1132 #define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */
1133 #define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */
1134 #define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */
1136 #define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */
1137 #define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */
1138 #define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */
1140 #define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
1141 #define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */
1142 #define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */
1144 #define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */
1145 #define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */
1146 #define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */
1148 #define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */
1149 #define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */
1150 #define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */
1151 #define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */
1152 #define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */
1153 #define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO<95-80> */
1154 #define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */
1155 #define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */
1157 #define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
1158 #define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
1159 #define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
1160 #define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */
1161 #define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
1162 #define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */
1163 #define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
1165 /* More handy macros. The argument is a literal GPIO number. */
1167 #define GPIO_bit(x) (1 << ((x) & 0x1f))
1169 #ifdef CONFIG_PXA27x
1171 /* Interrupt Controller */
1173 #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
1174 #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
1175 #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
1176 #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
1177 #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
1179 #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
1180 #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
1181 #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
1182 #define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
1183 #define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
1184 #define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
1185 #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
1186 #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
1188 #define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
1189 #define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
1190 #define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
1191 #define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
1192 #define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
1193 #define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
1194 #define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
1195 #define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
1196 ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
1199 #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
1200 #define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
1201 #define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
1202 #define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
1203 #define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
1204 #define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
1205 #define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
1206 #define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
1211 /* GPIO alternate function assignments */
1213 #define GPIO1_RST 1 /* reset */
1214 #define GPIO6_MMCCLK 6 /* MMC Clock */
1215 #define GPIO7_48MHz 7 /* 48 MHz clock output */
1216 #define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */
1217 #define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */
1218 #define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */
1219 #define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */
1220 #define GPIO12_32KHz 12 /* 32 kHz out */
1221 #define GPIO13_MBGNT 13 /* memory controller grant */
1222 #define GPIO14_MBREQ 14 /* alternate bus master request */
1223 #define GPIO15_nCS_1 15 /* chip select 1 */
1224 #define GPIO16_PWM0 16 /* PWM0 output */
1225 #define GPIO17_PWM1 17 /* PWM1 output */
1226 #define GPIO18_RDY 18 /* Ext. Bus Ready */
1227 #define GPIO19_DREQ1 19 /* External DMA Request */
1228 #define GPIO20_DREQ0 20 /* External DMA Request */
1229 #define GPIO23_SCLK 23 /* SSP clock */
1230 #define GPIO24_SFRM 24 /* SSP Frame */
1231 #define GPIO25_STXD 25 /* SSP transmit */
1232 #define GPIO26_SRXD 26 /* SSP receive */
1233 #define GPIO27_SEXTCLK 27 /* SSP ext_clk */
1234 #define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */
1235 #define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */
1236 #define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */
1237 #define GPIO31_SYNC 31 /* AC97/I2S sync */
1238 #define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */
1239 #define GPIO32_SYSCLK 32 /* I2S System Clock */
1240 #define GPIO32_MMCCLK 32 /* MMC Clock (PXA270) */
1241 #define GPIO33_nCS_5 33 /* chip select 5 */
1242 #define GPIO34_FFRXD 34 /* FFUART receive */
1243 #define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */
1244 #define GPIO35_FFCTS 35 /* FFUART Clear to send */
1245 #define GPIO36_FFDCD 36 /* FFUART Data carrier detect */
1246 #define GPIO37_FFDSR 37 /* FFUART data set ready */
1247 #define GPIO38_FFRI 38 /* FFUART Ring Indicator */
1248 #define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */
1249 #define GPIO39_FFTXD 39 /* FFUART transmit data */
1250 #define GPIO40_FFDTR 40 /* FFUART data terminal Ready */
1251 #define GPIO41_FFRTS 41 /* FFUART request to send */
1252 #define GPIO42_BTRXD 42 /* BTUART receive data */
1253 #define GPIO43_BTTXD 43 /* BTUART transmit data */
1254 #define GPIO44_BTCTS 44 /* BTUART clear to send */
1255 #define GPIO45_BTRTS 45 /* BTUART request to send */
1256 #define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */
1257 #define GPIO46_ICPRXD 46 /* ICP receive data */
1258 #define GPIO46_STRXD 46 /* STD_UART receive data */
1259 #define GPIO47_ICPTXD 47 /* ICP transmit data */
1260 #define GPIO47_STTXD 47 /* STD_UART transmit data */
1261 #define GPIO48_nPOE 48 /* Output Enable for Card Space */
1262 #define GPIO49_nPWE 49 /* Write Enable for Card Space */
1263 #define GPIO50_nPIOR 50 /* I/O Read for Card Space */
1264 #define GPIO51_nPIOW 51 /* I/O Write for Card Space */
1265 #define GPIO52_nPCE_1 52 /* Card Enable for Card Space */
1266 #define GPIO53_nPCE_2 53 /* Card Enable for Card Space */
1267 #define GPIO53_MMCCLK 53 /* MMC Clock */
1268 #define GPIO54_MMCCLK 54 /* MMC Clock */
1269 #define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */
1270 #define GPIO54_nPCE_2 54 /* Card Enable for Card Space (PXA27x) */
1271 #define GPIO55_nPREG 55 /* Card Address bit 26 */
1272 #define GPIO56_nPWAIT 56 /* Wait signal for Card Space */
1273 #define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */
1274 #define GPIO58_LDD_0 58 /* LCD data pin 0 */
1275 #define GPIO59_LDD_1 59 /* LCD data pin 1 */
1276 #define GPIO60_LDD_2 60 /* LCD data pin 2 */
1277 #define GPIO61_LDD_3 61 /* LCD data pin 3 */
1278 #define GPIO62_LDD_4 62 /* LCD data pin 4 */
1279 #define GPIO63_LDD_5 63 /* LCD data pin 5 */
1280 #define GPIO64_LDD_6 64 /* LCD data pin 6 */
1281 #define GPIO65_LDD_7 65 /* LCD data pin 7 */
1282 #define GPIO66_LDD_8 66 /* LCD data pin 8 */
1283 #define GPIO66_MBREQ 66 /* alternate bus master req */
1284 #define GPIO67_LDD_9 67 /* LCD data pin 9 */
1285 #define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */
1286 #define GPIO68_LDD_10 68 /* LCD data pin 10 */
1287 #define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */
1288 #define GPIO69_LDD_11 69 /* LCD data pin 11 */
1289 #define GPIO69_MMCCLK 69 /* MMC_CLK */
1290 #define GPIO70_LDD_12 70 /* LCD data pin 12 */
1291 #define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */
1292 #define GPIO71_LDD_13 71 /* LCD data pin 13 */
1293 #define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */
1294 #define GPIO72_LDD_14 72 /* LCD data pin 14 */
1295 #define GPIO72_32kHz 72 /* 32 kHz clock */
1296 #define GPIO73_LDD_15 73 /* LCD data pin 15 */
1297 #define GPIO73_MBGNT 73 /* Memory controller grant */
1298 #define GPIO74_LCD_FCLK 74 /* LCD Frame clock */
1299 #define GPIO75_LCD_LCLK 75 /* LCD line clock */
1300 #define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */
1301 #define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */
1302 #define GPIO78_nCS_2 78 /* chip select 2 */
1303 #define GPIO79_nCS_3 79 /* chip select 3 */
1304 #define GPIO80_nCS_4 80 /* chip select 4 */
1305 #define GPIO81_NSCLK 81 /* NSSP clock */
1306 #define GPIO82_NSFRM 82 /* NSSP Frame */
1307 #define GPIO83_NSTXD 83 /* NSSP transmit */
1308 #define GPIO84_NSRXD 84 /* NSSP receive */
1309 #define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */
1310 #define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */
1311 #define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */
1312 #define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */
1313 #define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */
1314 #define GPIO111_MMCDAT3 111 /* MMC DAT3 (PXA27x) */
1315 #define GPIO111_MMCCS1 111 /* MMC Chip Select 1 (PXA27x) */
1316 #define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */
1317 #define GPIO113_I2S_SYSCLK 113 /* I2S System Clock (PXA27x) */
1318 #define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) */
1320 /* GPIO alternate function mode & direction */
1322 #define GPIO_IN 0x000
1323 #define GPIO_OUT 0x080
1324 #define GPIO_ALT_FN_1_IN 0x100
1325 #define GPIO_ALT_FN_1_OUT 0x180
1326 #define GPIO_ALT_FN_2_IN 0x200
1327 #define GPIO_ALT_FN_2_OUT 0x280
1328 #define GPIO_ALT_FN_3_IN 0x300
1329 #define GPIO_ALT_FN_3_OUT 0x380
1330 #define GPIO_MD_MASK_NR 0x07f
1331 #define GPIO_MD_MASK_DIR 0x080
1332 #define GPIO_MD_MASK_FN 0x300
1333 #define GPIO_DFLT_LOW 0x400
1334 #define GPIO_DFLT_HIGH 0x800
1336 #define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN)
1337 #define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT)
1338 #define GPIO7_48MHz_MD ( 7 | GPIO_ALT_FN_1_OUT)
1339 #define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT)
1340 #define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT)
1341 #define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT)
1342 #define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT)
1343 #define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT)
1344 #define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT)
1345 #define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN)
1346 #define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT)
1347 #define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT)
1348 #define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT)
1349 #define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN)
1350 #define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN)
1351 #define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN)
1352 #define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT)
1353 #define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT)
1354 #define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT)
1355 #define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN)
1356 #define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN)
1357 #define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN)
1358 #define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN)
1359 #define GPIO28_BITCLK_OUT_I2S_MD (28 | GPIO_ALT_FN_1_OUT)
1360 #define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
1361 #define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN)
1362 #define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT)
1363 #define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
1364 #define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT)
1365 #define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT)
1366 #define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN)
1367 #define GPIO32_SYSCLK_I2S_MD (32 | GPIO_ALT_FN_1_OUT)
1368 #define GPIO32_MMCCLK_MD ( 32 | GPIO_ALT_FN_2_OUT)
1369 #define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT)
1370 #define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN)
1371 #define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT)
1372 #define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN)
1373 #define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN)
1374 #define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN)
1375 #define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN)
1376 #define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT)
1377 #define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT)
1378 #define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT)
1379 #define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
1380 #define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN)
1381 #define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT)
1382 #define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN)
1383 #define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT)
1384 #define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT)
1385 #define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN)
1386 #define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN)
1387 #define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT)
1388 #define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT)
1389 #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
1390 #define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT)
1391 #define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT)
1392 #define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT)
1393 #define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT)
1394 #define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT)
1395 #define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT)
1396 #define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT)
1397 #define GPIO54_nPCE_2_MD (54 | GPIO_ALT_FN_2_OUT)
1398 #define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT)
1399 #define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT)
1400 #define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN)
1401 #define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN)
1402 #define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT)
1403 #define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT)
1404 #define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT)
1405 #define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT)
1406 #define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT)
1407 #define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT)
1408 #define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT)
1409 #define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT)
1410 #define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT)
1411 #define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN)
1412 #define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT)
1413 #define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT)
1414 #define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT)
1415 #define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT)
1416 #define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT)
1417 #define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT)
1418 #define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT)
1419 #define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT)
1420 #define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT)
1421 #define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT)
1422 #define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT)
1423 #define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT)
1424 #define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT)
1425 #define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT)
1426 #define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT)
1427 #define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT)
1428 #define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT)
1429 #define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT)
1430 #define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT)
1431 #define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT)
1432 #define GPIO79_pSKTSEL_MD (79 | GPIO_ALT_FN_1_OUT)
1433 #define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT)
1434 #define GPIO81_NSSP_CLK_OUT (81 | GPIO_ALT_FN_1_OUT)
1435 #define GPIO81_NSSP_CLK_IN (81 | GPIO_ALT_FN_1_IN)
1436 #define GPIO82_NSSP_FRM_OUT (82 | GPIO_ALT_FN_1_OUT)
1437 #define GPIO82_NSSP_FRM_IN (82 | GPIO_ALT_FN_1_IN)
1438 #define GPIO83_NSSP_TX (83 | GPIO_ALT_FN_1_OUT)
1439 #define GPIO83_NSSP_RX (83 | GPIO_ALT_FN_2_IN)
1440 #define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT)
1441 #define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN)
1442 #define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT)
1443 #define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT)
1444 #define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT)
1445 #define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT)
1446 #define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT)
1447 #define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT)
1448 #define GPIO111_MMCDAT3_MD (111 | GPIO_ALT_FN_1_OUT)
1449 #define GPIO110_MMCCS1_MD (111 | GPIO_ALT_FN_1_OUT)
1450 #define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT)
1451 #define GPIO113_I2S_SYSCLK_MD (113 | GPIO_ALT_FN_1_OUT)
1452 #define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT)
1453 #define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_OUT)
1454 #define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN)
1460 #define PMCR __REG(0x40F00000) /* Power Manager Control Register */
1461 #define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
1462 #define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
1463 #define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
1464 #define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
1465 #define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
1466 #define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
1467 #define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
1468 #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
1469 #define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
1470 #define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
1471 #define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
1472 #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
1474 #define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
1475 #define PSTR __REG(0x40F00038) /*Power Manager Standby Config Register */
1476 #define PSNR __REG(0x40F0003C) /*Power Manager Sense Config Register */
1477 #define PVCR __REG(0x40F00040) /*Power Manager VoltageControl Register */
1478 #define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
1479 #define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
1480 #define PCMD(x) __REG2(0x40F00080, (x)<<2)
1481 #define PCMD0 __REG(0x40F00080 + 0 * 4)
1482 #define PCMD1 __REG(0x40F00080 + 1 * 4)
1483 #define PCMD2 __REG(0x40F00080 + 2 * 4)
1484 #define PCMD3 __REG(0x40F00080 + 3 * 4)
1485 #define PCMD4 __REG(0x40F00080 + 4 * 4)
1486 #define PCMD5 __REG(0x40F00080 + 5 * 4)
1487 #define PCMD6 __REG(0x40F00080 + 6 * 4)
1488 #define PCMD7 __REG(0x40F00080 + 7 * 4)
1489 #define PCMD8 __REG(0x40F00080 + 8 * 4)
1490 #define PCMD9 __REG(0x40F00080 + 9 * 4)
1491 #define PCMD10 __REG(0x40F00080 + 10 * 4)
1492 #define PCMD11 __REG(0x40F00080 + 11 * 4)
1493 #define PCMD12 __REG(0x40F00080 + 12 * 4)
1494 #define PCMD13 __REG(0x40F00080 + 13 * 4)
1495 #define PCMD14 __REG(0x40F00080 + 14 * 4)
1496 #define PCMD15 __REG(0x40F00080 + 15 * 4)
1497 #define PCMD16 __REG(0x40F00080 + 16 * 4)
1498 #define PCMD17 __REG(0x40F00080 + 17 * 4)
1499 #define PCMD18 __REG(0x40F00080 + 18 * 4)
1500 #define PCMD19 __REG(0x40F00080 + 19 * 4)
1501 #define PCMD20 __REG(0x40F00080 + 20 * 4)
1502 #define PCMD21 __REG(0x40F00080 + 21 * 4)
1503 #define PCMD22 __REG(0x40F00080 + 22 * 4)
1504 #define PCMD23 __REG(0x40F00080 + 23 * 4)
1505 #define PCMD24 __REG(0x40F00080 + 24 * 4)
1506 #define PCMD25 __REG(0x40F00080 + 25 * 4)
1507 #define PCMD26 __REG(0x40F00080 + 26 * 4)
1508 #define PCMD27 __REG(0x40F00080 + 27 * 4)
1509 #define PCMD28 __REG(0x40F00080 + 28 * 4)
1510 #define PCMD29 __REG(0x40F00080 + 29 * 4)
1511 #define PCMD30 __REG(0x40F00080 + 30 * 4)
1512 #define PCMD31 __REG(0x40F00080 + 31 * 4)
1514 #define PCMD_MBC (1<<12)
1515 #define PCMD_DCE (1<<11)
1516 #define PCMD_LC (1<<10)
1517 /* FIXME: PCMD_SQC need be checked. */
1518 #define PCMD_SQC (3<<8) /* currently only bit 8 is changeable,
1519 bit 9 should be 0 all day. */
1520 #define PVCR_VCSA (0x1<<14)
1521 #define PVCR_CommandDelay (0xf80)
1522 #define PCFR_PI2C_EN (0x1 << 6)
1524 #define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
1525 #define PSSR_RDH (1 << 5) /* Read Disable Hold */
1526 #define PSSR_PH (1 << 4) /* Peripheral Control Hold */
1527 #define PSSR_STS (1 << 3) /* Standby Mode Status */
1528 #define PSSR_VFS (1 << 2) /* VDD Fault Status */
1529 #define PSSR_BFS (1 << 1) /* Battery Fault Status */
1530 #define PSSR_SSS (1 << 0) /* Software Sleep Status */
1532 #define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
1534 #define PCFR_RO (1 << 15) /* RDH Override */
1535 #define PCFR_PO (1 << 14) /* PH Override */
1536 #define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
1537 #define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
1538 #define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
1539 #define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
1540 #define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
1541 #define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */
1542 #define PCFR_DS (1 << 3) /* Deep Sleep Mode */
1543 #define PCFR_FS (1 << 2) /* Float Static Chip Selects */
1544 #define PCFR_FP (1 << 1) /* Float PCMCIA controls */
1545 #define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
1547 #define RCSR_GPR (1 << 3) /* GPIO Reset */
1548 #define RCSR_SMR (1 << 2) /* Sleep Mode */
1549 #define RCSR_WDR (1 << 1) /* Watchdog Reset */
1550 #define RCSR_HWR (1 << 0) /* Hardware Reset */
1552 #define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */
1553 #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
1554 #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
1555 #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
1556 #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
1557 #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
1558 #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
1559 #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
1560 #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
1561 #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
1562 #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
1563 #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
1564 #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
1565 #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
1566 #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
1567 #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
1568 #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
1569 #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
1573 * SSP Serial Port Registers
1574 * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
1575 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
1578 /* Common PXA2xx bits first */
1579 #define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
1580 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
1581 #define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
1582 #define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
1583 #define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
1584 #define SSCR0_National (0x2 << 4) /* National Microwire */
1585 #define SSCR0_ECS (1 << 6) /* External clock select */
1586 #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
1587 #define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
1588 #define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
1590 #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
1591 #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
1592 #define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
1593 #define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
1594 #define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
1595 #define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
1596 #define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
1597 #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
1598 #define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
1599 #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
1601 #define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
1602 #define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
1603 #define SSSR_BSY (1 << 4) /* SSP Busy */
1604 #define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
1605 #define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
1606 #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
1608 #define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */
1609 #define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */
1610 #define SSCR0_NCS (1 << 21) /* Network Clock Select */
1611 #define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */
1613 /* extra bits in PXA255, PXA26x and PXA27x SSP ports */
1614 #define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
1615 #define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
1616 #define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
1617 #define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
1618 #define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
1619 #define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
1620 #define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
1621 #define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
1622 #define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
1623 #define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
1624 #define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
1625 #define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
1626 #define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
1627 #define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
1628 #define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */
1629 #define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
1630 #define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
1632 #define SSSR_BCE (1 << 23) /* Bit Count Error */
1633 #define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
1634 #define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
1635 #define SSSR_EOC (1 << 20) /* End Of Chain */
1636 #define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
1637 #define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
1639 #define SSPSP_DMYSTOP(x) (x << 23) /* Dummy Stop */
1640 #define SSPSP_SFRMWDTH(x) (x << 16) /* Serial Frame Width */
1641 #define SSPSP_SFRMDLY(x) (x << 9) /* Serial Frame Delay */
1642 #define SSPSP_DMYSTRT(x) (x << 7) /* Dummy Start */
1643 #define SSPSP_STRTDLY(x) (x << 4) /* Start Delay */
1644 #define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
1645 #define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
1646 #define SSPSP_SCMODE(x) (x << 0) /* Serial Bit Rate Clock Mode */
1649 #define SSCR0_P1 __REG(0x41000000) /* SSP Port 1 Control Register 0 */
1650 #define SSCR1_P1 __REG(0x41000004) /* SSP Port 1 Control Register 1 */
1651 #define SSSR_P1 __REG(0x41000008) /* SSP Port 1 Status Register */
1652 #define SSITR_P1 __REG(0x4100000C) /* SSP Port 1 Interrupt Test Register */
1653 #define SSDR_P1 __REG(0x41000010) /* (Write / Read) SSP Port 1 Data Write Register/SSP Data Read Register */
1655 /* Support existing PXA25x drivers */
1656 #define SSCR0 SSCR0_P1 /* SSP Control Register 0 */
1657 #define SSCR1 SSCR1_P1 /* SSP Control Register 1 */
1658 #define SSSR SSSR_P1 /* SSP Status Register */
1659 #define SSITR SSITR_P1 /* SSP Interrupt Test Register */
1660 #define SSDR SSDR_P1 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
1663 #if defined (CONFIG_PXA27x)
1664 #define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
1665 #define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
1666 #define SSCR0_P2 __REG(0x41700000) /* SSP Port 2 Control Register 0 */
1667 #define SSCR1_P2 __REG(0x41700004) /* SSP Port 2 Control Register 1 */
1668 #define SSSR_P2 __REG(0x41700008) /* SSP Port 2 Status Register */
1669 #define SSITR_P2 __REG(0x4170000C) /* SSP Port 2 Interrupt Test Register */
1670 #define SSDR_P2 __REG(0x41700010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
1671 #define SSTO_P2 __REG(0x41700028) /* SSP Port 2 Time Out Register */
1672 #define SSPSP_P2 __REG(0x4170002C) /* SSP Port 2 Programmable Serial Protocol */
1673 #define SSCR0_P3 __REG(0x41900000) /* SSP Port 3 Control Register 0 */
1674 #define SSCR1_P3 __REG(0x41900004) /* SSP Port 3 Control Register 1 */
1675 #define SSSR_P3 __REG(0x41900008) /* SSP Port 3 Status Register */
1676 #define SSITR_P3 __REG(0x4190000C) /* SSP Port 3 Interrupt Test Register */
1677 #define SSDR_P3 __REG(0x41900010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
1678 #define SSTO_P3 __REG(0x41900028) /* SSP Port 3 Time Out Register */
1679 #define SSPSP_P3 __REG(0x4190002C) /* SSP Port 3 Programmable Serial Protocol */
1680 #else /* PXA255 (only port 2) and PXA26x ports*/
1681 #define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
1682 #define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
1683 #define SSCR0_P2 __REG(0x41400000) /* SSP Port 2 Control Register 0 */
1684 #define SSCR1_P2 __REG(0x41400004) /* SSP Port 2 Control Register 1 */
1685 #define SSSR_P2 __REG(0x41400008) /* SSP Port 2 Status Register */
1686 #define SSITR_P2 __REG(0x4140000C) /* SSP Port 2 Interrupt Test Register */
1687 #define SSDR_P2 __REG(0x41400010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
1688 #define SSTO_P2 __REG(0x41400028) /* SSP Port 2 Time Out Register */
1689 #define SSPSP_P2 __REG(0x4140002C) /* SSP Port 2 Programmable Serial Protocol */
1690 #define SSCR0_P3 __REG(0x41500000) /* SSP Port 3 Control Register 0 */
1691 #define SSCR1_P3 __REG(0x41500004) /* SSP Port 3 Control Register 1 */
1692 #define SSSR_P3 __REG(0x41500008) /* SSP Port 3 Status Register */
1693 #define SSITR_P3 __REG(0x4150000C) /* SSP Port 3 Interrupt Test Register */
1694 #define SSDR_P3 __REG(0x41500010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
1695 #define SSTO_P3 __REG(0x41500028) /* SSP Port 3 Time Out Register */
1696 #define SSPSP_P3 __REG(0x4150002C) /* SSP Port 3 Programmable Serial Protocol */
1699 #define SSCR0_P(x) (*(((x) == 1) ? &SSCR0_P1 : ((x) == 2) ? &SSCR0_P2 : ((x) == 3) ? &SSCR0_P3 : NULL))
1700 #define SSCR1_P(x) (*(((x) == 1) ? &SSCR1_P1 : ((x) == 2) ? &SSCR1_P2 : ((x) == 3) ? &SSCR1_P3 : NULL))
1701 #define SSSR_P(x) (*(((x) == 1) ? &SSSR_P1 : ((x) == 2) ? &SSSR_P2 : ((x) == 3) ? &SSSR_P3 : NULL))
1702 #define SSITR_P(x) (*(((x) == 1) ? &SSITR_P1 : ((x) == 2) ? &SSITR_P2 : ((x) == 3) ? &SSITR_P3 : NULL))
1703 #define SSDR_P(x) (*(((x) == 1) ? &SSDR_P1 : ((x) == 2) ? &SSDR_P2 : ((x) == 3) ? &SSDR_P3 : NULL))
1704 #define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL))
1705 #define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL))
1708 * MultiMediaCard (MMC) controller
1711 #define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */
1712 #define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */
1713 #define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */
1714 #define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */
1715 #define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */
1716 #define MMC_RESTO __REG(0x41100014) /* Expected response time out */
1717 #define MMC_RDTO __REG(0x41100018) /* Expected data read time out */
1718 #define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */
1719 #define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */
1720 #define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */
1721 #define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */
1722 #define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */
1723 #define MMC_CMD __REG(0x41100030) /* Index of current command */
1724 #define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */
1725 #define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */
1726 #define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */
1727 #define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */
1728 #define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */
1735 #define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
1736 #define CKEN __REG(0x41300004) /* Clock Enable Register */
1737 #define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
1738 #define CCSR __REG(0x4130000C) /* Core Clock Status Register */
1740 #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
1741 #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
1742 #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
1744 #define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */
1745 #define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
1746 #define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */
1747 #define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */
1748 #define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */
1749 #define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
1750 #define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */
1751 #define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */
1752 #define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */
1753 #define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */
1754 #define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */
1755 #define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */
1756 #define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */
1757 #define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */
1758 #define CKEN10_ASSP (1 << 10) /* ASSP (SSP3) Clock Enable */
1759 #define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */
1760 #define CKEN9_OSTIMER (1 << 9) /* OS Timer Unit Clock Enable */
1761 #define CKEN9_NSSP (1 << 9) /* NSSP (SSP2) Clock Enable */
1762 #define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */
1763 #define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */
1764 #define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */
1765 #define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */
1766 #define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
1767 #define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */
1768 #define CKEN3_SSP2 (1 << 3) /* SSP2 Unit Clock Enable */
1769 #define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */
1770 #define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */
1771 #define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */
1773 #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
1774 #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
1781 #define LCCR0 __REG(0x44000000) /* LCD Controller Control Register 0 */
1782 #define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */
1783 #define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */
1784 #define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */
1785 #define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
1786 #define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
1787 #define LCSR __REG(0x44000038) /* LCD Controller Status Register */
1788 #define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */
1789 #define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */
1790 #define TMEDCR __REG(0x44000044) /* TMED Control Register */
1792 #define LCCR3_1BPP (0 << 24)
1793 #define LCCR3_2BPP (1 << 24)
1794 #define LCCR3_4BPP (2 << 24)
1795 #define LCCR3_8BPP (3 << 24)
1796 #define LCCR3_16BPP (4 << 24)
1798 #define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */
1799 #define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */
1800 #define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */
1801 #define LDCMD0 __REG(0x4400020C) /* DMA Channel 0 Command Register */
1802 #define FDADR1 __REG(0x44000210) /* DMA Channel 1 Frame Descriptor Address Register */
1803 #define FSADR1 __REG(0x44000214) /* DMA Channel 1 Frame Source Address Register */
1804 #define FIDR1 __REG(0x44000218) /* DMA Channel 1 Frame ID Register */
1805 #define LDCMD1 __REG(0x4400021C) /* DMA Channel 1 Command Register */
1807 #define LCCR0_ENB (1 << 0) /* LCD Controller enable */
1808 #define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */
1809 #define LCCR0_Color (LCCR0_CMS*0) /* Color display */
1810 #define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
1811 #define LCCR0_SDS (1 << 2) /* Single/Dual Panel Display */
1813 #define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
1814 #define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
1816 #define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */
1817 #define LCCR0_SFM (1 << 4) /* Start of frame mask */
1818 #define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */
1819 #define LCCR0_EFM (1 << 6) /* End of Frame mask */
1820 #define LCCR0_PAS (1 << 7) /* Passive/Active display Select */
1821 #define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
1822 #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
1823 #define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome */
1825 #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
1827 #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */
1829 #define LCCR0_DIS (1 << 10) /* LCD Disable */
1830 #define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */
1831 #define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */
1832 #define LCCR0_PDD_S 12
1833 #define LCCR0_BM (1 << 20) /* Branch mask */
1834 #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
1835 #define LCCR0_LCDT (1 << 22) /* LCD panel type */
1836 #define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */
1837 #define LCCR0_CMDIM (1 << 24) /* Command interrupt mask */
1838 #define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */
1839 #define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */
1841 #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
1842 #define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \
1843 (((Pixel) - 1) << FShft (LCCR1_PPL))
1845 #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
1846 #define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
1847 /* pulse Width [1..64 Tpix] */ \
1848 (((Tpix) - 1) << FShft (LCCR1_HSW))
1850 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
1851 /* count - 1 [Tpix] */
1852 #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
1853 /* [1..256 Tpix] */ \
1854 (((Tpix) - 1) << FShft (LCCR1_ELW))
1856 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
1857 /* Wait count - 1 [Tpix] */
1858 #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
1859 /* [1..256 Tpix] */ \
1860 (((Tpix) - 1) << FShft (LCCR1_BLW))
1863 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
1864 #define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
1865 (((Line) - 1) << FShft (LCCR2_LPP))
1867 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
1868 /* Width - 1 [Tln] (L_FCLK) */
1869 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
1870 /* Width [1..64 Tln] */ \
1871 (((Tln) - 1) << FShft (LCCR2_VSW))
1873 #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
1875 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
1876 /* [0..255 Tln] */ \
1877 ((Tln) << FShft (LCCR2_EFW))
1879 #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
1880 /* Wait count [Tln] */
1881 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
1882 /* [0..255 Tln] */ \
1883 ((Tln) << FShft (LCCR2_BFW))
1886 #define LCCR3_PCD (0xff) /* Pixel clock divisor */
1887 #define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */
1888 #define LCCR3_ACB_S 8
1891 #define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */
1892 #define LCCR3_API_S 16
1893 #define LCCR3_VSP (1 << 20) /* vertical sync polarity */
1894 #define LCCR3_HSP (1 << 21) /* horizontal sync polarity */
1895 #define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */
1896 #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
1897 #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
1899 #define LCCR3_OEP (1 << 23) /* Output Enable Polarity (L_BIAS, */
1900 /* active display mode) */
1901 #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
1902 #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
1905 #define LCCR3_BPP (7 << 24) /* bits per pixel */
1906 #define LCCR3_BPP_S 24
1908 #define LCCR3_DPC (1 << 27) /* double pixel clock mode */
1911 #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
1912 #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \
1913 (((Div) << FShft (LCCR3_PCD)))
1916 #define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */
1917 #define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \
1918 (((Bpp) << FShft (LCCR3_BPP)))
1920 #define LCCR3_ACB Fld (8, 8) /* AC Bias */
1921 #define LCCR3_Acb(Acb) /* BAC Bias */ \
1922 (((Acb) << FShft (LCCR3_ACB)))
1924 #define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
1925 /* pulse active High */
1926 #define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
1928 #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
1930 #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
1933 #define LCSR_LDD (1 << 0) /* LCD Disable Done */
1934 #define LCSR_SOF (1 << 1) /* Start of frame */
1935 #define LCSR_BER (1 << 2) /* Bus error */
1936 #define LCSR_ABC (1 << 3) /* AC Bias count */
1937 #define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
1938 #define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
1939 #define LCSR_OU (1 << 6) /* output FIFO underrun */
1940 #define LCSR_QD (1 << 7) /* quick disable */
1941 #define LCSR_EOF (1 << 8) /* end of frame */
1942 #define LCSR_BS (1 << 9) /* branch status */
1943 #define LCSR_SINT (1 << 10) /* subsequent interrupt */
1945 #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
1947 #define LCSR_LDD (1 << 0) /* LCD Disable Done */
1948 #define LCSR_SOF (1 << 1) /* Start of frame */
1949 #define LCSR_BER (1 << 2) /* Bus error */
1950 #define LCSR_ABC (1 << 3) /* AC Bias count */
1951 #define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
1952 #define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
1953 #define LCSR_OU (1 << 6) /* output FIFO underrun */
1954 #define LCSR_QD (1 << 7) /* quick disable */
1955 #define LCSR_EOF (1 << 8) /* end of frame */
1956 #define LCSR_BS (1 << 9) /* branch status */
1957 #define LCSR_SINT (1 << 10) /* subsequent interrupt */
1959 #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
1965 #define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
1966 #define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
1967 #define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
1968 #define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
1969 #define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
1970 #define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
1971 #define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
1972 #define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
1973 #define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
1974 #define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
1975 #define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
1976 #define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
1977 #define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
1978 #define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
1979 #define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
1980 #define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
1981 #define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
1984 * More handy macros for PCMCIA
1986 * Arg is socket number
1988 #define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */
1989 #define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */
1990 #define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */
1992 /* MECR register defines */
1993 #define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
1994 #define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
1996 #define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
1997 #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
1998 #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
1999 #define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
2000 #define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
2001 #define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
2002 #define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
2003 #define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
2004 #define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
2005 #define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
2006 #define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
2007 #define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
2008 #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
2009 #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
2012 #ifdef CONFIG_PXA27x
2017 #define KPC __REG(0x41500000) /* Keypad Interface Control register */
2018 #define KPDK __REG(0x41500008) /* Keypad Interface Direct Key register */
2019 #define KPREC __REG(0x41500010) /* Keypad Interface Rotary Encoder register */
2020 #define KPMK __REG(0x41500018) /* Keypad Interface Matrix Key register */
2021 #define KPAS __REG(0x41500020) /* Keypad Interface Automatic Scan register */
2022 #define KPASMKP0 __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
2023 #define KPASMKP1 __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
2024 #define KPASMKP2 __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
2025 #define KPASMKP3 __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
2026 #define KPKDI __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */
2028 #define KPC_AS (0x1 << 30) /* Automatic Scan bit */
2029 #define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */
2030 #define KPC_MI (0x1 << 22) /* Matrix interrupt bit */
2031 #define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */
2032 #define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */
2033 #define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */
2034 #define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */
2035 #define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */
2036 #define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */
2037 #define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */
2038 #define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */
2039 #define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */
2040 #define KPC_MS_ALL (KPC_MS0 | KPC_MS1 | KPC_MS2 | KPC_MS3 | KPC_MS4 | KPC_MS5 | KPC_MS6 | KPC_MS7)
2041 #define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */
2042 #define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */
2043 #define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Keypad Debounce Select */
2044 #define KPC_DI (0x1 << 5) /* Direct key interrupt bit */
2045 #define KPC_RE_ZERO_DEB (0x1 << 4) /* Rotary Encoder Zero Debounce */
2046 #define KPC_REE1 (0x1 << 3) /* Rotary Encoder1 Enable */
2047 #define KPC_REE0 (0x1 << 2) /* Rotary Encoder0 Enable */
2048 #define KPC_DE (0x1 << 1) /* Direct Keypad Enable */
2049 #define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */
2051 #define KPDK_DKP (0x1 << 31)
2052 #define KPDK_DK7 (0x1 << 7)
2053 #define KPDK_DK6 (0x1 << 6)
2054 #define KPDK_DK5 (0x1 << 5)
2055 #define KPDK_DK4 (0x1 << 4)
2056 #define KPDK_DK3 (0x1 << 3)
2057 #define KPDK_DK2 (0x1 << 2)
2058 #define KPDK_DK1 (0x1 << 1)
2059 #define KPDK_DK0 (0x1 << 0)
2061 #define KPREC_OF1 (0x1 << 31)
2062 #define kPREC_UF1 (0x1 << 30)
2063 #define KPREC_OF0 (0x1 << 15)
2064 #define KPREC_UF0 (0x1 << 14)
2066 #define KPMK_MKP (0x1 << 31)
2067 #define KPAS_SO (0x1 << 31)
2068 #define KPASMKPx_SO (0x1 << 31)
2071 * UHC: USB Host Controller (OHCI-like) register definitions
2073 #define UHC_BASE_PHYS (0x4C000000)
2074 #define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
2075 #define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
2076 #define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
2077 #define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
2078 #define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
2079 #define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
2080 #define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
2081 #define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
2082 #define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
2083 #define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
2084 #define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
2085 #define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
2086 #define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
2087 #define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
2088 #define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
2089 #define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
2090 #define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
2091 #define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
2093 #define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
2094 #define UHCRHDA_NOCP (1 << 12) /* No over current protection */
2096 #define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
2097 #define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
2098 #define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
2099 #define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
2100 #define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
2102 #define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
2103 #define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
2104 #define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
2105 #define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
2106 #define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
2107 #define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
2108 #define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
2109 #define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
2110 #define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
2111 #define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
2113 #define UHCHR __REG(0x4C000064) /* UHC Reset Register */
2114 #define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
2115 #define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
2116 #define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
2117 #define UHCHR_PCPL (1 << 7) /* Power control polarity low */
2118 #define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
2119 #define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
2120 #define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
2121 #define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
2122 #define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
2123 #define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
2124 #define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
2126 #define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
2127 #define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
2128 #define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
2129 #define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
2130 #define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
2131 #define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
2133 #define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
2134 #define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
2136 #define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
2138 /* Camera Interface */
2139 #define CICR0 __REG(0x50000000)
2140 #define CICR1 __REG(0x50000004)
2141 #define CICR2 __REG(0x50000008)
2142 #define CICR3 __REG(0x5000000C)
2143 #define CICR4 __REG(0x50000010)
2144 #define CISR __REG(0x50000014)
2145 #define CIFR __REG(0x50000018)
2146 #define CITOR __REG(0x5000001C)
2147 #define CIBR0 __REG(0x50000028)
2148 #define CIBR1 __REG(0x50000030)
2149 #define CIBR2 __REG(0x50000038)
2151 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
2152 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
2153 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
2154 #define CICR0_ENB (1 << 28) /* Camera interface enable */
2155 #define CICR0_DIS (1 << 27) /* Camera interface disable */
2156 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
2157 #define CICR0_TOM (1 << 9) /* Time-out mask */
2158 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
2159 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
2160 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
2161 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
2162 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
2163 #define CICR0_CDM (1 << 3) /* Disable-done mask */
2164 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
2165 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
2166 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
2168 #define CICR1_TBIT (1 << 31) /* Transparency bit */
2169 #define CICR1_RGBT_CONV (0x3 << 30) /* RGBT conversion mask */
2170 #define CICR1_PPL (0x3f << 15) /* Pixels per line mask */
2171 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
2172 #define CICR1_RGB_F (1 << 11) /* RGB format */
2173 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
2174 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
2175 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
2176 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
2177 #define CICR1_DW (0x7 << 0) /* Data width mask */
2179 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
2181 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
2183 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
2184 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
2186 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
2189 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
2191 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
2193 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
2194 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
2196 #define CICR3_LPF (0x3ff << 0) /* Lines per frame mask */
2198 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
2199 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
2200 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
2201 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
2202 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
2203 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
2204 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
2205 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
2207 #define CISR_FTO (1 << 15) /* FIFO time-out */
2208 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
2209 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
2210 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
2211 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
2212 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
2213 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
2214 #define CISR_EOL (1 << 8) /* End of line */
2215 #define CISR_PAR_ERR (1 << 7) /* Parity error */
2216 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
2217 #define CISR_SOF (1 << 5) /* Start of frame */
2218 #define CISR_CDD (1 << 4) /* Camera interface disable done */
2219 #define CISR_EOF (1 << 3) /* End of frame */
2220 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
2221 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
2222 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
2224 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
2225 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
2226 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
2227 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
2228 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
2229 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
2230 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
2231 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
2233 #define SRAM_SIZE 0x40000 /* 4x64K */
2235 #define SRAM_MEM_PHYS 0x5C000000
2237 #define IMPMCR __REG(0x58000000) /* IM Power Management Control Reg */
2238 #define IMPMSR __REG(0x58000008) /* IM Power Management Status Reg */
2240 #define IMPMCR_PC3 (0x3 << 22) /* Bank 3 Power Control */
2241 #define IMPMCR_PC3_RUN_MODE (0x0 << 22) /* Run mode */
2242 #define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /* Standby mode */
2243 #define IMPMCR_PC3_AUTO_MODE (0x3 << 22) /* Automatically controlled */
2245 #define IMPMCR_PC2 (0x3 << 20) /* Bank 2 Power Control */
2246 #define IMPMCR_PC2_RUN_MODE (0x0 << 20) /* Run mode */
2247 #define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /* Standby mode */
2248 #define IMPMCR_PC2_AUTO_MODE (0x3 << 20) /* Automatically controlled */
2250 #define IMPMCR_PC1 (0x3 << 18) /* Bank 1 Power Control */
2251 #define IMPMCR_PC1_RUN_MODE (0x0 << 18) /* Run mode */
2252 #define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /* Standby mode */
2253 #define IMPMCR_PC1_AUTO_MODE (0x3 << 18) /* Automatically controlled */
2255 #define IMPMCR_PC0 (0x3 << 16) /* Bank 0 Power Control */
2256 #define IMPMCR_PC0_RUN_MODE (0x0 << 16) /* Run mode */
2257 #define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /* Standby mode */
2258 #define IMPMCR_PC0_AUTO_MODE (0x3 << 16) /* Automatically controlled */
2260 #define IMPMCR_AW3 (1 << 11) /* Bank 3 Automatic Wake-up enable */
2261 #define IMPMCR_AW2 (1 << 10) /* Bank 2 Automatic Wake-up enable */
2262 #define IMPMCR_AW1 (1 << 9) /* Bank 1 Automatic Wake-up enable */
2263 #define IMPMCR_AW0 (1 << 8) /* Bank 0 Automatic Wake-up enable */
2265 #define IMPMCR_DST (0xFF << 0) /* Delay Standby Time, ms */
2267 #define IMPMSR_PS3 (0x3 << 6) /* Bank 3 Power Status: */
2268 #define IMPMSR_PS3_RUN_MODE (0x0 << 6) /* Run mode */
2269 #define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /* Standby mode */
2271 #define IMPMSR_PS2 (0x3 << 4) /* Bank 2 Power Status: */
2272 #define IMPMSR_PS2_RUN_MODE (0x0 << 4) /* Run mode */
2273 #define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /* Standby mode */
2275 #define IMPMSR_PS1 (0x3 << 2) /* Bank 1 Power Status: */
2276 #define IMPMSR_PS1_RUN_MODE (0x0 << 2) /* Run mode */
2277 #define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /* Standby mode */
2279 #define IMPMSR_PS0 (0x3 << 0) /* Bank 0 Power Status: */
2280 #define IMPMSR_PS0_RUN_MODE (0x0 << 0) /* Run mode */
2281 #define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /* Standby mode */
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