include/asm-arm/arch-s3c2410/dma.h

   1 /* linux/include/asm-arm/arch-s3c2410/dma.h
   2  *
   3  * Copyright (C) 2003,2004,2006 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * Samsung S3C241XX DMA support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #ifndef __ASM_ARCH_DMA_H
  14 #define __ASM_ARCH_DMA_H __FILE__
  15
  16 #include <linux/sysdev.h>
  17 #include "hardware.h"
  18
  19 /*
  20  * This is the maximum DMA address(physical address) that can be DMAd to.
  21  *
  22  */
  23 #define MAX_DMA_ADDRESS         0x40000000
  24 #define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */
  25
  26 /* we have 4 dma channels */
  27 #define S3C2410_DMA_CHANNELS        (4)
  28
  29 /* types */
  30
  31 enum s3c2410_dma_state {
  32         S3C2410_DMA_IDLE,
  33         S3C2410_DMA_RUNNING,
  34         S3C2410_DMA_PAUSED
  35 };
  36
  37
  38 /* enum s3c2410_dma_loadst
  39  *
  40  * This represents the state of the DMA engine, wrt to the loaded / running
  41  * transfers. Since we don't have any way of knowing exactly the state of
  42  * the DMA transfers, we need to know the state to make decisions on wether
  43  * we can
  44  *
  45  * S3C2410_DMA_NONE
  46  *
  47  * There are no buffers loaded (the channel should be inactive)
  48  *
  49  * S3C2410_DMA_1LOADED
  50  *
  51  * There is one buffer loaded, however it has not been confirmed to be
  52  * loaded by the DMA engine. This may be because the channel is not
  53  * yet running, or the DMA driver decided that it was too costly to
  54  * sit and wait for it to happen.
  55  *
  56  * S3C2410_DMA_1RUNNING
  57  *
  58  * The buffer has been confirmed running, and not finisged
  59  *
  60  * S3C2410_DMA_1LOADED_1RUNNING
  61  *
  62  * There is a buffer waiting to be loaded by the DMA engine, and one
  63  * currently running.
  64 */
  65
  66 enum s3c2410_dma_loadst {
  67         S3C2410_DMALOAD_NONE,
  68         S3C2410_DMALOAD_1LOADED,
  69         S3C2410_DMALOAD_1RUNNING,
  70         S3C2410_DMALOAD_1LOADED_1RUNNING,
  71 };
  72
  73 enum s3c2410_dma_buffresult {
  74         S3C2410_RES_OK,
  75         S3C2410_RES_ERR,
  76         S3C2410_RES_ABORT
  77 };
  78
  79 enum s3c2410_dmasrc {
  80         S3C2410_DMASRC_HW,              /* source is memory */
  81         S3C2410_DMASRC_MEM              /* source is hardware */
  82 };
  83
  84 /* enum s3c2410_chan_op
  85  *
  86  * operation codes passed to the DMA code by the user, and also used
  87  * to inform the current channel owner of any changes to the system state
  88 */
  89
  90 enum s3c2410_chan_op {
  91         S3C2410_DMAOP_START,
  92         S3C2410_DMAOP_STOP,
  93         S3C2410_DMAOP_PAUSE,
  94         S3C2410_DMAOP_RESUME,
  95         S3C2410_DMAOP_FLUSH,
  96         S3C2410_DMAOP_TIMEOUT,          /* internal signal to handler */
  97         S3C2410_DMAOP_STARTED,          /* indicate channel started */
  98 };
  99
 100 /* flags */
 101
 102 #define S3C2410_DMAF_SLOW         (1<<0)   /* slow, so don't worry about
 103                                             * waiting for reloads */
 104 #define S3C2410_DMAF_AUTOSTART    (1<<1)   /* auto-start if buffer queued */
 105
 106 /* dma buffer */
 107
 108 struct s3c2410_dma_client {
 109         char                *name;
 110 };
 111
 112 /* s3c2410_dma_buf_s
 113  *
 114  * internally used buffer structure to describe a queued or running
 115  * buffer.
 116 */
 117
 118 struct s3c2410_dma_buf;
 119 struct s3c2410_dma_buf {
 120         struct s3c2410_dma_buf  *next;
 121         int                      magic;         /* magic */
 122         int                      size;          /* buffer size in bytes */
 123         dma_addr_t               data;          /* start of DMA data */
 124         dma_addr_t               ptr;           /* where the DMA got to [1] */
 125         void                    *id;            /* client's id */
 126 };
 127
 128 /* [1] is this updated for both recv/send modes? */
 129
 130 struct s3c2410_dma_chan;
 131
 132 /* s3c2410_dma_cbfn_t
 133  *
 134  * buffer callback routine type
 135 */
 136
 137 typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
 138                                    void *buf, int size,
 139                                    enum s3c2410_dma_buffresult result);
 140
 141 typedef int  (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
 142                                    enum s3c2410_chan_op );
 143
 144 struct s3c2410_dma_stats {
 145         unsigned long           loads;
 146         unsigned long           timeout_longest;
 147         unsigned long           timeout_shortest;
 148         unsigned long           timeout_avg;
 149         unsigned long           timeout_failed;
 150 };
 151
 152 /* struct s3c2410_dma_chan
 153  *
 154  * full state information for each DMA channel
 155 */
 156
 157 struct s3c2410_dma_chan {
 158         /* channel state flags and information */
 159         unsigned char            number;      /* number of this dma channel */
 160         unsigned char            in_use;      /* channel allocated */
 161         unsigned char            irq_claimed; /* irq claimed for channel */
 162         unsigned char            irq_enabled; /* irq enabled for channel */
 163         unsigned char            xfer_unit;   /* size of an transfer */
 164
 165         /* channel state */
 166
 167         enum s3c2410_dma_state   state;
 168         enum s3c2410_dma_loadst  load_state;
 169         struct s3c2410_dma_client *client;
 170
 171         /* channel configuration */
 172         enum s3c2410_dmasrc      source;
 173         unsigned long            dev_addr;
 174         unsigned long            load_timeout;
 175         unsigned int             flags;         /* channel flags */
 176
 177         /* channel's hardware position and configuration */
 178         void __iomem            *regs;          /* channels registers */
 179         void __iomem            *addr_reg;      /* data address register */
 180         unsigned int             irq;           /* channel irq */
 181         unsigned long            dcon;          /* default value of DCON */
 182
 183         /* driver handles */
 184         s3c2410_dma_cbfn_t       callback_fn;   /* buffer done callback */
 185         s3c2410_dma_opfn_t       op_fn;         /* channel op callback */
 186
 187         /* stats gathering */
 188         struct s3c2410_dma_stats *stats;
 189         struct s3c2410_dma_stats  stats_store;
 190
 191         /* buffer list and information */
 192         struct s3c2410_dma_buf  *curr;          /* current dma buffer */
 193         struct s3c2410_dma_buf  *next;          /* next buffer to load */
 194         struct s3c2410_dma_buf  *end;           /* end of queue */
 195
 196         /* system device */
 197         struct sys_device       dev;
 198 };
 199
 200 /* the currently allocated channel information */
 201 extern struct s3c2410_dma_chan s3c2410_chans[];
 202
 203 /* note, we don't really use dma_device_t at the moment */
 204 typedef unsigned long dma_device_t;
 205
 206 /* functions --------------------------------------------------------------- */
 207
 208 /* s3c2410_dma_request
 209  *
 210  * request a dma channel exclusivley
 211 */
 212
 213 extern int s3c2410_dma_request(dmach_t channel,
 214                                struct s3c2410_dma_client *, void *dev);
 215
 216
 217 /* s3c2410_dma_ctrl
 218  *
 219  * change the state of the dma channel
 220 */
 221
 222 extern int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op);
 223
 224 /* s3c2410_dma_setflags
 225  *
 226  * set the channel's flags to a given state
 227 */
 228
 229 extern int s3c2410_dma_setflags(dmach_t channel,
 230                                 unsigned int flags);
 231
 232 /* s3c2410_dma_free
 233  *
 234  * free the dma channel (will also abort any outstanding operations)
 235 */
 236
 237 extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *);
 238
 239 /* s3c2410_dma_enqueue
 240  *
 241  * place the given buffer onto the queue of operations for the channel.
 242  * The buffer must be allocated from dma coherent memory, or the Dcache/WB
 243  * drained before the buffer is given to the DMA system.
 244 */
 245
 246 extern int s3c2410_dma_enqueue(dmach_t channel, void *id,
 247                                dma_addr_t data, int size);
 248
 249 /* s3c2410_dma_config
 250  *
 251  * configure the dma channel
 252 */
 253
 254 extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon);
 255
 256 /* s3c2410_dma_devconfig
 257  *
 258  * configure the device we're talking to
 259 */
 260
 261 extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
 262                                  int hwcfg, unsigned long devaddr);
 263
 264 /* s3c2410_dma_getposition
 265  *
 266  * get the position that the dma transfer is currently at
 267 */
 268
 269 extern int s3c2410_dma_getposition(dmach_t channel,
 270                                    dma_addr_t *src, dma_addr_t *dest);
 271
 272 extern int s3c2410_dma_set_opfn(dmach_t, s3c2410_dma_opfn_t rtn);
 273 extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
 274
 275 /* DMA Register definitions */
 276
 277 #define S3C2410_DMA_DISRC       (0x00)
 278 #define S3C2410_DMA_DISRCC      (0x04)
 279 #define S3C2410_DMA_DIDST       (0x08)
 280 #define S3C2410_DMA_DIDSTC      (0x0C)
 281 #define S3C2410_DMA_DCON        (0x10)
 282 #define S3C2410_DMA_DSTAT       (0x14)
 283 #define S3C2410_DMA_DCSRC       (0x18)
 284 #define S3C2410_DMA_DCDST       (0x1C)
 285 #define S3C2410_DMA_DMASKTRIG   (0x20)
 286
 287 #define S3C2410_DISRCC_INC      (1<<0)
 288 #define S3C2410_DISRCC_APB      (1<<1)
 289
 290 #define S3C2410_DMASKTRIG_STOP   (1<<2)
 291 #define S3C2410_DMASKTRIG_ON     (1<<1)
 292 #define S3C2410_DMASKTRIG_SWTRIG (1<<0)
 293
 294 #define S3C2410_DCON_DEMAND     (0<<31)
 295 #define S3C2410_DCON_HANDSHAKE  (1<<31)
 296 #define S3C2410_DCON_SYNC_PCLK  (0<<30)
 297 #define S3C2410_DCON_SYNC_HCLK  (1<<30)
 298
 299 #define S3C2410_DCON_INTREQ     (1<<29)
 300
 301 #define S3C2410_DCON_CH0_XDREQ0 (0<<24)
 302 #define S3C2410_DCON_CH0_UART0  (1<<24)
 303 #define S3C2410_DCON_CH0_SDI    (2<<24)
 304 #define S3C2410_DCON_CH0_TIMER  (3<<24)
 305 #define S3C2410_DCON_CH0_USBEP1 (4<<24)
 306
 307 #define S3C2410_DCON_CH1_XDREQ1 (0<<24)
 308 #define S3C2410_DCON_CH1_UART1  (1<<24)
 309 #define S3C2410_DCON_CH1_I2SSDI (2<<24)
 310 #define S3C2410_DCON_CH1_SPI    (3<<24)
 311 #define S3C2410_DCON_CH1_USBEP2 (4<<24)
 312
 313 #define S3C2410_DCON_CH2_I2SSDO (0<<24)
 314 #define S3C2410_DCON_CH2_I2SSDI (1<<24)
 315 #define S3C2410_DCON_CH2_SDI    (2<<24)
 316 #define S3C2410_DCON_CH2_TIMER  (3<<24)
 317 #define S3C2410_DCON_CH2_USBEP3 (4<<24)
 318
 319 #define S3C2410_DCON_CH3_UART2  (0<<24)
 320 #define S3C2410_DCON_CH3_SDI    (1<<24)
 321 #define S3C2410_DCON_CH3_SPI    (2<<24)
 322 #define S3C2410_DCON_CH3_TIMER  (3<<24)
 323 #define S3C2410_DCON_CH3_USBEP4 (4<<24)
 324
 325 #define S3C2410_DCON_SRCSHIFT   (24)
 326 #define S3C2410_DCON_SRCMASK    (7<<24)
 327
 328 #define S3C2410_DCON_BYTE       (0<<20)
 329 #define S3C2410_DCON_HALFWORD   (1<<20)
 330 #define S3C2410_DCON_WORD       (2<<20)
 331
 332 #define S3C2410_DCON_AUTORELOAD (0<<22)
 333 #define S3C2410_DCON_NORELOAD   (1<<22)
 334 #define S3C2410_DCON_HWTRIG     (1<<23)
 335
 336 #ifdef CONFIG_CPU_S3C2440
 337 #define S3C2440_DIDSTC_CHKINT   (1<<2)
 338
 339 #define S3C2440_DCON_CH0_I2SSDO (5<<24)
 340 #define S3C2440_DCON_CH0_PCMIN  (6<<24)
 341
 342 #define S3C2440_DCON_CH1_PCMOUT (5<<24)
 343 #define S3C2440_DCON_CH1_SDI    (6<<24)
 344
 345 #define S3C2440_DCON_CH2_PCMIN  (5<<24)
 346 #define S3C2440_DCON_CH2_MICIN  (6<<24)
 347
 348 #define S3C2440_DCON_CH3_MICIN  (5<<24)
 349 #define S3C2440_DCON_CH3_PCMOUT (6<<24)
 350 #endif
 351
 352 #endif /* __ASM_ARCH_DMA_H */