include/asm-i386/processor.h

   1 /*
   2  * include/asm-i386/processor.h
   3  *
   4  * Copyright (C) 1994 Linus Torvalds
   5  */
   6
   7 #ifndef __ASM_I386_PROCESSOR_H
   8 #define __ASM_I386_PROCESSOR_H
   9
  10 #include <asm/vm86.h>
  11 #include <asm/math_emu.h>
  12 #include <asm/segment.h>
  13 #include <asm/page.h>
  14 #include <asm/types.h>
  15 #include <asm/sigcontext.h>
  16 #include <asm/cpufeature.h>
  17 #include <asm/msr.h>
  18 #include <asm/system.h>
  19 #include <linux/cache.h>
  20 #include <linux/threads.h>
  21 #include <asm/percpu.h>
  22 #include <linux/cpumask.h>
  23 #include <linux/init.h>
  24 #include <asm/processor-flags.h>
  25
  26 /* flag for disabling the tsc */
  27 extern int tsc_disable;
  28
  29 struct desc_struct {
  30         unsigned long a,b;
  31 };
  32
  33 #define desc_empty(desc) \
  34                 (!((desc)->a | (desc)->b))
  35
  36 #define desc_equal(desc1, desc2) \
  37                 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
  38 /*
  39  * Default implementation of macro that returns current
  40  * instruction pointer ("program counter").
  41  */
  42 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
  43
  44 /*
  45  *  CPU type and hardware bug flags. Kept separately for each CPU.
  46  *  Members of this structure are referenced in head.S, so think twice
  47  *  before touching them. [mj]
  48  */
  49
  50 struct cpuinfo_x86 {
  51         __u8    x86;            /* CPU family */
  52         __u8    x86_vendor;     /* CPU vendor */
  53         __u8    x86_model;
  54         __u8    x86_mask;
  55         char    wp_works_ok;    /* It doesn't on 386's */
  56         char    hlt_works_ok;   /* Problems on some 486Dx4's and old 386's */
  57         char    hard_math;
  58         char    rfu;
  59         int     cpuid_level;    /* Maximum supported CPUID level, -1=no CPUID */
  60         unsigned long   x86_capability[NCAPINTS];
  61         char    x86_vendor_id[16];
  62         char    x86_model_id[64];
  63         int     x86_cache_size;  /* in KB - valid for CPUS which support this
  64                                     call  */
  65         int     x86_cache_alignment;    /* In bytes */
  66         char    fdiv_bug;
  67         char    f00f_bug;
  68         char    coma_bug;
  69         char    pad0;
  70         int     x86_power;
  71         unsigned long loops_per_jiffy;
  72 #ifdef CONFIG_SMP
  73         cpumask_t llc_shared_map;       /* cpus sharing the last level cache */
  74 #endif
  75         unsigned char x86_max_cores;    /* cpuid returned max cores value */
  76         unsigned char apicid;
  77         unsigned short x86_clflush_size;
  78 #ifdef CONFIG_SMP
  79         unsigned char booted_cores;     /* number of cores as seen by OS */
  80         __u8 phys_proc_id;              /* Physical processor id. */
  81         __u8 cpu_core_id;               /* Core id */
  82 #endif
  83 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
  84
  85 #define X86_VENDOR_INTEL 0
  86 #define X86_VENDOR_CYRIX 1
  87 #define X86_VENDOR_AMD 2
  88 #define X86_VENDOR_UMC 3
  89 #define X86_VENDOR_NEXGEN 4
  90 #define X86_VENDOR_CENTAUR 5
  91 #define X86_VENDOR_RISE 6
  92 #define X86_VENDOR_TRANSMETA 7
  93 #define X86_VENDOR_NSC 8
  94 #define X86_VENDOR_NUM 9
  95 #define X86_VENDOR_UNKNOWN 0xff
  96
  97 /*
  98  * capabilities of CPUs
  99  */
 100
 101 extern struct cpuinfo_x86 boot_cpu_data;
 102 extern struct cpuinfo_x86 new_cpu_data;
 103 extern struct tss_struct doublefault_tss;
 104 DECLARE_PER_CPU(struct tss_struct, init_tss);
 105
 106 #ifdef CONFIG_SMP
 107 extern struct cpuinfo_x86 cpu_data[];
 108 #define current_cpu_data cpu_data[smp_processor_id()]
 109 #else
 110 #define cpu_data (&boot_cpu_data)
 111 #define current_cpu_data boot_cpu_data
 112 #endif
 113
 114 extern  int cpu_llc_id[NR_CPUS];
 115 extern char ignore_fpu_irq;
 116
 117 void __init cpu_detect(struct cpuinfo_x86 *c);
 118
 119 extern void identify_boot_cpu(void);
 120 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 121 extern void print_cpu_info(struct cpuinfo_x86 *);
 122 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 123 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 124 extern unsigned short num_cache_leaves;
 125
 126 #ifdef CONFIG_X86_HT
 127 extern void detect_ht(struct cpuinfo_x86 *c);
 128 #else
 129 static inline void detect_ht(struct cpuinfo_x86 *c) {}
 130 #endif
 131
 132 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 133                                          unsigned int *ecx, unsigned int *edx)
 134 {
 135         /* ecx is often an input as well as an output. */
 136         __asm__("cpuid"
 137                 : "=a" (*eax),
 138                   "=b" (*ebx),
 139                   "=c" (*ecx),
 140                   "=d" (*edx)
 141                 : "0" (*eax), "2" (*ecx));
 142 }
 143
 144 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
 145
 146 /*
 147  * Save the cr4 feature set we're using (ie
 148  * Pentium 4MB enable and PPro Global page
 149  * enable), so that any CPU's that boot up
 150  * after us can get the correct flags.
 151  */
 152 extern unsigned long mmu_cr4_features;
 153
 154 static inline void set_in_cr4 (unsigned long mask)
 155 {
 156         unsigned cr4;
 157         mmu_cr4_features |= mask;
 158         cr4 = read_cr4();
 159         cr4 |= mask;
 160         write_cr4(cr4);
 161 }
 162
 163 static inline void clear_in_cr4 (unsigned long mask)
 164 {
 165         unsigned cr4;
 166         mmu_cr4_features &= ~mask;
 167         cr4 = read_cr4();
 168         cr4 &= ~mask;
 169         write_cr4(cr4);
 170 }
 171
 172 /*
 173  *      NSC/Cyrix CPU indexed register access macros
 174  */
 175
 176 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
 177
 178 #define setCx86(reg, data) do { \
 179         outb((reg), 0x22); \
 180         outb((data), 0x23); \
 181 } while (0)
 182
 183 /* Stop speculative execution */
 184 static inline void sync_core(void)
 185 {
 186         int tmp;
 187         asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
 188 }
 189
 190 static inline void __monitor(const void *eax, unsigned long ecx,
 191                 unsigned long edx)
 192 {
 193         /* "monitor %eax,%ecx,%edx;" */
 194         asm volatile(
 195                 ".byte 0x0f,0x01,0xc8;"
 196                 : :"a" (eax), "c" (ecx), "d"(edx));
 197 }
 198
 199 static inline void __mwait(unsigned long eax, unsigned long ecx)
 200 {
 201         /* "mwait %eax,%ecx;" */
 202         asm volatile(
 203                 ".byte 0x0f,0x01,0xc9;"
 204                 : :"a" (eax), "c" (ecx));
 205 }
 206
 207 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
 208
 209 /* from system description table in BIOS.  Mostly for MCA use, but
 210 others may find it useful. */
 211 extern unsigned int machine_id;
 212 extern unsigned int machine_submodel_id;
 213 extern unsigned int BIOS_revision;
 214 extern unsigned int mca_pentium_flag;
 215
 216 /* Boot loader type from the setup header */
 217 extern int bootloader_type;
 218
 219 /*
 220  * User space process size: 3GB (default).
 221  */
 222 #define TASK_SIZE       (PAGE_OFFSET)
 223
 224 /* This decides where the kernel will search for a free chunk of vm
 225  * space during mmap's.
 226  */
 227 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 228
 229 #define HAVE_ARCH_PICK_MMAP_LAYOUT
 230
 231 extern void hard_disable_TSC(void);
 232 extern void disable_TSC(void);
 233 extern void hard_enable_TSC(void);
 234
 235 /*
 236  * Size of io_bitmap.
 237  */
 238 #define IO_BITMAP_BITS  65536
 239 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
 240 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
 241 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
 242 #define INVALID_IO_BITMAP_OFFSET 0x8000
 243 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
 244
 245 struct i387_fsave_struct {
 246         long    cwd;
 247         long    swd;
 248         long    twd;
 249         long    fip;
 250         long    fcs;
 251         long    foo;
 252         long    fos;
 253         long    st_space[20];   /* 8*10 bytes for each FP-reg = 80 bytes */
 254         long    status;         /* software status information */
 255 };
 256
 257 struct i387_fxsave_struct {
 258         unsigned short  cwd;
 259         unsigned short  swd;
 260         unsigned short  twd;
 261         unsigned short  fop;
 262         long    fip;
 263         long    fcs;
 264         long    foo;
 265         long    fos;
 266         long    mxcsr;
 267         long    mxcsr_mask;
 268         long    st_space[32];   /* 8*16 bytes for each FP-reg = 128 bytes */
 269         long    xmm_space[32];  /* 8*16 bytes for each XMM-reg = 128 bytes */
 270         long    padding[56];
 271 } __attribute__ ((aligned (16)));
 272
 273 struct i387_soft_struct {
 274         long    cwd;
 275         long    swd;
 276         long    twd;
 277         long    fip;
 278         long    fcs;
 279         long    foo;
 280         long    fos;
 281         long    st_space[20];   /* 8*10 bytes for each FP-reg = 80 bytes */
 282         unsigned char   ftop, changed, lookahead, no_update, rm, alimit;
 283         struct info     *info;
 284         unsigned long   entry_eip;
 285 };
 286
 287 union i387_union {
 288         struct i387_fsave_struct        fsave;
 289         struct i387_fxsave_struct       fxsave;
 290         struct i387_soft_struct soft;
 291 };
 292
 293 typedef struct {
 294         unsigned long seg;
 295 } mm_segment_t;
 296
 297 struct thread_struct;
 298
 299 /* This is the TSS defined by the hardware. */
 300 struct i386_hw_tss {
 301         unsigned short  back_link,__blh;
 302         unsigned long   esp0;
 303         unsigned short  ss0,__ss0h;
 304         unsigned long   esp1;
 305         unsigned short  ss1,__ss1h;     /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
 306         unsigned long   esp2;
 307         unsigned short  ss2,__ss2h;
 308         unsigned long   __cr3;
 309         unsigned long   eip;
 310         unsigned long   eflags;
 311         unsigned long   eax,ecx,edx,ebx;
 312         unsigned long   esp;
 313         unsigned long   ebp;
 314         unsigned long   esi;
 315         unsigned long   edi;
 316         unsigned short  es, __esh;
 317         unsigned short  cs, __csh;
 318         unsigned short  ss, __ssh;
 319         unsigned short  ds, __dsh;
 320         unsigned short  fs, __fsh;
 321         unsigned short  gs, __gsh;
 322         unsigned short  ldt, __ldth;
 323         unsigned short  trace, io_bitmap_base;
 324 } __attribute__((packed));
 325
 326 struct tss_struct {
 327         struct i386_hw_tss x86_tss;
 328
 329         /*
 330          * The extra 1 is there because the CPU will access an
 331          * additional byte beyond the end of the IO permission
 332          * bitmap. The extra byte must be all 1 bits, and must
 333          * be within the limit.
 334          */
 335         unsigned long   io_bitmap[IO_BITMAP_LONGS + 1];
 336         /*
 337          * Cache the current maximum and the last task that used the bitmap:
 338          */
 339         unsigned long io_bitmap_max;
 340         struct thread_struct *io_bitmap_owner;
 341         /*
 342          * pads the TSS to be cacheline-aligned (size is 0x100)
 343          */
 344         unsigned long __cacheline_filler[35];
 345         /*
 346          * .. and then another 0x100 bytes for emergency kernel stack
 347          */
 348         unsigned long stack[64];
 349 } __attribute__((packed));
 350
 351 #define ARCH_MIN_TASKALIGN      16
 352
 353 struct thread_struct {
 354 /* cached TLS descriptors. */
 355         struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
 356         unsigned long   esp0;
 357         unsigned long   sysenter_cs;
 358         unsigned long   eip;
 359         unsigned long   esp;
 360         unsigned long   fs;
 361         unsigned long   gs;
 362 /* Hardware debugging registers */
 363         unsigned long   debugreg[8];  /* %%db0-7 debug registers */
 364 /* fault info */
 365         unsigned long   cr2, trap_no, error_code;
 366 /* floating point info */
 367         union i387_union        i387;
 368 /* virtual 86 mode info */
 369         struct vm86_struct __user * vm86_info;
 370         unsigned long           screen_bitmap;
 371         unsigned long           v86flags, v86mask, saved_esp0;
 372         unsigned int            saved_fs, saved_gs;
 373 /* IO permissions */
 374         unsigned long   *io_bitmap_ptr;
 375         unsigned long   iopl;
 376 /* max allowed port in the bitmap, in bytes: */
 377         unsigned long   io_bitmap_max;
 378 };
 379
 380 #define INIT_THREAD  {                                                  \
 381         .esp0 = sizeof(init_stack) + (long)&init_stack,                 \
 382         .vm86_info = NULL,                                              \
 383         .sysenter_cs = __KERNEL_CS,                                     \
 384         .io_bitmap_ptr = NULL,                                          \
 385         .fs = __KERNEL_PERCPU,                                          \
 386 }
 387
 388 /*
 389  * Note that the .io_bitmap member must be extra-big. This is because
 390  * the CPU will access an additional byte beyond the end of the IO
 391  * permission bitmap. The extra byte must be all 1 bits, and must
 392  * be within the limit.
 393  */
 394 #define INIT_TSS  {                                                     \
 395         .x86_tss = {                                                    \
 396                 .esp0           = sizeof(init_stack) + (long)&init_stack, \
 397                 .ss0            = __KERNEL_DS,                          \
 398                 .ss1            = __KERNEL_CS,                          \
 399                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,             \
 400          },                                                             \
 401         .io_bitmap      = { [ 0 ... IO_BITMAP_LONGS] = ~0 },            \
 402 }
 403
 404 #define start_thread(regs, new_eip, new_esp) do {               \
 405         __asm__("movl %0,%%gs": :"r" (0));                      \
 406         regs->xfs = 0;                                          \
 407         set_fs(USER_DS);                                        \
 408         regs->xds = __USER_DS;                                  \
 409         regs->xes = __USER_DS;                                  \
 410         regs->xss = __USER_DS;                                  \
 411         regs->xcs = __USER_CS;                                  \
 412         regs->eip = new_eip;                                    \
 413         regs->esp = new_esp;                                    \
 414 } while (0)
 415
 416 /* Forward declaration, a strange C thing */
 417 struct task_struct;
 418 struct mm_struct;
 419
 420 /* Free all resources held by a thread. */
 421 extern void release_thread(struct task_struct *);
 422
 423 /* Prepare to copy thread state - unlazy all lazy status */
 424 extern void prepare_to_copy(struct task_struct *tsk);
 425
 426 /*
 427  * create a kernel thread without removing it from tasklists
 428  */
 429 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
 430
 431 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 432 void show_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack);
 433
 434 unsigned long get_wchan(struct task_struct *p);
 435
 436 #define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
 437 #define KSTK_TOP(info)                                                 \
 438 ({                                                                     \
 439        unsigned long *__ptr = (unsigned long *)(info);                 \
 440        (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
 441 })
 442
 443 /*
 444  * The below -8 is to reserve 8 bytes on top of the ring0 stack.
 445  * This is necessary to guarantee that the entire "struct pt_regs"
 446  * is accessable even if the CPU haven't stored the SS/ESP registers
 447  * on the stack (interrupt gate does not save these registers
 448  * when switching to the same priv ring).
 449  * Therefore beware: accessing the xss/esp fields of the
 450  * "struct pt_regs" is possible, but they may contain the
 451  * completely wrong values.
 452  */
 453 #define task_pt_regs(task)                                             \
 454 ({                                                                     \
 455        struct pt_regs *__regs__;                                       \
 456        __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
 457        __regs__ - 1;                                                   \
 458 })
 459
 460 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
 461 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
 462
 463
 464 struct microcode_header {
 465         unsigned int hdrver;
 466         unsigned int rev;
 467         unsigned int date;
 468         unsigned int sig;
 469         unsigned int cksum;
 470         unsigned int ldrver;
 471         unsigned int pf;
 472         unsigned int datasize;
 473         unsigned int totalsize;
 474         unsigned int reserved[3];
 475 };
 476
 477 struct microcode {
 478         struct microcode_header hdr;
 479         unsigned int bits[0];
 480 };
 481
 482 typedef struct microcode microcode_t;
 483 typedef struct microcode_header microcode_header_t;
 484
 485 /* microcode format is extended from prescott processors */
 486 struct extended_signature {
 487         unsigned int sig;
 488         unsigned int pf;
 489         unsigned int cksum;
 490 };
 491
 492 struct extended_sigtable {
 493         unsigned int count;
 494         unsigned int cksum;
 495         unsigned int reserved[3];
 496         struct extended_signature sigs[0];
 497 };
 498
 499 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 500 static inline void rep_nop(void)
 501 {
 502         __asm__ __volatile__("rep;nop": : :"memory");
 503 }
 504
 505 #define cpu_relax()     rep_nop()
 506
 507 static inline void native_load_esp0(struct tss_struct *tss, struct thread_struct *thread)
 508 {
 509         tss->x86_tss.esp0 = thread->esp0;
 510         /* This can only happen when SEP is enabled, no need to test "SEP"arately */
 511         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
 512                 tss->x86_tss.ss1 = thread->sysenter_cs;
 513                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 514         }
 515 }
 516
 517
 518 static inline unsigned long native_get_debugreg(int regno)
 519 {
 520         unsigned long val = 0;  /* Damn you, gcc! */
 521
 522         switch (regno) {
 523         case 0:
 524                 asm("movl %%db0, %0" :"=r" (val)); break;
 525         case 1:
 526                 asm("movl %%db1, %0" :"=r" (val)); break;
 527         case 2:
 528                 asm("movl %%db2, %0" :"=r" (val)); break;
 529         case 3:
 530                 asm("movl %%db3, %0" :"=r" (val)); break;
 531         case 6:
 532                 asm("movl %%db6, %0" :"=r" (val)); break;
 533         case 7:
 534                 asm("movl %%db7, %0" :"=r" (val)); break;
 535         default:
 536                 BUG();
 537         }
 538         return val;
 539 }
 540
 541 static inline void native_set_debugreg(int regno, unsigned long value)
 542 {
 543         switch (regno) {
 544         case 0:
 545                 asm("movl %0,%%db0"     : /* no output */ :"r" (value));
 546                 break;
 547         case 1:
 548                 asm("movl %0,%%db1"     : /* no output */ :"r" (value));
 549                 break;
 550         case 2:
 551                 asm("movl %0,%%db2"     : /* no output */ :"r" (value));
 552                 break;
 553         case 3:
 554                 asm("movl %0,%%db3"     : /* no output */ :"r" (value));
 555                 break;
 556         case 6:
 557                 asm("movl %0,%%db6"     : /* no output */ :"r" (value));
 558                 break;
 559         case 7:
 560                 asm("movl %0,%%db7"     : /* no output */ :"r" (value));
 561                 break;
 562         default:
 563                 BUG();
 564         }
 565 }
 566
 567 /*
 568  * Set IOPL bits in EFLAGS from given mask
 569  */
 570 static inline void native_set_iopl_mask(unsigned mask)
 571 {
 572         unsigned int reg;
 573         __asm__ __volatile__ ("pushfl;"
 574                               "popl %0;"
 575                               "andl %1, %0;"
 576                               "orl %2, %0;"
 577                               "pushl %0;"
 578                               "popfl"
 579                                 : "=&r" (reg)
 580                                 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 581 }
 582
 583 #ifdef CONFIG_PARAVIRT
 584 #include <asm/paravirt.h>
 585 #else
 586 #define paravirt_enabled() 0
 587 #define __cpuid native_cpuid
 588
 589 static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
 590 {
 591         native_load_esp0(tss, thread);
 592 }
 593
 594 /*
 595  * These special macros can be used to get or set a debugging register
 596  */
 597 #define get_debugreg(var, register)                             \
 598         (var) = native_get_debugreg(register)
 599 #define set_debugreg(value, register)                           \
 600         native_set_debugreg(register, value)
 601
 602 #define set_iopl_mask native_set_iopl_mask
 603 #endif /* CONFIG_PARAVIRT */
 604
 605 /*
 606  * Generic CPUID function
 607  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 608  * resulting in stale register contents being returned.
 609  */
 610 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
 611 {
 612         *eax = op;
 613         *ecx = 0;
 614         __cpuid(eax, ebx, ecx, edx);
 615 }
 616
 617 /* Some CPUID calls want 'count' to be placed in ecx */
 618 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
 619                                int *edx)
 620 {
 621         *eax = op;
 622         *ecx = count;
 623         __cpuid(eax, ebx, ecx, edx);
 624 }
 625
 626 /*
 627  * CPUID functions returning a single datum
 628  */
 629 static inline unsigned int cpuid_eax(unsigned int op)
 630 {
 631         unsigned int eax, ebx, ecx, edx;
 632
 633         cpuid(op, &eax, &ebx, &ecx, &edx);
 634         return eax;
 635 }
 636 static inline unsigned int cpuid_ebx(unsigned int op)
 637 {
 638         unsigned int eax, ebx, ecx, edx;
 639
 640         cpuid(op, &eax, &ebx, &ecx, &edx);
 641         return ebx;
 642 }
 643 static inline unsigned int cpuid_ecx(unsigned int op)
 644 {
 645         unsigned int eax, ebx, ecx, edx;
 646
 647         cpuid(op, &eax, &ebx, &ecx, &edx);
 648         return ecx;
 649 }
 650 static inline unsigned int cpuid_edx(unsigned int op)
 651 {
 652         unsigned int eax, ebx, ecx, edx;
 653
 654         cpuid(op, &eax, &ebx, &ecx, &edx);
 655         return edx;
 656 }
 657
 658 /* generic versions from gas */
 659 #define GENERIC_NOP1    ".byte 0x90\n"
 660 #define GENERIC_NOP2            ".byte 0x89,0xf6\n"
 661 #define GENERIC_NOP3        ".byte 0x8d,0x76,0x00\n"
 662 #define GENERIC_NOP4        ".byte 0x8d,0x74,0x26,0x00\n"
 663 #define GENERIC_NOP5        GENERIC_NOP1 GENERIC_NOP4
 664 #define GENERIC_NOP6    ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
 665 #define GENERIC_NOP7    ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
 666 #define GENERIC_NOP8    GENERIC_NOP1 GENERIC_NOP7
 667
 668 /* Opteron nops */
 669 #define K8_NOP1 GENERIC_NOP1
 670 #define K8_NOP2 ".byte 0x66,0x90\n"
 671 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
 672 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
 673 #define K8_NOP5 K8_NOP3 K8_NOP2
 674 #define K8_NOP6 K8_NOP3 K8_NOP3
 675 #define K8_NOP7 K8_NOP4 K8_NOP3
 676 #define K8_NOP8 K8_NOP4 K8_NOP4
 677
 678 /* K7 nops */
 679 /* uses eax dependencies (arbitary choice) */
 680 #define K7_NOP1  GENERIC_NOP1
 681 #define K7_NOP2 ".byte 0x8b,0xc0\n"
 682 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
 683 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
 684 #define K7_NOP5 K7_NOP4 ASM_NOP1
 685 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
 686 #define K7_NOP7        ".byte 0x8D,0x04,0x05,0,0,0,0\n"
 687 #define K7_NOP8        K7_NOP7 ASM_NOP1
 688
 689 #ifdef CONFIG_MK8
 690 #define ASM_NOP1 K8_NOP1
 691 #define ASM_NOP2 K8_NOP2
 692 #define ASM_NOP3 K8_NOP3
 693 #define ASM_NOP4 K8_NOP4
 694 #define ASM_NOP5 K8_NOP5
 695 #define ASM_NOP6 K8_NOP6
 696 #define ASM_NOP7 K8_NOP7
 697 #define ASM_NOP8 K8_NOP8
 698 #elif defined(CONFIG_MK7)
 699 #define ASM_NOP1 K7_NOP1
 700 #define ASM_NOP2 K7_NOP2
 701 #define ASM_NOP3 K7_NOP3
 702 #define ASM_NOP4 K7_NOP4
 703 #define ASM_NOP5 K7_NOP5
 704 #define ASM_NOP6 K7_NOP6
 705 #define ASM_NOP7 K7_NOP7
 706 #define ASM_NOP8 K7_NOP8
 707 #else
 708 #define ASM_NOP1 GENERIC_NOP1
 709 #define ASM_NOP2 GENERIC_NOP2
 710 #define ASM_NOP3 GENERIC_NOP3
 711 #define ASM_NOP4 GENERIC_NOP4
 712 #define ASM_NOP5 GENERIC_NOP5
 713 #define ASM_NOP6 GENERIC_NOP6
 714 #define ASM_NOP7 GENERIC_NOP7
 715 #define ASM_NOP8 GENERIC_NOP8
 716 #endif
 717
 718 #define ASM_NOP_MAX 8
 719
 720 /* Prefetch instructions for Pentium III and AMD Athlon */
 721 /* It's not worth to care about 3dnow! prefetches for the K6
 722    because they are microcoded there and very slow.
 723    However we don't do prefetches for pre XP Athlons currently
 724    That should be fixed. */
 725 #define ARCH_HAS_PREFETCH
 726 static inline void prefetch(const void *x)
 727 {
 728         alternative_input(ASM_NOP4,
 729                           "prefetchnta (%1)",
 730                           X86_FEATURE_XMM,
 731                           "r" (x));
 732 }
 733
 734 #define ARCH_HAS_PREFETCH
 735 #define ARCH_HAS_PREFETCHW
 736 #define ARCH_HAS_SPINLOCK_PREFETCH
 737
 738 /* 3dnow! prefetch to get an exclusive cache line. Useful for
 739    spinlocks to avoid one state transition in the cache coherency protocol. */
 740 static inline void prefetchw(const void *x)
 741 {
 742         alternative_input(ASM_NOP4,
 743                           "prefetchw (%1)",
 744                           X86_FEATURE_3DNOW,
 745                           "r" (x));
 746 }
 747 #define spin_lock_prefetch(x)   prefetchw(x)
 748
 749 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 750
 751 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
 752
 753 extern unsigned long boot_option_idle_override;
 754 extern void enable_sep_cpu(void);
 755 extern int sysenter_setup(void);
 756
 757 /* Defined in head.S */
 758 extern struct Xgt_desc_struct early_gdt_descr;
 759
 760 extern void cpu_set_gdt(int);
 761 extern void switch_to_new_gdt(void);
 762 extern void cpu_init(void);
 763 extern void init_gdt(int cpu);
 764
 765 extern int force_mwait;
 766
 767 #endif /* __ASM_I386_PROCESSOR_H */