include/asm-i386/processor.h

   1 /*
   2  * include/asm-i386/processor.h
   3  *
   4  * Copyright (C) 1994 Linus Torvalds
   5  */
   6
   7 #ifndef __ASM_I386_PROCESSOR_H
   8 #define __ASM_I386_PROCESSOR_H
   9
  10 #include <asm/vm86.h>
  11 #include <asm/math_emu.h>
  12 #include <asm/segment.h>
  13 #include <asm/page.h>
  14 #include <asm/types.h>
  15 #include <asm/sigcontext.h>
  16 #include <asm/cpufeature.h>
  17 #include <asm/msr.h>
  18 #include <asm/system.h>
  19 #include <linux/cache.h>
  20 #include <linux/threads.h>
  21 #include <asm/percpu.h>
  22 #include <linux/cpumask.h>
  23 #include <linux/init.h>
  24 #include <asm/processor-flags.h>
  25
  26 /* flag for disabling the tsc */
  27 extern int tsc_disable;
  28
  29 struct desc_struct {
  30         unsigned long a,b;
  31 };
  32
  33 #define desc_empty(desc) \
  34                 (!((desc)->a | (desc)->b))
  35
  36 #define desc_equal(desc1, desc2) \
  37                 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
  38 /*
  39  * Default implementation of macro that returns current
  40  * instruction pointer ("program counter").
  41  */
  42 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
  43
  44 /*
  45  *  CPU type and hardware bug flags. Kept separately for each CPU.
  46  *  Members of this structure are referenced in head.S, so think twice
  47  *  before touching them. [mj]
  48  */
  49
  50 struct cpuinfo_x86 {
  51         __u8    x86;            /* CPU family */
  52         __u8    x86_vendor;     /* CPU vendor */
  53         __u8    x86_model;
  54         __u8    x86_mask;
  55         char    wp_works_ok;    /* It doesn't on 386's */
  56         char    hlt_works_ok;   /* Problems on some 486Dx4's and old 386's */
  57         char    hard_math;
  58         char    rfu;
  59         int     cpuid_level;    /* Maximum supported CPUID level, -1=no CPUID */
  60         unsigned long   x86_capability[NCAPINTS];
  61         char    x86_vendor_id[16];
  62         char    x86_model_id[64];
  63         int     x86_cache_size;  /* in KB - valid for CPUS which support this
  64                                     call  */
  65         int     x86_cache_alignment;    /* In bytes */
  66         char    fdiv_bug;
  67         char    f00f_bug;
  68         char    coma_bug;
  69         char    pad0;
  70         int     x86_power;
  71         unsigned long loops_per_jiffy;
  72 #ifdef CONFIG_SMP
  73         cpumask_t llc_shared_map;       /* cpus sharing the last level cache */
  74 #endif
  75         unsigned char x86_max_cores;    /* cpuid returned max cores value */
  76         unsigned char apicid;
  77         unsigned short x86_clflush_size;
  78 #ifdef CONFIG_SMP
  79         unsigned char booted_cores;     /* number of cores as seen by OS */
  80         __u8 phys_proc_id;              /* Physical processor id. */
  81         __u8 cpu_core_id;               /* Core id */
  82 #endif
  83 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
  84
  85 #define X86_VENDOR_INTEL 0
  86 #define X86_VENDOR_CYRIX 1
  87 #define X86_VENDOR_AMD 2
  88 #define X86_VENDOR_UMC 3
  89 #define X86_VENDOR_NEXGEN 4
  90 #define X86_VENDOR_CENTAUR 5
  91 #define X86_VENDOR_RISE 6
  92 #define X86_VENDOR_TRANSMETA 7
  93 #define X86_VENDOR_NSC 8
  94 #define X86_VENDOR_NUM 9
  95 #define X86_VENDOR_UNKNOWN 0xff
  96
  97 /*
  98  * capabilities of CPUs
  99  */
 100
 101 extern struct cpuinfo_x86 boot_cpu_data;
 102 extern struct cpuinfo_x86 new_cpu_data;
 103 extern struct tss_struct doublefault_tss;
 104 DECLARE_PER_CPU(struct tss_struct, init_tss);
 105
 106 #ifdef CONFIG_SMP
 107 extern struct cpuinfo_x86 cpu_data[];
 108 #define current_cpu_data cpu_data[smp_processor_id()]
 109 #else
 110 #define cpu_data (&boot_cpu_data)
 111 #define current_cpu_data boot_cpu_data
 112 #endif
 113
 114 extern  int cpu_llc_id[NR_CPUS];
 115 extern char ignore_fpu_irq;
 116
 117 void __init cpu_detect(struct cpuinfo_x86 *c);
 118
 119 extern void identify_boot_cpu(void);
 120 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 121 extern void print_cpu_info(struct cpuinfo_x86 *);
 122 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 123 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 124 extern unsigned short num_cache_leaves;
 125
 126 #ifdef CONFIG_X86_HT
 127 extern void detect_ht(struct cpuinfo_x86 *c);
 128 #else
 129 static inline void detect_ht(struct cpuinfo_x86 *c) {}
 130 #endif
 131
 132 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 133                                          unsigned int *ecx, unsigned int *edx)
 134 {
 135         /* ecx is often an input as well as an output. */
 136         __asm__("cpuid"
 137                 : "=a" (*eax),
 138                   "=b" (*ebx),
 139                   "=c" (*ecx),
 140                   "=d" (*edx)
 141                 : "0" (*eax), "2" (*ecx));
 142 }
 143
 144 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
 145
 146 /*
 147  * Save the cr4 feature set we're using (ie
 148  * Pentium 4MB enable and PPro Global page
 149  * enable), so that any CPU's that boot up
 150  * after us can get the correct flags.
 151  */
 152 extern unsigned long mmu_cr4_features;
 153
 154 static inline void set_in_cr4 (unsigned long mask)
 155 {
 156         unsigned cr4;
 157         mmu_cr4_features |= mask;
 158         cr4 = read_cr4();
 159         cr4 |= mask;
 160         write_cr4(cr4);
 161 }
 162
 163 static inline void clear_in_cr4 (unsigned long mask)
 164 {
 165         unsigned cr4;
 166         mmu_cr4_features &= ~mask;
 167         cr4 = read_cr4();
 168         cr4 &= ~mask;
 169         write_cr4(cr4);
 170 }
 171
 172 /*
 173  *      NSC/Cyrix CPU indexed register access macros
 174  */
 175
 176 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
 177
 178 #define setCx86(reg, data) do { \
 179         outb((reg), 0x22); \
 180         outb((data), 0x23); \
 181 } while (0)
 182
 183 /* Stop speculative execution */
 184 static inline void sync_core(void)
 185 {
 186         int tmp;
 187         asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
 188 }
 189
 190 static inline void __monitor(const void *eax, unsigned long ecx,
 191                 unsigned long edx)
 192 {
 193         /* "monitor %eax,%ecx,%edx;" */
 194         asm volatile(
 195                 ".byte 0x0f,0x01,0xc8;"
 196                 : :"a" (eax), "c" (ecx), "d"(edx));
 197 }
 198
 199 static inline void __mwait(unsigned long eax, unsigned long ecx)
 200 {
 201         /* "mwait %eax,%ecx;" */
 202         asm volatile(
 203                 ".byte 0x0f,0x01,0xc9;"
 204                 : :"a" (eax), "c" (ecx));
 205 }
 206
 207 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
 208
 209 /* from system description table in BIOS.  Mostly for MCA use, but
 210 others may find it useful. */
 211 extern unsigned int machine_id;
 212 extern unsigned int machine_submodel_id;
 213 extern unsigned int BIOS_revision;
 214 extern unsigned int mca_pentium_flag;
 215
 216 /* Boot loader type from the setup header */
 217 extern int bootloader_type;
 218
 219 /*
 220  * User space process size: 3GB (default).
 221  */
 222 #define TASK_SIZE       (PAGE_OFFSET)
 223
 224 /* This decides where the kernel will search for a free chunk of vm
 225  * space during mmap's.
 226  */
 227 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 228
 229 #define HAVE_ARCH_PICK_MMAP_LAYOUT
 230
 231 /*
 232  * Size of io_bitmap.
 233  */
 234 #define IO_BITMAP_BITS  65536
 235 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
 236 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
 237 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
 238 #define INVALID_IO_BITMAP_OFFSET 0x8000
 239 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
 240
 241 struct i387_fsave_struct {
 242         long    cwd;
 243         long    swd;
 244         long    twd;
 245         long    fip;
 246         long    fcs;
 247         long    foo;
 248         long    fos;
 249         long    st_space[20];   /* 8*10 bytes for each FP-reg = 80 bytes */
 250         long    status;         /* software status information */
 251 };
 252
 253 struct i387_fxsave_struct {
 254         unsigned short  cwd;
 255         unsigned short  swd;
 256         unsigned short  twd;
 257         unsigned short  fop;
 258         long    fip;
 259         long    fcs;
 260         long    foo;
 261         long    fos;
 262         long    mxcsr;
 263         long    mxcsr_mask;
 264         long    st_space[32];   /* 8*16 bytes for each FP-reg = 128 bytes */
 265         long    xmm_space[32];  /* 8*16 bytes for each XMM-reg = 128 bytes */
 266         long    padding[56];
 267 } __attribute__ ((aligned (16)));
 268
 269 struct i387_soft_struct {
 270         long    cwd;
 271         long    swd;
 272         long    twd;
 273         long    fip;
 274         long    fcs;
 275         long    foo;
 276         long    fos;
 277         long    st_space[20];   /* 8*10 bytes for each FP-reg = 80 bytes */
 278         unsigned char   ftop, changed, lookahead, no_update, rm, alimit;
 279         struct info     *info;
 280         unsigned long   entry_eip;
 281 };
 282
 283 union i387_union {
 284         struct i387_fsave_struct        fsave;
 285         struct i387_fxsave_struct       fxsave;
 286         struct i387_soft_struct soft;
 287 };
 288
 289 typedef struct {
 290         unsigned long seg;
 291 } mm_segment_t;
 292
 293 struct thread_struct;
 294
 295 /* This is the TSS defined by the hardware. */
 296 struct i386_hw_tss {
 297         unsigned short  back_link,__blh;
 298         unsigned long   esp0;
 299         unsigned short  ss0,__ss0h;
 300         unsigned long   esp1;
 301         unsigned short  ss1,__ss1h;     /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
 302         unsigned long   esp2;
 303         unsigned short  ss2,__ss2h;
 304         unsigned long   __cr3;
 305         unsigned long   eip;
 306         unsigned long   eflags;
 307         unsigned long   eax,ecx,edx,ebx;
 308         unsigned long   esp;
 309         unsigned long   ebp;
 310         unsigned long   esi;
 311         unsigned long   edi;
 312         unsigned short  es, __esh;
 313         unsigned short  cs, __csh;
 314         unsigned short  ss, __ssh;
 315         unsigned short  ds, __dsh;
 316         unsigned short  fs, __fsh;
 317         unsigned short  gs, __gsh;
 318         unsigned short  ldt, __ldth;
 319         unsigned short  trace, io_bitmap_base;
 320 } __attribute__((packed));
 321
 322 struct tss_struct {
 323         struct i386_hw_tss x86_tss;
 324
 325         /*
 326          * The extra 1 is there because the CPU will access an
 327          * additional byte beyond the end of the IO permission
 328          * bitmap. The extra byte must be all 1 bits, and must
 329          * be within the limit.
 330          */
 331         unsigned long   io_bitmap[IO_BITMAP_LONGS + 1];
 332         /*
 333          * Cache the current maximum and the last task that used the bitmap:
 334          */
 335         unsigned long io_bitmap_max;
 336         struct thread_struct *io_bitmap_owner;
 337         /*
 338          * pads the TSS to be cacheline-aligned (size is 0x100)
 339          */
 340         unsigned long __cacheline_filler[35];
 341         /*
 342          * .. and then another 0x100 bytes for emergency kernel stack
 343          */
 344         unsigned long stack[64];
 345 } __attribute__((packed));
 346
 347 #define ARCH_MIN_TASKALIGN      16
 348
 349 struct thread_struct {
 350 /* cached TLS descriptors. */
 351         struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
 352         unsigned long   esp0;
 353         unsigned long   sysenter_cs;
 354         unsigned long   eip;
 355         unsigned long   esp;
 356         unsigned long   fs;
 357         unsigned long   gs;
 358 /* Hardware debugging registers */
 359         unsigned long   debugreg[8];  /* %%db0-7 debug registers */
 360 /* fault info */
 361         unsigned long   cr2, trap_no, error_code;
 362 /* floating point info */
 363         union i387_union        i387;
 364 /* virtual 86 mode info */
 365         struct vm86_struct __user * vm86_info;
 366         unsigned long           screen_bitmap;
 367         unsigned long           v86flags, v86mask, saved_esp0;
 368         unsigned int            saved_fs, saved_gs;
 369 /* IO permissions */
 370         unsigned long   *io_bitmap_ptr;
 371         unsigned long   iopl;
 372 /* max allowed port in the bitmap, in bytes: */
 373         unsigned long   io_bitmap_max;
 374 };
 375
 376 #define INIT_THREAD  {                                                  \
 377         .esp0 = sizeof(init_stack) + (long)&init_stack,                 \
 378         .vm86_info = NULL,                                              \
 379         .sysenter_cs = __KERNEL_CS,                                     \
 380         .io_bitmap_ptr = NULL,                                          \
 381         .fs = __KERNEL_PERCPU,                                          \
 382 }
 383
 384 /*
 385  * Note that the .io_bitmap member must be extra-big. This is because
 386  * the CPU will access an additional byte beyond the end of the IO
 387  * permission bitmap. The extra byte must be all 1 bits, and must
 388  * be within the limit.
 389  */
 390 #define INIT_TSS  {                                                     \
 391         .x86_tss = {                                                    \
 392                 .esp0           = sizeof(init_stack) + (long)&init_stack, \
 393                 .ss0            = __KERNEL_DS,                          \
 394                 .ss1            = __KERNEL_CS,                          \
 395                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,             \
 396          },                                                             \
 397         .io_bitmap      = { [ 0 ... IO_BITMAP_LONGS] = ~0 },            \
 398 }
 399
 400 #define start_thread(regs, new_eip, new_esp) do {               \
 401         __asm__("movl %0,%%gs": :"r" (0));                      \
 402         regs->xfs = 0;                                          \
 403         set_fs(USER_DS);                                        \
 404         regs->xds = __USER_DS;                                  \
 405         regs->xes = __USER_DS;                                  \
 406         regs->xss = __USER_DS;                                  \
 407         regs->xcs = __USER_CS;                                  \
 408         regs->eip = new_eip;                                    \
 409         regs->esp = new_esp;                                    \
 410 } while (0)
 411
 412 /* Forward declaration, a strange C thing */
 413 struct task_struct;
 414 struct mm_struct;
 415
 416 /* Free all resources held by a thread. */
 417 extern void release_thread(struct task_struct *);
 418
 419 /* Prepare to copy thread state - unlazy all lazy status */
 420 extern void prepare_to_copy(struct task_struct *tsk);
 421
 422 /*
 423  * create a kernel thread without removing it from tasklists
 424  */
 425 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
 426
 427 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 428 void show_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack);
 429
 430 unsigned long get_wchan(struct task_struct *p);
 431
 432 #define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
 433 #define KSTK_TOP(info)                                                 \
 434 ({                                                                     \
 435        unsigned long *__ptr = (unsigned long *)(info);                 \
 436        (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
 437 })
 438
 439 /*
 440  * The below -8 is to reserve 8 bytes on top of the ring0 stack.
 441  * This is necessary to guarantee that the entire "struct pt_regs"
 442  * is accessable even if the CPU haven't stored the SS/ESP registers
 443  * on the stack (interrupt gate does not save these registers
 444  * when switching to the same priv ring).
 445  * Therefore beware: accessing the xss/esp fields of the
 446  * "struct pt_regs" is possible, but they may contain the
 447  * completely wrong values.
 448  */
 449 #define task_pt_regs(task)                                             \
 450 ({                                                                     \
 451        struct pt_regs *__regs__;                                       \
 452        __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
 453        __regs__ - 1;                                                   \
 454 })
 455
 456 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
 457 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
 458
 459
 460 struct microcode_header {
 461         unsigned int hdrver;
 462         unsigned int rev;
 463         unsigned int date;
 464         unsigned int sig;
 465         unsigned int cksum;
 466         unsigned int ldrver;
 467         unsigned int pf;
 468         unsigned int datasize;
 469         unsigned int totalsize;
 470         unsigned int reserved[3];
 471 };
 472
 473 struct microcode {
 474         struct microcode_header hdr;
 475         unsigned int bits[0];
 476 };
 477
 478 typedef struct microcode microcode_t;
 479 typedef struct microcode_header microcode_header_t;
 480
 481 /* microcode format is extended from prescott processors */
 482 struct extended_signature {
 483         unsigned int sig;
 484         unsigned int pf;
 485         unsigned int cksum;
 486 };
 487
 488 struct extended_sigtable {
 489         unsigned int count;
 490         unsigned int cksum;
 491         unsigned int reserved[3];
 492         struct extended_signature sigs[0];
 493 };
 494
 495 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 496 static inline void rep_nop(void)
 497 {
 498         __asm__ __volatile__("rep;nop": : :"memory");
 499 }
 500
 501 #define cpu_relax()     rep_nop()
 502
 503 static inline void native_load_esp0(struct tss_struct *tss, struct thread_struct *thread)
 504 {
 505         tss->x86_tss.esp0 = thread->esp0;
 506         /* This can only happen when SEP is enabled, no need to test "SEP"arately */
 507         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
 508                 tss->x86_tss.ss1 = thread->sysenter_cs;
 509                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 510         }
 511 }
 512
 513
 514 static inline unsigned long native_get_debugreg(int regno)
 515 {
 516         unsigned long val = 0;  /* Damn you, gcc! */
 517
 518         switch (regno) {
 519         case 0:
 520                 asm("movl %%db0, %0" :"=r" (val)); break;
 521         case 1:
 522                 asm("movl %%db1, %0" :"=r" (val)); break;
 523         case 2:
 524                 asm("movl %%db2, %0" :"=r" (val)); break;
 525         case 3:
 526                 asm("movl %%db3, %0" :"=r" (val)); break;
 527         case 6:
 528                 asm("movl %%db6, %0" :"=r" (val)); break;
 529         case 7:
 530                 asm("movl %%db7, %0" :"=r" (val)); break;
 531         default:
 532                 BUG();
 533         }
 534         return val;
 535 }
 536
 537 static inline void native_set_debugreg(int regno, unsigned long value)
 538 {
 539         switch (regno) {
 540         case 0:
 541                 asm("movl %0,%%db0"     : /* no output */ :"r" (value));
 542                 break;
 543         case 1:
 544                 asm("movl %0,%%db1"     : /* no output */ :"r" (value));
 545                 break;
 546         case 2:
 547                 asm("movl %0,%%db2"     : /* no output */ :"r" (value));
 548                 break;
 549         case 3:
 550                 asm("movl %0,%%db3"     : /* no output */ :"r" (value));
 551                 break;
 552         case 6:
 553                 asm("movl %0,%%db6"     : /* no output */ :"r" (value));
 554                 break;
 555         case 7:
 556                 asm("movl %0,%%db7"     : /* no output */ :"r" (value));
 557                 break;
 558         default:
 559                 BUG();
 560         }
 561 }
 562
 563 /*
 564  * Set IOPL bits in EFLAGS from given mask
 565  */
 566 static inline void native_set_iopl_mask(unsigned mask)
 567 {
 568         unsigned int reg;
 569         __asm__ __volatile__ ("pushfl;"
 570                               "popl %0;"
 571                               "andl %1, %0;"
 572                               "orl %2, %0;"
 573                               "pushl %0;"
 574                               "popfl"
 575                                 : "=&r" (reg)
 576                                 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 577 }
 578
 579 #ifdef CONFIG_PARAVIRT
 580 #include <asm/paravirt.h>
 581 #else
 582 #define paravirt_enabled() 0
 583 #define __cpuid native_cpuid
 584
 585 static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
 586 {
 587         native_load_esp0(tss, thread);
 588 }
 589
 590 /*
 591  * These special macros can be used to get or set a debugging register
 592  */
 593 #define get_debugreg(var, register)                             \
 594         (var) = native_get_debugreg(register)
 595 #define set_debugreg(value, register)                           \
 596         native_set_debugreg(register, value)
 597
 598 #define set_iopl_mask native_set_iopl_mask
 599 #endif /* CONFIG_PARAVIRT */
 600
 601 /*
 602  * Generic CPUID function
 603  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 604  * resulting in stale register contents being returned.
 605  */
 606 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
 607 {
 608         *eax = op;
 609         *ecx = 0;
 610         __cpuid(eax, ebx, ecx, edx);
 611 }
 612
 613 /* Some CPUID calls want 'count' to be placed in ecx */
 614 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
 615                                int *edx)
 616 {
 617         *eax = op;
 618         *ecx = count;
 619         __cpuid(eax, ebx, ecx, edx);
 620 }
 621
 622 /*
 623  * CPUID functions returning a single datum
 624  */
 625 static inline unsigned int cpuid_eax(unsigned int op)
 626 {
 627         unsigned int eax, ebx, ecx, edx;
 628
 629         cpuid(op, &eax, &ebx, &ecx, &edx);
 630         return eax;
 631 }
 632 static inline unsigned int cpuid_ebx(unsigned int op)
 633 {
 634         unsigned int eax, ebx, ecx, edx;
 635
 636         cpuid(op, &eax, &ebx, &ecx, &edx);
 637         return ebx;
 638 }
 639 static inline unsigned int cpuid_ecx(unsigned int op)
 640 {
 641         unsigned int eax, ebx, ecx, edx;
 642
 643         cpuid(op, &eax, &ebx, &ecx, &edx);
 644         return ecx;
 645 }
 646 static inline unsigned int cpuid_edx(unsigned int op)
 647 {
 648         unsigned int eax, ebx, ecx, edx;
 649
 650         cpuid(op, &eax, &ebx, &ecx, &edx);
 651         return edx;
 652 }
 653
 654 /* generic versions from gas */
 655 #define GENERIC_NOP1    ".byte 0x90\n"
 656 #define GENERIC_NOP2            ".byte 0x89,0xf6\n"
 657 #define GENERIC_NOP3        ".byte 0x8d,0x76,0x00\n"
 658 #define GENERIC_NOP4        ".byte 0x8d,0x74,0x26,0x00\n"
 659 #define GENERIC_NOP5        GENERIC_NOP1 GENERIC_NOP4
 660 #define GENERIC_NOP6    ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
 661 #define GENERIC_NOP7    ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
 662 #define GENERIC_NOP8    GENERIC_NOP1 GENERIC_NOP7
 663
 664 /* Opteron nops */
 665 #define K8_NOP1 GENERIC_NOP1
 666 #define K8_NOP2 ".byte 0x66,0x90\n"
 667 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
 668 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
 669 #define K8_NOP5 K8_NOP3 K8_NOP2
 670 #define K8_NOP6 K8_NOP3 K8_NOP3
 671 #define K8_NOP7 K8_NOP4 K8_NOP3
 672 #define K8_NOP8 K8_NOP4 K8_NOP4
 673
 674 /* K7 nops */
 675 /* uses eax dependencies (arbitary choice) */
 676 #define K7_NOP1  GENERIC_NOP1
 677 #define K7_NOP2 ".byte 0x8b,0xc0\n"
 678 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
 679 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
 680 #define K7_NOP5 K7_NOP4 ASM_NOP1
 681 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
 682 #define K7_NOP7        ".byte 0x8D,0x04,0x05,0,0,0,0\n"
 683 #define K7_NOP8        K7_NOP7 ASM_NOP1
 684
 685 #ifdef CONFIG_MK8
 686 #define ASM_NOP1 K8_NOP1
 687 #define ASM_NOP2 K8_NOP2
 688 #define ASM_NOP3 K8_NOP3
 689 #define ASM_NOP4 K8_NOP4
 690 #define ASM_NOP5 K8_NOP5
 691 #define ASM_NOP6 K8_NOP6
 692 #define ASM_NOP7 K8_NOP7
 693 #define ASM_NOP8 K8_NOP8
 694 #elif defined(CONFIG_MK7)
 695 #define ASM_NOP1 K7_NOP1
 696 #define ASM_NOP2 K7_NOP2
 697 #define ASM_NOP3 K7_NOP3
 698 #define ASM_NOP4 K7_NOP4
 699 #define ASM_NOP5 K7_NOP5
 700 #define ASM_NOP6 K7_NOP6
 701 #define ASM_NOP7 K7_NOP7
 702 #define ASM_NOP8 K7_NOP8
 703 #else
 704 #define ASM_NOP1 GENERIC_NOP1
 705 #define ASM_NOP2 GENERIC_NOP2
 706 #define ASM_NOP3 GENERIC_NOP3
 707 #define ASM_NOP4 GENERIC_NOP4
 708 #define ASM_NOP5 GENERIC_NOP5
 709 #define ASM_NOP6 GENERIC_NOP6
 710 #define ASM_NOP7 GENERIC_NOP7
 711 #define ASM_NOP8 GENERIC_NOP8
 712 #endif
 713
 714 #define ASM_NOP_MAX 8
 715
 716 /* Prefetch instructions for Pentium III and AMD Athlon */
 717 /* It's not worth to care about 3dnow! prefetches for the K6
 718    because they are microcoded there and very slow.
 719    However we don't do prefetches for pre XP Athlons currently
 720    That should be fixed. */
 721 #define ARCH_HAS_PREFETCH
 722 static inline void prefetch(const void *x)
 723 {
 724         alternative_input(ASM_NOP4,
 725                           "prefetchnta (%1)",
 726                           X86_FEATURE_XMM,
 727                           "r" (x));
 728 }
 729
 730 #define ARCH_HAS_PREFETCH
 731 #define ARCH_HAS_PREFETCHW
 732 #define ARCH_HAS_SPINLOCK_PREFETCH
 733
 734 /* 3dnow! prefetch to get an exclusive cache line. Useful for
 735    spinlocks to avoid one state transition in the cache coherency protocol. */
 736 static inline void prefetchw(const void *x)
 737 {
 738         alternative_input(ASM_NOP4,
 739                           "prefetchw (%1)",
 740                           X86_FEATURE_3DNOW,
 741                           "r" (x));
 742 }
 743 #define spin_lock_prefetch(x)   prefetchw(x)
 744
 745 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 746
 747 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
 748
 749 extern unsigned long boot_option_idle_override;
 750 extern void enable_sep_cpu(void);
 751 extern int sysenter_setup(void);
 752
 753 /* Defined in head.S */
 754 extern struct Xgt_desc_struct early_gdt_descr;
 755
 756 extern void cpu_set_gdt(int);
 757 extern void switch_to_new_gdt(void);
 758 extern void cpu_init(void);
 759 extern void init_gdt(int cpu);
 760
 761 extern int force_mwait;
 762
 763 #endif /* __ASM_I386_PROCESSOR_H */