include/asm-ia64/intel_intrin.h

   1 #ifndef _ASM_IA64_INTEL_INTRIN_H
   2 #define _ASM_IA64_INTEL_INTRIN_H
   3 /*
   4  * Intel Compiler Intrinsics
   5  *
   6  * Copyright (C) 2002,2003 Jun Nakajima <jun.nakajima@intel.com>
   7  * Copyright (C) 2002,2003 Suresh Siddha <suresh.b.siddha@intel.com>
   8  *
   9  */
  10 #include <asm/types.h>
  11
  12 void  __lfetch(int lfhint, void *y);
  13 void  __lfetch_excl(int lfhint, void *y);
  14 void  __lfetch_fault(int lfhint, void *y);
  15 void  __lfetch_fault_excl(int lfhint, void *y);
  16
  17 /* In the following, whichFloatReg should be an integer from 0-127 */
  18 void  __ldfs(const int whichFloatReg, void *src);
  19 void  __ldfd(const int whichFloatReg, void *src);
  20 void  __ldfe(const int whichFloatReg, void *src);
  21 void  __ldf8(const int whichFloatReg, void *src);
  22 void  __ldf_fill(const int whichFloatReg, void *src);
  23 void  __stfs(void *dst, const int whichFloatReg);
  24 void  __stfd(void *dst, const int whichFloatReg);
  25 void  __stfe(void *dst, const int whichFloatReg);
  26 void  __stf8(void *dst, const int whichFloatReg);
  27 void  __stf_spill(void *dst, const int whichFloatReg);
  28
  29 void  __st1_rel(void *dst, const __s8  value);
  30 void  __st2_rel(void *dst, const __s16 value);
  31 void  __st4_rel(void *dst, const __s32 value);
  32 void  __st8_rel(void *dst, const __s64 value);
  33 __u8  __ld1_acq(void *src);
  34 __u16 __ld2_acq(void *src);
  35 __u32 __ld4_acq(void *src);
  36 __u64 __ld8_acq(void *src);
  37
  38 __u64 __fetchadd4_acq(__u32 *addend, const int increment);
  39 __u64 __fetchadd4_rel(__u32 *addend, const int increment);
  40 __u64 __fetchadd8_acq(__u64 *addend, const int increment);
  41 __u64 __fetchadd8_rel(__u64 *addend, const int increment);
  42
  43 __u64 __getf_exp(double d);
  44
  45 /* OS Related Itanium(R) Intrinsics  */
  46
  47 /* The names to use for whichReg and whichIndReg below come from
  48    the include file asm/ia64regs.h */
  49
  50 __u64 __getIndReg(const int whichIndReg, __s64 index);
  51 __u64 __getReg(const int whichReg);
  52
  53 void  __setIndReg(const int whichIndReg, __s64 index, __u64 value);
  54 void  __setReg(const int whichReg, __u64 value);
  55
  56 void  __mf(void);
  57 void  __mfa(void);
  58 void  __synci(void);
  59 void  __itcd(__s64 pa);
  60 void  __itci(__s64 pa);
  61 void  __itrd(__s64 whichTransReg, __s64 pa);
  62 void  __itri(__s64 whichTransReg, __s64 pa);
  63 void  __ptce(__s64 va);
  64 void  __ptcl(__s64 va, __s64 pagesz);
  65 void  __ptcg(__s64 va, __s64 pagesz);
  66 void  __ptcga(__s64 va, __s64 pagesz);
  67 void  __ptri(__s64 va, __s64 pagesz);
  68 void  __ptrd(__s64 va, __s64 pagesz);
  69 void  __invala (void);
  70 void  __invala_gr(const int whichGeneralReg /* 0-127 */ );
  71 void  __invala_fr(const int whichFloatReg /* 0-127 */ );
  72 void  __nop(const int);
  73 void  __fc(__u64 *addr);
  74 void  __sum(int mask);
  75 void  __rum(int mask);
  76 void  __ssm(int mask);
  77 void  __rsm(int mask);
  78 __u64 __thash(__s64);
  79 __u64 __ttag(__s64);
  80 __s64 __tpa(__s64);
  81
  82 /* Intrinsics for implementing get/put_user macros */
  83 void __st_user(const char *tableName, __u64 addr, char size, char relocType, __u64 val);
  84 void __ld_user(const char *tableName, __u64 addr, char size, char relocType);
  85
  86 /* This intrinsic does not generate code, it creates a barrier across which
  87  * the compiler will not schedule data access instructions.
  88  */
  89 void __memory_barrier(void);
  90
  91 void __isrlz(void);
  92 void __dsrlz(void);
  93
  94 __u64  _m64_mux1(__u64 a, const int n);
  95 __u64  __thash(__u64);
  96
  97 /* Lock and Atomic Operation Related Intrinsics */
  98 __u64 _InterlockedExchange8(volatile __u8 *trgt, __u8 value);
  99 __u64 _InterlockedExchange16(volatile __u16 *trgt, __u16 value);
 100 __s64 _InterlockedExchange(volatile __u32 *trgt, __u32 value);
 101 __s64 _InterlockedExchange64(volatile __u64 *trgt, __u64 value);
 102
 103 __u64 _InterlockedCompareExchange8_rel(volatile __u8 *dest, __u64 xchg, __u64 comp);
 104 __u64 _InterlockedCompareExchange8_acq(volatile __u8 *dest, __u64 xchg, __u64 comp);
 105 __u64 _InterlockedCompareExchange16_rel(volatile __u16 *dest, __u64 xchg, __u64 comp);
 106 __u64 _InterlockedCompareExchange16_acq(volatile __u16 *dest, __u64 xchg, __u64 comp);
 107 __u64 _InterlockedCompareExchange_rel(volatile __u32 *dest, __u64 xchg, __u64 comp);
 108 __u64 _InterlockedCompareExchange_acq(volatile __u32 *dest, __u64 xchg, __u64 comp);
 109 __u64 _InterlockedCompareExchange64_rel(volatile __u64 *dest, __u64 xchg, __u64 comp);
 110 __u64 _InterlockedCompareExchange64_acq(volatile __u64 *dest, __u64 xchg, __u64 comp);
 111
 112 __s64 _m64_dep_mi(const int v, __s64 s, const int p, const int len);
 113 __s64 _m64_shrp(__s64 a, __s64 b, const int count);
 114 __s64 _m64_popcnt(__s64 a);
 115
 116 #define ia64_barrier()          __memory_barrier()
 117
 118 #define ia64_stop()     /* Nothing: As of now stop bit is generated for each
 119                          * intrinsic
 120                          */
 121
 122 #define ia64_getreg             __getReg
 123 #define ia64_setreg             __setReg
 124
 125 #define ia64_hint               __hint
 126 #define ia64_hint_pause         __hint_pause
 127
 128 #define ia64_mux1_brcst  0
 129 #define ia64_mux1_mix            8
 130 #define ia64_mux1_shuf           9
 131 #define ia64_mux1_alt           10
 132 #define ia64_mux1_rev           11
 133
 134 #define ia64_mux1               _m64_mux1
 135 #define ia64_popcnt             _m64_popcnt
 136 #define ia64_getf_exp           __getf_exp
 137 #define ia64_shrp               _m64_shrp
 138
 139 #define ia64_tpa                __tpa
 140 #define ia64_invala             __invala
 141 #define ia64_invala_gr          __invala_gr
 142 #define ia64_invala_fr          __invala_fr
 143 #define ia64_nop                __nop
 144 #define ia64_sum                __sum
 145 #define ia64_ssm                __ssm
 146 #define ia64_rum                __rum
 147 #define ia64_rsm                __rsm
 148 #define ia64_fc                 __fc
 149
 150 #define ia64_ldfs               __ldfs
 151 #define ia64_ldfd               __ldfd
 152 #define ia64_ldfe               __ldfe
 153 #define ia64_ldf8               __ldf8
 154 #define ia64_ldf_fill           __ldf_fill
 155
 156 #define ia64_stfs               __stfs
 157 #define ia64_stfd               __stfd
 158 #define ia64_stfe               __stfe
 159 #define ia64_stf8               __stf8
 160 #define ia64_stf_spill          __stf_spill
 161
 162 #define ia64_mf         __mf
 163 #define ia64_mfa                __mfa
 164
 165 #define ia64_fetchadd4_acq      __fetchadd4_acq
 166 #define ia64_fetchadd4_rel      __fetchadd4_rel
 167 #define ia64_fetchadd8_acq      __fetchadd8_acq
 168 #define ia64_fetchadd8_rel      __fetchadd8_rel
 169
 170 #define ia64_xchg1              _InterlockedExchange8
 171 #define ia64_xchg2              _InterlockedExchange16
 172 #define ia64_xchg4              _InterlockedExchange
 173 #define ia64_xchg8              _InterlockedExchange64
 174
 175 #define ia64_cmpxchg1_rel       _InterlockedCompareExchange8_rel
 176 #define ia64_cmpxchg1_acq       _InterlockedCompareExchange8_acq
 177 #define ia64_cmpxchg2_rel       _InterlockedCompareExchange16_rel
 178 #define ia64_cmpxchg2_acq       _InterlockedCompareExchange16_acq
 179 #define ia64_cmpxchg4_rel       _InterlockedCompareExchange_rel
 180 #define ia64_cmpxchg4_acq       _InterlockedCompareExchange_acq
 181 #define ia64_cmpxchg8_rel       _InterlockedCompareExchange64_rel
 182 #define ia64_cmpxchg8_acq       _InterlockedCompareExchange64_acq
 183
 184 #define __ia64_set_dbr(index, val)      \
 185                 __setIndReg(_IA64_REG_INDR_DBR, index, val)
 186 #define ia64_set_ibr(index, val)        \
 187                 __setIndReg(_IA64_REG_INDR_IBR, index, val)
 188 #define ia64_set_pkr(index, val)        \
 189                 __setIndReg(_IA64_REG_INDR_PKR, index, val)
 190 #define ia64_set_pmc(index, val)        \
 191                 __setIndReg(_IA64_REG_INDR_PMC, index, val)
 192 #define ia64_set_pmd(index, val)        \
 193                 __setIndReg(_IA64_REG_INDR_PMD, index, val)
 194 #define ia64_set_rr(index, val) \
 195                 __setIndReg(_IA64_REG_INDR_RR, index, val)
 196
 197 #define ia64_get_cpuid(index)   __getIndReg(_IA64_REG_INDR_CPUID, index)
 198 #define __ia64_get_dbr(index)   __getIndReg(_IA64_REG_INDR_DBR, index)
 199 #define ia64_get_ibr(index)     __getIndReg(_IA64_REG_INDR_IBR, index)
 200 #define ia64_get_pkr(index)     __getIndReg(_IA64_REG_INDR_PKR, index)
 201 #define ia64_get_pmc(index)     __getIndReg(_IA64_REG_INDR_PMC, index)
 202 #define ia64_get_pmd(index)     __getIndReg(_IA64_REG_INDR_PMD, index)
 203 #define ia64_get_rr(index)      __getIndReg(_IA64_REG_INDR_RR, index)
 204
 205 #define ia64_srlz_d             __dsrlz
 206 #define ia64_srlz_i             __isrlz
 207
 208 #define ia64_dv_serialize_data()
 209 #define ia64_dv_serialize_instruction()
 210
 211 #define ia64_st1_rel            __st1_rel
 212 #define ia64_st2_rel            __st2_rel
 213 #define ia64_st4_rel            __st4_rel
 214 #define ia64_st8_rel            __st8_rel
 215
 216 #define ia64_ld1_acq            __ld1_acq
 217 #define ia64_ld2_acq            __ld2_acq
 218 #define ia64_ld4_acq            __ld4_acq
 219 #define ia64_ld8_acq            __ld8_acq
 220
 221 #define ia64_sync_i             __synci
 222 #define ia64_thash              __thash
 223 #define ia64_ttag               __ttag
 224 #define ia64_itcd               __itcd
 225 #define ia64_itci               __itci
 226 #define ia64_itrd               __itrd
 227 #define ia64_itri               __itri
 228 #define ia64_ptce               __ptce
 229 #define ia64_ptcl               __ptcl
 230 #define ia64_ptcg               __ptcg
 231 #define ia64_ptcga              __ptcga
 232 #define ia64_ptri               __ptri
 233 #define ia64_ptrd               __ptrd
 234 #define ia64_dep_mi             _m64_dep_mi
 235
 236 /* Values for lfhint in __lfetch and __lfetch_fault */
 237
 238 #define ia64_lfhint_none        0
 239 #define ia64_lfhint_nt1         1
 240 #define ia64_lfhint_nt2         2
 241 #define ia64_lfhint_nta         3
 242
 243 #define ia64_lfetch             __lfetch
 244 #define ia64_lfetch_excl        __lfetch_excl
 245 #define ia64_lfetch_fault       __lfetch_fault
 246 #define ia64_lfetch_fault_excl  __lfetch_fault_excl
 247
 248 #define ia64_intrin_local_irq_restore(x)                \
 249 do {                                                    \
 250         if ((x) != 0) {                                 \
 251                 ia64_ssm(IA64_PSR_I);                   \
 252                 ia64_srlz_d();                          \
 253         } else {                                        \
 254                 ia64_rsm(IA64_PSR_I);                   \
 255         }                                               \
 256 } while (0)
 257
 258 #endif /* _ASM_IA64_INTEL_INTRIN_H */