[MIPS] Use the proper technical term for naming some of the cache macros.
[deliverable/linux.git] / include / asm-mips / mach-ip27 / cpu-feature-overrides.h
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 Ralf Baechle
7 */
8 #ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
9 #define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
10
11 /*
12 * IP27 only comes with R10000 family processors all using the same config
13 */
14 #define cpu_has_watch 1
15 #define cpu_has_mips16 0
16 #define cpu_has_divec 0
17 #define cpu_has_vce 0
18 #define cpu_has_cache_cdex_p 0
19 #define cpu_has_cache_cdex_s 0
20 #define cpu_has_prefetch 1
21 #define cpu_has_mcheck 0
22 #define cpu_has_ejtag 0
23
24 #define cpu_has_llsc 1
25 #define cpu_has_vtag_icache 0
26 #define cpu_has_dc_aliases 0
27 #define cpu_has_ic_fills_f_dc 0
28 #define cpu_has_dsp 0
29 #define cpu_icache_snoops_remote_store 1
30
31 #define cpu_has_nofpuex 0
32 #define cpu_has_64bits 1
33
34 #define cpu_has_4kex 1
35 #define cpu_has_4k_cache 1
36
37 #define cpu_has_inclusive_pcaches 1
38
39 #define cpu_dcache_line_size() 32
40 #define cpu_icache_line_size() 64
41 #define cpu_scache_line_size() 128
42
43 #define cpu_has_mips32r1 0
44 #define cpu_has_mips32r2 0
45 #define cpu_has_mips64r1 0
46 #define cpu_has_mips64r2 0
47
48 #endif /* __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H */
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