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Support the MIPS32 / MIPS64 DSP ASE.
[deliverable/linux.git] / include / asm-mips / mipsregs.h
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
15
16 #include <linux/config.h>
17 #include <linux/linkage.h>
18 #include <asm/hazards.h>
19
20 /*
21 * The following macros are especially useful for __asm__
22 * inline assembler.
23 */
24 #ifndef __STR
25 #define __STR(x) #x
26 #endif
27 #ifndef STR
28 #define STR(x) __STR(x)
29 #endif
30
31 /*
32 * Configure language
33 */
34 #ifdef __ASSEMBLY__
35 #define _ULCAST_
36 #else
37 #define _ULCAST_ (unsigned long)
38 #endif
39
40 /*
41 * Coprocessor 0 register names
42 */
43 #define CP0_INDEX $0
44 #define CP0_RANDOM $1
45 #define CP0_ENTRYLO0 $2
46 #define CP0_ENTRYLO1 $3
47 #define CP0_CONF $3
48 #define CP0_CONTEXT $4
49 #define CP0_PAGEMASK $5
50 #define CP0_WIRED $6
51 #define CP0_INFO $7
52 #define CP0_BADVADDR $8
53 #define CP0_COUNT $9
54 #define CP0_ENTRYHI $10
55 #define CP0_COMPARE $11
56 #define CP0_STATUS $12
57 #define CP0_CAUSE $13
58 #define CP0_EPC $14
59 #define CP0_PRID $15
60 #define CP0_CONFIG $16
61 #define CP0_LLADDR $17
62 #define CP0_WATCHLO $18
63 #define CP0_WATCHHI $19
64 #define CP0_XCONTEXT $20
65 #define CP0_FRAMEMASK $21
66 #define CP0_DIAGNOSTIC $22
67 #define CP0_DEBUG $23
68 #define CP0_DEPC $24
69 #define CP0_PERFORMANCE $25
70 #define CP0_ECC $26
71 #define CP0_CACHEERR $27
72 #define CP0_TAGLO $28
73 #define CP0_TAGHI $29
74 #define CP0_ERROREPC $30
75 #define CP0_DESAVE $31
76
77 /*
78 * R4640/R4650 cp0 register names. These registers are listed
79 * here only for completeness; without MMU these CPUs are not useable
80 * by Linux. A future ELKS port might take make Linux run on them
81 * though ...
82 */
83 #define CP0_IBASE $0
84 #define CP0_IBOUND $1
85 #define CP0_DBASE $2
86 #define CP0_DBOUND $3
87 #define CP0_CALG $17
88 #define CP0_IWATCH $18
89 #define CP0_DWATCH $19
90
91 /*
92 * Coprocessor 0 Set 1 register names
93 */
94 #define CP0_S1_DERRADDR0 $26
95 #define CP0_S1_DERRADDR1 $27
96 #define CP0_S1_INTCONTROL $20
97
98 /*
99 * TX39 Series
100 */
101 #define CP0_TX39_CACHE $7
102
103 /*
104 * Coprocessor 1 (FPU) register names
105 */
106 #define CP1_REVISION $0
107 #define CP1_STATUS $31
108
109 /*
110 * FPU Status Register Values
111 */
112 /*
113 * Status Register Values
114 */
115
116 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
117 #define FPU_CSR_COND 0x00800000 /* $fcc0 */
118 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */
119 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */
120 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */
121 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */
122 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */
123 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */
124 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */
125 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */
126
127 /*
128 * X the exception cause indicator
129 * E the exception enable
130 * S the sticky/flag bit
131 */
132 #define FPU_CSR_ALL_X 0x0003f000
133 #define FPU_CSR_UNI_X 0x00020000
134 #define FPU_CSR_INV_X 0x00010000
135 #define FPU_CSR_DIV_X 0x00008000
136 #define FPU_CSR_OVF_X 0x00004000
137 #define FPU_CSR_UDF_X 0x00002000
138 #define FPU_CSR_INE_X 0x00001000
139
140 #define FPU_CSR_ALL_E 0x00000f80
141 #define FPU_CSR_INV_E 0x00000800
142 #define FPU_CSR_DIV_E 0x00000400
143 #define FPU_CSR_OVF_E 0x00000200
144 #define FPU_CSR_UDF_E 0x00000100
145 #define FPU_CSR_INE_E 0x00000080
146
147 #define FPU_CSR_ALL_S 0x0000007c
148 #define FPU_CSR_INV_S 0x00000040
149 #define FPU_CSR_DIV_S 0x00000020
150 #define FPU_CSR_OVF_S 0x00000010
151 #define FPU_CSR_UDF_S 0x00000008
152 #define FPU_CSR_INE_S 0x00000004
153
154 /* rounding mode */
155 #define FPU_CSR_RN 0x0 /* nearest */
156 #define FPU_CSR_RZ 0x1 /* towards zero */
157 #define FPU_CSR_RU 0x2 /* towards +Infinity */
158 #define FPU_CSR_RD 0x3 /* towards -Infinity */
159
160
161 /*
162 * Values for PageMask register
163 */
164 #ifdef CONFIG_CPU_VR41XX
165
166 /* Why doesn't stupidity hurt ... */
167
168 #define PM_1K 0x00000000
169 #define PM_4K 0x00001800
170 #define PM_16K 0x00007800
171 #define PM_64K 0x0001f800
172 #define PM_256K 0x0007f800
173
174 #else
175
176 #define PM_4K 0x00000000
177 #define PM_16K 0x00006000
178 #define PM_64K 0x0001e000
179 #define PM_256K 0x0007e000
180 #define PM_1M 0x001fe000
181 #define PM_4M 0x007fe000
182 #define PM_16M 0x01ffe000
183 #define PM_64M 0x07ffe000
184 #define PM_256M 0x1fffe000
185
186 #endif
187
188 /*
189 * Default page size for a given kernel configuration
190 */
191 #ifdef CONFIG_PAGE_SIZE_4KB
192 #define PM_DEFAULT_MASK PM_4K
193 #elif defined(CONFIG_PAGE_SIZE_16KB)
194 #define PM_DEFAULT_MASK PM_16K
195 #elif defined(CONFIG_PAGE_SIZE_64KB)
196 #define PM_DEFAULT_MASK PM_64K
197 #else
198 #error Bad page size configuration!
199 #endif
200
201
202 /*
203 * Values used for computation of new tlb entries
204 */
205 #define PL_4K 12
206 #define PL_16K 14
207 #define PL_64K 16
208 #define PL_256K 18
209 #define PL_1M 20
210 #define PL_4M 22
211 #define PL_16M 24
212 #define PL_64M 26
213 #define PL_256M 28
214
215 /*
216 * R4x00 interrupt enable / cause bits
217 */
218 #define IE_SW0 (_ULCAST_(1) << 8)
219 #define IE_SW1 (_ULCAST_(1) << 9)
220 #define IE_IRQ0 (_ULCAST_(1) << 10)
221 #define IE_IRQ1 (_ULCAST_(1) << 11)
222 #define IE_IRQ2 (_ULCAST_(1) << 12)
223 #define IE_IRQ3 (_ULCAST_(1) << 13)
224 #define IE_IRQ4 (_ULCAST_(1) << 14)
225 #define IE_IRQ5 (_ULCAST_(1) << 15)
226
227 /*
228 * R4x00 interrupt cause bits
229 */
230 #define C_SW0 (_ULCAST_(1) << 8)
231 #define C_SW1 (_ULCAST_(1) << 9)
232 #define C_IRQ0 (_ULCAST_(1) << 10)
233 #define C_IRQ1 (_ULCAST_(1) << 11)
234 #define C_IRQ2 (_ULCAST_(1) << 12)
235 #define C_IRQ3 (_ULCAST_(1) << 13)
236 #define C_IRQ4 (_ULCAST_(1) << 14)
237 #define C_IRQ5 (_ULCAST_(1) << 15)
238
239 /*
240 * Bitfields in the R4xx0 cp0 status register
241 */
242 #define ST0_IE 0x00000001
243 #define ST0_EXL 0x00000002
244 #define ST0_ERL 0x00000004
245 #define ST0_KSU 0x00000018
246 # define KSU_USER 0x00000010
247 # define KSU_SUPERVISOR 0x00000008
248 # define KSU_KERNEL 0x00000000
249 #define ST0_UX 0x00000020
250 #define ST0_SX 0x00000040
251 #define ST0_KX 0x00000080
252 #define ST0_DE 0x00010000
253 #define ST0_CE 0x00020000
254
255 /*
256 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
257 * cacheops in userspace. This bit exists only on RM7000 and RM9000
258 * processors.
259 */
260 #define ST0_CO 0x08000000
261
262 /*
263 * Bitfields in the R[23]000 cp0 status register.
264 */
265 #define ST0_IEC 0x00000001
266 #define ST0_KUC 0x00000002
267 #define ST0_IEP 0x00000004
268 #define ST0_KUP 0x00000008
269 #define ST0_IEO 0x00000010
270 #define ST0_KUO 0x00000020
271 /* bits 6 & 7 are reserved on R[23]000 */
272 #define ST0_ISC 0x00010000
273 #define ST0_SWC 0x00020000
274 #define ST0_CM 0x00080000
275
276 /*
277 * Bits specific to the R4640/R4650
278 */
279 #define ST0_UM (_ULCAST_(1) << 4)
280 #define ST0_IL (_ULCAST_(1) << 23)
281 #define ST0_DL (_ULCAST_(1) << 24)
282
283 /*
284 * Enable the MIPS DSP ASE
285 */
286 #define ST0_MX 0x01000000
287
288 /*
289 * Bitfields in the TX39 family CP0 Configuration Register 3
290 */
291 #define TX39_CONF_ICS_SHIFT 19
292 #define TX39_CONF_ICS_MASK 0x00380000
293 #define TX39_CONF_ICS_1KB 0x00000000
294 #define TX39_CONF_ICS_2KB 0x00080000
295 #define TX39_CONF_ICS_4KB 0x00100000
296 #define TX39_CONF_ICS_8KB 0x00180000
297 #define TX39_CONF_ICS_16KB 0x00200000
298
299 #define TX39_CONF_DCS_SHIFT 16
300 #define TX39_CONF_DCS_MASK 0x00070000
301 #define TX39_CONF_DCS_1KB 0x00000000
302 #define TX39_CONF_DCS_2KB 0x00010000
303 #define TX39_CONF_DCS_4KB 0x00020000
304 #define TX39_CONF_DCS_8KB 0x00030000
305 #define TX39_CONF_DCS_16KB 0x00040000
306
307 #define TX39_CONF_CWFON 0x00004000
308 #define TX39_CONF_WBON 0x00002000
309 #define TX39_CONF_RF_SHIFT 10
310 #define TX39_CONF_RF_MASK 0x00000c00
311 #define TX39_CONF_DOZE 0x00000200
312 #define TX39_CONF_HALT 0x00000100
313 #define TX39_CONF_LOCK 0x00000080
314 #define TX39_CONF_ICE 0x00000020
315 #define TX39_CONF_DCE 0x00000010
316 #define TX39_CONF_IRSIZE_SHIFT 2
317 #define TX39_CONF_IRSIZE_MASK 0x0000000c
318 #define TX39_CONF_DRSIZE_SHIFT 0
319 #define TX39_CONF_DRSIZE_MASK 0x00000003
320
321 /*
322 * Status register bits available in all MIPS CPUs.
323 */
324 #define ST0_IM 0x0000ff00
325 #define STATUSB_IP0 8
326 #define STATUSF_IP0 (_ULCAST_(1) << 8)
327 #define STATUSB_IP1 9
328 #define STATUSF_IP1 (_ULCAST_(1) << 9)
329 #define STATUSB_IP2 10
330 #define STATUSF_IP2 (_ULCAST_(1) << 10)
331 #define STATUSB_IP3 11
332 #define STATUSF_IP3 (_ULCAST_(1) << 11)
333 #define STATUSB_IP4 12
334 #define STATUSF_IP4 (_ULCAST_(1) << 12)
335 #define STATUSB_IP5 13
336 #define STATUSF_IP5 (_ULCAST_(1) << 13)
337 #define STATUSB_IP6 14
338 #define STATUSF_IP6 (_ULCAST_(1) << 14)
339 #define STATUSB_IP7 15
340 #define STATUSF_IP7 (_ULCAST_(1) << 15)
341 #define STATUSB_IP8 0
342 #define STATUSF_IP8 (_ULCAST_(1) << 0)
343 #define STATUSB_IP9 1
344 #define STATUSF_IP9 (_ULCAST_(1) << 1)
345 #define STATUSB_IP10 2
346 #define STATUSF_IP10 (_ULCAST_(1) << 2)
347 #define STATUSB_IP11 3
348 #define STATUSF_IP11 (_ULCAST_(1) << 3)
349 #define STATUSB_IP12 4
350 #define STATUSF_IP12 (_ULCAST_(1) << 4)
351 #define STATUSB_IP13 5
352 #define STATUSF_IP13 (_ULCAST_(1) << 5)
353 #define STATUSB_IP14 6
354 #define STATUSF_IP14 (_ULCAST_(1) << 6)
355 #define STATUSB_IP15 7
356 #define STATUSF_IP15 (_ULCAST_(1) << 7)
357 #define ST0_CH 0x00040000
358 #define ST0_SR 0x00100000
359 #define ST0_TS 0x00200000
360 #define ST0_BEV 0x00400000
361 #define ST0_RE 0x02000000
362 #define ST0_FR 0x04000000
363 #define ST0_CU 0xf0000000
364 #define ST0_CU0 0x10000000
365 #define ST0_CU1 0x20000000
366 #define ST0_CU2 0x40000000
367 #define ST0_CU3 0x80000000
368 #define ST0_XX 0x80000000 /* MIPS IV naming */
369
370 /*
371 * Bitfields and bit numbers in the coprocessor 0 cause register.
372 *
373 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
374 */
375 #define CAUSEB_EXCCODE 2
376 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
377 #define CAUSEB_IP 8
378 #define CAUSEF_IP (_ULCAST_(255) << 8)
379 #define CAUSEB_IP0 8
380 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
381 #define CAUSEB_IP1 9
382 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
383 #define CAUSEB_IP2 10
384 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
385 #define CAUSEB_IP3 11
386 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
387 #define CAUSEB_IP4 12
388 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
389 #define CAUSEB_IP5 13
390 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
391 #define CAUSEB_IP6 14
392 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
393 #define CAUSEB_IP7 15
394 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
395 #define CAUSEB_IV 23
396 #define CAUSEF_IV (_ULCAST_(1) << 23)
397 #define CAUSEB_CE 28
398 #define CAUSEF_CE (_ULCAST_(3) << 28)
399 #define CAUSEB_BD 31
400 #define CAUSEF_BD (_ULCAST_(1) << 31)
401
402 /*
403 * Bits in the coprocessor 0 config register.
404 */
405 /* Generic bits. */
406 #define CONF_CM_CACHABLE_NO_WA 0
407 #define CONF_CM_CACHABLE_WA 1
408 #define CONF_CM_UNCACHED 2
409 #define CONF_CM_CACHABLE_NONCOHERENT 3
410 #define CONF_CM_CACHABLE_CE 4
411 #define CONF_CM_CACHABLE_COW 5
412 #define CONF_CM_CACHABLE_CUW 6
413 #define CONF_CM_CACHABLE_ACCELERATED 7
414 #define CONF_CM_CMASK 7
415 #define CONF_BE (_ULCAST_(1) << 15)
416
417 /* Bits common to various processors. */
418 #define CONF_CU (_ULCAST_(1) << 3)
419 #define CONF_DB (_ULCAST_(1) << 4)
420 #define CONF_IB (_ULCAST_(1) << 5)
421 #define CONF_DC (_ULCAST_(7) << 6)
422 #define CONF_IC (_ULCAST_(7) << 9)
423 #define CONF_EB (_ULCAST_(1) << 13)
424 #define CONF_EM (_ULCAST_(1) << 14)
425 #define CONF_SM (_ULCAST_(1) << 16)
426 #define CONF_SC (_ULCAST_(1) << 17)
427 #define CONF_EW (_ULCAST_(3) << 18)
428 #define CONF_EP (_ULCAST_(15)<< 24)
429 #define CONF_EC (_ULCAST_(7) << 28)
430 #define CONF_CM (_ULCAST_(1) << 31)
431
432 /* Bits specific to the R4xx0. */
433 #define R4K_CONF_SW (_ULCAST_(1) << 20)
434 #define R4K_CONF_SS (_ULCAST_(1) << 21)
435 #define R4K_CONF_SB (_ULCAST_(3) << 22)
436
437 /* Bits specific to the R5000. */
438 #define R5K_CONF_SE (_ULCAST_(1) << 12)
439 #define R5K_CONF_SS (_ULCAST_(3) << 20)
440
441 /* Bits specific to the RM7000. */
442 #define R7K_CONF_SE (_ULCAST_(1) << 3)
443
444 /* Bits specific to the R10000. */
445 #define R10K_CONF_DN (_ULCAST_(3) << 3)
446 #define R10K_CONF_CT (_ULCAST_(1) << 5)
447 #define R10K_CONF_PE (_ULCAST_(1) << 6)
448 #define R10K_CONF_PM (_ULCAST_(3) << 7)
449 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
450 #define R10K_CONF_SB (_ULCAST_(1) << 13)
451 #define R10K_CONF_SK (_ULCAST_(1) << 14)
452 #define R10K_CONF_SS (_ULCAST_(7) << 16)
453 #define R10K_CONF_SC (_ULCAST_(7) << 19)
454 #define R10K_CONF_DC (_ULCAST_(7) << 26)
455 #define R10K_CONF_IC (_ULCAST_(7) << 29)
456
457 /* Bits specific to the VR41xx. */
458 #define VR41_CONF_CS (_ULCAST_(1) << 12)
459 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
460 #define VR41_CONF_AD (_ULCAST_(1) << 23)
461
462 /* Bits specific to the R30xx. */
463 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
464 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
465 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
466 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
467 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
468 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
469 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
470 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
471 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
472
473 /* Bits specific to the TX49. */
474 #define TX49_CONF_DC (_ULCAST_(1) << 16)
475 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
476 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
477 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
478
479 /* Bits specific to the MIPS32/64 PRA. */
480 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
481 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
482 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
483 #define MIPS_CONF_M (_ULCAST_(1) << 31)
484
485 /*
486 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
487 */
488 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
489 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
490 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
491 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
492 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
493 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
494 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
495 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
496 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
497 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
498 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
499 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
500 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
501 #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
502
503 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
504 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
505 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
506 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
507 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
508 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
509 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
510 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
511
512 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
513 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
514 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
515 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
516 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
517 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
518 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
519
520 /*
521 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
522 */
523 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
524 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
525 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
526 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
527 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
528 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
529 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
530
531 /*
532 * R10000 performance counter definitions.
533 *
534 * FIXME: The R10000 performance counter opens a nice way to implement CPU
535 * time accounting with a precission of one cycle. I don't have
536 * R10000 silicon but just a manual, so ...
537 */
538
539 /*
540 * Events counted by counter #0
541 */
542 #define CE0_CYCLES 0
543 #define CE0_INSN_ISSUED 1
544 #define CE0_LPSC_ISSUED 2
545 #define CE0_S_ISSUED 3
546 #define CE0_SC_ISSUED 4
547 #define CE0_SC_FAILED 5
548 #define CE0_BRANCH_DECODED 6
549 #define CE0_QW_WB_SECONDARY 7
550 #define CE0_CORRECTED_ECC_ERRORS 8
551 #define CE0_ICACHE_MISSES 9
552 #define CE0_SCACHE_I_MISSES 10
553 #define CE0_SCACHE_I_WAY_MISSPREDICTED 11
554 #define CE0_EXT_INTERVENTIONS_REQ 12
555 #define CE0_EXT_INVALIDATE_REQ 13
556 #define CE0_VIRTUAL_COHERENCY_COND 14
557 #define CE0_INSN_GRADUATED 15
558
559 /*
560 * Events counted by counter #1
561 */
562 #define CE1_CYCLES 0
563 #define CE1_INSN_GRADUATED 1
564 #define CE1_LPSC_GRADUATED 2
565 #define CE1_S_GRADUATED 3
566 #define CE1_SC_GRADUATED 4
567 #define CE1_FP_INSN_GRADUATED 5
568 #define CE1_QW_WB_PRIMARY 6
569 #define CE1_TLB_REFILL 7
570 #define CE1_BRANCH_MISSPREDICTED 8
571 #define CE1_DCACHE_MISS 9
572 #define CE1_SCACHE_D_MISSES 10
573 #define CE1_SCACHE_D_WAY_MISSPREDICTED 11
574 #define CE1_EXT_INTERVENTION_HITS 12
575 #define CE1_EXT_INVALIDATE_REQ 13
576 #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
577 #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
578
579 /*
580 * These flags define in which privilege mode the counters count events
581 */
582 #define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
583 #define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
584 #define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
585 #define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
586
587 #ifndef __ASSEMBLY__
588
589 /*
590 * Functions to access the R10000 performance counters. These are basically
591 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
592 * performance counter number encoded into bits 1 ... 5 of the instruction.
593 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
594 * disassembler these will look like an access to sel 0 or 1.
595 */
596 #define read_r10k_perf_cntr(counter) \
597 ({ \
598 unsigned int __res; \
599 __asm__ __volatile__( \
600 "mfpc\t%0, %1" \
601 : "=r" (__res) \
602 : "i" (counter)); \
603 \
604 __res; \
605 })
606
607 #define write_r10k_perf_cntr(counter,val) \
608 do { \
609 __asm__ __volatile__( \
610 "mtpc\t%0, %1" \
611 : \
612 : "r" (val), "i" (counter)); \
613 } while (0)
614
615 #define read_r10k_perf_event(counter) \
616 ({ \
617 unsigned int __res; \
618 __asm__ __volatile__( \
619 "mfps\t%0, %1" \
620 : "=r" (__res) \
621 : "i" (counter)); \
622 \
623 __res; \
624 })
625
626 #define write_r10k_perf_cntl(counter,val) \
627 do { \
628 __asm__ __volatile__( \
629 "mtps\t%0, %1" \
630 : \
631 : "r" (val), "i" (counter)); \
632 } while (0)
633
634
635 /*
636 * Macros to access the system control coprocessor
637 */
638
639 #define __read_32bit_c0_register(source, sel) \
640 ({ int __res; \
641 if (sel == 0) \
642 __asm__ __volatile__( \
643 "mfc0\t%0, " #source "\n\t" \
644 : "=r" (__res)); \
645 else \
646 __asm__ __volatile__( \
647 ".set\tmips32\n\t" \
648 "mfc0\t%0, " #source ", " #sel "\n\t" \
649 ".set\tmips0\n\t" \
650 : "=r" (__res)); \
651 __res; \
652 })
653
654 #define __read_64bit_c0_register(source, sel) \
655 ({ unsigned long long __res; \
656 if (sizeof(unsigned long) == 4) \
657 __res = __read_64bit_c0_split(source, sel); \
658 else if (sel == 0) \
659 __asm__ __volatile__( \
660 ".set\tmips3\n\t" \
661 "dmfc0\t%0, " #source "\n\t" \
662 ".set\tmips0" \
663 : "=r" (__res)); \
664 else \
665 __asm__ __volatile__( \
666 ".set\tmips64\n\t" \
667 "dmfc0\t%0, " #source ", " #sel "\n\t" \
668 ".set\tmips0" \
669 : "=r" (__res)); \
670 __res; \
671 })
672
673 #define __write_32bit_c0_register(register, sel, value) \
674 do { \
675 if (sel == 0) \
676 __asm__ __volatile__( \
677 "mtc0\t%z0, " #register "\n\t" \
678 : : "Jr" ((unsigned int)value)); \
679 else \
680 __asm__ __volatile__( \
681 ".set\tmips32\n\t" \
682 "mtc0\t%z0, " #register ", " #sel "\n\t" \
683 ".set\tmips0" \
684 : : "Jr" ((unsigned int)value)); \
685 } while (0)
686
687 #define __write_64bit_c0_register(register, sel, value) \
688 do { \
689 if (sizeof(unsigned long) == 4) \
690 __write_64bit_c0_split(register, sel, value); \
691 else if (sel == 0) \
692 __asm__ __volatile__( \
693 ".set\tmips3\n\t" \
694 "dmtc0\t%z0, " #register "\n\t" \
695 ".set\tmips0" \
696 : : "Jr" (value)); \
697 else \
698 __asm__ __volatile__( \
699 ".set\tmips64\n\t" \
700 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
701 ".set\tmips0" \
702 : : "Jr" (value)); \
703 } while (0)
704
705 #define __read_ulong_c0_register(reg, sel) \
706 ((sizeof(unsigned long) == 4) ? \
707 (unsigned long) __read_32bit_c0_register(reg, sel) : \
708 (unsigned long) __read_64bit_c0_register(reg, sel))
709
710 #define __write_ulong_c0_register(reg, sel, val) \
711 do { \
712 if (sizeof(unsigned long) == 4) \
713 __write_32bit_c0_register(reg, sel, val); \
714 else \
715 __write_64bit_c0_register(reg, sel, val); \
716 } while (0)
717
718 /*
719 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
720 */
721 #define __read_32bit_c0_ctrl_register(source) \
722 ({ int __res; \
723 __asm__ __volatile__( \
724 "cfc0\t%0, " #source "\n\t" \
725 : "=r" (__res)); \
726 __res; \
727 })
728
729 #define __write_32bit_c0_ctrl_register(register, value) \
730 do { \
731 __asm__ __volatile__( \
732 "ctc0\t%z0, " #register "\n\t" \
733 : : "Jr" ((unsigned int)value)); \
734 } while (0)
735
736 /*
737 * These versions are only needed for systems with more than 38 bits of
738 * physical address space running the 32-bit kernel. That's none atm :-)
739 */
740 #define __read_64bit_c0_split(source, sel) \
741 ({ \
742 unsigned long long val; \
743 unsigned long flags; \
744 \
745 local_irq_save(flags); \
746 if (sel == 0) \
747 __asm__ __volatile__( \
748 ".set\tmips64\n\t" \
749 "dmfc0\t%M0, " #source "\n\t" \
750 "dsll\t%L0, %M0, 32\n\t" \
751 "dsrl\t%M0, %M0, 32\n\t" \
752 "dsrl\t%L0, %L0, 32\n\t" \
753 ".set\tmips0" \
754 : "=r" (val)); \
755 else \
756 __asm__ __volatile__( \
757 ".set\tmips64\n\t" \
758 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
759 "dsll\t%L0, %M0, 32\n\t" \
760 "dsrl\t%M0, %M0, 32\n\t" \
761 "dsrl\t%L0, %L0, 32\n\t" \
762 ".set\tmips0" \
763 : "=r" (val)); \
764 local_irq_restore(flags); \
765 \
766 val; \
767 })
768
769 #define __write_64bit_c0_split(source, sel, val) \
770 do { \
771 unsigned long flags; \
772 \
773 local_irq_save(flags); \
774 if (sel == 0) \
775 __asm__ __volatile__( \
776 ".set\tmips64\n\t" \
777 "dsll\t%L0, %L0, 32\n\t" \
778 "dsrl\t%L0, %L0, 32\n\t" \
779 "dsll\t%M0, %M0, 32\n\t" \
780 "or\t%L0, %L0, %M0\n\t" \
781 "dmtc0\t%L0, " #source "\n\t" \
782 ".set\tmips0" \
783 : : "r" (val)); \
784 else \
785 __asm__ __volatile__( \
786 ".set\tmips64\n\t" \
787 "dsll\t%L0, %L0, 32\n\t" \
788 "dsrl\t%L0, %L0, 32\n\t" \
789 "dsll\t%M0, %M0, 32\n\t" \
790 "or\t%L0, %L0, %M0\n\t" \
791 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
792 ".set\tmips0" \
793 : : "r" (val)); \
794 local_irq_restore(flags); \
795 } while (0)
796
797 #define read_c0_index() __read_32bit_c0_register($0, 0)
798 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
799
800 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
801 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
802
803 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
804 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
805
806 #define read_c0_conf() __read_32bit_c0_register($3, 0)
807 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
808
809 #define read_c0_context() __read_ulong_c0_register($4, 0)
810 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
811
812 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
813 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
814
815 #define read_c0_wired() __read_32bit_c0_register($6, 0)
816 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
817
818 #define read_c0_info() __read_32bit_c0_register($7, 0)
819
820 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
821 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
822
823 #define read_c0_count() __read_32bit_c0_register($9, 0)
824 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
825
826 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
827 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
828
829 #define read_c0_compare() __read_32bit_c0_register($11, 0)
830 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
831
832 #define read_c0_status() __read_32bit_c0_register($12, 0)
833 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
834
835 #define read_c0_cause() __read_32bit_c0_register($13, 0)
836 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
837
838 #define read_c0_epc() __read_ulong_c0_register($14, 0)
839 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
840
841 #define read_c0_prid() __read_32bit_c0_register($15, 0)
842
843 #define read_c0_config() __read_32bit_c0_register($16, 0)
844 #define read_c0_config1() __read_32bit_c0_register($16, 1)
845 #define read_c0_config2() __read_32bit_c0_register($16, 2)
846 #define read_c0_config3() __read_32bit_c0_register($16, 3)
847 #define read_c0_config4() __read_32bit_c0_register($16, 4)
848 #define read_c0_config5() __read_32bit_c0_register($16, 5)
849 #define read_c0_config6() __read_32bit_c0_register($16, 6)
850 #define read_c0_config7() __read_32bit_c0_register($16, 7)
851 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
852 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
853 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
854 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
855 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
856 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
857 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
858 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
859
860 /*
861 * The WatchLo register. There may be upto 8 of them.
862 */
863 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
864 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
865 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
866 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
867 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
868 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
869 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
870 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
871 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
872 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
873 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
874 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
875 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
876 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
877 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
878 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
879
880 /*
881 * The WatchHi register. There may be upto 8 of them.
882 */
883 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
884 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
885 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
886 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
887 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
888 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
889 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
890 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
891
892 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
893 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
894 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
895 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
896 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
897 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
898 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
899 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
900
901 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
902 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
903
904 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
905 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
906
907 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
908 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
909
910 /* RM9000 PerfControl performance counter control register */
911 #define read_c0_perfcontrol() __read_32bit_c0_register($22, 0)
912 #define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
913
914 #define read_c0_diag() __read_32bit_c0_register($22, 0)
915 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
916
917 #define read_c0_diag1() __read_32bit_c0_register($22, 1)
918 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
919
920 #define read_c0_diag2() __read_32bit_c0_register($22, 2)
921 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
922
923 #define read_c0_diag3() __read_32bit_c0_register($22, 3)
924 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
925
926 #define read_c0_diag4() __read_32bit_c0_register($22, 4)
927 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
928
929 #define read_c0_diag5() __read_32bit_c0_register($22, 5)
930 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
931
932 #define read_c0_debug() __read_32bit_c0_register($23, 0)
933 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
934
935 #define read_c0_depc() __read_ulong_c0_register($24, 0)
936 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
937
938 /*
939 * MIPS32 / MIPS64 performance counters
940 */
941 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
942 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
943 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
944 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
945 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
946 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
947 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
948 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
949 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
950 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
951 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
952 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
953 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
954 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
955 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
956 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
957
958 /* RM9000 PerfCount performance counter register */
959 #define read_c0_perfcount() __read_64bit_c0_register($25, 0)
960 #define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
961
962 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
963 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
964
965 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
966 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
967
968 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
969
970 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
971 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
972
973 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
974 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
975
976 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
977 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
978
979 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
980 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
981
982 /*
983 * Macros to access the floating point coprocessor control registers
984 */
985 #define read_32bit_cp1_register(source) \
986 ({ int __res; \
987 __asm__ __volatile__( \
988 ".set\tpush\n\t" \
989 ".set\treorder\n\t" \
990 "cfc1\t%0,"STR(source)"\n\t" \
991 ".set\tpop" \
992 : "=r" (__res)); \
993 __res;})
994
995 #define rddsp(mask) \
996 ({ \
997 unsigned int __res; \
998 \
999 __asm__ __volatile__( \
1000 " .set push \n" \
1001 " .set noat \n" \
1002 " # rddsp $1, %x1 \n" \
1003 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1004 " move %0, $1 \n" \
1005 " .set pop \n" \
1006 : "=r" (__res) \
1007 : "i" (mask)); \
1008 __res; \
1009 })
1010
1011 #define wrdsp(val, mask) \
1012 do { \
1013 unsigned int __res; \
1014 \
1015 __asm__ __volatile__( \
1016 " .set push \n" \
1017 " .set noat \n" \
1018 " move $1, %0 \n" \
1019 " # wrdsp $1, %x1 \n" \
1020 " .word 0x7c2004f8 | (%x1 << 15) \n" \
1021 " .set pop \n" \
1022 : \
1023 : "r" (val), "i" (mask)); \
1024 __res; \
1025 } while (0)
1026
1027 #if 0 /* Need DSP ASE capable assembler ... */
1028 #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
1029 #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
1030 #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
1031 #define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
1032
1033 #define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
1034 #define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
1035 #define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
1036 #define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
1037
1038 #define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
1039 #define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
1040 #define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
1041 #define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
1042
1043 #define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
1044 #define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
1045 #define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
1046 #define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
1047
1048 #else
1049
1050 #define mfhi0() \
1051 ({ \
1052 unsigned long __treg; \
1053 \
1054 __asm__ __volatile__( \
1055 " .set push \n" \
1056 " .set noat \n" \
1057 " # mfhi %0, $ac0 \n" \
1058 " .word 0x00000810 \n" \
1059 " move %0, $1 \n" \
1060 " .set pop \n" \
1061 : "=r" (__treg)); \
1062 __treg; \
1063 })
1064
1065 #define mfhi1() \
1066 ({ \
1067 unsigned long __treg; \
1068 \
1069 __asm__ __volatile__( \
1070 " .set push \n" \
1071 " .set noat \n" \
1072 " # mfhi %0, $ac1 \n" \
1073 " .word 0x00200810 \n" \
1074 " move %0, $1 \n" \
1075 " .set pop \n" \
1076 : "=r" (__treg)); \
1077 __treg; \
1078 })
1079
1080 #define mfhi2() \
1081 ({ \
1082 unsigned long __treg; \
1083 \
1084 __asm__ __volatile__( \
1085 " .set push \n" \
1086 " .set noat \n" \
1087 " # mfhi %0, $ac2 \n" \
1088 " .word 0x00400810 \n" \
1089 " move %0, $1 \n" \
1090 " .set pop \n" \
1091 : "=r" (__treg)); \
1092 __treg; \
1093 })
1094
1095 #define mfhi3() \
1096 ({ \
1097 unsigned long __treg; \
1098 \
1099 __asm__ __volatile__( \
1100 " .set push \n" \
1101 " .set noat \n" \
1102 " # mfhi %0, $ac3 \n" \
1103 " .word 0x00600810 \n" \
1104 " move %0, $1 \n" \
1105 " .set pop \n" \
1106 : "=r" (__treg)); \
1107 __treg; \
1108 })
1109
1110 #define mflo0() \
1111 ({ \
1112 unsigned long __treg; \
1113 \
1114 __asm__ __volatile__( \
1115 " .set push \n" \
1116 " .set noat \n" \
1117 " # mflo %0, $ac0 \n" \
1118 " .word 0x00000812 \n" \
1119 " move %0, $1 \n" \
1120 " .set pop \n" \
1121 : "=r" (__treg)); \
1122 __treg; \
1123 })
1124
1125 #define mflo1() \
1126 ({ \
1127 unsigned long __treg; \
1128 \
1129 __asm__ __volatile__( \
1130 " .set push \n" \
1131 " .set noat \n" \
1132 " # mflo %0, $ac1 \n" \
1133 " .word 0x00200812 \n" \
1134 " move %0, $1 \n" \
1135 " .set pop \n" \
1136 : "=r" (__treg)); \
1137 __treg; \
1138 })
1139
1140 #define mflo2() \
1141 ({ \
1142 unsigned long __treg; \
1143 \
1144 __asm__ __volatile__( \
1145 " .set push \n" \
1146 " .set noat \n" \
1147 " # mflo %0, $ac2 \n" \
1148 " .word 0x00400812 \n" \
1149 " move %0, $1 \n" \
1150 " .set pop \n" \
1151 : "=r" (__treg)); \
1152 __treg; \
1153 })
1154
1155 #define mflo3() \
1156 ({ \
1157 unsigned long __treg; \
1158 \
1159 __asm__ __volatile__( \
1160 " .set push \n" \
1161 " .set noat \n" \
1162 " # mflo %0, $ac3 \n" \
1163 " .word 0x00600812 \n" \
1164 " move %0, $1 \n" \
1165 " .set pop \n" \
1166 : "=r" (__treg)); \
1167 __treg; \
1168 })
1169
1170 #define mthi0(x) \
1171 do { \
1172 __asm__ __volatile__( \
1173 " .set push \n" \
1174 " .set noat \n" \
1175 " move $1, %0 \n" \
1176 " # mthi $1, $ac0 \n" \
1177 " .word 0x00200011 \n" \
1178 " .set pop \n" \
1179 : \
1180 : "r" (x)); \
1181 } while (0)
1182
1183 #define mthi1(x) \
1184 do { \
1185 __asm__ __volatile__( \
1186 " .set push \n" \
1187 " .set noat \n" \
1188 " move $1, %0 \n" \
1189 " # mthi $1, $ac1 \n" \
1190 " .word 0x00200811 \n" \
1191 " .set pop \n" \
1192 : \
1193 : "r" (x)); \
1194 } while (0)
1195
1196 #define mthi2(x) \
1197 do { \
1198 __asm__ __volatile__( \
1199 " .set push \n" \
1200 " .set noat \n" \
1201 " move $1, %0 \n" \
1202 " # mthi $1, $ac2 \n" \
1203 " .word 0x00201011 \n" \
1204 " .set pop \n" \
1205 : \
1206 : "r" (x)); \
1207 } while (0)
1208
1209 #define mthi3(x) \
1210 do { \
1211 __asm__ __volatile__( \
1212 " .set push \n" \
1213 " .set noat \n" \
1214 " move $1, %0 \n" \
1215 " # mthi $1, $ac3 \n" \
1216 " .word 0x00201811 \n" \
1217 " .set pop \n" \
1218 : \
1219 : "r" (x)); \
1220 } while (0)
1221
1222 #define mtlo0(x) \
1223 do { \
1224 __asm__ __volatile__( \
1225 " .set push \n" \
1226 " .set noat \n" \
1227 " move $1, %0 \n" \
1228 " # mtlo $1, $ac0 \n" \
1229 " .word 0x00200013 \n" \
1230 " .set pop \n" \
1231 : \
1232 : "r" (x)); \
1233 } while (0)
1234
1235 #define mtlo1(x) \
1236 do { \
1237 __asm__ __volatile__( \
1238 " .set push \n" \
1239 " .set noat \n" \
1240 " move $1, %0 \n" \
1241 " # mtlo $1, $ac1 \n" \
1242 " .word 0x00200813 \n" \
1243 " .set pop \n" \
1244 : \
1245 : "r" (x)); \
1246 } while (0)
1247
1248 #define mtlo2(x) \
1249 do { \
1250 __asm__ __volatile__( \
1251 " .set push \n" \
1252 " .set noat \n" \
1253 " move $1, %0 \n" \
1254 " # mtlo $1, $ac2 \n" \
1255 " .word 0x00201013 \n" \
1256 " .set pop \n" \
1257 : \
1258 : "r" (x)); \
1259 } while (0)
1260
1261 #define mtlo3(x) \
1262 do { \
1263 __asm__ __volatile__( \
1264 " .set push \n" \
1265 " .set noat \n" \
1266 " move $1, %0 \n" \
1267 " # mtlo $1, $ac3 \n" \
1268 " .word 0x00201813 \n" \
1269 " .set pop \n" \
1270 : \
1271 : "r" (x)); \
1272 } while (0)
1273
1274 #endif
1275
1276 /*
1277 * TLB operations.
1278 *
1279 * It is responsibility of the caller to take care of any TLB hazards.
1280 */
1281 static inline void tlb_probe(void)
1282 {
1283 __asm__ __volatile__(
1284 ".set noreorder\n\t"
1285 "tlbp\n\t"
1286 ".set reorder");
1287 }
1288
1289 static inline void tlb_read(void)
1290 {
1291 __asm__ __volatile__(
1292 ".set noreorder\n\t"
1293 "tlbr\n\t"
1294 ".set reorder");
1295 }
1296
1297 static inline void tlb_write_indexed(void)
1298 {
1299 __asm__ __volatile__(
1300 ".set noreorder\n\t"
1301 "tlbwi\n\t"
1302 ".set reorder");
1303 }
1304
1305 static inline void tlb_write_random(void)
1306 {
1307 __asm__ __volatile__(
1308 ".set noreorder\n\t"
1309 "tlbwr\n\t"
1310 ".set reorder");
1311 }
1312
1313 /*
1314 * Manipulate bits in a c0 register.
1315 */
1316 #define __BUILD_SET_C0(name) \
1317 static inline unsigned int \
1318 set_c0_##name(unsigned int set) \
1319 { \
1320 unsigned int res; \
1321 \
1322 res = read_c0_##name(); \
1323 res |= set; \
1324 write_c0_##name(res); \
1325 \
1326 return res; \
1327 } \
1328 \
1329 static inline unsigned int \
1330 clear_c0_##name(unsigned int clear) \
1331 { \
1332 unsigned int res; \
1333 \
1334 res = read_c0_##name(); \
1335 res &= ~clear; \
1336 write_c0_##name(res); \
1337 \
1338 return res; \
1339 } \
1340 \
1341 static inline unsigned int \
1342 change_c0_##name(unsigned int change, unsigned int new) \
1343 { \
1344 unsigned int res; \
1345 \
1346 res = read_c0_##name(); \
1347 res &= ~change; \
1348 res |= (new & change); \
1349 write_c0_##name(res); \
1350 \
1351 return res; \
1352 }
1353
1354 __BUILD_SET_C0(status)
1355 __BUILD_SET_C0(cause)
1356 __BUILD_SET_C0(config)
1357 __BUILD_SET_C0(intcontrol)
1358
1359 #endif /* !__ASSEMBLY__ */
1360
1361 #endif /* _ASM_MIPSREGS_H */
Linux kernel - Deliverables
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