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Fix types for firmware arguments. Don't define unneeded messages.
[deliverable/linux.git] / include / asm-mips / system.h
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
7 * Copyright (C) 1996 by Paul M. Antoine
8 * Copyright (C) 1999 Silicon Graphics
9 * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc.
11 */
12 #ifndef _ASM_SYSTEM_H
13 #define _ASM_SYSTEM_H
14
15 #include <linux/config.h>
16 #include <linux/types.h>
17
18 #include <asm/addrspace.h>
19 #include <asm/cpu-features.h>
20 #include <asm/dsp.h>
21 #include <asm/ptrace.h>
22 #include <asm/war.h>
23 #include <asm/interrupt.h>
24
25 /*
26 * read_barrier_depends - Flush all pending reads that subsequents reads
27 * depend on.
28 *
29 * No data-dependent reads from memory-like regions are ever reordered
30 * over this barrier. All reads preceding this primitive are guaranteed
31 * to access memory (but not necessarily other CPUs' caches) before any
32 * reads following this primitive that depend on the data return by
33 * any of the preceding reads. This primitive is much lighter weight than
34 * rmb() on most CPUs, and is never heavier weight than is
35 * rmb().
36 *
37 * These ordering constraints are respected by both the local CPU
38 * and the compiler.
39 *
40 * Ordering is not guaranteed by anything other than these primitives,
41 * not even by data dependencies. See the documentation for
42 * memory_barrier() for examples and URLs to more information.
43 *
44 * For example, the following code would force ordering (the initial
45 * value of "a" is zero, "b" is one, and "p" is "&a"):
46 *
47 * <programlisting>
48 * CPU 0 CPU 1
49 *
50 * b = 2;
51 * memory_barrier();
52 * p = &b; q = p;
53 * read_barrier_depends();
54 * d = *q;
55 * </programlisting>
56 *
57 * because the read of "*q" depends on the read of "p" and these
58 * two reads are separated by a read_barrier_depends(). However,
59 * the following code, with the same initial values for "a" and "b":
60 *
61 * <programlisting>
62 * CPU 0 CPU 1
63 *
64 * a = 2;
65 * memory_barrier();
66 * b = 3; y = b;
67 * read_barrier_depends();
68 * x = a;
69 * </programlisting>
70 *
71 * does not enforce ordering, since there is no data dependency between
72 * the read of "a" and the read of "b". Therefore, on some CPUs, such
73 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
74 * in cases like thiswhere there are no data dependencies.
75 */
76
77 #define read_barrier_depends() do { } while(0)
78
79 #ifdef CONFIG_CPU_HAS_SYNC
80 #define __sync() \
81 __asm__ __volatile__( \
82 ".set push\n\t" \
83 ".set noreorder\n\t" \
84 ".set mips2\n\t" \
85 "sync\n\t" \
86 ".set pop" \
87 : /* no output */ \
88 : /* no input */ \
89 : "memory")
90 #else
91 #define __sync() do { } while(0)
92 #endif
93
94 #define __fast_iob() \
95 __asm__ __volatile__( \
96 ".set push\n\t" \
97 ".set noreorder\n\t" \
98 "lw $0,%0\n\t" \
99 "nop\n\t" \
100 ".set pop" \
101 : /* no output */ \
102 : "m" (*(int *)CKSEG1) \
103 : "memory")
104
105 #define fast_wmb() __sync()
106 #define fast_rmb() __sync()
107 #define fast_mb() __sync()
108 #define fast_iob() \
109 do { \
110 __sync(); \
111 __fast_iob(); \
112 } while (0)
113
114 #ifdef CONFIG_CPU_HAS_WB
115
116 #include <asm/wbflush.h>
117
118 #define wmb() fast_wmb()
119 #define rmb() fast_rmb()
120 #define mb() wbflush()
121 #define iob() wbflush()
122
123 #else /* !CONFIG_CPU_HAS_WB */
124
125 #define wmb() fast_wmb()
126 #define rmb() fast_rmb()
127 #define mb() fast_mb()
128 #define iob() fast_iob()
129
130 #endif /* !CONFIG_CPU_HAS_WB */
131
132 #ifdef CONFIG_SMP
133 #define smp_mb() mb()
134 #define smp_rmb() rmb()
135 #define smp_wmb() wmb()
136 #define smp_read_barrier_depends() read_barrier_depends()
137 #else
138 #define smp_mb() barrier()
139 #define smp_rmb() barrier()
140 #define smp_wmb() barrier()
141 #define smp_read_barrier_depends() do { } while(0)
142 #endif
143
144 #define set_mb(var, value) \
145 do { var = value; mb(); } while (0)
146
147 #define set_wmb(var, value) \
148 do { var = value; wmb(); } while (0)
149
150 /*
151 * switch_to(n) should switch tasks to task nr n, first
152 * checking that n isn't the current task, in which case it does nothing.
153 */
154 extern asmlinkage void *resume(void *last, void *next, void *next_ti);
155
156 struct task_struct;
157
158 #define switch_to(prev,next,last) \
159 do { \
160 if (cpu_has_dsp) \
161 __save_dsp(prev); \
162 (last) = resume(prev, next, next->thread_info); \
163 if (cpu_has_dsp) \
164 __restore_dsp(current); \
165 } while(0)
166
167 #define ROT_IN_PIECES \
168 " .set noreorder \n" \
169 " .set reorder \n"
170
171 static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
172 {
173 __u32 retval;
174
175 if (cpu_has_llsc && R10000_LLSC_WAR) {
176 unsigned long dummy;
177
178 __asm__ __volatile__(
179 " .set mips2 \n"
180 "1: ll %0, %3 # xchg_u32 \n"
181 " move %2, %z4 \n"
182 " sc %2, %1 \n"
183 " beqzl %2, 1b \n"
184 ROT_IN_PIECES
185 #ifdef CONFIG_SMP
186 " sync \n"
187 #endif
188 " .set mips0 \n"
189 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
190 : "R" (*m), "Jr" (val)
191 : "memory");
192 } else if (cpu_has_llsc) {
193 unsigned long dummy;
194
195 __asm__ __volatile__(
196 " .set mips2 \n"
197 "1: ll %0, %3 # xchg_u32 \n"
198 " move %2, %z4 \n"
199 " sc %2, %1 \n"
200 " beqz %2, 1b \n"
201 #ifdef CONFIG_SMP
202 " sync \n"
203 #endif
204 " .set mips0 \n"
205 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
206 : "R" (*m), "Jr" (val)
207 : "memory");
208 } else {
209 unsigned long flags;
210
211 local_irq_save(flags);
212 retval = *m;
213 *m = val;
214 local_irq_restore(flags); /* implies memory barrier */
215 }
216
217 return retval;
218 }
219
220 #ifdef CONFIG_64BIT
221 static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
222 {
223 __u64 retval;
224
225 if (cpu_has_llsc && R10000_LLSC_WAR) {
226 unsigned long dummy;
227
228 __asm__ __volatile__(
229 " .set mips3 \n"
230 "1: lld %0, %3 # xchg_u64 \n"
231 " move %2, %z4 \n"
232 " scd %2, %1 \n"
233 " beqzl %2, 1b \n"
234 ROT_IN_PIECES
235 #ifdef CONFIG_SMP
236 " sync \n"
237 #endif
238 " .set mips0 \n"
239 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
240 : "R" (*m), "Jr" (val)
241 : "memory");
242 } else if (cpu_has_llsc) {
243 unsigned long dummy;
244
245 __asm__ __volatile__(
246 " .set mips3 \n"
247 "1: lld %0, %3 # xchg_u64 \n"
248 " move %2, %z4 \n"
249 " scd %2, %1 \n"
250 " beqz %2, 1b \n"
251 #ifdef CONFIG_SMP
252 " sync \n"
253 #endif
254 " .set mips0 \n"
255 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
256 : "R" (*m), "Jr" (val)
257 : "memory");
258 } else {
259 unsigned long flags;
260
261 local_irq_save(flags);
262 retval = *m;
263 *m = val;
264 local_irq_restore(flags); /* implies memory barrier */
265 }
266
267 return retval;
268 }
269 #else
270 extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
271 #define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
272 #endif
273
274 /* This function doesn't exist, so you'll get a linker error
275 if something tries to do an invalid xchg(). */
276 extern void __xchg_called_with_bad_pointer(void);
277
278 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
279 {
280 switch (size) {
281 case 4:
282 return __xchg_u32(ptr, x);
283 case 8:
284 return __xchg_u64(ptr, x);
285 }
286 __xchg_called_with_bad_pointer();
287 return x;
288 }
289
290 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
291 #define tas(ptr) (xchg((ptr),1))
292
293 #define __HAVE_ARCH_CMPXCHG 1
294
295 static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
296 unsigned long new)
297 {
298 __u32 retval;
299
300 if (cpu_has_llsc && R10000_LLSC_WAR) {
301 __asm__ __volatile__(
302 " .set push \n"
303 " .set noat \n"
304 " .set mips2 \n"
305 "1: ll %0, %2 # __cmpxchg_u32 \n"
306 " bne %0, %z3, 2f \n"
307 " move $1, %z4 \n"
308 " sc $1, %1 \n"
309 " beqzl $1, 1b \n"
310 ROT_IN_PIECES
311 #ifdef CONFIG_SMP
312 " sync \n"
313 #endif
314 "2: \n"
315 " .set pop \n"
316 : "=&r" (retval), "=m" (*m)
317 : "R" (*m), "Jr" (old), "Jr" (new)
318 : "memory");
319 } else if (cpu_has_llsc) {
320 __asm__ __volatile__(
321 " .set push \n"
322 " .set noat \n"
323 " .set mips2 \n"
324 "1: ll %0, %2 # __cmpxchg_u32 \n"
325 " bne %0, %z3, 2f \n"
326 " move $1, %z4 \n"
327 " sc $1, %1 \n"
328 " beqz $1, 1b \n"
329 #ifdef CONFIG_SMP
330 " sync \n"
331 #endif
332 "2: \n"
333 " .set pop \n"
334 : "=&r" (retval), "=m" (*m)
335 : "R" (*m), "Jr" (old), "Jr" (new)
336 : "memory");
337 } else {
338 unsigned long flags;
339
340 local_irq_save(flags);
341 retval = *m;
342 if (retval == old)
343 *m = new;
344 local_irq_restore(flags); /* implies memory barrier */
345 }
346
347 return retval;
348 }
349
350 #ifdef CONFIG_64BIT
351 static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
352 unsigned long new)
353 {
354 __u64 retval;
355
356 if (cpu_has_llsc) {
357 __asm__ __volatile__(
358 " .set push \n"
359 " .set noat \n"
360 " .set mips3 \n"
361 "1: lld %0, %2 # __cmpxchg_u64 \n"
362 " bne %0, %z3, 2f \n"
363 " move $1, %z4 \n"
364 " scd $1, %1 \n"
365 " beqzl $1, 1b \n"
366 ROT_IN_PIECES
367 #ifdef CONFIG_SMP
368 " sync \n"
369 #endif
370 "2: \n"
371 " .set pop \n"
372 : "=&r" (retval), "=m" (*m)
373 : "R" (*m), "Jr" (old), "Jr" (new)
374 : "memory");
375 } else if (cpu_has_llsc) {
376 __asm__ __volatile__(
377 " .set push \n"
378 " .set noat \n"
379 " .set mips2 \n"
380 "1: lld %0, %2 # __cmpxchg_u64 \n"
381 " bne %0, %z3, 2f \n"
382 " move $1, %z4 \n"
383 " scd $1, %1 \n"
384 " beqz $1, 1b \n"
385 #ifdef CONFIG_SMP
386 " sync \n"
387 #endif
388 "2: \n"
389 " .set pop \n"
390 : "=&r" (retval), "=m" (*m)
391 : "R" (*m), "Jr" (old), "Jr" (new)
392 : "memory");
393 } else {
394 unsigned long flags;
395
396 local_irq_save(flags);
397 retval = *m;
398 if (retval == old)
399 *m = new;
400 local_irq_restore(flags); /* implies memory barrier */
401 }
402
403 return retval;
404 }
405 #else
406 extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels(
407 volatile int * m, unsigned long old, unsigned long new);
408 #define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels
409 #endif
410
411 /* This function doesn't exist, so you'll get a linker error
412 if something tries to do an invalid cmpxchg(). */
413 extern void __cmpxchg_called_with_bad_pointer(void);
414
415 static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
416 unsigned long new, int size)
417 {
418 switch (size) {
419 case 4:
420 return __cmpxchg_u32(ptr, old, new);
421 case 8:
422 return __cmpxchg_u64(ptr, old, new);
423 }
424 __cmpxchg_called_with_bad_pointer();
425 return old;
426 }
427
428 #define cmpxchg(ptr,old,new) ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
429
430 extern void *set_except_vector(int n, void *addr);
431 extern void per_cpu_trap_init(void);
432
433 extern NORET_TYPE void __die(const char *, struct pt_regs *, const char *file,
434 const char *func, unsigned long line) ATTRIB_NORET;
435 extern void __die_if_kernel(const char *, struct pt_regs *, const char *file,
436 const char *func, unsigned long line);
437
438 #define die(msg, regs) \
439 __die(msg, regs, __FILE__ ":", __FUNCTION__, __LINE__)
440 #define die_if_kernel(msg, regs) \
441 __die_if_kernel(msg, regs, __FILE__ ":", __FUNCTION__, __LINE__)
442
443 extern int stop_a_enabled;
444
445 /*
446 * See include/asm-ia64/system.h; prevents deadlock on SMP
447 * systems.
448 */
449 #define __ARCH_WANT_UNLOCKED_CTXSW
450
451 #define arch_align_stack(x) (x)
452
453 #endif /* _ASM_SYSTEM_H */
Linux kernel - Deliverables
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