include/asm-parisc/pci.h

   1 #ifndef __ASM_PARISC_PCI_H
   2 #define __ASM_PARISC_PCI_H
   3
   4 #include <linux/config.h>
   5 #include <asm/scatterlist.h>
   6
   7
   8
   9 /*
  10 ** HP PCI platforms generally support multiple bus adapters.
  11 **    (workstations 1-~4, servers 2-~32)
  12 **
  13 ** Newer platforms number the busses across PCI bus adapters *sparsely*.
  14 ** E.g. 0, 8, 16, ...
  15 **
  16 ** Under a PCI bus, most HP platforms support PPBs up to two or three
  17 ** levels deep. See "Bit3" product line.
  18 */
  19 #define PCI_MAX_BUSSES  256
  20
  21 /*
  22 ** pci_hba_data (aka H2P_OBJECT in HP/UX)
  23 **
  24 ** This is the "common" or "base" data structure which HBA drivers
  25 ** (eg Dino or LBA) are required to place at the top of their own
  26 ** platform_data structure.  I've heard this called "C inheritance" too.
  27 **
  28 ** Data needed by pcibios layer belongs here.
  29 */
  30 struct pci_hba_data {
  31         void __iomem   *base_addr;      /* aka Host Physical Address */
  32         const struct parisc_device *dev; /* device from PA bus walk */
  33         struct pci_bus *hba_bus;        /* primary PCI bus below HBA */
  34         int             hba_num;        /* I/O port space access "key" */
  35         struct resource bus_num;        /* PCI bus numbers */
  36         struct resource io_space;       /* PIOP */
  37         struct resource lmmio_space;    /* bus addresses < 4Gb */
  38         struct resource elmmio_space;   /* additional bus addresses < 4Gb */
  39         struct resource gmmio_space;    /* bus addresses > 4Gb */
  40
  41         /* NOTE: Dino code assumes it can use *all* of the lmmio_space,
  42          * elmmio_space and gmmio_space as a contiguous array of
  43          * resources.  This #define represents the array size */
  44         #define DINO_MAX_LMMIO_RESOURCES        3
  45
  46         unsigned long   lmmio_space_offset;  /* CPU view - PCI view */
  47         void *          iommu;          /* IOMMU this device is under */
  48         /* REVISIT - spinlock to protect resources? */
  49
  50         #define HBA_NAME_SIZE 16
  51         char io_name[HBA_NAME_SIZE];
  52         char lmmio_name[HBA_NAME_SIZE];
  53         char elmmio_name[HBA_NAME_SIZE];
  54         char gmmio_name[HBA_NAME_SIZE];
  55 };
  56
  57 #define HBA_DATA(d)             ((struct pci_hba_data *) (d))
  58
  59 /*
  60 ** We support 2^16 I/O ports per HBA.  These are set up in the form
  61 ** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port
  62 ** space address.
  63 */
  64 #define HBA_PORT_SPACE_BITS     16
  65
  66 #define HBA_PORT_BASE(h)        ((h) << HBA_PORT_SPACE_BITS)
  67 #define HBA_PORT_SPACE_SIZE     (1UL << HBA_PORT_SPACE_BITS)
  68
  69 #define PCI_PORT_HBA(a)         ((a) >> HBA_PORT_SPACE_BITS)
  70 #define PCI_PORT_ADDR(a)        ((a) & (HBA_PORT_SPACE_SIZE - 1))
  71
  72 #ifdef CONFIG_64BIT
  73 #define PCI_F_EXTEND            0xffffffff00000000UL
  74 #define PCI_IS_LMMIO(hba,a)     pci_is_lmmio(hba,a)
  75
  76 /* We need to know if an address is LMMMIO or GMMIO.
  77  * LMMIO requires mangling and GMMIO we must use as-is.
  78  */
  79 static __inline__  int pci_is_lmmio(struct pci_hba_data *hba, unsigned long a)
  80 {
  81         return(((a) & PCI_F_EXTEND) == PCI_F_EXTEND);
  82 }
  83
  84 /*
  85 ** Convert between PCI (IO_VIEW) addresses and processor (PA_VIEW) addresses.
  86 ** See pcibios.c for more conversions used by Generic PCI code.
  87 **
  88 ** Platform characteristics/firmware guarantee that
  89 **      (1) PA_VIEW - IO_VIEW = lmmio_offset for both LMMIO and ELMMIO
  90 **      (2) PA_VIEW == IO_VIEW for GMMIO
  91 */
  92 #define PCI_BUS_ADDR(hba,a)     (PCI_IS_LMMIO(hba,a)    \
  93                 ?  ((a) - hba->lmmio_space_offset)      /* mangle LMMIO */ \
  94                 : (a))                                  /* GMMIO */
  95 #define PCI_HOST_ADDR(hba,a)    (((a) & PCI_F_EXTEND) == 0 \
  96                 ? (a) + hba->lmmio_space_offset \
  97                 : (a))
  98
  99 #else   /* !CONFIG_64BIT */
 100
 101 #define PCI_BUS_ADDR(hba,a)     (a)
 102 #define PCI_HOST_ADDR(hba,a)    (a)
 103 #define PCI_F_EXTEND            0UL
 104 #define PCI_IS_LMMIO(hba,a)     (1)     /* 32-bit doesn't support GMMIO */
 105
 106 #endif /* !CONFIG_64BIT */
 107
 108 /*
 109 ** KLUGE: linux/pci.h include asm/pci.h BEFORE declaring struct pci_bus
 110 ** (This eliminates some of the warnings).
 111 */
 112 struct pci_bus;
 113 struct pci_dev;
 114
 115 /*
 116  * If the PCI device's view of memory is the same as the CPU's view of memory,
 117  * PCI_DMA_BUS_IS_PHYS is true.  The networking and block device layers use
 118  * this boolean for bounce buffer decisions.
 119  */
 120 #ifdef CONFIG_PA20
 121 /* All PA-2.0 machines have an IOMMU. */
 122 #define PCI_DMA_BUS_IS_PHYS     0
 123 #define parisc_has_iommu()      do { } while (0)
 124 #else
 125
 126 #if defined(CONFIG_IOMMU_CCIO) || defined(CONFIG_IOMMU_SBA)
 127 extern int parisc_bus_is_phys;  /* in arch/parisc/kernel/setup.c */
 128 #define PCI_DMA_BUS_IS_PHYS     parisc_bus_is_phys
 129 #define parisc_has_iommu()      do { parisc_bus_is_phys = 0; } while (0)
 130 #else
 131 #define PCI_DMA_BUS_IS_PHYS     1
 132 #define parisc_has_iommu()      do { } while (0)
 133 #endif
 134
 135 #endif  /* !CONFIG_PA20 */
 136
 137
 138 /*
 139 ** Most PCI devices (eg Tulip, NCR720) also export the same registers
 140 ** to both MMIO and I/O port space.  Due to poor performance of I/O Port
 141 ** access under HP PCI bus adapters, strongly reccomend use of MMIO
 142 ** address space.
 143 **
 144 ** While I'm at it more PA programming notes:
 145 **
 146 ** 1) MMIO stores (writes) are posted operations. This means the processor
 147 **    gets an "ACK" before the write actually gets to the device. A read
 148 **    to the same device (or typically the bus adapter above it) will
 149 **    force in-flight write transaction(s) out to the targeted device
 150 **    before the read can complete.
 151 **
 152 ** 2) The Programmed I/O (PIO) data may not always be strongly ordered with
 153 **    respect to DMA on all platforms. Ie PIO data can reach the processor
 154 **    before in-flight DMA reaches memory. Since most SMP PA platforms
 155 **    are I/O coherent, it generally doesn't matter...but sometimes
 156 **    it does.
 157 **
 158 ** I've helped device driver writers debug both types of problems.
 159 */
 160 struct pci_port_ops {
 161           u8 (*inb)  (struct pci_hba_data *hba, u16 port);
 162          u16 (*inw)  (struct pci_hba_data *hba, u16 port);
 163          u32 (*inl)  (struct pci_hba_data *hba, u16 port);
 164         void (*outb) (struct pci_hba_data *hba, u16 port,  u8 data);
 165         void (*outw) (struct pci_hba_data *hba, u16 port, u16 data);
 166         void (*outl) (struct pci_hba_data *hba, u16 port, u32 data);
 167 };
 168
 169
 170 struct pci_bios_ops {
 171         void (*init)(void);
 172         void (*fixup_bus)(struct pci_bus *bus);
 173 };
 174
 175 /* pci_unmap_{single,page} is not a nop, thus... */
 176 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
 177         dma_addr_t ADDR_NAME;
 178 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         \
 179         __u32 LEN_NAME;
 180 #define pci_unmap_addr(PTR, ADDR_NAME)                  \
 181         ((PTR)->ADDR_NAME)
 182 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)         \
 183         (((PTR)->ADDR_NAME) = (VAL))
 184 #define pci_unmap_len(PTR, LEN_NAME)                    \
 185         ((PTR)->LEN_NAME)
 186 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
 187         (((PTR)->LEN_NAME) = (VAL))
 188
 189 /*
 190 ** Stuff declared in arch/parisc/kernel/pci.c
 191 */
 192 extern struct pci_port_ops *pci_port;
 193 extern struct pci_bios_ops *pci_bios;
 194 extern int pci_post_reset_delay;        /* delay after de-asserting #RESET */
 195 extern int pci_hba_count;
 196 extern struct pci_hba_data *parisc_pci_hba[];
 197
 198 #ifdef CONFIG_PCI
 199 extern void pcibios_register_hba(struct pci_hba_data *);
 200 extern void pcibios_set_master(struct pci_dev *);
 201 #else
 202 extern inline void pcibios_register_hba(struct pci_hba_data *x)
 203 {
 204 }
 205 #endif
 206
 207 /*
 208  * pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus()
 209  *   0 == check if bridge is numbered before re-numbering.
 210  *   1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges.
 211  *
 212  *   We *should* set this to zero for "legacy" platforms and one
 213  *   for PAT platforms.
 214  *
 215  *   But legacy platforms also need to renumber the busses below a Host
 216  *   Bus controller.  Adding a 4-port Tulip card on the first PCI root
 217  *   bus of a C200 resulted in the secondary bus being numbered as 1.
 218  *   The second PCI host bus controller's root bus had already been
 219  *   assigned bus number 1 by firmware and sysfs complained.
 220  *
 221  *   Firmware isn't doing anything wrong here since each controller
 222  *   is its own PCI domain.  It's simpler and easier for us to renumber
 223  *   the busses rather than treat each Dino as a separate PCI domain.
 224  *   Eventually, we may want to introduce PCI domains for Superdome or
 225  *   rp7420/8420 boxes and then revisit this issue.
 226  */
 227 #define pcibios_assign_all_busses()     (1)
 228 #define pcibios_scan_all_fns(a, b)      (0)
 229
 230 #define PCIBIOS_MIN_IO          0x10
 231 #define PCIBIOS_MIN_MEM         0x1000 /* NBPG - but pci/setup-res.c dies */
 232
 233 /* Don't support DAC yet. */
 234 #define pci_dac_dma_supported(pci_dev, mask)   (0)
 235
 236 /* export the pci_ DMA API in terms of the dma_ one */
 237 #include <asm-generic/pci-dma-compat.h>
 238
 239 #ifdef CONFIG_PCI
 240 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 241                                         enum pci_dma_burst_strategy *strat,
 242                                         unsigned long *strategy_parameter)
 243 {
 244         unsigned long cacheline_size;
 245         u8 byte;
 246
 247         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
 248         if (byte == 0)
 249                 cacheline_size = 1024;
 250         else
 251                 cacheline_size = (int) byte * 4;
 252
 253         *strat = PCI_DMA_BURST_MULTIPLE;
 254         *strategy_parameter = cacheline_size;
 255 }
 256 #endif
 257
 258 extern void
 259 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
 260                          struct resource *res);
 261
 262 extern void
 263 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
 264                         struct pci_bus_region *region);
 265
 266 static inline struct resource *
 267 pcibios_select_root(struct pci_dev *pdev, struct resource *res)
 268 {
 269         struct resource *root = NULL;
 270
 271         if (res->flags & IORESOURCE_IO)
 272                 root = &ioport_resource;
 273         if (res->flags & IORESOURCE_MEM)
 274                 root = &iomem_resource;
 275
 276         return root;
 277 }
 278
 279 static inline void pcibios_add_platform_entries(struct pci_dev *dev)
 280 {
 281 }
 282
 283 #endif /* __ASM_PARISC_PCI_H */