include/asm-powerpc/mmu-hash32.h

   1 #ifndef _ASM_POWERPC_MMU_HASH32_H_
   2 #define _ASM_POWERPC_MMU_HASH32_H_
   3 /*
   4  * 32-bit hash table MMU support
   5  */
   6
   7 /*
   8  * BATs
   9  */
  10
  11 /* Block size masks */
  12 #define BL_128K 0x000
  13 #define BL_256K 0x001
  14 #define BL_512K 0x003
  15 #define BL_1M   0x007
  16 #define BL_2M   0x00F
  17 #define BL_4M   0x01F
  18 #define BL_8M   0x03F
  19 #define BL_16M  0x07F
  20 #define BL_32M  0x0FF
  21 #define BL_64M  0x1FF
  22 #define BL_128M 0x3FF
  23 #define BL_256M 0x7FF
  24
  25 /* BAT Access Protection */
  26 #define BPP_XX  0x00            /* No access */
  27 #define BPP_RX  0x01            /* Read only */
  28 #define BPP_RW  0x02            /* Read/write */
  29
  30 #ifndef __ASSEMBLY__
  31 /* Contort a phys_addr_t into the right format/bits for a BAT */
  32 #ifdef CONFIG_PHYS_64BIT
  33 #define BAT_PHYS_ADDR(x) ((u32)((x & 0x00000000fffe0000ULL) | \
  34                                 ((x & 0x0000000e00000000ULL) >> 24) | \
  35                                 ((x & 0x0000000100000000ULL) >> 30)))
  36 #else
  37 #define BAT_PHYS_ADDR(x) (x)
  38 #endif
  39
  40 struct ppc_bat {
  41         struct {
  42                 unsigned long bepi:15;  /* Effective page index (virtual address) */
  43                 unsigned long :4;       /* Unused */
  44                 unsigned long bl:11;    /* Block size mask */
  45                 unsigned long vs:1;     /* Supervisor valid */
  46                 unsigned long vp:1;     /* User valid */
  47         } batu;                 /* Upper register */
  48         struct {
  49                 unsigned long brpn:15;  /* Real page index (physical address) */
  50                 unsigned long :10;      /* Unused */
  51                 unsigned long w:1;      /* Write-thru cache */
  52                 unsigned long i:1;      /* Cache inhibit */
  53                 unsigned long m:1;      /* Memory coherence */
  54                 unsigned long g:1;      /* Guarded (MBZ in IBAT) */
  55                 unsigned long :1;       /* Unused */
  56                 unsigned long pp:2;     /* Page access protections */
  57         } batl;                 /* Lower register */
  58 };
  59 #endif /* !__ASSEMBLY__ */
  60
  61 /*
  62  * Hash table
  63  */
  64
  65 /* Values for PP (assumes Ks=0, Kp=1) */
  66 #define PP_RWXX 0       /* Supervisor read/write, User none */
  67 #define PP_RWRX 1       /* Supervisor read/write, User read */
  68 #define PP_RWRW 2       /* Supervisor read/write, User read/write */
  69 #define PP_RXRX 3       /* Supervisor read,       User read */
  70
  71 #ifndef __ASSEMBLY__
  72
  73 /* Hardware Page Table Entry */
  74 struct hash_pte {
  75         unsigned long v:1;      /* Entry is valid */
  76         unsigned long vsid:24;  /* Virtual segment identifier */
  77         unsigned long h:1;      /* Hash algorithm indicator */
  78         unsigned long api:6;    /* Abbreviated page index */
  79         unsigned long rpn:20;   /* Real (physical) page number */
  80         unsigned long    :3;    /* Unused */
  81         unsigned long r:1;      /* Referenced */
  82         unsigned long c:1;      /* Changed */
  83         unsigned long w:1;      /* Write-thru cache mode */
  84         unsigned long i:1;      /* Cache inhibited */
  85         unsigned long m:1;      /* Memory coherence */
  86         unsigned long g:1;      /* Guarded */
  87         unsigned long  :1;      /* Unused */
  88         unsigned long pp:2;     /* Page protection */
  89 };
  90
  91 typedef struct {
  92         unsigned long id;
  93         unsigned long vdso_base;
  94 } mm_context_t;
  95
  96 #endif /* !__ASSEMBLY__ */
  97
  98 #endif /* _ASM_POWERPC_MMU_HASH32_H_ */