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[deliverable/linux.git] / include / asm-powerpc / ppc_asm.h
1 /*
2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
3 */
4 #ifndef _ASM_POWERPC_PPC_ASM_H
5 #define _ASM_POWERPC_PPC_ASM_H
6
7 #include <linux/stringify.h>
8 #include <linux/config.h>
9 #include <asm/asm-compat.h>
10
11 #ifndef __ASSEMBLY__
12 #error __FILE__ should only be used in assembler files
13 #else
14
15 #define SZL (BITS_PER_LONG/8)
16
17 /*
18 * Macros for storing registers into and loading registers from
19 * exception frames.
20 */
21 #ifdef __powerpc64__
22 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
23 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
24 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
25 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
26 #else
27 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
28 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
29 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
30 SAVE_10GPRS(22, base)
31 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
32 REST_10GPRS(22, base)
33 #endif
34
35
36 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
37 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
38 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
39 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
40 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
41 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
42 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
43 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
44
45 #define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
46 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
47 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
48 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
49 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
50 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
51 #define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
52 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
53 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
54 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
55 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
56 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
57
58 #define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
59 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
60 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
61 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
62 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
63 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
64 #define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
65 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
66 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
67 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
68 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
69 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
70
71 #define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
72 #define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
73 #define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
74 #define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
75 #define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
76 #define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
77 #define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
78 #define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base)
79 #define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
80 #define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
81 #define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
82 #define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
83
84 /* Macros to adjust thread priority for hardware multithreading */
85 #define HMT_VERY_LOW or 31,31,31 # very low priority
86 #define HMT_LOW or 1,1,1
87 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
88 #define HMT_MEDIUM or 2,2,2
89 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
90 #define HMT_HIGH or 3,3,3
91
92 /* handle instructions that older assemblers may not know */
93 #define RFCI .long 0x4c000066 /* rfci instruction */
94 #define RFDI .long 0x4c00004e /* rfdi instruction */
95 #define RFMCI .long 0x4c00004c /* rfmci instruction */
96
97 #ifdef __KERNEL__
98 #ifdef CONFIG_PPC64
99
100 #define XGLUE(a,b) a##b
101 #define GLUE(a,b) XGLUE(a,b)
102
103 #define _GLOBAL(name) \
104 .section ".text"; \
105 .align 2 ; \
106 .globl name; \
107 .globl GLUE(.,name); \
108 .section ".opd","aw"; \
109 name: \
110 .quad GLUE(.,name); \
111 .quad .TOC.@tocbase; \
112 .quad 0; \
113 .previous; \
114 .type GLUE(.,name),@function; \
115 GLUE(.,name):
116
117 #define _KPROBE(name) \
118 .section ".kprobes.text","a"; \
119 .align 2 ; \
120 .globl name; \
121 .globl GLUE(.,name); \
122 .section ".opd","aw"; \
123 name: \
124 .quad GLUE(.,name); \
125 .quad .TOC.@tocbase; \
126 .quad 0; \
127 .previous; \
128 .type GLUE(.,name),@function; \
129 GLUE(.,name):
130
131 #define _STATIC(name) \
132 .section ".text"; \
133 .align 2 ; \
134 .section ".opd","aw"; \
135 name: \
136 .quad GLUE(.,name); \
137 .quad .TOC.@tocbase; \
138 .quad 0; \
139 .previous; \
140 .type GLUE(.,name),@function; \
141 GLUE(.,name):
142
143 #else /* 32-bit */
144
145 #define _GLOBAL(n) \
146 .text; \
147 .stabs __stringify(n:F-1),N_FUN,0,0,n;\
148 .globl n; \
149 n:
150
151 #define _KPROBE(n) \
152 .section ".kprobes.text","a"; \
153 .globl n; \
154 n:
155
156 #endif
157
158 /*
159 * LOAD_REG_IMMEDIATE(rn, expr)
160 * Loads the value of the constant expression 'expr' into register 'rn'
161 * using immediate instructions only. Use this when it's important not
162 * to reference other data (i.e. on ppc64 when the TOC pointer is not
163 * valid).
164 *
165 * LOAD_REG_ADDR(rn, name)
166 * Loads the address of label 'name' into register 'rn'. Use this when
167 * you don't particularly need immediate instructions only, but you need
168 * the whole address in one register (e.g. it's a structure address and
169 * you want to access various offsets within it). On ppc32 this is
170 * identical to LOAD_REG_IMMEDIATE.
171 *
172 * LOAD_REG_ADDRBASE(rn, name)
173 * ADDROFF(name)
174 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
175 * register 'rn'. ADDROFF(name) returns the remainder of the address as
176 * a constant expression. ADDROFF(name) is a signed expression < 16 bits
177 * in size, so is suitable for use directly as an offset in load and store
178 * instructions. Use this when loading/storing a single word or less as:
179 * LOAD_REG_ADDRBASE(rX, name)
180 * ld rY,ADDROFF(name)(rX)
181 */
182 #ifdef __powerpc64__
183 #define LOAD_REG_IMMEDIATE(reg,expr) \
184 lis (reg),(expr)@highest; \
185 ori (reg),(reg),(expr)@higher; \
186 rldicr (reg),(reg),32,31; \
187 oris (reg),(reg),(expr)@h; \
188 ori (reg),(reg),(expr)@l;
189
190 #define LOAD_REG_ADDR(reg,name) \
191 ld (reg),name@got(r2)
192
193 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
194 #define ADDROFF(name) 0
195
196 /* offsets for stack frame layout */
197 #define LRSAVE 16
198
199 #else /* 32-bit */
200
201 #define LOAD_REG_IMMEDIATE(reg,expr) \
202 lis (reg),(expr)@ha; \
203 addi (reg),(reg),(expr)@l;
204
205 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name)
206
207 #define LOAD_REG_ADDRBASE(reg, name) lis (reg),name@ha
208 #define ADDROFF(name) name@l
209
210 /* offsets for stack frame layout */
211 #define LRSAVE 4
212
213 #endif
214
215 /* various errata or part fixups */
216 #ifdef CONFIG_PPC601_SYNC_FIX
217 #define SYNC \
218 BEGIN_FTR_SECTION \
219 sync; \
220 isync; \
221 END_FTR_SECTION_IFSET(CPU_FTR_601)
222 #define SYNC_601 \
223 BEGIN_FTR_SECTION \
224 sync; \
225 END_FTR_SECTION_IFSET(CPU_FTR_601)
226 #define ISYNC_601 \
227 BEGIN_FTR_SECTION \
228 isync; \
229 END_FTR_SECTION_IFSET(CPU_FTR_601)
230 #else
231 #define SYNC
232 #define SYNC_601
233 #define ISYNC_601
234 #endif
235
236
237 #ifndef CONFIG_SMP
238 #define TLBSYNC
239 #else /* CONFIG_SMP */
240 /* tlbsync is not implemented on 601 */
241 #define TLBSYNC \
242 BEGIN_FTR_SECTION \
243 tlbsync; \
244 sync; \
245 END_FTR_SECTION_IFCLR(CPU_FTR_601)
246 #endif
247
248
249 /*
250 * This instruction is not implemented on the PPC 603 or 601; however, on
251 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
252 * All of these instructions exist in the 8xx, they have magical powers,
253 * and they must be used.
254 */
255
256 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
257 #define tlbia \
258 li r4,1024; \
259 mtctr r4; \
260 lis r4,KERNELBASE@h; \
261 0: tlbie r4; \
262 addi r4,r4,0x1000; \
263 bdnz 0b
264 #endif
265
266
267 #ifdef CONFIG_IBM440EP_ERR42
268 #define PPC440EP_ERR42 isync
269 #else
270 #define PPC440EP_ERR42
271 #endif
272
273
274 #if defined(CONFIG_BOOKE)
275 #define toreal(rd)
276 #define fromreal(rd)
277
278 #define tophys(rd,rs) \
279 addis rd,rs,0
280
281 #define tovirt(rd,rs) \
282 addis rd,rs,0
283
284 #elif defined(CONFIG_PPC64)
285 #define toreal(rd) /* we can access c000... in real mode */
286 #define fromreal(rd)
287
288 #define tophys(rd,rs) \
289 clrldi rd,rs,2
290
291 #define tovirt(rd,rs) \
292 rotldi rd,rs,16; \
293 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
294 rotldi rd,rd,48
295 #else
296 /*
297 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
298 * physical base address of RAM at compile time.
299 */
300 #define toreal(rd) tophys(rd,rd)
301 #define fromreal(rd) tovirt(rd,rd)
302
303 #define tophys(rd,rs) \
304 0: addis rd,rs,-KERNELBASE@h; \
305 .section ".vtop_fixup","aw"; \
306 .align 1; \
307 .long 0b; \
308 .previous
309
310 #define tovirt(rd,rs) \
311 0: addis rd,rs,KERNELBASE@h; \
312 .section ".ptov_fixup","aw"; \
313 .align 1; \
314 .long 0b; \
315 .previous
316 #endif
317
318 #ifdef CONFIG_PPC64
319 #define RFI rfid
320 #define MTMSRD(r) mtmsrd r
321
322 #else
323 #define FIX_SRR1(ra, rb)
324 #ifndef CONFIG_40x
325 #define RFI rfi
326 #else
327 #define RFI rfi; b . /* Prevent prefetch past rfi */
328 #endif
329 #define MTMSRD(r) mtmsr r
330 #define CLR_TOP32(r)
331 #endif
332
333 #endif /* __KERNEL__ */
334
335 /* The boring bits... */
336
337 /* Condition Register Bit Fields */
338
339 #define cr0 0
340 #define cr1 1
341 #define cr2 2
342 #define cr3 3
343 #define cr4 4
344 #define cr5 5
345 #define cr6 6
346 #define cr7 7
347
348
349 /* General Purpose Registers (GPRs) */
350
351 #define r0 0
352 #define r1 1
353 #define r2 2
354 #define r3 3
355 #define r4 4
356 #define r5 5
357 #define r6 6
358 #define r7 7
359 #define r8 8
360 #define r9 9
361 #define r10 10
362 #define r11 11
363 #define r12 12
364 #define r13 13
365 #define r14 14
366 #define r15 15
367 #define r16 16
368 #define r17 17
369 #define r18 18
370 #define r19 19
371 #define r20 20
372 #define r21 21
373 #define r22 22
374 #define r23 23
375 #define r24 24
376 #define r25 25
377 #define r26 26
378 #define r27 27
379 #define r28 28
380 #define r29 29
381 #define r30 30
382 #define r31 31
383
384
385 /* Floating Point Registers (FPRs) */
386
387 #define fr0 0
388 #define fr1 1
389 #define fr2 2
390 #define fr3 3
391 #define fr4 4
392 #define fr5 5
393 #define fr6 6
394 #define fr7 7
395 #define fr8 8
396 #define fr9 9
397 #define fr10 10
398 #define fr11 11
399 #define fr12 12
400 #define fr13 13
401 #define fr14 14
402 #define fr15 15
403 #define fr16 16
404 #define fr17 17
405 #define fr18 18
406 #define fr19 19
407 #define fr20 20
408 #define fr21 21
409 #define fr22 22
410 #define fr23 23
411 #define fr24 24
412 #define fr25 25
413 #define fr26 26
414 #define fr27 27
415 #define fr28 28
416 #define fr29 29
417 #define fr30 30
418 #define fr31 31
419
420 /* AltiVec Registers (VPRs) */
421
422 #define vr0 0
423 #define vr1 1
424 #define vr2 2
425 #define vr3 3
426 #define vr4 4
427 #define vr5 5
428 #define vr6 6
429 #define vr7 7
430 #define vr8 8
431 #define vr9 9
432 #define vr10 10
433 #define vr11 11
434 #define vr12 12
435 #define vr13 13
436 #define vr14 14
437 #define vr15 15
438 #define vr16 16
439 #define vr17 17
440 #define vr18 18
441 #define vr19 19
442 #define vr20 20
443 #define vr21 21
444 #define vr22 22
445 #define vr23 23
446 #define vr24 24
447 #define vr25 25
448 #define vr26 26
449 #define vr27 27
450 #define vr28 28
451 #define vr29 29
452 #define vr30 30
453 #define vr31 31
454
455 /* SPE Registers (EVPRs) */
456
457 #define evr0 0
458 #define evr1 1
459 #define evr2 2
460 #define evr3 3
461 #define evr4 4
462 #define evr5 5
463 #define evr6 6
464 #define evr7 7
465 #define evr8 8
466 #define evr9 9
467 #define evr10 10
468 #define evr11 11
469 #define evr12 12
470 #define evr13 13
471 #define evr14 14
472 #define evr15 15
473 #define evr16 16
474 #define evr17 17
475 #define evr18 18
476 #define evr19 19
477 #define evr20 20
478 #define evr21 21
479 #define evr22 22
480 #define evr23 23
481 #define evr24 24
482 #define evr25 25
483 #define evr26 26
484 #define evr27 27
485 #define evr28 28
486 #define evr29 29
487 #define evr30 30
488 #define evr31 31
489
490 /* some stab codes */
491 #define N_FUN 36
492 #define N_RSYM 64
493 #define N_SLINE 68
494 #define N_SO 100
495
496 #endif /* __ASSEMBLY__ */
497
498 #endif /* _ASM_POWERPC_PPC_ASM_H */
Linux kernel - Deliverables
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