5 * Definitions for talking to the SMU chip in newer G5 PowerMacs
8 #include <linux/config.h>
9 #include <linux/list.h>
14 * Most of what is below comes from looking at the Open Firmware driver,
15 * though this is still incomplete and could use better documentation here
21 * Partition info commands
23 * I do not know what those are for at this point
25 #define SMU_CMD_PARTITION_COMMAND 0x3e
31 * This is a "mux" for fan control commands, first byte is the
34 #define SMU_CMD_FAN_COMMAND 0x4a
40 * Same command number as the PMU, could it be same syntax ?
42 #define SMU_CMD_BATTERY_COMMAND 0x6f
43 #define SMU_CMD_GET_BATTERY_INFO 0x00
46 * Real time clock control
48 * This is a "mux", first data byte contains the "sub" command.
49 * The "RTC" part of the SMU controls the date, time, powerup
50 * timer, but also a PRAM
52 * Dates are in BCD format on 7 bytes:
53 * [sec] [min] [hour] [weekday] [month day] [month] [year]
54 * with month being 1 based and year minus 100
56 #define SMU_CMD_RTC_COMMAND 0x8e
57 #define SMU_CMD_RTC_SET_PWRUP_TIMER 0x00 /* i: 7 bytes date */
58 #define SMU_CMD_RTC_GET_PWRUP_TIMER 0x01 /* o: 7 bytes date */
59 #define SMU_CMD_RTC_STOP_PWRUP_TIMER 0x02
60 #define SMU_CMD_RTC_SET_PRAM_BYTE_ACC 0x20 /* i: 1 byte (address?) */
61 #define SMU_CMD_RTC_SET_PRAM_AUTOINC 0x21 /* i: 1 byte (data?) */
62 #define SMU_CMD_RTC_SET_PRAM_LO_BYTES 0x22 /* i: 10 bytes */
63 #define SMU_CMD_RTC_SET_PRAM_HI_BYTES 0x23 /* i: 10 bytes */
64 #define SMU_CMD_RTC_GET_PRAM_BYTE 0x28 /* i: 1 bytes (address?) */
65 #define SMU_CMD_RTC_GET_PRAM_LO_BYTES 0x29 /* o: 10 bytes */
66 #define SMU_CMD_RTC_GET_PRAM_HI_BYTES 0x2a /* o: 10 bytes */
67 #define SMU_CMD_RTC_SET_DATETIME 0x80 /* i: 7 bytes date */
68 #define SMU_CMD_RTC_GET_DATETIME 0x81 /* o: 7 bytes date */
73 * To issue an i2c command, first is to send a parameter block to the
74 * the SMU. This is a command of type 0x9a with 9 bytes of header
75 * eventually followed by data for a write:
77 * 0: bus number (from device-tree usually, SMU has lots of busses !)
78 * 1: transfer type/format (see below)
79 * 2: device address. For combined and combined4 type transfers, this
80 * is the "write" version of the address (bit 0x01 cleared)
81 * 3: subaddress length (0..3)
82 * 4: subaddress byte 0 (or only byte for subaddress length 1)
83 * 5: subaddress byte 1
84 * 6: subaddress byte 2
85 * 7: combined address (device address for combined mode data phase)
88 * The transfer types are the same good old Apple ones it seems,
90 * - 0x00: Simple transfer
91 * - 0x01: Subaddress transfer (addr write + data tx, no restart)
92 * - 0x02: Combined transfer (addr write + restart + data tx)
94 * This is then followed by actual data for a write.
96 * At this point, the OF driver seems to have a limitation on transfer
97 * sizes of 0xd bytes on reads and 0x5 bytes on writes. I do not know
98 * wether this is just an OF limit due to some temporary buffer size
99 * or if this is an SMU imposed limit. This driver has the same limitation
100 * for now as I use a 0x10 bytes temporary buffer as well
102 * Once that is completed, a response is expected from the SMU. This is
103 * obtained via a command of type 0x9a with a length of 1 byte containing
104 * 0 as the data byte. OF also fills the rest of the data buffer with 0xff's
105 * though I can't tell yet if this is actually necessary. Once this command
106 * is complete, at this point, all I can tell is what OF does. OF tests
107 * byte 0 of the reply:
108 * - on read, 0xfe or 0xfc : bus is busy, wait (see below) or nak ?
109 * - on read, 0x00 or 0x01 : reply is in buffer (after the byte 0)
110 * - on write, < 0 -> failure (immediate exit)
111 * - else, OF just exists (without error, weird)
113 * So on read, there is this wait-for-busy thing when getting a 0xfc or
114 * 0xfe result. OF does a loop of up to 64 retries, waiting 20ms and
115 * doing the above again until either the retries expire or the result
116 * is no longer 0xfe or 0xfc
118 * The Darwin I2C driver is less subtle though. On any non-success status
119 * from the response command, it waits 5ms and tries again up to 20 times,
120 * it doesn't differenciate between fatal errors or "busy" status.
122 * This driver provides an asynchronous paramblock based i2c command
123 * interface to be used either directly by low level code or by a higher
124 * level driver interfacing to the linux i2c layer. The current
125 * implementation of this relies on working timers & timer interrupts
126 * though, so be careful of calling context for now. This may be "fixed"
127 * in the future by adding a polling facility.
129 #define SMU_CMD_I2C_COMMAND 0x9a
131 #define SMU_I2C_TRANSFER_SIMPLE 0x00
132 #define SMU_I2C_TRANSFER_STDSUB 0x01
133 #define SMU_I2C_TRANSFER_COMBINED 0x02
136 * Power supply control
138 * The "sub" command is an ASCII string in the data, the
139 * data lenght is that of the string.
141 * The VSLEW command can be used to get or set the voltage slewing.
142 * - lenght 5 (only "VSLEW") : it returns "DONE" and 3 bytes of
143 * reply at data offset 6, 7 and 8.
144 * - lenght 8 ("VSLEWxyz") has 3 additional bytes appended, and is
145 * used to set the voltage slewing point. The SMU replies with "DONE"
146 * I yet have to figure out their exact meaning of those 3 bytes in
147 * both cases. They seem to be:
149 * y = op. point index
150 * z = processor freq. step index
151 * I haven't yet decyphered result codes
154 #define SMU_CMD_POWER_COMMAND 0xaa
155 #define SMU_CMD_POWER_RESTART "RESTART"
156 #define SMU_CMD_POWER_SHUTDOWN "SHUTDOWN"
157 #define SMU_CMD_POWER_VOLTAGE_SLEW "VSLEW"
161 * This command seem to be a grab bag of various things
163 #define SMU_CMD_MISC_df_COMMAND 0xdf
164 #define SMU_CMD_MISC_df_SET_DISPLAY_LIT 0x02 /* i: 1 byte */
165 #define SMU_CMD_MISC_df_NMI_OPTION 0x04
168 * Version info commands
170 * I haven't quite tried to figure out how these work
172 #define SMU_CMD_VERSION_COMMAND 0xea
178 * This command seem to be a grab bag of various things
180 #define SMU_CMD_MISC_ee_COMMAND 0xee
181 #define SMU_CMD_MISC_ee_GET_DATABLOCK_REC 0x02
182 #define SMU_CMD_MISC_ee_LEDS_CTRL 0x04 /* i: 00 (00,01) [00] */
183 #define SMU_CMD_MISC_ee_GET_DATA 0x05 /* i: 00 , o: ?? */
188 * - Kernel side interface -
194 * Asynchronous SMU commands
196 * Fill up this structure and submit it via smu_queue_command(),
197 * and get notified by the optional done() callback, or because
198 * status becomes != 1
206 u8 cmd
; /* command */
207 int data_len
; /* data len */
208 int reply_len
; /* reply len */
209 void *data_buf
; /* data buffer */
210 void *reply_buf
; /* reply buffer */
211 int status
; /* command status */
212 void (*done
)(struct smu_cmd
*cmd
, void *misc
);
216 struct list_head link
;
220 * Queues an SMU command, all fields have to be initialized
222 extern int smu_queue_cmd(struct smu_cmd
*cmd
);
225 * Simple command wrapper. This structure embeds a small buffer
226 * to ease sending simple SMU commands from the stack
228 struct smu_simple_cmd
235 * Queues a simple command. All fields will be initialized by that
238 extern int smu_queue_simple(struct smu_simple_cmd
*scmd
, u8 command
,
239 unsigned int data_len
,
240 void (*done
)(struct smu_cmd
*cmd
, void *misc
),
245 * Completion helper. Pass it to smu_queue_simple or as 'done'
246 * member to smu_queue_cmd, it will call complete() on the struct
247 * completion passed in the "misc" argument
249 extern void smu_done_complete(struct smu_cmd
*cmd
, void *misc
);
252 * Synchronous helpers. Will spin-wait for completion of a command
254 extern void smu_spinwait_cmd(struct smu_cmd
*cmd
);
256 static inline void smu_spinwait_simple(struct smu_simple_cmd
*scmd
)
258 smu_spinwait_cmd(&scmd
->cmd
);
262 * Poll routine to call if blocked with irqs off
264 extern void smu_poll(void);
268 * Init routine, presence check....
270 extern int smu_init(void);
271 extern int smu_present(void);
273 extern struct of_device
*smu_get_ofdev(void);
277 * Common command wrappers
279 extern void smu_shutdown(void);
280 extern void smu_restart(void);
282 extern int smu_get_rtc_time(struct rtc_time
*time
, int spinwait
);
283 extern int smu_set_rtc_time(struct rtc_time
*time
, int spinwait
);
286 * SMU command buffer absolute address, exported by pmac_setup,
287 * this is allocated very early during boot.
289 extern unsigned long smu_cmdbuf_abs
;
293 * Kenrel asynchronous i2c interface
296 /* SMU i2c header, exactly matches i2c header on wire */
299 u8 bus
; /* SMU bus ID (from device tree) */
300 u8 type
; /* i2c transfer type */
301 u8 devaddr
; /* device address (includes direction) */
302 u8 sublen
; /* subaddress length */
303 u8 subaddr
[3]; /* subaddress */
304 u8 caddr
; /* combined address, filled by SMU driver */
305 u8 datalen
; /* length of transfer */
306 u8 data
[7]; /* data */
309 #define SMU_I2C_READ_MAX 0x0d
310 #define SMU_I2C_WRITE_MAX 0x05
315 struct smu_i2c_param info
;
316 void (*done
)(struct smu_i2c_cmd
*cmd
, void *misc
);
318 int status
; /* 1 = pending, 0 = ok, <0 = fail */
326 struct list_head link
;
330 * Call this to queue an i2c command to the SMU. You must fill info,
331 * including info.data for a write, done and misc.
332 * For now, no polling interface is provided so you have to use completion
335 extern int smu_queue_i2c(struct smu_i2c_cmd
*cmd
);
338 #endif /* __KERNEL__ */
342 * - SMU "sdb" partitions informations -
347 * Partition header format
349 struct smu_sdbp_header
{
357 * 32 bits integers are usually encoded with 2x16 bits swapped,
358 * this demangles them
360 #define SMU_U32_MIX(x) ((((x) << 16) & 0xffff0000u) | (((x) >> 16) & 0xffffu))
362 /* This is the definition of the SMU sdb-partition-0x12 table (called
363 * CPU F/V/T operating points in Darwin). The definition for all those
364 * SMU tables should be moved to some separate file
366 #define SMU_SDB_FVT_ID 0x12
368 struct smu_sdbp_fvt
{
369 __u32 sysclk
; /* Base SysClk frequency in Hz for
370 * this operating point
373 __u8 maxtemp
; /* Max temp. supported by this
377 __u16 volts
[3]; /* CPU core voltage for the 3
378 * PowerTune modes, a mode with
379 * 0V = not supported.
385 * This returns the pointer to an SMU "sdb" partition data or NULL
386 * if not found. The data format is described below
388 extern struct smu_sdbp_header
*smu_get_sdb_partition(int id
,
391 #endif /* __KERNEL__ */
395 * - Userland interface -
399 * A given instance of the device can be configured for 2 different
400 * things at the moment:
402 * - sending SMU commands (default at open() time)
403 * - receiving SMU events (not yet implemented)
405 * Commands are written with write() of a command block. They can be
406 * "driver" commands (for example to switch to event reception mode)
407 * or real SMU commands. They are made of a header followed by command
410 * For SMU commands (not for driver commands), you can then read() back
411 * a reply. The reader will be blocked or not depending on how the device
412 * file is opened. poll() isn't implemented yet. The reply will consist
413 * of a header as well, followed by the reply data if any. You should
414 * always provide a buffer large enough for the maximum reply data, I
415 * recommand one page.
417 * It is illegal to send SMU commands through a file descriptor configured
418 * for events reception
421 struct smu_user_cmd_hdr
424 #define SMU_CMDTYPE_SMU 0 /* SMU command */
425 #define SMU_CMDTYPE_WANTS_EVENTS 1 /* switch fd to events mode */
427 __u8 cmd
; /* SMU command byte */
428 __u32 data_len
; /* Lenght of data following */
431 struct smu_user_reply_hdr
433 __u32 status
; /* Command status */
434 __u32 reply_len
; /* Lenght of data follwing */
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