include/asm-powerpc/system.h

   1 /*
   2  * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
   3  */
   4 #ifndef _ASM_POWERPC_SYSTEM_H
   5 #define _ASM_POWERPC_SYSTEM_H
   6
   7 #include <linux/kernel.h>
   8 #include <linux/irqflags.h>
   9
  10 #include <asm/hw_irq.h>
  11
  12 /*
  13  * Memory barrier.
  14  * The sync instruction guarantees that all memory accesses initiated
  15  * by this processor have been performed (with respect to all other
  16  * mechanisms that access memory).  The eieio instruction is a barrier
  17  * providing an ordering (separately) for (a) cacheable stores and (b)
  18  * loads and stores to non-cacheable memory (e.g. I/O devices).
  19  *
  20  * mb() prevents loads and stores being reordered across this point.
  21  * rmb() prevents loads being reordered across this point.
  22  * wmb() prevents stores being reordered across this point.
  23  * read_barrier_depends() prevents data-dependent loads being reordered
  24  *      across this point (nop on PPC).
  25  *
  26  * We have to use the sync instructions for mb(), since lwsync doesn't
  27  * order loads with respect to previous stores.  Lwsync is fine for
  28  * rmb(), though. Note that rmb() actually uses a sync on 32-bit
  29  * architectures.
  30  *
  31  * For wmb(), we use sync since wmb is used in drivers to order
  32  * stores to system memory with respect to writes to the device.
  33  * However, smp_wmb() can be a lighter-weight eieio barrier on
  34  * SMP since it is only used to order updates to system memory.
  35  */
  36 #define mb()   __asm__ __volatile__ ("sync" : : : "memory")
  37 #define rmb()  __asm__ __volatile__ ("sync" : : : "memory")
  38 #define wmb()  __asm__ __volatile__ ("sync" : : : "memory")
  39 #define read_barrier_depends()  do { } while(0)
  40
  41 #define set_mb(var, value)      do { var = value; mb(); } while (0)
  42
  43 #ifdef __KERNEL__
  44 #define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */
  45 #ifdef CONFIG_SMP
  46 #define smp_mb()        mb()
  47 #define smp_rmb()       rmb()
  48 #define smp_wmb()       eieio()
  49 #define smp_read_barrier_depends()      read_barrier_depends()
  50 #else
  51 #define smp_mb()        barrier()
  52 #define smp_rmb()       barrier()
  53 #define smp_wmb()       barrier()
  54 #define smp_read_barrier_depends()      do { } while(0)
  55 #endif /* CONFIG_SMP */
  56
  57 /*
  58  * This is a barrier which prevents following instructions from being
  59  * started until the value of the argument x is known.  For example, if
  60  * x is a variable loaded from memory, this prevents following
  61  * instructions from being executed until the load has been performed.
  62  */
  63 #define data_barrier(x) \
  64         asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
  65
  66 struct task_struct;
  67 struct pt_regs;
  68
  69 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
  70
  71 extern int (*__debugger)(struct pt_regs *regs);
  72 extern int (*__debugger_ipi)(struct pt_regs *regs);
  73 extern int (*__debugger_bpt)(struct pt_regs *regs);
  74 extern int (*__debugger_sstep)(struct pt_regs *regs);
  75 extern int (*__debugger_iabr_match)(struct pt_regs *regs);
  76 extern int (*__debugger_dabr_match)(struct pt_regs *regs);
  77 extern int (*__debugger_fault_handler)(struct pt_regs *regs);
  78
  79 #define DEBUGGER_BOILERPLATE(__NAME) \
  80 static inline int __NAME(struct pt_regs *regs) \
  81 { \
  82         if (unlikely(__ ## __NAME)) \
  83                 return __ ## __NAME(regs); \
  84         return 0; \
  85 }
  86
  87 DEBUGGER_BOILERPLATE(debugger)
  88 DEBUGGER_BOILERPLATE(debugger_ipi)
  89 DEBUGGER_BOILERPLATE(debugger_bpt)
  90 DEBUGGER_BOILERPLATE(debugger_sstep)
  91 DEBUGGER_BOILERPLATE(debugger_iabr_match)
  92 DEBUGGER_BOILERPLATE(debugger_dabr_match)
  93 DEBUGGER_BOILERPLATE(debugger_fault_handler)
  94
  95 #else
  96 static inline int debugger(struct pt_regs *regs) { return 0; }
  97 static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
  98 static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
  99 static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
 100 static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
 101 static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
 102 static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
 103 #endif
 104
 105 extern int set_dabr(unsigned long dabr);
 106 extern void print_backtrace(unsigned long *);
 107 extern void show_regs(struct pt_regs * regs);
 108 extern void flush_instruction_cache(void);
 109 extern void hard_reset_now(void);
 110 extern void poweroff_now(void);
 111
 112 #ifdef CONFIG_6xx
 113 extern long _get_L2CR(void);
 114 extern long _get_L3CR(void);
 115 extern void _set_L2CR(unsigned long);
 116 extern void _set_L3CR(unsigned long);
 117 #else
 118 #define _get_L2CR()     0L
 119 #define _get_L3CR()     0L
 120 #define _set_L2CR(val)  do { } while(0)
 121 #define _set_L3CR(val)  do { } while(0)
 122 #endif
 123
 124 extern void via_cuda_init(void);
 125 extern void read_rtc_time(void);
 126 extern void pmac_find_display(void);
 127 extern void giveup_fpu(struct task_struct *);
 128 extern void disable_kernel_fp(void);
 129 extern void enable_kernel_fp(void);
 130 extern void flush_fp_to_thread(struct task_struct *);
 131 extern void enable_kernel_altivec(void);
 132 extern void giveup_altivec(struct task_struct *);
 133 extern void load_up_altivec(struct task_struct *);
 134 extern int emulate_altivec(struct pt_regs *);
 135 extern void enable_kernel_spe(void);
 136 extern void giveup_spe(struct task_struct *);
 137 extern void load_up_spe(struct task_struct *);
 138 extern int fix_alignment(struct pt_regs *);
 139 extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
 140 extern void cvt_df(double *from, float *to, struct thread_struct *thread);
 141
 142 #ifndef CONFIG_SMP
 143 extern void discard_lazy_cpu_state(void);
 144 #else
 145 static inline void discard_lazy_cpu_state(void)
 146 {
 147 }
 148 #endif
 149
 150 #ifdef CONFIG_ALTIVEC
 151 extern void flush_altivec_to_thread(struct task_struct *);
 152 #else
 153 static inline void flush_altivec_to_thread(struct task_struct *t)
 154 {
 155 }
 156 #endif
 157
 158 #ifdef CONFIG_SPE
 159 extern void flush_spe_to_thread(struct task_struct *);
 160 #else
 161 static inline void flush_spe_to_thread(struct task_struct *t)
 162 {
 163 }
 164 #endif
 165
 166 extern int call_rtas(const char *, int, int, unsigned long *, ...);
 167 extern void cacheable_memzero(void *p, unsigned int nb);
 168 extern void *cacheable_memcpy(void *, const void *, unsigned int);
 169 extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
 170 extern void bad_page_fault(struct pt_regs *, unsigned long, int);
 171 extern int die(const char *, struct pt_regs *, long);
 172 extern void _exception(int, struct pt_regs *, int, unsigned long);
 173 extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 174
 175 #ifdef CONFIG_BOOKE_WDT
 176 extern u32 booke_wdt_enabled;
 177 extern u32 booke_wdt_period;
 178 #endif /* CONFIG_BOOKE_WDT */
 179
 180 struct device_node;
 181 extern void note_scsi_host(struct device_node *, void *);
 182
 183 extern struct task_struct *__switch_to(struct task_struct *,
 184         struct task_struct *);
 185 #define switch_to(prev, next, last)     ((last) = __switch_to((prev), (next)))
 186
 187 struct thread_struct;
 188 extern struct task_struct *_switch(struct thread_struct *prev,
 189                                    struct thread_struct *next);
 190
 191 extern unsigned int rtas_data;
 192 extern int mem_init_done;       /* set on boot once kmalloc can be called */
 193 extern int init_bootmem_done;   /* set on !NUMA once bootmem is available */
 194 extern unsigned long memory_limit;
 195 extern unsigned long klimit;
 196
 197 extern void *alloc_maybe_bootmem(size_t size, gfp_t mask);
 198 extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
 199
 200 extern int powersave_nap;       /* set if nap mode can be used in idle loop */
 201
 202 /*
 203  * Atomic exchange
 204  *
 205  * Changes the memory location '*ptr' to be val and returns
 206  * the previous value stored there.
 207  */
 208 static __always_inline unsigned long
 209 __xchg_u32(volatile void *p, unsigned long val)
 210 {
 211         unsigned long prev;
 212
 213         __asm__ __volatile__(
 214         LWSYNC_ON_SMP
 215 "1:     lwarx   %0,0,%2 \n"
 216         PPC405_ERR77(0,%2)
 217 "       stwcx.  %3,0,%2 \n\
 218         bne-    1b"
 219         ISYNC_ON_SMP
 220         : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
 221         : "r" (p), "r" (val)
 222         : "cc", "memory");
 223
 224         return prev;
 225 }
 226
 227 /*
 228  * Atomic exchange
 229  *
 230  * Changes the memory location '*ptr' to be val and returns
 231  * the previous value stored there.
 232  */
 233 static __always_inline unsigned long
 234 __xchg_u32_local(volatile void *p, unsigned long val)
 235 {
 236         unsigned long prev;
 237
 238         __asm__ __volatile__(
 239 "1:     lwarx   %0,0,%2 \n"
 240         PPC405_ERR77(0,%2)
 241 "       stwcx.  %3,0,%2 \n\
 242         bne-    1b"
 243         : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
 244         : "r" (p), "r" (val)
 245         : "cc", "memory");
 246
 247         return prev;
 248 }
 249
 250 #ifdef CONFIG_PPC64
 251 static __always_inline unsigned long
 252 __xchg_u64(volatile void *p, unsigned long val)
 253 {
 254         unsigned long prev;
 255
 256         __asm__ __volatile__(
 257         LWSYNC_ON_SMP
 258 "1:     ldarx   %0,0,%2 \n"
 259         PPC405_ERR77(0,%2)
 260 "       stdcx.  %3,0,%2 \n\
 261         bne-    1b"
 262         ISYNC_ON_SMP
 263         : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
 264         : "r" (p), "r" (val)
 265         : "cc", "memory");
 266
 267         return prev;
 268 }
 269
 270 static __always_inline unsigned long
 271 __xchg_u64_local(volatile void *p, unsigned long val)
 272 {
 273         unsigned long prev;
 274
 275         __asm__ __volatile__(
 276 "1:     ldarx   %0,0,%2 \n"
 277         PPC405_ERR77(0,%2)
 278 "       stdcx.  %3,0,%2 \n\
 279         bne-    1b"
 280         : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
 281         : "r" (p), "r" (val)
 282         : "cc", "memory");
 283
 284         return prev;
 285 }
 286 #endif
 287
 288 /*
 289  * This function doesn't exist, so you'll get a linker error
 290  * if something tries to do an invalid xchg().
 291  */
 292 extern void __xchg_called_with_bad_pointer(void);
 293
 294 static __always_inline unsigned long
 295 __xchg(volatile void *ptr, unsigned long x, unsigned int size)
 296 {
 297         switch (size) {
 298         case 4:
 299                 return __xchg_u32(ptr, x);
 300 #ifdef CONFIG_PPC64
 301         case 8:
 302                 return __xchg_u64(ptr, x);
 303 #endif
 304         }
 305         __xchg_called_with_bad_pointer();
 306         return x;
 307 }
 308
 309 static __always_inline unsigned long
 310 __xchg_local(volatile void *ptr, unsigned long x, unsigned int size)
 311 {
 312         switch (size) {
 313         case 4:
 314                 return __xchg_u32_local(ptr, x);
 315 #ifdef CONFIG_PPC64
 316         case 8:
 317                 return __xchg_u64_local(ptr, x);
 318 #endif
 319         }
 320         __xchg_called_with_bad_pointer();
 321         return x;
 322 }
 323 #define xchg(ptr,x)                                                          \
 324   ({                                                                         \
 325      __typeof__(*(ptr)) _x_ = (x);                                           \
 326      (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
 327   })
 328
 329 #define xchg_local(ptr,x)                                                    \
 330   ({                                                                         \
 331      __typeof__(*(ptr)) _x_ = (x);                                           \
 332      (__typeof__(*(ptr))) __xchg_local((ptr),                                \
 333                 (unsigned long)_x_, sizeof(*(ptr)));                         \
 334   })
 335
 336 /*
 337  * Compare and exchange - if *p == old, set it to new,
 338  * and return the old value of *p.
 339  */
 340 #define __HAVE_ARCH_CMPXCHG     1
 341
 342 static __always_inline unsigned long
 343 __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
 344 {
 345         unsigned int prev;
 346
 347         __asm__ __volatile__ (
 348         LWSYNC_ON_SMP
 349 "1:     lwarx   %0,0,%2         # __cmpxchg_u32\n\
 350         cmpw    0,%0,%3\n\
 351         bne-    2f\n"
 352         PPC405_ERR77(0,%2)
 353 "       stwcx.  %4,0,%2\n\
 354         bne-    1b"
 355         ISYNC_ON_SMP
 356         "\n\
 357 2:"
 358         : "=&r" (prev), "+m" (*p)
 359         : "r" (p), "r" (old), "r" (new)
 360         : "cc", "memory");
 361
 362         return prev;
 363 }
 364
 365 static __always_inline unsigned long
 366 __cmpxchg_u32_local(volatile unsigned int *p, unsigned long old,
 367                         unsigned long new)
 368 {
 369         unsigned int prev;
 370
 371         __asm__ __volatile__ (
 372 "1:     lwarx   %0,0,%2         # __cmpxchg_u32\n\
 373         cmpw    0,%0,%3\n\
 374         bne-    2f\n"
 375         PPC405_ERR77(0,%2)
 376 "       stwcx.  %4,0,%2\n\
 377         bne-    1b"
 378         "\n\
 379 2:"
 380         : "=&r" (prev), "+m" (*p)
 381         : "r" (p), "r" (old), "r" (new)
 382         : "cc", "memory");
 383
 384         return prev;
 385 }
 386
 387 #ifdef CONFIG_PPC64
 388 static __always_inline unsigned long
 389 __cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
 390 {
 391         unsigned long prev;
 392
 393         __asm__ __volatile__ (
 394         LWSYNC_ON_SMP
 395 "1:     ldarx   %0,0,%2         # __cmpxchg_u64\n\
 396         cmpd    0,%0,%3\n\
 397         bne-    2f\n\
 398         stdcx.  %4,0,%2\n\
 399         bne-    1b"
 400         ISYNC_ON_SMP
 401         "\n\
 402 2:"
 403         : "=&r" (prev), "+m" (*p)
 404         : "r" (p), "r" (old), "r" (new)
 405         : "cc", "memory");
 406
 407         return prev;
 408 }
 409
 410 static __always_inline unsigned long
 411 __cmpxchg_u64_local(volatile unsigned long *p, unsigned long old,
 412                         unsigned long new)
 413 {
 414         unsigned long prev;
 415
 416         __asm__ __volatile__ (
 417 "1:     ldarx   %0,0,%2         # __cmpxchg_u64\n\
 418         cmpd    0,%0,%3\n\
 419         bne-    2f\n\
 420         stdcx.  %4,0,%2\n\
 421         bne-    1b"
 422         "\n\
 423 2:"
 424         : "=&r" (prev), "+m" (*p)
 425         : "r" (p), "r" (old), "r" (new)
 426         : "cc", "memory");
 427
 428         return prev;
 429 }
 430 #endif
 431
 432 /* This function doesn't exist, so you'll get a linker error
 433    if something tries to do an invalid cmpxchg().  */
 434 extern void __cmpxchg_called_with_bad_pointer(void);
 435
 436 static __always_inline unsigned long
 437 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
 438           unsigned int size)
 439 {
 440         switch (size) {
 441         case 4:
 442                 return __cmpxchg_u32(ptr, old, new);
 443 #ifdef CONFIG_PPC64
 444         case 8:
 445                 return __cmpxchg_u64(ptr, old, new);
 446 #endif
 447         }
 448         __cmpxchg_called_with_bad_pointer();
 449         return old;
 450 }
 451
 452 static __always_inline unsigned long
 453 __cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
 454           unsigned int size)
 455 {
 456         switch (size) {
 457         case 4:
 458                 return __cmpxchg_u32_local(ptr, old, new);
 459 #ifdef CONFIG_PPC64
 460         case 8:
 461                 return __cmpxchg_u64_local(ptr, old, new);
 462 #endif
 463         }
 464         __cmpxchg_called_with_bad_pointer();
 465         return old;
 466 }
 467
 468 #define cmpxchg(ptr, o, n)                                               \
 469   ({                                                                     \
 470      __typeof__(*(ptr)) _o_ = (o);                                       \
 471      __typeof__(*(ptr)) _n_ = (n);                                       \
 472      (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
 473                                     (unsigned long)_n_, sizeof(*(ptr))); \
 474   })
 475
 476
 477 #define cmpxchg_local(ptr, o, n)                                         \
 478   ({                                                                     \
 479      __typeof__(*(ptr)) _o_ = (o);                                       \
 480      __typeof__(*(ptr)) _n_ = (n);                                       \
 481      (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_,     \
 482                                     (unsigned long)_n_, sizeof(*(ptr))); \
 483   })
 484
 485 #ifdef CONFIG_PPC64
 486 /*
 487  * We handle most unaligned accesses in hardware. On the other hand
 488  * unaligned DMA can be very expensive on some ppc64 IO chips (it does
 489  * powers of 2 writes until it reaches sufficient alignment).
 490  *
 491  * Based on this we disable the IP header alignment in network drivers.
 492  * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
 493  * cacheline alignment of buffers.
 494  */
 495 #define NET_IP_ALIGN    0
 496 #define NET_SKB_PAD     L1_CACHE_BYTES
 497
 498 #define cmpxchg64(ptr, o, n)                                            \
 499   ({                                                                    \
 500         BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
 501         cmpxchg((ptr), (o), (n));                                       \
 502   })
 503 #define cmpxchg64_local(ptr, o, n)                                      \
 504   ({                                                                    \
 505         BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
 506         cmpxchg_local((ptr), (o), (n));                                 \
 507   })
 508 #else
 509 #include <asm-generic/cmpxchg-local.h>
 510 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
 511 #endif
 512
 513 #define arch_align_stack(x) (x)
 514
 515 /* Used in very early kernel initialization. */
 516 extern unsigned long reloc_offset(void);
 517 extern unsigned long add_reloc_offset(unsigned long);
 518 extern void reloc_got2(unsigned long);
 519
 520 #define PTRRELOC(x)     ((typeof(x)) add_reloc_offset((unsigned long)(x)))
 521
 522 static inline void create_instruction(unsigned long addr, unsigned int instr)
 523 {
 524         unsigned int *p;
 525         p  = (unsigned int *)addr;
 526         *p = instr;
 527         asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (p));
 528 }
 529
 530 /* Flags for create_branch:
 531  * "b"   == create_branch(addr, target, 0);
 532  * "ba"  == create_branch(addr, target, BRANCH_ABSOLUTE);
 533  * "bl"  == create_branch(addr, target, BRANCH_SET_LINK);
 534  * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK);
 535  */
 536 #define BRANCH_SET_LINK 0x1
 537 #define BRANCH_ABSOLUTE 0x2
 538
 539 static inline void create_branch(unsigned long addr,
 540                 unsigned long target, int flags)
 541 {
 542         unsigned int instruction;
 543
 544         if (! (flags & BRANCH_ABSOLUTE))
 545                 target = target - addr;
 546
 547         /* Mask out the flags and target, so they don't step on each other. */
 548         instruction = 0x48000000 | (flags & 0x3) | (target & 0x03FFFFFC);
 549
 550         create_instruction(addr, instruction);
 551 }
 552
 553 static inline void create_function_call(unsigned long addr, void * func)
 554 {
 555         unsigned long func_addr;
 556
 557 #ifdef CONFIG_PPC64
 558         /*
 559          * On PPC64 the function pointer actually points to the function's
 560          * descriptor. The first entry in the descriptor is the address
 561          * of the function text.
 562          */
 563         func_addr = *(unsigned long *)func;
 564 #else
 565         func_addr = (unsigned long)func;
 566 #endif
 567         create_branch(addr, func_addr, BRANCH_SET_LINK);
 568 }
 569
 570 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
 571 extern void account_system_vtime(struct task_struct *);
 572 #endif
 573
 574 extern struct dentry *powerpc_debugfs_root;
 575
 576 #endif /* __KERNEL__ */
 577 #endif /* _ASM_POWERPC_SYSTEM_H */