include/asm-ppc/pci-bridge.h

   1 #ifdef __KERNEL__
   2 #ifndef _ASM_PCI_BRIDGE_H
   3 #define _ASM_PCI_BRIDGE_H
   4
   5 #include <linux/ioport.h>
   6 #include <linux/pci.h>
   7
   8 struct device_node;
   9 struct pci_controller;
  10
  11 /*
  12  * pci_io_base returns the memory address at which you can access
  13  * the I/O space for PCI bus number `bus' (or NULL on error).
  14  */
  15 extern void __iomem *pci_bus_io_base(unsigned int bus);
  16 extern unsigned long pci_bus_io_base_phys(unsigned int bus);
  17 extern unsigned long pci_bus_mem_base_phys(unsigned int bus);
  18
  19 /* Allocate a new PCI host bridge structure */
  20 extern struct pci_controller* pcibios_alloc_controller(void);
  21
  22 /* Helper function for setting up resources */
  23 extern void pci_init_resource(struct resource *res, resource_size_t start,
  24                               resource_size_t end, int flags, char *name);
  25
  26 /* Get the PCI host controller for a bus */
  27 extern struct pci_controller* pci_bus_to_hose(int bus);
  28
  29 /* Get the PCI host controller for an OF device */
  30 extern struct pci_controller*
  31 pci_find_hose_for_OF_device(struct device_node* node);
  32
  33 /* Fill up host controller resources from the OF node */
  34 extern void
  35 pci_process_bridge_OF_ranges(struct pci_controller *hose,
  36                            struct device_node *dev, int primary);
  37
  38 /*
  39  * Structure of a PCI controller (host bridge)
  40  */
  41 struct pci_controller {
  42         int index;                      /* PCI domain number */
  43         struct pci_controller *next;
  44         struct pci_bus *bus;
  45         void *arch_data;
  46         struct device *parent;
  47
  48         int first_busno;
  49         int last_busno;
  50         int self_busno;
  51         /* bus_offset is only used by ARCH=ppc */
  52         int bus_offset;
  53
  54         void __iomem *io_base_virt;
  55         resource_size_t io_base_phys;
  56
  57         /* Some machines (PReP) have a non 1:1 mapping of
  58          * the PCI memory space in the CPU bus space
  59          */
  60         resource_size_t pci_mem_offset;
  61
  62         struct pci_ops *ops;
  63         volatile unsigned int __iomem *cfg_addr;
  64         volatile void __iomem *cfg_data;
  65         /*
  66          * If set, indirect method will set the cfg_type bit as
  67          * needed to generate type 1 configuration transactions.
  68          */
  69         int set_cfg_type;
  70
  71         /* Currently, we limit ourselves to 1 IO range and 3 mem
  72          * ranges since the common pci_bus structure can't handle more
  73          */
  74         struct resource io_resource;
  75         struct resource mem_resources[3];
  76         int mem_resource_count;
  77
  78         /* Host bridge I/O and Memory space
  79          * Used for BAR placement algorithms
  80          */
  81         struct resource io_space;
  82         struct resource mem_space;
  83 };
  84
  85 static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
  86 {
  87         return bus->sysdata;
  88 }
  89
  90 /* These are used for config access before all the PCI probing
  91    has been done. */
  92 int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
  93                            int where, u8 *val);
  94 int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
  95                            int where, u16 *val);
  96 int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
  97                             int where, u32 *val);
  98 int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
  99                             int where, u8 val);
 100 int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
 101                             int where, u16 val);
 102 int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
 103                              int where, u32 val);
 104
 105 extern void setup_indirect_pci_nomap(struct pci_controller* hose,
 106                                void __iomem *cfg_addr, void __iomem *cfg_data);
 107 extern void setup_indirect_pci(struct pci_controller* hose,
 108                                u32 cfg_addr, u32 cfg_data);
 109 extern void setup_grackle(struct pci_controller *hose);
 110
 111 extern unsigned char common_swizzle(struct pci_dev *, unsigned char *);
 112
 113 /*
 114  *   The following code swizzles for exactly one bridge.  The routine
 115  *   common_swizzle below handles multiple bridges.  But there are a
 116  *   some boards that don't follow the PCI spec's suggestion so we
 117  *   break this piece out separately.
 118  */
 119 static inline unsigned char bridge_swizzle(unsigned char pin,
 120                 unsigned char idsel)
 121 {
 122         return (((pin-1) + idsel) % 4) + 1;
 123 }
 124
 125 /*
 126  * The following macro is used to lookup irqs in a standard table
 127  * format for those PPC systems that do not already have PCI
 128  * interrupts properly routed.
 129  */
 130 /* FIXME - double check this */
 131 #define PCI_IRQ_TABLE_LOOKUP                                                \
 132 ({ long _ctl_ = -1;                                                         \
 133    if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot)    \
 134      _ctl_ = pci_irq_table[idsel - min_idsel][pin-1];                       \
 135    _ctl_; })
 136
 137 /*
 138  * Scan the buses below a given PCI host bridge and assign suitable
 139  * resources to all devices found.
 140  */
 141 extern int pciauto_bus_scan(struct pci_controller *, int);
 142
 143 #ifdef CONFIG_PCI
 144 extern unsigned long pci_address_to_pio(phys_addr_t address);
 145 #else
 146 static inline unsigned long pci_address_to_pio(phys_addr_t address)
 147 {
 148         return (unsigned long)-1;
 149 }
 150 #endif
 151
 152 #endif
 153 #endif /* __KERNEL__ */