include/asm-sh/cpu-sh2a/irq.h

   1 #ifndef __ASM_SH_CPU_SH2A_IRQ_H
   2 #define __ASM_SH_CPU_SH2A_IRQ_H
   3
   4 #define INTC_IPR01      0xfffe0818UL
   5 #define INTC_IPR02      0xfffe081aUL
   6 #define INTC_IPR05      0xfffe0820UL
   7 #define INTC_IPR06      0xfffe0c00UL
   8 #define INTC_IPR07      0xfffe0c02UL
   9 #define INTC_IPR08      0xfffe0c04UL
  10 #define INTC_IPR09      0xfffe0c06UL
  11 #define INTC_IPR10      0xfffe0c08UL
  12 #define INTC_IPR11      0xfffe0c0aUL
  13 #define INTC_IPR12      0xfffe0c0cUL
  14 #define INTC_IPR13      0xfffe0c0eUL
  15 #define INTC_IPR14      0xfffe0c10UL
  16
  17 #define INTC_ICR0       0xfffe0800UL
  18 #define INTC_ICR1       0xfffe0802UL
  19 #define INTC_ICR2       0xfffe0804UL
  20 #define INTC_ISR        0xfffe0806UL
  21
  22 #define IRQ0_IRQ        64
  23 #define IRQ1_IRQ        65
  24 #define IRQ2_IRQ        66
  25 #define IRQ3_IRQ        67
  26 #define IRQ4_IRQ        68
  27 #define IRQ5_IRQ        69
  28 #define IRQ6_IRQ        70
  29 #define IRQ7_IRQ        71
  30
  31 #define PINT0_IRQ       80
  32 #define PINT1_IRQ       81
  33 #define PINT2_IRQ       82
  34 #define PINT3_IRQ       83
  35 #define PINT4_IRQ       84
  36 #define PINT5_IRQ       85
  37 #define PINT6_IRQ       86
  38 #define PINT7_IRQ       87
  39
  40 #define CMI0_IRQ        140
  41 #define CMI1_IRQ        141
  42
  43 #define SCIF_BRI_IRQ    240
  44 #define SCIF_ERI_IRQ    241
  45 #define SCIF_RXI_IRQ    242
  46 #define SCIF_TXI_IRQ    243
  47 #define SCIF_IPR_ADDR   INTC_IPR14
  48 #define SCIF_IPR_POS    3
  49 #define SCIF_PRIORITY   3
  50
  51 #define SCIF1_BRI_IRQ   244
  52 #define SCIF1_ERI_IRQ   245
  53 #define SCIF1_RXI_IRQ   246
  54 #define SCIF1_TXI_IRQ   247
  55 #define SCIF1_IPR_ADDR  INTC_IPR14
  56 #define SCIF1_IPR_POS   2
  57 #define SCIF1_PRIORITY  3
  58
  59 #define SCIF2_BRI_IRQ   248
  60 #define SCIF2_ERI_IRQ   249
  61 #define SCIF2_RXI_IRQ   250
  62 #define SCIF2_TXI_IRQ   251
  63 #define SCIF2_IPR_ADDR  INTC_IPR14
  64 #define SCIF2_IPR_POS   1
  65 #define SCIF2_PRIORITY  3
  66
  67 #define SCIF3_BRI_IRQ   252
  68 #define SCIF3_ERI_IRQ   253
  69 #define SCIF3_RXI_IRQ   254
  70 #define SCIF3_TXI_IRQ   255
  71 #define SCIF3_IPR_ADDR  INTC_IPR14
  72 #define SCIF3_IPR_POS   0
  73 #define SCIF3_PRIORITY  3
  74
  75 #endif /* __ASM_SH_CPU_SH2A_IRQ_H */