include/asm-sh/irq.h

   1 #ifndef __ASM_SH_IRQ_H
   2 #define __ASM_SH_IRQ_H
   3
   4 /*
   5  *
   6  * linux/include/asm-sh/irq.h
   7  *
   8  * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi
   9  * Copyright (C) 2000  Kazumoto Kojima
  10  * Copyright (C) 2003  Paul Mundt
  11  *
  12  */
  13
  14 #include <asm/machvec.h>
  15 #include <asm/ptrace.h>         /* for pt_regs */
  16
  17 #if defined(CONFIG_CPU_SH2)
  18 #include <asm/cpu/irq.h>
  19 #endif
  20
  21 #ifndef CONFIG_CPU_SUBTYPE_SH7780
  22
  23 #define INTC_DMAC0_MSK  0
  24
  25 #if defined(CONFIG_CPU_SH3)
  26 #define INTC_IPRA       0xfffffee2UL
  27 #define INTC_IPRB       0xfffffee4UL
  28 #elif defined(CONFIG_CPU_SH4)
  29 #define INTC_IPRA       0xffd00004UL
  30 #define INTC_IPRB       0xffd00008UL
  31 #define INTC_IPRC       0xffd0000cUL
  32 #define INTC_IPRD       0xffd00010UL
  33 #endif
  34
  35 #if defined(CONFIG_CPU_SUBTYPE_SH7206)
  36 #ifdef CONFIG_SH_CMT
  37 #define TIMER_IRQ       CMI0_IRQ
  38 #define TIMER_IPR_ADDR  INTC_IPR08
  39 #define TIMER_IPR_POS    3
  40 #define TIMER_PRIORITY   2
  41
  42 #define TIMER1_IRQ      CMI1_IRQ
  43 #define TIMER1_IPR_ADDR INTC_IPR08
  44 #define TIMER1_IPR_POS   2
  45 #define TIMER1_PRIORITY  2
  46 #endif
  47
  48 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
  49 #define TIMER_IRQ       CMI0_IRQ
  50 #define TIMER_IPR_ADDR  INTC_IPRC
  51 #define TIMER_IPR_POS    1
  52 #define TIMER_PRIORITY   2
  53
  54 #define TIMER1_IRQ      CMI1_IRQ
  55 #define TIMER1_IPR_ADDR INTC_IPRC
  56 #define TIMER1_IPR_POS   0
  57 #define TIMER1_PRIORITY  4
  58
  59 #else
  60 #define TIMER_IRQ       16
  61 #define TIMER_IPR_ADDR  INTC_IPRA
  62 #define TIMER_IPR_POS    3
  63 #define TIMER_PRIORITY   2
  64
  65 #define TIMER1_IRQ      17
  66 #define TIMER1_IPR_ADDR INTC_IPRA
  67 #define TIMER1_IPR_POS   2
  68 #define TIMER1_PRIORITY  4
  69 #endif
  70
  71 #if !defined(CONFIG_CPU_SH2)
  72 #define RTC_IRQ         22
  73 #define RTC_IPR_ADDR    INTC_IPRA
  74 #define RTC_IPR_POS      0
  75 #define RTC_PRIORITY    TIMER_PRIORITY
  76 #endif
  77
  78 #if defined(CONFIG_CPU_SH3)
  79 #define DMTE0_IRQ       48
  80 #define DMTE1_IRQ       49
  81 #define DMTE2_IRQ       50
  82 #define DMTE3_IRQ       51
  83 #define DMA_IPR_ADDR    INTC_IPRE
  84 #define DMA_IPR_POS     3
  85 #define DMA_PRIORITY    7
  86 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
  87 /* TMU2 */
  88 #define TIMER2_IRQ      18
  89 #define TIMER2_IPR_ADDR INTC_IPRA
  90 #define TIMER2_IPR_POS   1
  91 #define TIMER2_PRIORITY  2
  92
  93 /* WDT */
  94 #define WDT_IRQ         27
  95 #define WDT_IPR_ADDR    INTC_IPRB
  96 #define WDT_IPR_POS      3
  97 #define WDT_PRIORITY     2
  98
  99 /* SIM (SIM Card Module) */
 100 #define SIM_ERI_IRQ     23
 101 #define SIM_RXI_IRQ     24
 102 #define SIM_TXI_IRQ     25
 103 #define SIM_TEND_IRQ    26
 104 #define SIM_IPR_ADDR    INTC_IPRB
 105 #define SIM_IPR_POS      1
 106 #define SIM_PRIORITY     2
 107
 108 /* VIO (Video I/O) */
 109 #define VIO_IRQ         52
 110 #define VIO_IPR_ADDR    INTC_IPRE
 111 #define VIO_IPR_POS      2
 112 #define VIO_PRIORITY     2
 113
 114 /* MFI (Multi Functional Interface) */
 115 #define MFI_IRQ         56
 116 #define MFI_IPR_ADDR    INTC_IPRE
 117 #define MFI_IPR_POS      1
 118 #define MFI_PRIORITY     2
 119
 120 /* VPU (Video Processing Unit) */
 121 #define VPU_IRQ         60
 122 #define VPU_IPR_ADDR    INTC_IPRE
 123 #define VPU_IPR_POS      0
 124 #define VPU_PRIORITY     2
 125
 126 /* KEY (Key Scan Interface) */
 127 #define KEY_IRQ         79
 128 #define KEY_IPR_ADDR    INTC_IPRF
 129 #define KEY_IPR_POS      3
 130 #define KEY_PRIORITY     2
 131
 132 /* CMT (Compare Match Timer) */
 133 #define CMT_IRQ         104
 134 #define CMT_IPR_ADDR    INTC_IPRF
 135 #define CMT_IPR_POS      0
 136 #define CMT_PRIORITY     2
 137
 138 /* DMAC(1) */
 139 #define DMTE0_IRQ       48
 140 #define DMTE1_IRQ       49
 141 #define DMTE2_IRQ       50
 142 #define DMTE3_IRQ       51
 143 #define DMA1_IPR_ADDR   INTC_IPRE
 144 #define DMA1_IPR_POS    3
 145 #define DMA1_PRIORITY   7
 146
 147 /* DMAC(2) */
 148 #define DMTE4_IRQ       76
 149 #define DMTE5_IRQ       77
 150 #define DMA2_IPR_ADDR   INTC_IPRF
 151 #define DMA2_IPR_POS    2
 152 #define DMA2_PRIORITY   7
 153
 154 /* SIOF0 */
 155 #define SIOF0_IRQ       84
 156 #define SIOF0_IPR_ADDR  INTC_IPRH
 157 #define SIOF0_IPR_POS   3
 158 #define SIOF0_PRIORITY  3
 159
 160 /* FLCTL (Flash Memory Controller) */
 161 #define FLSTE_IRQ       92
 162 #define FLTEND_IRQ      93
 163 #define FLTRQ0_IRQ      94
 164 #define FLTRQ1_IRQ      95
 165 #define FLCTL_IPR_ADDR  INTC_IPRH
 166 #define FLCTL_IPR_POS   1
 167 #define FLCTL_PRIORITY  3
 168
 169 /* IIC (IIC Bus Interface) */
 170 #define IIC_ALI_IRQ     96
 171 #define IIC_TACKI_IRQ   97
 172 #define IIC_WAITI_IRQ   98
 173 #define IIC_DTEI_IRQ    99
 174 #define IIC_IPR_ADDR    INTC_IPRH
 175 #define IIC_IPR_POS     0
 176 #define IIC_PRIORITY    3
 177
 178 /* SIO0 */
 179 #define SIO0_IRQ        88
 180 #define SIO0_IPR_ADDR   INTC_IPRI
 181 #define SIO0_IPR_POS    3
 182 #define SIO0_PRIORITY   3
 183
 184 /* SIU (Sound Interface Unit) */
 185 #define SIU_IRQ         108
 186 #define SIU_IPR_ADDR    INTC_IPRJ
 187 #define SIU_IPR_POS     1
 188 #define SIU_PRIORITY    3
 189
 190 #endif
 191 #elif defined(CONFIG_CPU_SH4)
 192 #define DMTE0_IRQ       34
 193 #define DMTE1_IRQ       35
 194 #define DMTE2_IRQ       36
 195 #define DMTE3_IRQ       37
 196 #define DMTE4_IRQ       44      /* 7751R only */
 197 #define DMTE5_IRQ       45      /* 7751R only */
 198 #define DMTE6_IRQ       46      /* 7751R only */
 199 #define DMTE7_IRQ       47      /* 7751R only */
 200 #define DMAE_IRQ        38
 201 #define DMA_IPR_ADDR    INTC_IPRC
 202 #define DMA_IPR_POS     2
 203 #define DMA_PRIORITY    7
 204 #endif
 205
 206 #if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
 207     defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
 208     defined (CONFIG_CPU_SUBTYPE_SH7751) || defined (CONFIG_CPU_SUBTYPE_SH7706)
 209 #define SCI_ERI_IRQ     23
 210 #define SCI_RXI_IRQ     24
 211 #define SCI_TXI_IRQ     25
 212 #define SCI_IPR_ADDR    INTC_IPRB
 213 #define SCI_IPR_POS     1
 214 #define SCI_PRIORITY    3
 215 #endif
 216
 217 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
 218 #define SCIF0_IRQ       80
 219 #define SCIF0_IPR_ADDR  INTC_IPRG
 220 #define SCIF0_IPR_POS   3
 221 #define SCIF0_PRIORITY  3
 222 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 223       defined(CONFIG_CPU_SUBTYPE_SH7706) || \
 224       defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 225       defined(CONFIG_CPU_SUBTYPE_SH7709)
 226 #define SCIF_ERI_IRQ    56
 227 #define SCIF_RXI_IRQ    57
 228 #define SCIF_BRI_IRQ    58
 229 #define SCIF_TXI_IRQ    59
 230 #define SCIF_IPR_ADDR   INTC_IPRE
 231 #define SCIF_IPR_POS    1
 232 #define SCIF_PRIORITY   3
 233
 234 #define IRDA_ERI_IRQ    52
 235 #define IRDA_RXI_IRQ    53
 236 #define IRDA_BRI_IRQ    54
 237 #define IRDA_TXI_IRQ    55
 238 #define IRDA_IPR_ADDR   INTC_IPRE
 239 #define IRDA_IPR_POS    2
 240 #define IRDA_PRIORITY   3
 241 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 242       defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
 243 #define SCIF_ERI_IRQ    40
 244 #define SCIF_RXI_IRQ    41
 245 #define SCIF_BRI_IRQ    42
 246 #define SCIF_TXI_IRQ    43
 247 #define SCIF_IPR_ADDR   INTC_IPRC
 248 #define SCIF_IPR_POS    1
 249 #define SCIF_PRIORITY   3
 250 #if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 251 #define SCIF1_ERI_IRQ   23
 252 #define SCIF1_RXI_IRQ   24
 253 #define SCIF1_BRI_IRQ   25
 254 #define SCIF1_TXI_IRQ   26
 255 #define SCIF1_IPR_ADDR  INTC_IPRB
 256 #define SCIF1_IPR_POS   1
 257 #define SCIF1_PRIORITY  3
 258 #endif /* ST40STB1 */
 259
 260 #endif /* 775x / SH4-202 / ST40STB1 */
 261 #endif /* 7780 */
 262
 263 /* NR_IRQS is made from three components:
 264  *   1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
 265  *   2. PINT_NR_IRQS   - number of PINT interrupts
 266  *   3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
 267  */
 268
 269 /* 1. ONCHIP_NR_IRQS */
 270 #if defined(CONFIG_CPU_SUBTYPE_SH7604)
 271 # define ONCHIP_NR_IRQS 24      // Actually 21
 272 #elif defined(CONFIG_CPU_SUBTYPE_SH7707)
 273 # define ONCHIP_NR_IRQS 64
 274 # define PINT_NR_IRQS   16
 275 #elif defined(CONFIG_CPU_SUBTYPE_SH7708)
 276 # define ONCHIP_NR_IRQS 32
 277 #elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
 278       defined(CONFIG_CPU_SUBTYPE_SH7706) || \
 279       defined(CONFIG_CPU_SUBTYPE_SH7705)
 280 # define ONCHIP_NR_IRQS 64      // Actually 61
 281 # define PINT_NR_IRQS   16
 282 #elif defined(CONFIG_CPU_SUBTYPE_SH7710)
 283 # define ONCHIP_NR_IRQS 104
 284 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)
 285 # define ONCHIP_NR_IRQS 48      // Actually 44
 286 #elif defined(CONFIG_CPU_SUBTYPE_SH7751)
 287 # define ONCHIP_NR_IRQS 72
 288 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
 289 # define ONCHIP_NR_IRQS 112     /* XXX */
 290 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
 291 # define ONCHIP_NR_IRQS 72
 292 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 293 # define ONCHIP_NR_IRQS 144
 294 #elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
 295       defined(CONFIG_CPU_SUBTYPE_SH73180) || \
 296       defined(CONFIG_CPU_SUBTYPE_SH7343)
 297 # define ONCHIP_NR_IRQS 109
 298 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 299 # define ONCHIP_NR_IRQS 111
 300 #elif defined(CONFIG_CPU_SUBTYPE_SH7206)
 301 # define ONCHIP_NR_IRQS 256
 302 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
 303 # define ONCHIP_NR_IRQS 128
 304 #elif defined(CONFIG_SH_UNKNOWN)        /* Most be last */
 305 # define ONCHIP_NR_IRQS 144
 306 #endif
 307
 308 /* 2. PINT_NR_IRQS */
 309 #ifdef CONFIG_SH_UNKNOWN
 310 # define PINT_NR_IRQS 16
 311 #else
 312 # ifndef PINT_NR_IRQS
 313 #  define PINT_NR_IRQS 0
 314 # endif
 315 #endif
 316
 317 #if PINT_NR_IRQS > 0
 318 # define PINT_IRQ_BASE  ONCHIP_NR_IRQS
 319 #endif
 320
 321 /* 3. OFFCHIP_NR_IRQS */
 322 #if defined(CONFIG_HD64461)
 323 # define OFFCHIP_NR_IRQS 18
 324 #elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
 325 # define OFFCHIP_NR_IRQS 48
 326 #elif defined(CONFIG_HD64465)
 327 # define OFFCHIP_NR_IRQS 16
 328 #elif defined (CONFIG_SH_EC3104)
 329 # define OFFCHIP_NR_IRQS 16
 330 #elif defined (CONFIG_SH_DREAMCAST)
 331 # define OFFCHIP_NR_IRQS 96
 332 #elif defined (CONFIG_SH_TITAN)
 333 # define OFFCHIP_NR_IRQS 4
 334 #elif defined(CONFIG_SH_R7780RP)
 335 # define OFFCHIP_NR_IRQS 16
 336 #elif defined(CONFIG_SH_7343_SOLUTION_ENGINE)
 337 # define OFFCHIP_NR_IRQS 12
 338 #elif defined(CONFIG_SH_UNKNOWN)
 339 # define OFFCHIP_NR_IRQS 16     /* Must also be last */
 340 #else
 341 # define OFFCHIP_NR_IRQS 0
 342 #endif
 343
 344 #if OFFCHIP_NR_IRQS > 0
 345 # define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
 346 #endif
 347
 348 /* NR_IRQS. 1+2+3 */
 349 #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
 350
 351 extern void disable_irq(unsigned int);
 352 extern void disable_irq_nosync(unsigned int);
 353 extern void enable_irq(unsigned int);
 354
 355 /*
 356  * Simple Mask Register Support
 357  */
 358 extern void make_maskreg_irq(unsigned int irq);
 359 extern unsigned short *irq_mask_register;
 360
 361 #if defined(CONFIG_CPU_SUBTYPE_SH7619)
 362 #define IRQ0_IRQ        16
 363 #define IRQ1_IRQ        17
 364 #define IRQ2_IRQ        18
 365 #define IRQ3_IRQ        19
 366 #define IRQ4_IRQ        32
 367 #define IRQ5_IRQ        33
 368 #define IRQ6_IRQ        34
 369 #define IRQ7_IRQ        35
 370 #elif !defined(CONFIG_CPU_SUBTYPE_SH7206)
 371 #define IRQ0_IRQ        32
 372 #define IRQ1_IRQ        33
 373 #define IRQ2_IRQ        34
 374 #define IRQ3_IRQ        35
 375 #define IRQ4_IRQ        36
 376 #define IRQ5_IRQ        37
 377 #endif
 378
 379 #define IRQ0_PRIORITY   1
 380 #define IRQ1_PRIORITY   1
 381 #define IRQ2_PRIORITY   1
 382 #define IRQ3_PRIORITY   1
 383 #define IRQ4_PRIORITY   1
 384 #define IRQ5_PRIORITY   1
 385
 386 #ifndef IRQ0_IPR_POS
 387 #define IRQ0_IPR_POS    0
 388 #define IRQ1_IPR_POS    1
 389 #define IRQ2_IPR_POS    2
 390 #define IRQ3_IPR_POS    3
 391 #define IRQ4_IPR_POS    0
 392 #define IRQ5_IPR_POS    1
 393 #endif
 394
 395 /*
 396  * PINT IRQs
 397  */
 398 void init_IRQ_pint(void);
 399
 400 struct ipr_data {
 401         unsigned int irq;
 402         unsigned int addr;      /* Address of Interrupt Priority Register */
 403         int shift;              /* Shifts of the 16-bit data */
 404         int priority;           /* The priority */
 405 };
 406
 407 /*
 408  * Function for "on chip support modules".
 409  */
 410 extern void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
 411 extern void make_imask_irq(unsigned int irq);
 412
 413 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
 414 #undef INTC_IPRA
 415 #undef INTC_IPRB
 416 #define INTC_IPRA       0xA414FEE2UL
 417 #define INTC_IPRB       0xA414FEE4UL
 418 #define INTC_IPRC       0xA4140016UL
 419 #define INTC_IPRD       0xA4140018UL
 420 #define INTC_IPRE       0xA414001AUL
 421 #define INTC_IPRF       0xA4080000UL
 422 #define INTC_IPRG       0xA4080002UL
 423 #define INTC_IPRH       0xA4080004UL
 424 #define INTC_IPRI       0xA4080006UL
 425 #define INTC_IPRJ       0xA4080008UL
 426
 427 #define INTC_IMR0       0xA4080040UL
 428 #define INTC_IMR1       0xA4080042UL
 429 #define INTC_IMR2       0xA4080044UL
 430 #define INTC_IMR3       0xA4080046UL
 431 #define INTC_IMR4       0xA4080048UL
 432 #define INTC_IMR5       0xA408004AUL
 433 #define INTC_IMR6       0xA408004CUL
 434 #define INTC_IMR7       0xA408004EUL
 435 #define INTC_IMR8       0xA4080050UL
 436 #define INTC_IMR9       0xA4080052UL
 437 #define INTC_IMR10      0xA4080054UL
 438
 439 #define INTC_IMCR0      0xA4080060UL
 440 #define INTC_IMCR1      0xA4080062UL
 441 #define INTC_IMCR2      0xA4080064UL
 442 #define INTC_IMCR3      0xA4080066UL
 443 #define INTC_IMCR4      0xA4080068UL
 444 #define INTC_IMCR5      0xA408006AUL
 445 #define INTC_IMCR6      0xA408006CUL
 446 #define INTC_IMCR7      0xA408006EUL
 447 #define INTC_IMCR8      0xA4080070UL
 448 #define INTC_IMCR9      0xA4080072UL
 449 #define INTC_IMCR10     0xA4080074UL
 450
 451 #define INTC_ICR0       0xA414FEE0UL
 452 #define INTC_ICR1       0xA4140010UL
 453
 454 #define INTC_IRR0       0xA4140004UL
 455
 456 #define PORT_PACR       0xA4050100UL
 457 #define PORT_PBCR       0xA4050102UL
 458 #define PORT_PCCR       0xA4050104UL
 459 #define PORT_PDCR       0xA4050106UL
 460 #define PORT_PECR       0xA4050108UL
 461 #define PORT_PFCR       0xA405010AUL
 462 #define PORT_PGCR       0xA405010CUL
 463 #define PORT_PHCR       0xA405010EUL
 464 #define PORT_PJCR       0xA4050110UL
 465 #define PORT_PKCR       0xA4050112UL
 466 #define PORT_PLCR       0xA4050114UL
 467 #define PORT_SCPCR      0xA4050116UL
 468 #define PORT_PMCR       0xA4050118UL
 469 #define PORT_PNCR       0xA405011AUL
 470 #define PORT_PQCR       0xA405011CUL
 471
 472 #define PORT_PSELA      0xA4050140UL
 473 #define PORT_PSELB      0xA4050142UL
 474 #define PORT_PSELC      0xA4050144UL
 475
 476 #define PORT_HIZCRA     0xA4050146UL
 477 #define PORT_HIZCRB     0xA4050148UL
 478 #define PORT_DRVCR      0xA4050150UL
 479
 480 #define PORT_PADR       0xA4050120UL
 481 #define PORT_PBDR       0xA4050122UL
 482 #define PORT_PCDR       0xA4050124UL
 483 #define PORT_PDDR       0xA4050126UL
 484 #define PORT_PEDR       0xA4050128UL
 485 #define PORT_PFDR       0xA405012AUL
 486 #define PORT_PGDR       0xA405012CUL
 487 #define PORT_PHDR       0xA405012EUL
 488 #define PORT_PJDR       0xA4050130UL
 489 #define PORT_PKDR       0xA4050132UL
 490 #define PORT_PLDR       0xA4050134UL
 491 #define PORT_SCPDR      0xA4050136UL
 492 #define PORT_PMDR       0xA4050138UL
 493 #define PORT_PNDR       0xA405013AUL
 494 #define PORT_PQDR       0xA405013CUL
 495
 496 #define IRQ0_IRQ        32
 497 #define IRQ1_IRQ        33
 498 #define IRQ2_IRQ        34
 499 #define IRQ3_IRQ        35
 500 #define IRQ4_IRQ        36
 501 #define IRQ5_IRQ        37
 502
 503 #define IRQ0_IPR_ADDR   INTC_IPRC
 504 #define IRQ1_IPR_ADDR   INTC_IPRC
 505 #define IRQ2_IPR_ADDR   INTC_IPRC
 506 #define IRQ3_IPR_ADDR   INTC_IPRC
 507 #define IRQ4_IPR_ADDR   INTC_IPRD
 508 #define IRQ5_IPR_ADDR   INTC_IPRD
 509
 510 #define IRQ0_IPR_POS    0
 511 #define IRQ1_IPR_POS    1
 512 #define IRQ2_IPR_POS    2
 513 #define IRQ3_IPR_POS    3
 514 #define IRQ4_IPR_POS    0
 515 #define IRQ5_IPR_POS    1
 516
 517 #define IRQ0_PRIORITY   1
 518 #define IRQ1_PRIORITY   1
 519 #define IRQ2_PRIORITY   1
 520 #define IRQ3_PRIORITY   1
 521 #define IRQ4_PRIORITY   1
 522 #define IRQ5_PRIORITY   1
 523
 524 extern int ipr_irq_demux(int irq);
 525 #define __irq_demux(irq) ipr_irq_demux(irq)
 526
 527 #elif defined(CONFIG_CPU_SUBTYPE_SH7604)
 528 #define INTC_IPRA       0xfffffee2UL
 529 #define INTC_IPRB       0xfffffe60UL
 530
 531 #define INTC_VCRA       0xfffffe62UL
 532 #define INTC_VCRB       0xfffffe64UL
 533 #define INTC_VCRC       0xfffffe66UL
 534 #define INTC_VCRD       0xfffffe68UL
 535
 536 #define INTC_VCRWDT     0xfffffee4UL
 537 #define INTC_VCRDIV     0xffffff0cUL
 538 #define INTC_VCRDMA0    0xffffffa0UL
 539 #define INTC_VCRDMA1    0xffffffa8UL
 540
 541 #define INTC_ICR        0xfffffee0UL
 542 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 543       defined(CONFIG_CPU_SUBTYPE_SH7706) || \
 544       defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 545       defined(CONFIG_CPU_SUBTYPE_SH7709) || \
 546       defined(CONFIG_CPU_SUBTYPE_SH7710)
 547 #define INTC_IRR0       0xa4000004UL
 548 #define INTC_IRR1       0xa4000006UL
 549 #define INTC_IRR2       0xa4000008UL
 550
 551 #define INTC_ICR0       0xfffffee0UL
 552 #define INTC_ICR1       0xa4000010UL
 553 #define INTC_ICR2       0xa4000012UL
 554 #define INTC_INTER      0xa4000014UL
 555
 556 #define INTC_IPRC       0xa4000016UL
 557 #define INTC_IPRD       0xa4000018UL
 558 #define INTC_IPRE       0xa400001aUL
 559 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
 560 #define INTC_IPRF       0xa400001cUL
 561 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
 562 #define INTC_IPRF       0xa4080000UL
 563 #define INTC_IPRG       0xa4080002UL
 564 #define INTC_IPRH       0xa4080004UL
 565 #elif defined(CONFIG_CPU_SUBTYPE_SH7710)
 566 /* Interrupt Controller Registers */
 567 #undef INTC_IPRA
 568 #undef INTC_IPRB
 569 #define INTC_IPRA       0xA414FEE2UL
 570 #define INTC_IPRB       0xA414FEE4UL
 571 #define INTC_IPRF       0xA4080000UL
 572 #define INTC_IPRG       0xA4080002UL
 573 #define INTC_IPRH       0xA4080004UL
 574 #define INTC_IPRI       0xA4080006UL
 575
 576 #undef INTC_ICR0
 577 #undef INTC_ICR1
 578 #define INTC_ICR0       0xA414FEE0UL
 579 #define INTC_ICR1       0xA4140010UL
 580
 581 #define INTC_IRR0       0xa4000004UL
 582 #define INTC_IRR1       0xa4000006UL
 583 #define INTC_IRR2       0xa4000008UL
 584 #define INTC_IRR3       0xa400000AUL
 585 #define INTC_IRR4       0xa400000CUL
 586 #define INTC_IRR5       0xa4080020UL
 587 #define INTC_IRR7       0xa4080024UL
 588 #define INTC_IRR8       0xa4080026UL
 589
 590 /* Interrupt numbers */
 591 #define TIMER2_IRQ      18
 592 #define TIMER2_IPR_ADDR INTC_IPRA
 593 #define TIMER2_IPR_POS   1
 594 #define TIMER2_PRIORITY  2
 595
 596 /* WDT */
 597 #define WDT_IRQ         27
 598 #define WDT_IPR_ADDR    INTC_IPRB
 599 #define WDT_IPR_POS      3
 600 #define WDT_PRIORITY     2
 601
 602 #define SCIF0_ERI_IRQ   52
 603 #define SCIF0_RXI_IRQ   53
 604 #define SCIF0_BRI_IRQ   54
 605 #define SCIF0_TXI_IRQ   55
 606 #define SCIF0_IPR_ADDR  INTC_IPRE
 607 #define SCIF0_IPR_POS   2
 608 #define SCIF0_PRIORITY  3
 609
 610 #define DMTE4_IRQ       76
 611 #define DMTE5_IRQ       77
 612 #define DMA2_IPR_ADDR   INTC_IPRF
 613 #define DMA2_IPR_POS    2
 614 #define DMA2_PRIORITY   7
 615
 616 #define IPSEC_IRQ       79
 617 #define IPSEC_IPR_ADDR  INTC_IPRF
 618 #define IPSEC_IPR_POS   3
 619 #define IPSEC_PRIORITY  3
 620
 621 /* EDMAC */
 622 #define EDMAC0_IRQ      80
 623 #define EDMAC0_IPR_ADDR INTC_IPRG
 624 #define EDMAC0_IPR_POS  3
 625 #define EDMAC0_PRIORITY 3
 626
 627 #define EDMAC1_IRQ      81
 628 #define EDMAC1_IPR_ADDR INTC_IPRG
 629 #define EDMAC1_IPR_POS  2
 630 #define EDMAC1_PRIORITY 3
 631
 632 #define EDMAC2_IRQ      82
 633 #define EDMAC2_IPR_ADDR INTC_IPRG
 634 #define EDMAC2_IPR_POS  1
 635 #define EDMAC2_PRIORITY 3
 636
 637 /* SIOF */
 638 #define SIOF0_ERI_IRQ   96
 639 #define SIOF0_TXI_IRQ   97
 640 #define SIOF0_RXI_IRQ   98
 641 #define SIOF0_CCI_IRQ   99
 642 #define SIOF0_IPR_ADDR  INTC_IPRH
 643 #define SIOF0_IPR_POS   0
 644 #define SIOF0_PRIORITY  7
 645
 646 #define SIOF1_ERI_IRQ   100
 647 #define SIOF1_TXI_IRQ   101
 648 #define SIOF1_RXI_IRQ   102
 649 #define SIOF1_CCI_IRQ   103
 650 #define SIOF1_IPR_ADDR  INTC_IPRI
 651 #define SIOF1_IPR_POS   1
 652 #define SIOF1_PRIORITY  7
 653 #endif /* CONFIG_CPU_SUBTYPE_SH7710 */
 654
 655 #if defined(CONFIG_CPU_SUBTYPE_SH7710)
 656 #define PORT_PACR       0xa4050100UL
 657 #define PORT_PBCR       0xa4050102UL
 658 #define PORT_PCCR       0xa4050104UL
 659 #define PORT_PETCR      0xa4050106UL
 660 #define PORT_PADR       0xa4050120UL
 661 #define PORT_PBDR       0xa4050122UL
 662 #define PORT_PCDR       0xa4050124UL
 663 #else
 664 #define PORT_PACR       0xa4000100UL
 665 #define PORT_PBCR       0xa4000102UL
 666 #define PORT_PCCR       0xa4000104UL
 667 #define PORT_PFCR       0xa400010aUL
 668 #define PORT_PADR       0xa4000120UL
 669 #define PORT_PBDR       0xa4000122UL
 670 #define PORT_PCDR       0xa4000124UL
 671 #define PORT_PFDR       0xa400012aUL
 672 #endif
 673
 674 #define IRQ0_IRQ        32
 675 #define IRQ1_IRQ        33
 676 #define IRQ2_IRQ        34
 677 #define IRQ3_IRQ        35
 678 #define IRQ4_IRQ        36
 679 #define IRQ5_IRQ        37
 680
 681 #define IRQ0_IPR_ADDR   INTC_IPRC
 682 #define IRQ1_IPR_ADDR   INTC_IPRC
 683 #define IRQ2_IPR_ADDR   INTC_IPRC
 684 #define IRQ3_IPR_ADDR   INTC_IPRC
 685 #define IRQ4_IPR_ADDR   INTC_IPRD
 686 #define IRQ5_IPR_ADDR   INTC_IPRD
 687
 688 #define IRQ0_IPR_POS    0
 689 #define IRQ1_IPR_POS    1
 690 #define IRQ2_IPR_POS    2
 691 #define IRQ3_IPR_POS    3
 692 #define IRQ4_IPR_POS    0
 693 #define IRQ5_IPR_POS    1
 694
 695 #define IRQ0_PRIORITY   1
 696 #define IRQ1_PRIORITY   1
 697 #define IRQ2_PRIORITY   1
 698 #define IRQ3_PRIORITY   1
 699 #define IRQ4_PRIORITY   1
 700 #define IRQ5_PRIORITY   1
 701
 702 #define PINT0_IRQ       40
 703 #define PINT8_IRQ       41
 704
 705 #define PINT0_IPR_ADDR  INTC_IPRD
 706 #define PINT8_IPR_ADDR  INTC_IPRD
 707
 708 #define PINT0_IPR_POS   3
 709 #define PINT8_IPR_POS   2
 710 #define PINT0_PRIORITY  2
 711 #define PINT8_PRIORITY  2
 712
 713 extern int ipr_irq_demux(int irq);
 714 #define __irq_demux(irq) ipr_irq_demux(irq)
 715 #endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
 716
 717 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 718     defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
 719 #define INTC_ICR        0xffd00000
 720 #define INTC_ICR_NMIL   (1<<15)
 721 #define INTC_ICR_MAI    (1<<14)
 722 #define INTC_ICR_NMIB   (1<<9)
 723 #define INTC_ICR_NMIE   (1<<8)
 724 #define INTC_ICR_IRLM   (1<<7)
 725 #endif
 726
 727 #ifdef CONFIG_CPU_SUBTYPE_SH7780
 728 #include <asm/irq-sh7780.h>
 729 #endif
 730
 731 /* SH with INTC2-style interrupts */
 732 #ifdef CONFIG_CPU_HAS_INTC2_IRQ
 733 #if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 734 #define INTC2_BASE      0xfe080000
 735 #define INTC2_FIRST_IRQ 64
 736 #define INTC2_INTREQ_OFFSET     0x20
 737 #define INTC2_INTMSK_OFFSET     0x40
 738 #define INTC2_INTMSKCLR_OFFSET  0x60
 739 #define NR_INTC2_IRQS   25
 740 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
 741 #define INTC2_BASE      0xfe080000
 742 #define INTC2_FIRST_IRQ 48      /* INTEVT 0x800 */
 743 #define INTC2_INTREQ_OFFSET     0x20
 744 #define INTC2_INTMSK_OFFSET     0x40
 745 #define INTC2_INTMSKCLR_OFFSET  0x60
 746 #define NR_INTC2_IRQS   64
 747 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 748 #define INTC2_BASE      0xffd40000
 749 #define INTC2_FIRST_IRQ 21
 750 #define INTC2_INTMSK_OFFSET     (0x38)
 751 #define INTC2_INTMSKCLR_OFFSET  (0x3c)
 752 #define NR_INTC2_IRQS   60
 753 #endif
 754
 755 #define INTC2_INTPRI_OFFSET     0x00
 756
 757 struct intc2_data {
 758         unsigned short irq;
 759         unsigned char ipr_offset, ipr_shift;
 760         unsigned char msk_offset, msk_shift;
 761         unsigned char priority;
 762 };
 763
 764 void make_intc2_irq(struct intc2_data *, unsigned int nr_irqs);
 765 void init_IRQ_intc2(void);
 766 #endif
 767
 768 extern int shmse_irq_demux(int irq);
 769
 770 static inline int generic_irq_demux(int irq)
 771 {
 772         return irq;
 773 }
 774
 775 #ifndef __irq_demux
 776 #define __irq_demux(irq)        (irq)
 777 #endif
 778 #define irq_canonicalize(irq)   (irq)
 779 #define irq_demux(irq)          __irq_demux(sh_mv.mv_irq_demux(irq))
 780
 781 #ifdef CONFIG_4KSTACKS
 782 extern void irq_ctx_init(int cpu);
 783 extern void irq_ctx_exit(int cpu);
 784 # define __ARCH_HAS_DO_SOFTIRQ
 785 #else
 786 # define irq_ctx_init(cpu) do { } while (0)
 787 # define irq_ctx_exit(cpu) do { } while (0)
 788 #endif
 789
 790 #if defined(CONFIG_CPU_SUBTYPE_SH73180)
 791 #include <asm/irq-sh73180.h>
 792 #endif
 793
 794 #if defined(CONFIG_CPU_SUBTYPE_SH7343)
 795 #include <asm/irq-sh7343.h>
 796 #endif
 797
 798 #endif /* __ASM_SH_IRQ_H */