include/asm-sh/system.h

   1 #ifndef __ASM_SH_SYSTEM_H
   2 #define __ASM_SH_SYSTEM_H
   3
   4 /*
   5  * Copyright (C) 1999, 2000  Niibe Yutaka  &  Kaz Kojima
   6  * Copyright (C) 2002 Paul Mundt
   7  */
   8
   9 #include <linux/irqflags.h>
  10 #include <linux/compiler.h>
  11 #include <linux/linkage.h>
  12 #include <asm/types.h>
  13 #include <asm/ptrace.h>
  14
  15 struct task_struct *__switch_to(struct task_struct *prev,
  16                                 struct task_struct *next);
  17
  18 /*
  19  *      switch_to() should switch tasks to task nr n, first
  20  */
  21
  22 #define switch_to(prev, next, last) do {                                \
  23  struct task_struct *__last;                                            \
  24  register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp;       \
  25  register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc;       \
  26  register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev;  \
  27  register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next;  \
  28  register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp;       \
  29  register unsigned long __ts7 __asm__ ("r7") = next->thread.pc;         \
  30  __asm__ __volatile__ (".balign 4\n\t"                                  \
  31                        "stc.l   gbr, @-r15\n\t"                         \
  32                        "sts.l   pr, @-r15\n\t"                          \
  33                        "mov.l   r8, @-r15\n\t"                          \
  34                        "mov.l   r9, @-r15\n\t"                          \
  35                        "mov.l   r10, @-r15\n\t"                         \
  36                        "mov.l   r11, @-r15\n\t"                         \
  37                        "mov.l   r12, @-r15\n\t"                         \
  38                        "mov.l   r13, @-r15\n\t"                         \
  39                        "mov.l   r14, @-r15\n\t"                         \
  40                        "mov.l   r15, @r1        ! save SP\n\t"          \
  41                        "mov.l   @r6, r15        ! change to new stack\n\t" \
  42                        "mova    1f, %0\n\t"                             \
  43                        "mov.l   %0, @r2         ! save PC\n\t"          \
  44                        "mov.l   2f, %0\n\t"                             \
  45                        "jmp     @%0             ! call __switch_to\n\t" \
  46                        " lds    r7, pr          !  with return to new PC\n\t" \
  47                        ".balign 4\n"                                    \
  48                        "2:\n\t"                                         \
  49                        ".long   __switch_to\n"                          \
  50                        "1:\n\t"                                         \
  51                        "mov.l   @r15+, r14\n\t"                         \
  52                        "mov.l   @r15+, r13\n\t"                         \
  53                        "mov.l   @r15+, r12\n\t"                         \
  54                        "mov.l   @r15+, r11\n\t"                         \
  55                        "mov.l   @r15+, r10\n\t"                         \
  56                        "mov.l   @r15+, r9\n\t"                          \
  57                        "mov.l   @r15+, r8\n\t"                          \
  58                        "lds.l   @r15+, pr\n\t"                          \
  59                        "ldc.l   @r15+, gbr\n\t"                         \
  60                        : "=z" (__last)                                  \
  61                        : "r" (__ts1), "r" (__ts2), "r" (__ts4),         \
  62                          "r" (__ts5), "r" (__ts6), "r" (__ts7)          \
  63                        : "r3", "t");                                    \
  64         last = __last;                                                  \
  65 } while (0)
  66
  67 #ifdef CONFIG_CPU_SH4A
  68 #define __icbi()                        \
  69 {                                       \
  70         unsigned long __addr;           \
  71         __addr = 0xa8000000;            \
  72         __asm__ __volatile__(           \
  73                 "icbi   %0\n\t"         \
  74                 : /* no output */       \
  75                 : "m" (__m(__addr)));   \
  76 }
  77 #endif
  78
  79 /*
  80  * A brief note on ctrl_barrier(), the control register write barrier.
  81  *
  82  * Legacy SH cores typically require a sequence of 8 nops after
  83  * modification of a control register in order for the changes to take
  84  * effect. On newer cores (like the sh4a and sh5) this is accomplished
  85  * with icbi.
  86  *
  87  * Also note that on sh4a in the icbi case we can forego a synco for the
  88  * write barrier, as it's not necessary for control registers.
  89  *
  90  * Historically we have only done this type of barrier for the MMUCR, but
  91  * it's also necessary for the CCR, so we make it generic here instead.
  92  */
  93 #ifdef CONFIG_CPU_SH4A
  94 #define mb()            __asm__ __volatile__ ("synco": : :"memory")
  95 #define rmb()           mb()
  96 #define wmb()           __asm__ __volatile__ ("synco": : :"memory")
  97 #define ctrl_barrier()  __icbi()
  98 #define read_barrier_depends()  do { } while(0)
  99 #else
 100 #define mb()            __asm__ __volatile__ ("": : :"memory")
 101 #define rmb()           mb()
 102 #define wmb()           __asm__ __volatile__ ("": : :"memory")
 103 #define ctrl_barrier()  __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
 104 #define read_barrier_depends()  do { } while(0)
 105 #endif
 106
 107 #ifdef CONFIG_SMP
 108 #define smp_mb()        mb()
 109 #define smp_rmb()       rmb()
 110 #define smp_wmb()       wmb()
 111 #define smp_read_barrier_depends()      read_barrier_depends()
 112 #else
 113 #define smp_mb()        barrier()
 114 #define smp_rmb()       barrier()
 115 #define smp_wmb()       barrier()
 116 #define smp_read_barrier_depends()      do { } while(0)
 117 #endif
 118
 119 #define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
 120
 121 /*
 122  * Jump to P2 area.
 123  * When handling TLB or caches, we need to do it from P2 area.
 124  */
 125 #define jump_to_P2()                    \
 126 do {                                    \
 127         unsigned long __dummy;          \
 128         __asm__ __volatile__(           \
 129                 "mov.l  1f, %0\n\t"     \
 130                 "or     %1, %0\n\t"     \
 131                 "jmp    @%0\n\t"        \
 132                 " nop\n\t"              \
 133                 ".balign 4\n"           \
 134                 "1:     .long 2f\n"     \
 135                 "2:"                    \
 136                 : "=&r" (__dummy)       \
 137                 : "r" (0x20000000));    \
 138 } while (0)
 139
 140 /*
 141  * Back to P1 area.
 142  */
 143 #define back_to_P1()                                    \
 144 do {                                                    \
 145         unsigned long __dummy;                          \
 146         ctrl_barrier();                                 \
 147         __asm__ __volatile__(                           \
 148                 "mov.l  1f, %0\n\t"                     \
 149                 "jmp    @%0\n\t"                        \
 150                 " nop\n\t"                              \
 151                 ".balign 4\n"                           \
 152                 "1:     .long 2f\n"                     \
 153                 "2:"                                    \
 154                 : "=&r" (__dummy));                     \
 155 } while (0)
 156
 157 static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
 158 {
 159         unsigned long flags, retval;
 160
 161         local_irq_save(flags);
 162         retval = *m;
 163         *m = val;
 164         local_irq_restore(flags);
 165         return retval;
 166 }
 167
 168 static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
 169 {
 170         unsigned long flags, retval;
 171
 172         local_irq_save(flags);
 173         retval = *m;
 174         *m = val & 0xff;
 175         local_irq_restore(flags);
 176         return retval;
 177 }
 178
 179 extern void __xchg_called_with_bad_pointer(void);
 180
 181 #define __xchg(ptr, x, size)                            \
 182 ({                                                      \
 183         unsigned long __xchg__res;                      \
 184         volatile void *__xchg_ptr = (ptr);              \
 185         switch (size) {                                 \
 186         case 4:                                         \
 187                 __xchg__res = xchg_u32(__xchg_ptr, x);  \
 188                 break;                                  \
 189         case 1:                                         \
 190                 __xchg__res = xchg_u8(__xchg_ptr, x);   \
 191                 break;                                  \
 192         default:                                        \
 193                 __xchg_called_with_bad_pointer();       \
 194                 __xchg__res = x;                        \
 195                 break;                                  \
 196         }                                               \
 197                                                         \
 198         __xchg__res;                                    \
 199 })
 200
 201 #define xchg(ptr,x)     \
 202         ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
 203
 204 static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
 205         unsigned long new)
 206 {
 207         __u32 retval;
 208         unsigned long flags;
 209
 210         local_irq_save(flags);
 211         retval = *m;
 212         if (retval == old)
 213                 *m = new;
 214         local_irq_restore(flags);       /* implies memory barrier  */
 215         return retval;
 216 }
 217
 218 /* This function doesn't exist, so you'll get a linker error
 219  * if something tries to do an invalid cmpxchg(). */
 220 extern void __cmpxchg_called_with_bad_pointer(void);
 221
 222 #define __HAVE_ARCH_CMPXCHG 1
 223
 224 static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
 225                 unsigned long new, int size)
 226 {
 227         switch (size) {
 228         case 4:
 229                 return __cmpxchg_u32(ptr, old, new);
 230         }
 231         __cmpxchg_called_with_bad_pointer();
 232         return old;
 233 }
 234
 235 #define cmpxchg(ptr,o,n)                                                 \
 236   ({                                                                     \
 237      __typeof__(*(ptr)) _o_ = (o);                                       \
 238      __typeof__(*(ptr)) _n_ = (n);                                       \
 239      (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
 240                                     (unsigned long)_n_, sizeof(*(ptr))); \
 241   })
 242
 243 extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
 244
 245 extern void *set_exception_table_vec(unsigned int vec, void *handler);
 246
 247 static inline void *set_exception_table_evt(unsigned int evt, void *handler)
 248 {
 249         return set_exception_table_vec(evt >> 5, handler);
 250 }
 251
 252 /*
 253  * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks.
 254  */
 255 #ifdef CONFIG_CPU_SH2A
 256 extern unsigned int instruction_size(unsigned int insn);
 257 #else
 258 #define instruction_size(insn)  (2)
 259 #endif
 260
 261 /* XXX
 262  * disable hlt during certain critical i/o operations
 263  */
 264 #define HAVE_DISABLE_HLT
 265 void disable_hlt(void);
 266 void enable_hlt(void);
 267
 268 void default_idle(void);
 269
 270 asmlinkage void break_point_trap(void);
 271 asmlinkage void debug_trap_handler(unsigned long r4, unsigned long r5,
 272                                    unsigned long r6, unsigned long r7,
 273                                    struct pt_regs __regs);
 274 asmlinkage void bug_trap_handler(unsigned long r4, unsigned long r5,
 275                                  unsigned long r6, unsigned long r7,
 276                                  struct pt_regs __regs);
 277
 278 #define arch_align_stack(x) (x)
 279
 280 #endif