include/asm-sparc64/cpudata.h

   1 /* cpudata.h: Per-cpu parameters.
   2  *
   3  * Copyright (C) 2003, 2005, 2006 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #ifndef _SPARC64_CPUDATA_H
   7 #define _SPARC64_CPUDATA_H
   8
   9 #include <asm/hypervisor.h>
  10 #include <asm/asi.h>
  11
  12 #ifndef __ASSEMBLY__
  13
  14 #include <linux/percpu.h>
  15 #include <linux/threads.h>
  16
  17 typedef struct {
  18         /* Dcache line 1 */
  19         unsigned int    __softirq_pending; /* must be 1st, see rtrap.S */
  20         unsigned int    multiplier;
  21         unsigned int    counter;
  22         unsigned int    idle_volume;
  23         unsigned long   clock_tick;     /* %tick's per second */
  24         unsigned long   udelay_val;
  25
  26         /* Dcache line 2, rarely used */
  27         unsigned int    dcache_size;
  28         unsigned int    dcache_line_size;
  29         unsigned int    icache_size;
  30         unsigned int    icache_line_size;
  31         unsigned int    ecache_size;
  32         unsigned int    ecache_line_size;
  33         unsigned int    __pad3;
  34         unsigned int    __pad4;
  35 } cpuinfo_sparc;
  36
  37 DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
  38 #define cpu_data(__cpu)         per_cpu(__cpu_data, (__cpu))
  39 #define local_cpu_data()        __get_cpu_var(__cpu_data)
  40
  41 /* Trap handling code needs to get at a few critical values upon
  42  * trap entry and to process TSB misses.  These cannot be in the
  43  * per_cpu() area as we really need to lock them into the TLB and
  44  * thus make them part of the main kernel image.  As a result we
  45  * try to make this as small as possible.
  46  *
  47  * This is padded out and aligned to 64-bytes to avoid false sharing
  48  * on SMP.
  49  */
  50
  51 /* If you modify the size of this structure, please update
  52  * TRAP_BLOCK_SZ_SHIFT below.
  53  */
  54 struct thread_info;
  55 struct trap_per_cpu {
  56 /* D-cache line 1: Basic thread information, cpu and device mondo queues */
  57         struct thread_info      *thread;
  58         unsigned long           pgd_paddr;
  59         unsigned long           cpu_mondo_pa;
  60         unsigned long           dev_mondo_pa;
  61
  62 /* D-cache line 2: Error Mondo Queue and kernel buffer pointers */
  63         unsigned long           resum_mondo_pa;
  64         unsigned long           resum_kernel_buf_pa;
  65         unsigned long           nonresum_mondo_pa;
  66         unsigned long           nonresum_kernel_buf_pa;
  67
  68 /* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */
  69         struct hv_fault_status  fault_info;
  70
  71 /* Dcache line 7: Physical addresses of CPU send mondo block and CPU list.  */
  72         unsigned long           cpu_mondo_block_pa;
  73         unsigned long           cpu_list_pa;
  74         unsigned long           __pad1[2];
  75
  76 /* Dcache line 8: Unused, needed to keep trap_block a power-of-2 in size.  */
  77         unsigned long           __pad2[4];
  78 } __attribute__((aligned(64)));
  79 extern struct trap_per_cpu trap_block[NR_CPUS];
  80 extern void init_cur_cpu_trap(struct thread_info *);
  81 extern void setup_tba(void);
  82
  83 #ifdef CONFIG_SMP
  84 struct cpuid_patch_entry {
  85         unsigned int    addr;
  86         unsigned int    cheetah_safari[4];
  87         unsigned int    cheetah_jbus[4];
  88         unsigned int    starfire[4];
  89         unsigned int    sun4v[4];
  90 };
  91 extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
  92 #endif
  93
  94 struct sun4v_1insn_patch_entry {
  95         unsigned int    addr;
  96         unsigned int    insn;
  97 };
  98 extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch,
  99         __sun4v_1insn_patch_end;
 100
 101 struct sun4v_2insn_patch_entry {
 102         unsigned int    addr;
 103         unsigned int    insns[2];
 104 };
 105 extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
 106         __sun4v_2insn_patch_end;
 107
 108 #endif /* !(__ASSEMBLY__) */
 109
 110 #define TRAP_PER_CPU_THREAD             0x00
 111 #define TRAP_PER_CPU_PGD_PADDR          0x08
 112 #define TRAP_PER_CPU_CPU_MONDO_PA       0x10
 113 #define TRAP_PER_CPU_DEV_MONDO_PA       0x18
 114 #define TRAP_PER_CPU_RESUM_MONDO_PA     0x20
 115 #define TRAP_PER_CPU_RESUM_KBUF_PA      0x28
 116 #define TRAP_PER_CPU_NONRESUM_MONDO_PA  0x30
 117 #define TRAP_PER_CPU_NONRESUM_KBUF_PA   0x38
 118 #define TRAP_PER_CPU_FAULT_INFO         0x40
 119 #define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA 0xc0
 120 #define TRAP_PER_CPU_CPU_LIST_PA        0xc8
 121
 122 #define TRAP_BLOCK_SZ_SHIFT             8
 123
 124 #include <asm/scratchpad.h>
 125
 126 #ifdef CONFIG_SMP
 127
 128 #define __GET_CPUID(REG)                                \
 129         /* Spitfire implementation (default). */        \
 130 661:    ldxa            [%g0] ASI_UPA_CONFIG, REG;      \
 131         srlx            REG, 17, REG;                   \
 132          and            REG, 0x1f, REG;                 \
 133         nop;                                            \
 134         .section        .cpuid_patch, "ax";             \
 135         /* Instruction location. */                     \
 136         .word           661b;                           \
 137         /* Cheetah Safari implementation. */            \
 138         ldxa            [%g0] ASI_SAFARI_CONFIG, REG;   \
 139         srlx            REG, 17, REG;                   \
 140         and             REG, 0x3ff, REG;                \
 141         nop;                                            \
 142         /* Cheetah JBUS implementation. */              \
 143         ldxa            [%g0] ASI_JBUS_CONFIG, REG;     \
 144         srlx            REG, 17, REG;                   \
 145         and             REG, 0x1f, REG;                 \
 146         nop;                                            \
 147         /* Starfire implementation. */                  \
 148         sethi           %hi(0x1fff40000d0 >> 9), REG;   \
 149         sllx            REG, 9, REG;                    \
 150         or              REG, 0xd0, REG;                 \
 151         lduwa           [REG] ASI_PHYS_BYPASS_EC_E, REG;\
 152         /* sun4v implementation. */                     \
 153         mov             SCRATCHPAD_CPUID, REG;          \
 154         ldxa            [REG] ASI_SCRATCHPAD, REG;      \
 155         nop;                                            \
 156         nop;                                            \
 157         .previous;
 158
 159 #define TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
 160         __GET_CPUID(TMP)                        \
 161         sethi   %hi(trap_block), DEST;          \
 162         sllx    TMP, TRAP_BLOCK_SZ_SHIFT, TMP;  \
 163         or      DEST, %lo(trap_block), DEST;    \
 164         add     DEST, TMP, DEST;                \
 165
 166 /* Clobbers TMP, current address space PGD phys address into DEST.  */
 167 #define TRAP_LOAD_PGD_PHYS(DEST, TMP)           \
 168         TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
 169         ldx     [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
 170
 171 /* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
 172 #define TRAP_LOAD_IRQ_WORK(DEST, TMP)           \
 173         __GET_CPUID(TMP)                        \
 174         sethi   %hi(__irq_work), DEST;          \
 175         sllx    TMP, 6, TMP;                    \
 176         or      DEST, %lo(__irq_work), DEST;    \
 177         add     DEST, TMP, DEST;
 178
 179 /* Clobbers TMP, loads DEST with current thread info pointer.  */
 180 #define TRAP_LOAD_THREAD_REG(DEST, TMP)         \
 181         TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
 182         ldx     [DEST + TRAP_PER_CPU_THREAD], DEST;
 183
 184 /* Given the current thread info pointer in THR, load the per-cpu
 185  * area base of the current processor into DEST.  REG1, REG2, and REG3 are
 186  * clobbered.
 187  *
 188  * You absolutely cannot use DEST as a temporary in this code.  The
 189  * reason is that traps can happen during execution, and return from
 190  * trap will load the fully resolved DEST per-cpu base.  This can corrupt
 191  * the calculations done by the macro mid-stream.
 192  */
 193 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)  \
 194         ldub    [THR + TI_CPU], REG1;                   \
 195         sethi   %hi(__per_cpu_shift), REG3;             \
 196         sethi   %hi(__per_cpu_base), REG2;              \
 197         ldx     [REG3 + %lo(__per_cpu_shift)], REG3;    \
 198         ldx     [REG2 + %lo(__per_cpu_base)], REG2;     \
 199         sllx    REG1, REG3, REG3;                       \
 200         add     REG3, REG2, DEST;
 201
 202 #else
 203
 204 #define TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
 205         sethi   %hi(trap_block), DEST;          \
 206         or      DEST, %lo(trap_block), DEST;    \
 207
 208 /* Uniprocessor versions, we know the cpuid is zero.  */
 209 #define TRAP_LOAD_PGD_PHYS(DEST, TMP)           \
 210         TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
 211         ldx     [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
 212
 213 #define TRAP_LOAD_IRQ_WORK(DEST, TMP)           \
 214         sethi   %hi(__irq_work), DEST;          \
 215         or      DEST, %lo(__irq_work), DEST;
 216
 217 #define TRAP_LOAD_THREAD_REG(DEST, TMP)         \
 218         TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
 219         ldx     [DEST + TRAP_PER_CPU_THREAD], DEST;
 220
 221 /* No per-cpu areas on uniprocessor, so no need to load DEST.  */
 222 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
 223
 224 #endif /* !(CONFIG_SMP) */
 225
 226 #endif /* _SPARC64_CPUDATA_H */