include/asm-sparc64/cpudata.h

   1 /* cpudata.h: Per-cpu parameters.
   2  *
   3  * Copyright (C) 2003, 2005, 2006 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #ifndef _SPARC64_CPUDATA_H
   7 #define _SPARC64_CPUDATA_H
   8
   9 #ifndef __ASSEMBLY__
  10
  11 #include <linux/percpu.h>
  12 #include <linux/threads.h>
  13
  14 typedef struct {
  15         /* Dcache line 1 */
  16         unsigned int    __softirq_pending; /* must be 1st, see rtrap.S */
  17         unsigned int    multiplier;
  18         unsigned int    counter;
  19         unsigned int    idle_volume;
  20         unsigned long   clock_tick;     /* %tick's per second */
  21         unsigned long   udelay_val;
  22
  23         /* Dcache line 2, rarely used */
  24         unsigned int    dcache_size;
  25         unsigned int    dcache_line_size;
  26         unsigned int    icache_size;
  27         unsigned int    icache_line_size;
  28         unsigned int    ecache_size;
  29         unsigned int    ecache_line_size;
  30         unsigned int    __pad3;
  31         unsigned int    __pad4;
  32 } cpuinfo_sparc;
  33
  34 DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
  35 #define cpu_data(__cpu)         per_cpu(__cpu_data, (__cpu))
  36 #define local_cpu_data()        __get_cpu_var(__cpu_data)
  37
  38 /* Trap handling code needs to get at a few critical values upon
  39  * trap entry and to process TSB misses.  These cannot be in the
  40  * per_cpu() area as we really need to lock them into the TLB and
  41  * thus make them part of the main kernel image.  As a result we
  42  * try to make this as small as possible.
  43  *
  44  * This is padded out and aligned to 64-bytes to avoid false sharing
  45  * on SMP.
  46  */
  47
  48 /* If you modify the size of this structure, please update
  49  * TRAP_BLOCK_SZ_SHIFT below.
  50  */
  51 struct thread_info;
  52 struct trap_per_cpu {
  53 /* D-cache line 1 */
  54         struct thread_info      *thread;
  55         unsigned long           pgd_paddr;
  56         unsigned long           __pad1[2];
  57
  58 /* D-cache line 2 */
  59         unsigned long           __pad2[4];
  60 } __attribute__((aligned(64)));
  61 extern struct trap_per_cpu trap_block[NR_CPUS];
  62 extern void init_cur_cpu_trap(void);
  63 extern void setup_tba(void);
  64
  65 #ifdef CONFIG_SMP
  66 struct cpuid_patch_entry {
  67         unsigned int    addr;
  68         unsigned int    cheetah_safari[4];
  69         unsigned int    cheetah_jbus[4];
  70         unsigned int    starfire[4];
  71 };
  72 extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
  73 #endif
  74
  75 #endif /* !(__ASSEMBLY__) */
  76
  77 #define TRAP_PER_CPU_THREAD     0x00
  78 #define TRAP_PER_CPU_PGD_PADDR  0x08
  79
  80 #define TRAP_BLOCK_SZ_SHIFT     6
  81
  82 #ifdef CONFIG_SMP
  83
  84 #define __GET_CPUID(REG)                                \
  85         /* Spitfire implementation (default). */        \
  86 661:    ldxa            [%g0] ASI_UPA_CONFIG, REG;      \
  87         srlx            REG, 17, REG;                   \
  88          and            REG, 0x1f, REG;                 \
  89         nop;                                            \
  90         .section        .cpuid_patch, "ax";             \
  91         /* Instruction location. */                     \
  92         .word           661b;                           \
  93         /* Cheetah Safari implementation. */            \
  94         ldxa            [%g0] ASI_SAFARI_CONFIG, REG;   \
  95         srlx            REG, 17, REG;                   \
  96         and             REG, 0x3ff, REG;                \
  97         nop;                                            \
  98         /* Cheetah JBUS implementation. */              \
  99         ldxa            [%g0] ASI_JBUS_CONFIG, REG;     \
 100         srlx            REG, 17, REG;                   \
 101         and             REG, 0x1f, REG;                 \
 102         nop;                                            \
 103         /* Starfire implementation. */                  \
 104         sethi           %hi(0x1fff40000d0 >> 9), REG;   \
 105         sllx            REG, 9, REG;                    \
 106         or              REG, 0xd0, REG;                 \
 107         lduwa           [REG] ASI_PHYS_BYPASS_EC_E, REG;\
 108         .previous;
 109
 110 /* Clobbers TMP, current address space PGD phys address into DEST.  */
 111 #define TRAP_LOAD_PGD_PHYS(DEST, TMP)           \
 112         __GET_CPUID(TMP)                        \
 113         sethi   %hi(trap_block), DEST;          \
 114         sllx    TMP, TRAP_BLOCK_SZ_SHIFT, TMP;  \
 115         or      DEST, %lo(trap_block), DEST;    \
 116         add     DEST, TMP, DEST;                \
 117         ldx     [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
 118
 119 /* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
 120 #define TRAP_LOAD_IRQ_WORK(DEST, TMP)           \
 121         __GET_CPUID(TMP)                        \
 122         sethi   %hi(__irq_work), DEST;          \
 123         sllx    TMP, 6, TMP;                    \
 124         or      DEST, %lo(__irq_work), DEST;    \
 125         add     DEST, TMP, DEST;
 126
 127 /* Clobbers TMP, loads DEST with current thread info pointer.  */
 128 #define TRAP_LOAD_THREAD_REG(DEST, TMP)         \
 129         __GET_CPUID(TMP)                        \
 130         sethi   %hi(trap_block), DEST;          \
 131         sllx    TMP, TRAP_BLOCK_SZ_SHIFT, TMP;  \
 132         or      DEST, %lo(trap_block), DEST;    \
 133         ldx     [DEST + TMP], DEST;
 134
 135 /* Given the current thread info pointer in THR, load the per-cpu
 136  * area base of the current processor into DEST.  REG1, REG2, and REG3 are
 137  * clobbered.
 138  *
 139  * You absolutely cannot use DEST as a temporary in this code.  The
 140  * reason is that traps can happen during execution, and return from
 141  * trap will load the fully resolved DEST per-cpu base.  This can corrupt
 142  * the calculations done by the macro mid-stream.
 143  */
 144 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)  \
 145         ldub    [THR + TI_CPU], REG1;                   \
 146         sethi   %hi(__per_cpu_shift), REG3;             \
 147         sethi   %hi(__per_cpu_base), REG2;              \
 148         ldx     [REG3 + %lo(__per_cpu_shift)], REG3;    \
 149         ldx     [REG2 + %lo(__per_cpu_base)], REG2;     \
 150         sllx    REG1, REG3, REG3;                       \
 151         add     REG3, REG2, DEST;
 152
 153 #else
 154
 155 /* Uniprocessor versions, we know the cpuid is zero.  */
 156 #define TRAP_LOAD_PGD_PHYS(DEST, TMP)           \
 157         sethi   %hi(trap_block), DEST;          \
 158         or      DEST, %lo(trap_block), DEST;    \
 159         ldx     [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
 160
 161 #define TRAP_LOAD_IRQ_WORK(DEST, TMP)           \
 162         sethi   %hi(__irq_work), DEST;          \
 163         or      DEST, %lo(__irq_work), DEST;
 164
 165 #define TRAP_LOAD_THREAD_REG(DEST, TMP)         \
 166         sethi   %hi(trap_block), DEST;          \
 167         ldx     [DEST + %lo(trap_block)], DEST;
 168
 169 /* No per-cpu areas on uniprocessor, so no need to load DEST.  */
 170 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
 171
 172 #endif /* !(CONFIG_SMP) */
 173
 174 #endif /* _SPARC64_CPUDATA_H */