include/asm-sparc64/mmu.h

   1 #ifndef __MMU_H
   2 #define __MMU_H
   3
   4 #include <linux/config.h>
   5 #include <asm/page.h>
   6 #include <asm/const.h>
   7 #include <asm/hypervisor.h>
   8
   9 #define CTX_NR_BITS             13
  10
  11 #define TAG_CONTEXT_BITS        ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL))
  12
  13 /* UltraSPARC-III+ and later have a feature whereby you can
  14  * select what page size the various Data-TLB instances in the
  15  * chip.  In order to gracefully support this, we put the version
  16  * field in a spot outside of the areas of the context register
  17  * where this parameter is specified.
  18  */
  19 #define CTX_VERSION_SHIFT       22
  20 #define CTX_VERSION_MASK        ((~0UL) << CTX_VERSION_SHIFT)
  21
  22 #define CTX_PGSZ_8KB            _AC(0x0,UL)
  23 #define CTX_PGSZ_64KB           _AC(0x1,UL)
  24 #define CTX_PGSZ_512KB          _AC(0x2,UL)
  25 #define CTX_PGSZ_4MB            _AC(0x3,UL)
  26 #define CTX_PGSZ_BITS           _AC(0x7,UL)
  27 #define CTX_PGSZ0_NUC_SHIFT     61
  28 #define CTX_PGSZ1_NUC_SHIFT     58
  29 #define CTX_PGSZ0_SHIFT         16
  30 #define CTX_PGSZ1_SHIFT         19
  31 #define CTX_PGSZ_MASK           ((CTX_PGSZ_BITS << CTX_PGSZ0_SHIFT) | \
  32                                  (CTX_PGSZ_BITS << CTX_PGSZ1_SHIFT))
  33
  34 #if defined(CONFIG_SPARC64_PAGE_SIZE_8KB)
  35 #define CTX_PGSZ_BASE   CTX_PGSZ_8KB
  36 #elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB)
  37 #define CTX_PGSZ_BASE   CTX_PGSZ_64KB
  38 #elif defined(CONFIG_SPARC64_PAGE_SIZE_512KB)
  39 #define CTX_PGSZ_BASE   CTX_PGSZ_512KB
  40 #elif defined(CONFIG_SPARC64_PAGE_SIZE_4MB)
  41 #define CTX_PGSZ_BASE   CTX_PGSZ_4MB
  42 #else
  43 #error No page size specified in kernel configuration
  44 #endif
  45
  46 #if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
  47 #define CTX_PGSZ_HUGE           CTX_PGSZ_4MB
  48 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
  49 #define CTX_PGSZ_HUGE           CTX_PGSZ_512KB
  50 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
  51 #define CTX_PGSZ_HUGE           CTX_PGSZ_64KB
  52 #endif
  53
  54 #define CTX_PGSZ_KERN   CTX_PGSZ_4MB
  55
  56 /* Thus, when running on UltraSPARC-III+ and later, we use the following
  57  * PRIMARY_CONTEXT register values for the kernel context.
  58  */
  59 #define CTX_CHEETAH_PLUS_NUC \
  60         ((CTX_PGSZ_KERN << CTX_PGSZ0_NUC_SHIFT) | \
  61          (CTX_PGSZ_BASE << CTX_PGSZ1_NUC_SHIFT))
  62
  63 #define CTX_CHEETAH_PLUS_CTX0 \
  64         ((CTX_PGSZ_KERN << CTX_PGSZ0_SHIFT) | \
  65          (CTX_PGSZ_BASE << CTX_PGSZ1_SHIFT))
  66
  67 /* If you want "the TLB context number" use CTX_NR_MASK.  If you
  68  * want "the bits I program into the context registers" use
  69  * CTX_HW_MASK.
  70  */
  71 #define CTX_NR_MASK             TAG_CONTEXT_BITS
  72 #define CTX_HW_MASK             (CTX_NR_MASK | CTX_PGSZ_MASK)
  73
  74 #define CTX_FIRST_VERSION       ((_AC(1,UL) << CTX_VERSION_SHIFT) + _AC(1,UL))
  75 #define CTX_VALID(__ctx)        \
  76          (!(((__ctx.sparc64_ctx_val) ^ tlb_context_cache) & CTX_VERSION_MASK))
  77 #define CTX_HWBITS(__ctx)       ((__ctx.sparc64_ctx_val) & CTX_HW_MASK)
  78 #define CTX_NRBITS(__ctx)       ((__ctx.sparc64_ctx_val) & CTX_NR_MASK)
  79
  80 #ifndef __ASSEMBLY__
  81
  82 #define TSB_ENTRY_ALIGNMENT     16
  83
  84 struct tsb {
  85         unsigned long tag;
  86         unsigned long pte;
  87 } __attribute__((aligned(TSB_ENTRY_ALIGNMENT)));
  88
  89 extern void __tsb_insert(unsigned long ent, unsigned long tag, unsigned long pte);
  90 extern void tsb_flush(unsigned long ent, unsigned long tag);
  91 extern void tsb_init(struct tsb *tsb, unsigned long size);
  92
  93 typedef struct {
  94         spinlock_t              lock;
  95         unsigned long           sparc64_ctx_val;
  96         struct tsb              *tsb;
  97         unsigned long           tsb_rss_limit;
  98         unsigned long           tsb_nentries;
  99         unsigned long           tsb_reg_val;
 100         unsigned long           tsb_map_vaddr;
 101         unsigned long           tsb_map_pte;
 102         struct hv_tsb_descr     tsb_descr;
 103 } mm_context_t;
 104
 105 #endif /* !__ASSEMBLY__ */
 106
 107 #endif /* __MMU_H */